mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-06 05:09:18 +03:00
17c7b6c3fd
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8653 3c298f89-4303-0410-b956-a3cf2f4a3e73
97 lines
4.5 KiB
C
97 lines
4.5 KiB
C
//*************************************************************************
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//* Summary of definitions which are used in each peripheral *
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//*************************************************************************
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#ifndef peripheral_definitions_h
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#define peripheral_definitions_h
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typedef unsigned char UINT8;
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typedef signed char INT8;
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typedef unsigned short UINT16;
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typedef signed short INT16;
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typedef unsigned int UINT32;
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typedef signed int INT32;
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typedef unsigned long long UINT64;
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typedef signed long long INT64;
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#define REG8( addr ) (*(volatile UINT8 *) (addr))
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#define REG16( addr ) (*(volatile UINT16 *)(addr))
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#define REG32( addr ) (*(volatile UINT32 *)(addr))
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#define REG64( addr ) (*(volatile UINT64 *)(addr))
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/* define routine to set FPI access in Supervisor Mode */
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#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG)
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm
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/* enable all Interrupts in IIU */
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//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask
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///* get all high priority interrupt bits in IIU */
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//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED)
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///* signal ends of interrupt to IIU */
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//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit
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///* force IIU interrupt register */
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//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data
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///* get all bits of interrupt register */
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//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR)
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/* insert a NOP instruction */
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#define NOP _nop()
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/* CPU goes to power down mode until interrupt occurs */
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#define IFX_CPU_SLEEP _sleep()
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/* enable all interrupts to CPU */
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#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int()
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/* get all low priority interrupt bits in peripheral */
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#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg)
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/* clear low priority interrupt bit in peripheral */
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#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit
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/* write FPI bus */
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#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data
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#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data
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#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data
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/* read FPI bus */
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#define READ_FPI_BYTE(addr) REG8(addr)
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#define READ_FPI_16BIT(addr) REG16(addr)
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#define READ_FPI_32BIT(addr) REG32(addr)
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/* write peripheral register */
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#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
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#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
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#else //not CONFIG_CPU_LITTLE_ENDIAN
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#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
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#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
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#endif //CONFIG_CPU_LITTLE_ENDIAN
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/* read peripheral register */
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#define READ_PERIPHERAL_REGISTER(addr) REG32(addr)
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/* read/modify(or)/write peripheral register */
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#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data
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/* read/modify(and)/write peripheral register */
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#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
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/* CPU-independent mnemonic constants */
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/* CLC register bits */
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#define IFX_CLC_ENABLE 0x00000000
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#define IFX_CLC_DISABLE 0x00000001
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#define IFX_CLC_DISABLE_STATUS 0x00000002
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#define IFX_CLC_SUSPEND_ENABLE 0x00000004
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#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008
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#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010
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#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
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#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00
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#define IFX_CLC_RUN_DIVIDER_OFFSET 8
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#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000
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#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16
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#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
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#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
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/* number of cycles to wait for interrupt service routine to be called */
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#define WAIT_CYCLES 50
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#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */
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