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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33335 3c298f89-4303-0410-b956-a3cf2f4a3e73
206 lines
6.8 KiB
Diff
206 lines
6.8 KiB
Diff
From 3f735e202d5099a5b7c621443bea365b87b0e3bb Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sat, 8 Sep 2012 12:12:50 +0200
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Subject: [PATCH] MIPS: ath79: fix CPU/DDR frequency calculation for SRIF PLLs
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Besides the CPU and DDR PLLs, the CPU and DDR frequencies
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can be derived from other PLLs in the SRIF block on the
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AR934x SoCs. The current code does not checks if the SRIF
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PLLs are used and this can lead to incorrectly calculated
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CPU/DDR frequencies.
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Fix it by calculating the frequencies from SRIF PLLs if
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those are used on a given board.
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Cc: <stable@vger.kernel.org>
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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This depends on the following patch:
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'MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x'
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https://patchwork.linux-mips.org/patch/4305/
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arch/mips/ath79/clock.c | 109 ++++++++++++++++++------
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 23 +++++
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2 files changed, 104 insertions(+), 28 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -17,6 +17,8 @@
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#include <linux/err.h>
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#include <linux/clk.h>
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+#include <asm/div64.h>
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+
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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@@ -166,11 +168,34 @@ static void __init ar933x_clocks_init(vo
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ath79_uart_clk.rate = ath79_ref_clk.rate;
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}
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+static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
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+ u32 frac, u32 out_div)
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+{
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+ u64 t;
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+ u32 ret;
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+
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+ t = ath79_ref_clk.rate;
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+ t *= nint;
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+ do_div(t, ref_div);
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+ ret = t;
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+
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+ t = ath79_ref_clk.rate;
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+ t *= nfrac;
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+ do_div(t, ref_div * frac);
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+ ret += t;
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+
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+ ret /= (1 << out_div);
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+ return ret;
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+}
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+
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static void __init ar934x_clocks_init(void)
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{
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- u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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+ void __iomem *dpll_base;
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+
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+ dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
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bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
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@@ -178,33 +203,59 @@ static void __init ar934x_clocks_init(vo
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else
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ath79_ref_clk.rate = 25 * 1000 * 1000;
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- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
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- out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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- AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
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- ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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- AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
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- nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
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- AR934X_PLL_CPU_CONFIG_NINT_MASK;
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- frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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- AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
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-
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- cpu_pll = nint * ath79_ref_clk.rate / ref_div;
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- cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
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- cpu_pll /= (1 << out_div);
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-
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- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
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- out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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- AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
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- ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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- AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
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- nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
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- AR934X_PLL_DDR_CONFIG_NINT_MASK;
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- frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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- AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
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-
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- ddr_pll = nint * ath79_ref_clk.rate / ref_div;
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- ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
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- ddr_pll /= (1 << out_div);
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+ pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
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+ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
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+ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
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+ AR934X_SRIF_DPLL2_OUTDIV_MASK;
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+ pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
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+ nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
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+ AR934X_SRIF_DPLL1_NINT_MASK;
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+ nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
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+ ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
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+ AR934X_SRIF_DPLL1_REFDIV_MASK;
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+ frac = 1 << 18;
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+ } else {
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+ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
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+ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
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+ AR934X_PLL_CPU_CONFIG_NINT_MASK;
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+ nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
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+ frac = 1 << 6;
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+ }
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+
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+ cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
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+ nfrac, frac, out_div);
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+
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+ pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
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+ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
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+ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
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+ AR934X_SRIF_DPLL2_OUTDIV_MASK;
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+ pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
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+ nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
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+ AR934X_SRIF_DPLL1_NINT_MASK;
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+ nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
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+ ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
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+ AR934X_SRIF_DPLL1_REFDIV_MASK;
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+ frac = 1 << 18;
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+ } else {
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+ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
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+ AR934X_PLL_DDR_CONFIG_NINT_MASK;
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+ nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
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+ frac = 1 << 10;
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+ }
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+
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+ ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
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+ nfrac, frac, out_div);
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clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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@@ -240,6 +291,8 @@ static void __init ar934x_clocks_init(vo
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ath79_wdt_clk.rate = ath79_ref_clk.rate;
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ath79_uart_clk.rate = ath79_ref_clk.rate;
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+
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+ iounmap(dpll_base);
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}
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void __init ath79_clocks_init(void)
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -65,6 +65,8 @@
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#define AR934X_WMAC_SIZE 0x20000
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#define AR934X_EHCI_BASE 0x1b000000
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#define AR934X_EHCI_SIZE 0x200
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+#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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+#define AR934X_SRIF_SIZE 0x1000
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/*
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* DDR_CTRL block
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@@ -405,4 +407,25 @@
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#define AR933X_GPIO_COUNT 30
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#define AR934X_GPIO_COUNT 23
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+/*
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+ * SRIF block
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+ */
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+#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
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+#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
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+#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
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+
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+#define AR934X_SRIF_DDR_DPLL1_REG 0x240
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+#define AR934X_SRIF_DDR_DPLL2_REG 0x244
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+#define AR934X_SRIF_DDR_DPLL3_REG 0x248
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+
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+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
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+#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
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+#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
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+#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
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+#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
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+
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+#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
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+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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+#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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+
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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