mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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df88996997
The nand subtarget is not working yet. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33983 3c298f89-4303-0410-b956-a3cf2f4a3e73
154 lines
3.9 KiB
Diff
154 lines
3.9 KiB
Diff
--- a/arch/mips/ath79/mach-pb44.c
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+++ b/arch/mips/ath79/mach-pb44.c
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@@ -8,23 +8,48 @@
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* by the Free Software Foundation.
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*/
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+#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/i2c-gpio.h>
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#include <linux/i2c/pcf857x.h>
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+#include <linux/i2c/pcf857x.h>
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+#include <linux/spi/flash.h>
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+#include <linux/spi/vsc7385.h>
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-#include "machtypes.h"
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+#include <asm/mach-ath79/ath79.h>
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+
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+#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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+#include "machtypes.h"
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#include "pci.h"
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#define PB44_GPIO_I2C_SCL 0
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#define PB44_GPIO_I2C_SDA 1
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+#define PB44_PCF8757_VSC7395_CS 0
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+#define PB44_PCF8757_STEREO_CS 1
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+#define PB44_PCF8757_SLIC_CS0 2
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+#define PB44_PCF8757_SLIC_TEST 3
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+#define PB44_PCF8757_SLIC_INT0 4
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+#define PB44_PCF8757_SLIC_INT1 5
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+#define PB44_PCF8757_SW_RESET 6
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+#define PB44_PCF8757_SW_JUMP 8
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+#define PB44_PCF8757_LED_JUMP1 9
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+#define PB44_PCF8757_LED_JUMP2 10
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+#define PB44_PCF8757_TP24 11
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+#define PB44_PCF8757_TP25 12
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+#define PB44_PCF8757_TP26 13
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+#define PB44_PCF8757_TP27 14
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+#define PB44_PCF8757_TP28 15
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+
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#define PB44_GPIO_EXP_BASE 16
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+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
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#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
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#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
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#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
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@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
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.cs_line = 0,
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};
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+static struct ath79_spi_controller_data pb44_spi1_data = {
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+ .cs_type = ATH79_SPI_CS_TYPE_GPIO,
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+ .cs_line = PB44_GPIO_VSC7395_CS,
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+};
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+
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+static void pb44_vsc7395_reset(void)
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+{
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+ ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
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+ udelay(10);
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+ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
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+ mdelay(50);
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+}
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+
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+static struct vsc7385_platform_data pb44_vsc7395_data = {
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+ .reset = pb44_vsc7395_reset,
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+ .ucode_name = "vsc7395_ucode_pb44.bin",
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+ .mac_cfg = {
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+ .tx_ipg = 6,
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+ .bit2 = 1,
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+ .clk_sel = 0,
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+ },
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+};
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+
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+static const char *pb44_part_probes[] = {
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+ "RedBoot",
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+ NULL,
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+};
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+
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+static struct flash_platform_data pb44_flash_data = {
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+ .part_probes = pb44_part_probes,
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+};
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+
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static struct spi_board_info pb44_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p64",
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+ .platform_data = &pb44_flash_data,
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.controller_data = &pb44_spi0_data,
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},
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+ {
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+ .bus_num = 0,
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+ .chip_select = 1,
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+ .max_speed_hz = 25000000,
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+ .modalias = "spi-vsc7385",
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+ .platform_data = &pb44_vsc7395_data,
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+ .controller_data = &pb44_spi1_data,
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+ }
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};
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static struct ath79_spi_platform_data pb44_spi_data = {
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.bus_num = 0,
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- .num_chipselect = 1,
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+ .num_chipselect = 2,
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};
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+#define PB44_WAN_PHYMASK BIT(0)
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+#define PB44_LAN_PHYMASK 0
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+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
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+
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static void __init pb44_init(void)
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{
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i2c_register_board_info(0, pb44_i2c_board_info,
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@@ -122,6 +192,22 @@ static void __init pb44_init(void)
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ARRAY_SIZE(pb44_spi_info));
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ath79_register_usb();
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ath79_register_pci();
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+
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+ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
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+
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+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
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+
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+ ath79_register_eth(0);
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+
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+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
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+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth1_data.speed = SPEED_1000;
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+ ath79_eth1_data.duplex = DUPLEX_FULL;
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+ ath79_eth1_pll_data.pll_1000 = 0x110000;
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+
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+ ath79_register_eth(1);
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}
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MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -58,6 +58,7 @@ config ATH79_MACH_DB120
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config ATH79_MACH_PB44
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bool "Atheros PB44 reference board"
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select SOC_AR71XX
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+ select ATH79_DEV_ETH
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_SPI
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