mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-28 02:36:15 +02:00
42fc31c396
Combine two pcie patches (2nd patch undid the 1st patch) together and refresh the other affected patches Signed-off-by: Tim Harvey <tharvey@gateworks.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34132 3c298f89-4303-0410-b956-a3cf2f4a3e73
118 lines
3.2 KiB
Diff
118 lines
3.2 KiB
Diff
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -213,7 +213,7 @@ static struct map_desc cns3420_io_desc[]
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static void __init cns3420_map_io(void)
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{
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- cns3xxx_map_io();
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+ cns3xxx_common_init();
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iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
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cns3420_early_serial_setup();
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -21,6 +21,7 @@
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#include <asm/hardware/gic.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/cache-l2x0.h>
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+#include <asm/gpio.h>
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#include <mach/cns3xxx.h>
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#include "core.h"
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@@ -72,12 +73,73 @@ static struct map_desc cns3xxx_io_desc[]
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},
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};
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-void __init cns3xxx_map_io(void)
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+static inline void gpio_line_config(u8 line, u32 direction)
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+{
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+ u32 reg;
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+ if (direction) {
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+ if (line < 32) {
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+ reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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+ reg |= (1 << line);
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+ __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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+ } else {
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+ reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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+ reg |= (1 << (line - 32));
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+ __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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+ }
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+ } else {
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+ if (line < 32) {
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+ reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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+ reg &= ~(1 << line);
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+ __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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+ } else {
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+ reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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+ reg &= ~(1 << (line - 32));
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+ __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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+ }
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+ }
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+}
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+
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+static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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+{
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+ gpio_line_config(gpio, CNS3XXX_GPIO_IN);
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+ return 0;
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+}
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+
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+static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
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+{
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+ gpio_line_set(gpio, level);
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+ gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
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+ return 0;
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+}
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+
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+static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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+{
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+ return gpio_get_value(gpio);
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+}
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+
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+static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
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+{
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+ gpio_set_value(gpio, value);
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+}
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+
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+static struct gpio_chip cns3xxx_gpio_chip = {
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+ .label = "CNS3XXX_GPIO_CHIP",
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+ .direction_input = cns3xxx_gpio_direction_input,
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+ .direction_output = cns3xxx_gpio_direction_output,
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+ .get = cns3xxx_gpio_get_value,
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+ .set = cns3xxx_gpio_set_value,
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+ .base = 0,
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+ .ngpio = 64,
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+};
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+
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+void __init cns3xxx_common_init(void)
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{
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
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#endif
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iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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+
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+ gpiochip_add(&cns3xxx_gpio_chip);
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}
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/* used by entry-macro.S */
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -19,7 +19,7 @@ void __init cns3xxx_l2x0_init(void);
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static inline void cns3xxx_l2x0_init(void) {}
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#endif /* CONFIG_CACHE_L2X0 */
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-void __init cns3xxx_map_io(void);
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+void __init cns3xxx_common_init(void);
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void __init cns3xxx_init_irq(void);
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void cns3xxx_power_off(void);
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void cns3xxx_restart(char, const char *);
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--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -366,6 +366,7 @@ config ARCH_CLPS711X
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config ARCH_CNS3XXX
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bool "Cavium Networks CNS3XXX family"
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select CPU_V6K
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+ select ARCH_WANT_OPTIONAL_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select ARM_GIC
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select CLKDEV_LOOKUP
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