mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-29 04:47:30 +02:00
dc3d3f1c49
it's basically also provided by ingenic and nativly based on 2.6.27, adjusted to fit into the OpenWrt-environment
308 lines
5.4 KiB
ArmAsm
308 lines
5.4 KiB
ArmAsm
/*
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* linux/arch/mips/jz4730/sleep.S
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*
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* jz4730 Assembler Sleep/WakeUp Management Routines
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*
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* Copyright (C) 2005 Ingenic Semiconductor
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* Author: <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-jz4730/regs.h>
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.text
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.set noreorder
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.set noat
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.extern jz_flush_cache_all
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/*
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* jz_cpu_suspend()
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*
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* Forces CPU into hibernate mode
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*/
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.globl jz_cpu_suspend
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jz_cpu_suspend:
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/* save hi, lo and general registers except k0($26) and k1($27) (total 32) */
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move k0, sp
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addiu k0, k0, -(32*4)
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mfhi k1
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sw $0, 0(k0)
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sw $1, 4(k0)
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sw k1, 120(k0) /* hi */
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mflo k1
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sw $2, 8(k0)
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sw $3, 12(k0)
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sw k1, 124(k0) /* lo */
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sw $4, 16(k0)
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sw $5, 20(k0)
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sw $6, 24(k0)
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sw $7, 28(k0)
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sw $8, 32(k0)
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sw $9, 36(k0)
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sw $10, 40(k0)
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sw $11, 44(k0)
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sw $12, 48(k0)
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sw $13, 52(k0)
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sw $14, 56(k0)
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sw $15, 60(k0)
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sw $16, 64(k0)
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sw $17, 68(k0)
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sw $18, 72(k0)
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sw $19, 76(k0)
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sw $20, 80(k0)
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sw $21, 84(k0)
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sw $22, 88(k0)
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sw $23, 92(k0)
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sw $24, 96(k0)
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sw $25, 100(k0)
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sw $28, 104(k0)
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sw $29, 108(k0) /* saved sp */
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sw $30, 112(k0)
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sw $31, 116(k0) /* saved ra */
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move sp, k0
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/* save CP0 registers and sp (total 26) */
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move k0, sp
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addiu k0, k0, -(26*4)
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mfc0 $1, CP0_INDEX
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mfc0 $2, CP0_RANDOM
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mfc0 $3, CP0_ENTRYLO0
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mfc0 $4, CP0_ENTRYLO1
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mfc0 $5, CP0_CONTEXT
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mfc0 $6, CP0_PAGEMASK
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mfc0 $7, CP0_WIRED
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mfc0 $8, CP0_BADVADDR
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mfc0 $9, CP0_ENTRYHI
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mfc0 $10, CP0_STATUS
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/* mfc0 $11, $12, 1*/ /* IntCtl */
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mfc0 $12, CP0_CAUSE
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mfc0 $13, CP0_EPC
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/* mfc0 $14, $15, 1*/ /* EBase */
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mfc0 $15, CP0_CONFIG
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/* mfc0 $16, CP0_CONFIG, 7*/ /* Config 7 */
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mfc0 $17, CP0_LLADDR
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mfc0 $18, CP0_WATCHLO
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mfc0 $19, CP0_WATCHHI
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mfc0 $20, CP0_DEBUG
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mfc0 $21, CP0_DEPC
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mfc0 $22, CP0_ECC
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mfc0 $23, CP0_TAGLO
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mfc0 $24, CP0_ERROREPC
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mfc0 $25, CP0_DESAVE
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sw $1, 0(k0)
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sw $2, 4(k0)
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sw $3, 8(k0)
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sw $4, 12(k0)
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sw $5, 16(k0)
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sw $6, 20(k0)
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sw $7, 24(k0)
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sw $8, 28(k0)
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sw $9, 32(k0)
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sw $10, 36(k0)
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sw $11, 40(k0)
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sw $12, 44(k0)
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sw $13, 48(k0)
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sw $14, 52(k0)
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sw $15, 56(k0)
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sw $16, 60(k0)
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sw $17, 64(k0)
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sw $18, 68(k0)
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sw $19, 72(k0)
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sw $20, 76(k0)
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sw $21, 80(k0)
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sw $22, 84(k0)
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sw $23, 88(k0)
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sw $24, 92(k0)
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sw $25, 96(k0)
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sw $29, 100(k0) /* saved sp */
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move sp, k0
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/* preserve virtual address of stack */
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la k0, suspend_save_sp
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sw sp, 0(k0)
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/* flush caches and write buffers */
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jal jz_flush_cache_all
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nop
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/* set new sdram refresh constant */
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li t0, 1
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la t1, EMC_RTCOR
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sh t0, 0(t1)
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/* disable PLL */
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la t0, CPM_PLCR1
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sw $0, 0(t0)
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/* put CPU to hibernate mode */
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la t0, CPM_LPCR
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lw t1, 0(t0)
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li t2, ~CPM_LPCR_LPM_MASK
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and t1, t2
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ori t1, CPM_LPCR_LPM_HIBERNATE
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.align 5
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/* align execution to a cache line */
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j 1f
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.align 5
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1:
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/* all needed values are now in registers.
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* These last instructions should be in cache
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*/
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nop
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nop
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/* set hibernate mode */
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sw t1, 0(t0)
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nop
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/* enter hibernate mode */
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.set mips3
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wait
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nop
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.set mips2
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2: j 2b /* loop waiting for suspended */
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nop
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/*
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* jz_cpu_resume()
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*
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* entry point from bootloader into kernel during resume
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*/
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.align 5
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.globl jz_cpu_resume
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jz_cpu_resume:
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/* clear SCR.HGP */
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la t0, CPM_SCR
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lw t1, 0(t0)
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li t2, ~CPM_SCR_HGP
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and t1, t2
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sw t1, 0(t0)
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/* restore LPCR.LPM to IDLE mode */
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la t0, CPM_LPCR
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lw t1, 0(t0)
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li t2, ~CPM_LPCR_LPM_MASK
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and t1, t2
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ori t1, CPM_LPCR_LPM_IDLE
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sw t1, 0(t0)
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/* restore saved sp */
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la t0, suspend_save_sp
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lw sp, 0(t0)
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/* restore CP0 registers */
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move k0, sp
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lw $1, 0(k0)
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lw $2, 4(k0)
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lw $3, 8(k0)
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lw $4, 12(k0)
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lw $5, 16(k0)
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lw $6, 20(k0)
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lw $7, 24(k0)
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lw $8, 28(k0)
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lw $9, 32(k0)
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lw $10, 36(k0)
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lw $11, 40(k0)
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lw $12, 44(k0)
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lw $13, 48(k0)
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lw $14, 52(k0)
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lw $15, 56(k0)
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lw $16, 60(k0)
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lw $17, 64(k0)
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lw $18, 68(k0)
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lw $19, 72(k0)
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lw $20, 76(k0)
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lw $21, 80(k0)
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lw $22, 84(k0)
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lw $23, 88(k0)
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lw $24, 92(k0)
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lw $25, 96(k0)
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lw $29, 100(k0) /* saved sp */
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mtc0 $1, CP0_INDEX
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mtc0 $2, CP0_RANDOM
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mtc0 $3, CP0_ENTRYLO0
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mtc0 $4, CP0_ENTRYLO1
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mtc0 $5, CP0_CONTEXT
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mtc0 $6, CP0_PAGEMASK
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mtc0 $7, CP0_WIRED
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mtc0 $8, CP0_BADVADDR
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mtc0 $9, CP0_ENTRYHI
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mtc0 $10, CP0_STATUS
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/* mtc0 $11, $12, 1*/ /* IntCtl */
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mtc0 $12, CP0_CAUSE
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mtc0 $13, CP0_EPC
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/* mtc0 $14, $15, 1*/ /* EBase */
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mtc0 $15, CP0_CONFIG
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/* mtc0 $16, CP0_CONFIG, 7*/ /* Config 7 */
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mtc0 $17, CP0_LLADDR
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mtc0 $18, CP0_WATCHLO
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mtc0 $19, CP0_WATCHHI
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mtc0 $20, CP0_DEBUG
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mtc0 $21, CP0_DEPC
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mtc0 $22, CP0_ECC
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mtc0 $23, CP0_TAGLO
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mtc0 $24, CP0_ERROREPC
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mtc0 $25, CP0_DESAVE
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/* restore general registers */
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move k0, sp
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lw k1, 120(k0) /* hi */
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lw $0, 0(k0)
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lw $1, 4(k0)
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mthi k1
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lw k1, 124(k0) /* lo */
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lw $2, 8(k0)
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lw $3, 12(k0)
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mtlo k1
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lw $4, 16(k0)
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lw $5, 20(k0)
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lw $6, 24(k0)
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lw $7, 28(k0)
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lw $8, 32(k0)
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lw $9, 36(k0)
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lw $10, 40(k0)
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lw $11, 44(k0)
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lw $12, 48(k0)
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lw $13, 52(k0)
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lw $14, 56(k0)
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lw $15, 60(k0)
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lw $16, 64(k0)
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lw $17, 68(k0)
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lw $18, 72(k0)
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lw $19, 76(k0)
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lw $20, 80(k0)
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lw $21, 84(k0)
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lw $22, 88(k0)
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lw $23, 92(k0)
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lw $24, 96(k0)
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lw $25, 100(k0)
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lw $28, 104(k0)
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lw $29, 108(k0) /* saved sp */
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lw $30, 112(k0)
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lw $31, 116(k0) /* saved ra */
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/* return to caller */
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jr ra
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nop
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suspend_save_sp:
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.word 0 /* preserve sp here */
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.set reorder
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