mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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940b26969e
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@18700 3c298f89-4303-0410-b956-a3cf2f4a3e73
274 lines
8.4 KiB
C
274 lines
8.4 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This file contains the configuration parameters for the danube board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define USE_REFERENCE_BOARD
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//#define USE_EVALUATION_BOARD
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//#define DANUBE_BOOT_FROM_EBU
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#define DANUBE_USE_DDR_RAM
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#ifdef DANUBE_USE_DDR_RAM
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//#define DANUBE_DDR_RAM_111M
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//#define DANUBE_DDR_RAM_166M
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//#define PROMOSDDR400
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//#define DDR_SAMSUNG_166M
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#define DDR_PSC_166M
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//#define DANUBE_DDR_RAM_133M
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#define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */
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#endif
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#define CONFIG_LZMA 1 /* use LZMA for compression */
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#define CLK_OUT2_25MHZ
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#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
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#define CONFIG_IFX_MIPS 1 /* in an Infineon chip */
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#define CONFIG_DANUBE 1 /* on a danube Board */
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#define RAM_SIZE 0x2000000 /*32M ram*/
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#define CPU_CLOCK_RATE 235000000 /* 235 MHz clock for the MIPS core */
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#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#define CONFIG_BAUDRATE 115200
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#define DEBUG_PARSER 2
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 300, 9600, 19200, 38400, 57600, 115200 }
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#ifndef CFG_BOOTSTRAP_CODE
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#endif
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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/* by MarsLin 2005/05/10, to support different hardware configuations */
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//#define CONFIG_EXTRA_ENV_SETTINGS <configs/ifx_extra_env.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"ethaddr=11:22:33:44:55:66\0" \
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"serverip=192.168.45.100\0" \
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"ipaddr=192.168.45.108\0" \
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"ram_addr=0x80500000\0" \
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"kernel_addr=0xb0030000\0" \
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"flashargs=setenv bootargs rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} init=/etc/preinit\0" \
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"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
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"addmisc=setenv bootargs ${bootargs} console=ttyS1,115200 ethaddr=${ethaddr} ${mtdparts}\0" \
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"flash_flash=run flashargs addip addmisc;bootm ${kernel_addr}\0" \
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"flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \
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"net_flash=run load_kernel flashargs addip addmisc;bootm ${ram_addr}\0" \
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"net_nfs=run load_kernel nfsargs addip addmisc;bootm ${ram_addr}\0" \
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"load_kernel=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-uImage\0" \
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"update_uboot=tftp 0x80500000 u-boot.ifx;era 1:0-10; cp.b 0x80500000 0xb0000000 0x10000\0" \
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"update_openwrt=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-squashfs.image; era ${kernel_addr} +${filesize} 0; cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
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#define CONFIG_BOOTCOMMAND "run flash_flash"
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#define CONFIG_COMMANDS_YES (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_NET )
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#define CONFIG_COMMANDS_NO (CFG_CMD_NFS | \
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CFG_CMD_FPGA | \
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CFG_CMD_IMLS | \
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CFG_CMD_ITEST | \
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CFG_CMD_XING | \
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CFG_CMD_IMI | \
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CFG_CMD_BMP | \
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CFG_CMD_BOOTD | \
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CFG_CMD_CONSOLE | \
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CFG_CMD_LOADS | \
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CFG_CMD_LOADB )
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#define CONFIG_COMMANDS (CONFIG_COMMANDS_YES & ~CONFIG_COMMANDS_NO)
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#if 0
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CFG_CMD_DHCP
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CFG_CMD_ELF
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CFG_CMD_NAND
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#endif
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "DANUBE # " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args*/
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#define CFG_MALLOC_LEN 128*1024
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#define CFG_BOOTPARAMS_LEN 128*1024
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#define CFG_HZ (CPU_CLOCK_RATE / 2)
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#define CFG_LOAD_ADDR 0x80100000 /* default load address */
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#define CFG_MEMTEST_START 0x80100000
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#define CFG_MEMTEST_END 0x80400000
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT (135) /* max number of sectors on one chip */
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#define PHYS_FLASH_1 0xB0000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0xB4000000 /* Flash Bank #2 */
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#define BOOTSTRAP_TEXT_BASE 0xb0000000
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/* The following #defines are needed to get flash environment right */
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#define CFG_MONITOR_BASE UBOOT_RAM_TEXT_BASE /* board/danube/config.mk. = 0xA0800000 */
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#define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE /* board/danube/config.mk. = 0xA0800000 */
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#define CFG_MONITOR_LEN (256 << 10)
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#define CFG_INIT_SP_OFFSET 0x400000
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (20 * CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (20 * CFG_HZ) /* Timeout for Flash Write */
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#define CFG_ENV_IS_IN_FLASH 1
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//#define CFG_ENV_IS_NOWHERE 1
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//#define CFG_ENV_IS_IN_NVRAM 1
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/* Address and size of Primary Environment Sector */
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#define CFG_ENV_ADDR 0xB0020000
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#define CFG_ENV_SIZE 0x10000
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#define CONFIG_FLASH_16BIT
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_DANUBE_SWITCH
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#define CONFIG_NET_MULTI
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#define CONFIG_ENV_OVERWRITE
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#define EXCEPTION_BASE 0x200
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/**
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*\brief definition for nand
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*
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*/
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define NAND_ChipID_UNKNOWN 0x00
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#define SECTORSIZE 512
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
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#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
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#define NAND_DISABLE_CE(nand)
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#define NAND_ENABLE_CE(nand)
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#define NAND_WAIT_READY(nand)
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#define WRITE_NAND_COMMAND(d, adr)
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#define WRITE_NAND_ADDRESS(d, adr)
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#define WRITE_NAND(d, adr)
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#define READ_NAND(adr)
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/* the following are NOP's in our implementation */
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_SETCLE(nandptr)
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#define NAND_BASE_ADDRESS 0xB4000000
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#define NAND_WRITE(addr, val) *((u8*)(NAND_BASE_ADDRESS | (addr))) = val;while((*EBU_NAND_WAIT & 0x08) == 0);
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#define NAND_READ(addr, val) val = *((u8*)(NAND_BASE_ADDRESS | (addr)))
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#define NAND_CE_SET
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#define NAND_CE_CLEAR
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#define NAND_READY ( ((*EBU_NAND_WAIT)&0x07) == 7)
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#define NAND_READY_CLEAR *EBU_NAND_WAIT = 0;
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#define WRITE_CMD 0x18
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#define WRITE_ADDR 0x14
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#define WRITE_LADDR 0x10
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#define WRITE_DATA 0x10
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#define READ_DATA 0x10
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#define READ_LDATA 0x00
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#define ACCESS_WAIT
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#define IFX_ATC_NAND 0xc176
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#define IFX_BTC_NAND 0xc166
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#define ST_512WB2_NAND 0x2076
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#define NAND_OK 0x00000000 /* Bootstrap succesful, start address in BOOT_RVEC */
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#define NAND_ERR 0x80000000
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#define NAND_ACC_TIMEOUT (NAND_ERR | 0x00000001)
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#define NAND_ACC_ERR (NAND_ERR | 0x00000002)
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/*****************************************************************************
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* DANUBE
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*****************************************************************************/
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/* lock cache for C program stack */
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/* points to ROM */
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/* stack size is 16K */
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#define LOCK_DCACHE_ADDR 0x9FC00000
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#define LOCK_DCACHE_SIZE 0x1000
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/*
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* Memory layout
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*/
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#define CFG_SDRAM_BASE 0x80000000
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#define CFG_SDRAM_BASE_UNCACHE 0xA0000000
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#define CFG_CACHE_LOCK_SIZE LOCK_DCACHE_SIZE
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/*
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* Cache settings
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*/
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#define CFG_CACHE_SIZE 16384
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#define CFG_CACHE_LINES 32
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#define CFG_CACHE_WAYS 4
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#define CFG_CACHE_SETS 128
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#define CFG_ICACHE_SIZE CFG_CACHE_SIZE
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#define CFG_DCACHE_SIZE CFG_CACHE_SIZE
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#define CFG_CACHELINE_SIZE CFG_CACHE_LINES
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#endif /* __CONFIG_H */
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