mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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dc3d3f1c49
it's basically also provided by ingenic and nativly based on 2.6.27, adjusted to fit into the OpenWrt-environment
273 lines
7.0 KiB
C
273 lines
7.0 KiB
C
/*
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* linux/include/asm-mips/mach-jz4730/dma.h
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*
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* JZ4730 DMA definition.
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*
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* Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
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*
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* Author: <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_JZ4730_DMA_H__
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#define __ASM_JZ4730_DMA_H__
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#include <linux/interrupt.h>
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#include <asm/io.h> /* need byte IO */
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#include <linux/spinlock.h> /* And spinlocks */
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#include <linux/delay.h>
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#include <asm/system.h>
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#define DMA_UNIT_32 32
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#define DMA_UNIT_16 16
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/* block-mode EOP: high DREQ: high DACK: low*/
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#define DMA_BLOCK_CONF \
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DMAC_DCCSR_TM | \
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DMAC_DCCSR_DS_8b | DMAC_DCCSR_RDIL_IGN | \
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DMAC_DCCSR_ERDM_HLEVEL | DMAC_DCCSR_EACKS
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/* single-mode EOP: high DREQ: high DACK: low */
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#define DMA_SINGLE_CONF \
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DMAC_DCCSR_DS_8b | DMAC_DCCSR_RDIL_IGN | \
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DMAC_DCCSR_ERDM_HLEVEL | DMAC_DCCSR_EACKS
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#define DMA_8bit_RX_CONF \
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DMAC_DCCSR_DAM | \
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DMAC_DCCSR_SWDH_8 | DMAC_DCCSR_DWDH_32 | \
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DMAC_DCCSR_DS_8b | DMAC_DCCSR_RDIL_IGN
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#define DMA_8bit_TX_CONF \
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DMAC_DCCSR_SAM | \
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DMAC_DCCSR_SWDH_32 | DMAC_DCCSR_DWDH_8 | \
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DMAC_DCCSR_DS_8b | DMAC_DCCSR_RDIL_IGN
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#define DMA_16bit_RX_CONF \
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DMAC_DCCSR_DAM | \
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DMAC_DCCSR_SWDH_16 | DMAC_DCCSR_DWDH_32 | \
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DMAC_DCCSR_DS_16b | DMAC_DCCSR_RDIL_IGN
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#define DMA_16bit_TX_CONF \
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DMAC_DCCSR_SAM | \
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DMAC_DCCSR_SWDH_32 | DMAC_DCCSR_DWDH_16 | \
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DMAC_DCCSR_DS_16b | DMAC_DCCSR_RDIL_IGN
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#define DMA_32bit_RX_CONF \
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DMAC_DCCSR_DAM | \
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DMAC_DCCSR_SWDH_32 | DMAC_DCCSR_DWDH_32 | \
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DMAC_DCCSR_DS_32b | DMAC_DCCSR_RDIL_IGN
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#define DMA_32bit_TX_CONF \
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DMAC_DCCSR_SAM | \
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DMAC_DCCSR_SWDH_32 | DMAC_DCCSR_DWDH_32 | \
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DMAC_DCCSR_DS_32b | DMAC_DCCSR_RDIL_IGN
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#define DMA_16BYTE_RX_CONF \
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DMAC_DCCSR_DAM | \
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DMAC_DCCSR_SWDH_8 | DMAC_DCCSR_DWDH_32 | \
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DMAC_DCCSR_DS_16B | DMAC_DCCSR_RDIL_IGN
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#define DMA_16BYTE_TX_CONF \
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DMAC_DCCSR_SAM | \
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DMAC_DCCSR_SWDH_32 | DMAC_DCCSR_DWDH_8 | \
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DMAC_DCCSR_DS_16B | DMAC_DCCSR_RDIL_IGN
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#define DMA_AIC_32_16BYTE_TX_CMD \
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DMAC_DCCSR_SAM | \
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DMAC_DCCSR_SWDH_32 | DMAC_DCCSR_DWDH_32 | \
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DMAC_DCCSR_DS_16B | DMAC_DCCSR_RDIL_IGN
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#define DMA_AIC_32_16BYTE_RX_CMD \
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DMAC_DCCSR_DAM | \
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DMAC_DCCSR_SWDH_32 | DMAC_DCCSR_DWDH_32 | \
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DMAC_DCCSR_DS_16B | DMAC_DCCSR_RDIL_IGN
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#define DMA_AIC_16BIT_TX_CMD \
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DMAC_DCCSR_SAM | \
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DMAC_DCCSR_SWDH_16 | DMAC_DCCSR_DWDH_16 | \
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DMAC_DCCSR_DS_16b | DMAC_DCCSR_RDIL_IGN
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#define DMA_AIC_16BIT_RX_CMD \
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DMAC_DCCSR_DAM | \
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DMAC_DCCSR_SWDH_16 | DMAC_DCCSR_DWDH_16 | \
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DMAC_DCCSR_DS_16b | DMAC_DCCSR_RDIL_IGN
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#define DMA_AIC_16BYTE_RX_CMD \
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DMAC_DCCSR_DAM | \
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DMAC_DCCSR_SWDH_16 | DMAC_DCCSR_DWDH_16 | \
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DMAC_DCCSR_DS_16B | DMAC_DCCSR_RDIL_IGN
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#define DMA_AIC_16BYTE_TX_CMD \
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DMAC_DCCSR_SAM | \
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DMAC_DCCSR_SWDH_16 | DMAC_DCCSR_DWDH_16 | \
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DMAC_DCCSR_DS_16B | DMAC_DCCSR_RDIL_IGN
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/* DMA Device ID's follow */
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enum {
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DMA_ID_UART0_TX = 0,
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DMA_ID_UART0_RX,
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DMA_ID_UART1_TX,
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DMA_ID_UART1_RX,
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DMA_ID_UART2_TX,
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DMA_ID_UART2_RX,
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DMA_ID_UART3_TX,
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DMA_ID_UART3_RX,
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DMA_ID_SSI_TX,
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DMA_ID_SSI_RX,
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DMA_ID_MSC_TX,
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DMA_ID_MSC_RX,
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DMA_ID_AIC_TX,
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DMA_ID_AIC_RX,
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DMA_ID_BLOCK, /* DREQ */
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DMA_ID_SINGLE, /* DREQ */
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DMA_ID_PCMCIA0_TX,
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DMA_ID_PCMCIA0_RX,
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DMA_ID_PCMCIA1_TX,
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DMA_ID_PCMCIA2_RX,
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DMA_ID_AUTO,
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DMA_ID_RAW_SET,
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NUM_DMA_DEV
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};
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/* dummy DCCSR bit, i386 style DMA macros compitable */
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#define DMA_MODE_READ 0 /* I/O to memory, no autoinit,
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* increment, single mode */
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#define DMA_MODE_WRITE 1 /* memory to I/O, no autoinit,
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* increment, single mode */
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#define DMA_MODE_CASCADE 2 /* pass thru DREQ->HRQ,
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* DACK<-HLDA only */
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#define DMA_AUTOINIT 3
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#define DMA_MODE_MASK 3
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struct jz_dma_chan {
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int dev_id; /* this channel is allocated if >=0,
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* free otherwise */
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unsigned int io;
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const char *dev_str;
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int irq;
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void *irq_dev;
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unsigned int fifo_addr;
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unsigned int mode;
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unsigned int source;
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};
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extern struct jz_dma_chan jz_dma_table[];
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extern int jz_request_dma(int dev_id,
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const char *dev_str,
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irqreturn_t (*irqhandler)(int, void *),
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unsigned long irqflags,
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void *irq_dev_id);
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extern void jz_free_dma(unsigned int dmanr);
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extern int jz_dma_read_proc(char *buf, char **start, off_t fpos,
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int length, int *eof, void *data);
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extern void dump_jz_dma_channel(unsigned int dmanr);
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extern void enable_dma(unsigned int dmanr);
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extern void disable_dma(unsigned int dmanr);
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extern void set_dma_addr(unsigned int dmanr, unsigned int a);
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extern void set_dma_count(unsigned int dmanr, unsigned int count);
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extern void set_dma_mode(unsigned int dmanr, unsigned int mode);
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extern void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
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extern void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
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extern int get_dma_residue(unsigned int dmanr);
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extern spinlock_t dma_spin_lock;
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static __inline__ unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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static __inline__ void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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/* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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*/
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#define clear_dma_ff(channel)
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static __inline__ struct jz_dma_chan *get_dma_chan(unsigned int dmanr)
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{
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if (dmanr > NUM_DMA
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|| jz_dma_table[dmanr].dev_id < 0)
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return NULL;
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return &jz_dma_table[dmanr];
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}
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static __inline__ int dma_halted(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 1;
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return __dmac_channel_transmit_halt_detected(dmanr) ? 1 : 0;
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}
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static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 0;
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return chan->mode;
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}
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static __inline__ void clear_dma_done(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TC | DMAC_DCCSR_AR);
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}
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static __inline__ void clear_dma_halt(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT);
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REG_DMAC_DMACR &= ~(DMAC_DMACR_HTR);
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}
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static __inline__ void clear_dma_flag(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TC | DMAC_DCCSR_AR);
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REG_DMAC_DMACR &= ~(DMAC_DMACR_HTR | DMAC_DMACR_AER);
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}
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static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
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{
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}
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static __inline__ unsigned int get_dma_done_status(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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unsigned long dccsr;
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if (!chan)
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return 0;
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dccsr = REG_DMAC_DCCSR(chan->io);
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return dccsr & (DMAC_DCCSR_HLT | DMAC_DCCSR_TC | DMAC_DCCSR_AR);
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}
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static __inline__ int get_dma_done_irq(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return -1;
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return chan->irq;
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}
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#endif /* __ASM_JZ4730_DMA_H__ */
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