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git://projects.qi-hardware.com/openwrt-xburst.git
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7edabb16a1
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34137 3c298f89-4303-0410-b956-a3cf2f4a3e73
111 lines
3.1 KiB
Diff
111 lines
3.1 KiB
Diff
From e49546bf3f255f028d0877ceeb7ed6466fe37d8a Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Mon, 21 Nov 2011 00:53:26 +0100
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Subject: [PATCH 56/84] MIPS: BCM63XX: enable pcie for BCM6362
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 3 +-
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arch/mips/pci/pci-bcm63xx.c | 57 +++++++++++++++------
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2 files changed, 44 insertions(+), 16 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1231,7 +1231,8 @@
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/*************************************************************************
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* _REG relative to RSET_MISC
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*************************************************************************/
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-#define MISC_SERDES_CTRL_REG 0x0
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+#define MISC_SERDES_CTRL_6328_REG 0x0
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+#define MISC_SERDES_CTRL_6362_REG 0x4
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#define SERDES_PCIE_EN (1 << 0)
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#define SERDES_PCIE_EXD_EN (1 << 15)
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--- a/arch/mips/pci/pci-bcm63xx.c
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -118,35 +118,61 @@ void __iomem *pci_iospace_start;
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static void __init bcm63xx_reset_pcie(void)
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{
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u32 val;
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+ u32 reg;
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+ u32 mask;
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/* enable clock */
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+
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+ if (BCMCPU_IS_6328())
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+ mask = CKCTL_6328_PCIE_EN;
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+ else
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+ mask = CKCTL_6362_PCIE_EN;
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+
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val = bcm_perf_readl(PERF_CKCTL_REG);
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- val |= CKCTL_6328_PCIE_EN;
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+ val |= mask;
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bcm_perf_writel(val, PERF_CKCTL_REG);
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/* enable SERDES */
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- val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
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+
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+ if (BCMCPU_IS_6328())
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+ reg = MISC_SERDES_CTRL_6328_REG;
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+ else
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+ reg = MISC_SERDES_CTRL_6362_REG;
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+
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+ val = bcm_misc_readl(reg);
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val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
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- bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
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+ bcm_misc_writel(val, reg);
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/* reset the PCIe core */
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- val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
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+ if (BCMCPU_IS_6328()) {
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+ reg = PERF_SOFTRESET_6328_REG;
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+ mask = SOFTRESET_6328_PCIE_MASK | SOFTRESET_6328_PCIE_CORE_MASK
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+ | SOFTRESET_6328_PCIE_HARD_MASK;
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+ } else {
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+ reg = PERF_SOFTRESET_6362_REG;
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+ mask = SOFTRESET_6362_PCIE_MASK | SOFTRESET_6362_PCIE_CORE_MASK;
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+ }
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+ val = bcm_perf_readl(reg);
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+ val &= ~mask;
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+
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+ if (BCMCPU_IS_6328())
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+ val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
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+ else
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+ val &= ~SOFTRESET_6362_PCIE_EXT_MASK;
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- val &= ~SOFTRESET_6328_PCIE_MASK;
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- val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
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- val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
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- val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ bcm_perf_writel(val, reg);
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mdelay(10);
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- val |= SOFTRESET_6328_PCIE_MASK;
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- val |= SOFTRESET_6328_PCIE_CORE_MASK;
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- val |= SOFTRESET_6328_PCIE_HARD_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ val |= mask;
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+ bcm_perf_writel(val, reg);
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mdelay(10);
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- val |= SOFTRESET_6328_PCIE_EXT_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ if (BCMCPU_IS_6328())
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+ val |= SOFTRESET_6328_PCIE_EXT_MASK;
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+ else
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+ val |= SOFTRESET_6362_PCIE_EXT_MASK;
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+
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+ bcm_perf_writel(val, reg);
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mdelay(200);
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}
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@@ -332,6 +358,7 @@ static int __init bcm63xx_pci_init(void)
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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+ case BCM6362_CPU_ID:
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return bcm63xx_register_pcie();
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case BCM6348_CPU_ID:
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case BCM6358_CPU_ID:
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