mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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7fa43ebaa8
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14655 3c298f89-4303-0410-b956-a3cf2f4a3e73
991 lines
22 KiB
C
991 lines
22 KiB
C
/*
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* Atheros AR71xx built-in ethernet mac driver
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Based on Atheros' AG7100 driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include "ag71xx.h"
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#define AG71XX_DEFAULT_MSG_ENABLE \
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( NETIF_MSG_DRV \
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| NETIF_MSG_PROBE \
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| NETIF_MSG_LINK \
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| NETIF_MSG_TIMER \
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| NETIF_MSG_IFDOWN \
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| NETIF_MSG_IFUP \
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| NETIF_MSG_RX_ERR \
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| NETIF_MSG_TX_ERR )
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static int ag71xx_debug = -1;
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module_param(ag71xx_debug, int, 0);
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MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
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static void ag71xx_dump_dma_regs(struct ag71xx *ag)
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{
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DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
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ag71xx_rr(ag, AG71XX_REG_TX_DESC),
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ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
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DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
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ag71xx_rr(ag, AG71XX_REG_RX_DESC),
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ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
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}
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static void ag71xx_dump_regs(struct ag71xx *ag)
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{
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DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
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ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
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ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
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ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
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ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
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DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
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ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
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ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
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DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
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DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
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}
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static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
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{
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DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
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ag->dev->name, label, intr,
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(intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
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(intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
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(intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
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(intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
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(intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
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(intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
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}
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static void ag71xx_ring_free(struct ag71xx_ring *ring)
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{
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kfree(ring->buf);
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if (ring->descs)
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dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
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ring->descs, ring->descs_dma);
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}
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static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
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{
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int err;
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ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
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&ring->descs_dma,
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GFP_ATOMIC);
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if (!ring->descs) {
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err = -ENOMEM;
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goto err;
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}
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ring->size = size;
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ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
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if (!ring->buf) {
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err = -ENOMEM;
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goto err;
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}
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return 0;
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err:
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return err;
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}
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static void ag71xx_ring_tx_clean(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->tx_ring;
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struct net_device *dev = ag->dev;
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while (ring->curr != ring->dirty) {
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u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
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if (!ag71xx_desc_empty(&ring->descs[i])) {
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ring->descs[i].ctrl = 0;
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dev->stats.tx_errors++;
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}
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if (ring->buf[i].skb)
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dev_kfree_skb_any(ring->buf[i].skb);
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ring->buf[i].skb = NULL;
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ring->dirty++;
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}
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/* flush descriptors */
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wmb();
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}
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static void ag71xx_ring_tx_init(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->tx_ring;
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int i;
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for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
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ring->descs[i].next = (u32) (ring->descs_dma +
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sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
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ring->descs[i].ctrl = DESC_EMPTY;
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ring->buf[i].skb = NULL;
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}
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/* flush descriptors */
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wmb();
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ring->curr = 0;
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ring->dirty = 0;
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}
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static void ag71xx_ring_rx_clean(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->rx_ring;
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int i;
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if (!ring->buf)
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return;
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for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
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if (ring->buf[i].skb)
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kfree_skb(ring->buf[i].skb);
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}
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static int ag71xx_ring_rx_init(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->rx_ring;
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unsigned int i;
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int ret;
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ret = 0;
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for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
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ring->descs[i].next = (u32) (ring->descs_dma +
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sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
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for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
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struct sk_buff *skb;
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skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
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if (!skb) {
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ret = -ENOMEM;
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break;
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}
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dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
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DMA_FROM_DEVICE);
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skb->dev = ag->dev;
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skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
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ring->buf[i].skb = skb;
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ring->descs[i].data = virt_to_phys(skb->data);
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ring->descs[i].ctrl = DESC_EMPTY;
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}
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/* flush descriptors */
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wmb();
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ring->curr = 0;
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ring->dirty = 0;
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return ret;
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}
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static int ag71xx_ring_rx_refill(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->rx_ring;
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unsigned int count;
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count = 0;
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for (; ring->curr - ring->dirty > 0; ring->dirty++) {
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unsigned int i;
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i = ring->dirty % AG71XX_RX_RING_SIZE;
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if (ring->buf[i].skb == NULL) {
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struct sk_buff *skb;
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skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
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if (skb == NULL)
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break;
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dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
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DMA_FROM_DEVICE);
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skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
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skb->dev = ag->dev;
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ring->buf[i].skb = skb;
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ring->descs[i].data = virt_to_phys(skb->data);
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}
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ring->descs[i].ctrl = DESC_EMPTY;
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count++;
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}
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/* flush descriptors */
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wmb();
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DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
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return count;
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}
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static int ag71xx_rings_init(struct ag71xx *ag)
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{
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int ret;
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ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
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if (ret)
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return ret;
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ag71xx_ring_tx_init(ag);
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ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
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if (ret)
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return ret;
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ret = ag71xx_ring_rx_init(ag);
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return ret;
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}
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static void ag71xx_rings_cleanup(struct ag71xx *ag)
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{
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ag71xx_ring_rx_clean(ag);
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ag71xx_ring_free(&ag->rx_ring);
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ag71xx_ring_tx_clean(ag);
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ag71xx_ring_free(&ag->tx_ring);
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}
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static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
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{
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u32 t;
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t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
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| (((u32) mac[2]) << 8) | ((u32) mac[3]);
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ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
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t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
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ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
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}
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static void ag71xx_dma_reset(struct ag71xx *ag)
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{
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int i;
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ag71xx_dump_dma_regs(ag);
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/* stop RX and TX */
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
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ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
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/* clear descriptor addresses */
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ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
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ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
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/* clear pending RX/TX interrupts */
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for (i = 0; i < 256; i++) {
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
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}
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/* clear pending errors */
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
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if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
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printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
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ag->dev->name);
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if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
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printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
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ag->dev->name);
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ag71xx_dump_dma_regs(ag);
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}
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#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
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MAC_CFG1_SRX | MAC_CFG1_STX)
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#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
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#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
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FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
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FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
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FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
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FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
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FIFO_CFG4_VT)
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#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
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FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
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FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
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FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
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FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
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FIFO_CFG5_17 | FIFO_CFG5_SF)
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static void ag71xx_hw_init(struct ag71xx *ag)
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{
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
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udelay(20);
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ar71xx_device_stop(pdata->reset_bit);
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mdelay(100);
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ar71xx_device_start(pdata->reset_bit);
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mdelay(100);
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/* setup MAC configuration registers */
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
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ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
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MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
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/* setup max frame length */
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ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
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/* setup MII interface type */
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ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
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/* setup FIFO configuration registers */
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
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ag71xx_dma_reset(ag);
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}
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static void ag71xx_hw_start(struct ag71xx *ag)
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{
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/* start RX engine */
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
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/* enable interrupts */
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ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
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}
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static void ag71xx_hw_stop(struct ag71xx *ag)
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{
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/* disable all interrupts */
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ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
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ag71xx_dma_reset(ag);
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}
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static int ag71xx_open(struct net_device *dev)
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{
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struct ag71xx *ag = netdev_priv(dev);
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int ret;
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ret = ag71xx_rings_init(ag);
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if (ret)
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goto err;
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napi_enable(&ag->napi);
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netif_carrier_off(dev);
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ag71xx_phy_start(ag);
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ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
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ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
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ag71xx_hw_set_macaddr(ag, dev->dev_addr);
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ag71xx_hw_start(ag);
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netif_start_queue(dev);
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return 0;
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err:
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ag71xx_rings_cleanup(ag);
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return ret;
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}
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static int ag71xx_stop(struct net_device *dev)
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{
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struct ag71xx *ag = netdev_priv(dev);
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unsigned long flags;
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spin_lock_irqsave(&ag->lock, flags);
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netif_stop_queue(dev);
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ag71xx_hw_stop(ag);
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netif_carrier_off(dev);
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ag71xx_phy_stop(ag);
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napi_disable(&ag->napi);
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del_timer_sync(&ag->oom_timer);
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spin_unlock_irqrestore(&ag->lock, flags);
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ag71xx_rings_cleanup(ag);
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return 0;
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}
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static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct ag71xx *ag = netdev_priv(dev);
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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struct ag71xx_ring *ring = &ag->tx_ring;
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struct ag71xx_desc *desc;
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unsigned long flags;
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int i;
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i = ring->curr % AG71XX_TX_RING_SIZE;
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desc = &ring->descs[i];
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spin_lock_irqsave(&ag->lock, flags);
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pdata->ddr_flush();
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spin_unlock_irqrestore(&ag->lock, flags);
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if (!ag71xx_desc_empty(desc))
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goto err_drop;
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ag71xx_add_ar8216_header(ag, skb);
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if (skb->len <= 0) {
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DBG("%s: packet len is too small\n", ag->dev->name);
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goto err_drop;
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|
}
|
|
|
|
dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
|
|
|
|
ring->buf[i].skb = skb;
|
|
|
|
/* setup descriptor fields */
|
|
desc->data = virt_to_phys(skb->data);
|
|
desc->ctrl = (skb->len & DESC_PKTLEN_M);
|
|
|
|
/* flush descriptor */
|
|
wmb();
|
|
|
|
ring->curr++;
|
|
if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
|
|
DBG("%s: tx queue full\n", ag->dev->name);
|
|
netif_stop_queue(dev);
|
|
}
|
|
|
|
DBG("%s: packet injected into TX queue\n", ag->dev->name);
|
|
|
|
/* enable TX engine */
|
|
ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
|
|
|
|
dev->trans_start = jiffies;
|
|
|
|
return 0;
|
|
|
|
err_drop:
|
|
dev->stats.tx_dropped++;
|
|
|
|
dev_kfree_skb(skb);
|
|
return 0;
|
|
}
|
|
|
|
static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|
{
|
|
struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
int ret;
|
|
|
|
switch (cmd) {
|
|
case SIOCETHTOOL:
|
|
if (ag->phy_dev == NULL)
|
|
break;
|
|
|
|
spin_lock_irq(&ag->lock);
|
|
ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
|
|
spin_unlock_irq(&ag->lock);
|
|
return ret;
|
|
|
|
case SIOCSIFHWADDR:
|
|
if (copy_from_user
|
|
(dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
|
|
return -EFAULT;
|
|
return 0;
|
|
|
|
case SIOCGIFHWADDR:
|
|
if (copy_to_user
|
|
(ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
|
|
return -EFAULT;
|
|
return 0;
|
|
|
|
case SIOCGMIIPHY:
|
|
case SIOCGMIIREG:
|
|
case SIOCSMIIREG:
|
|
if (ag->phy_dev == NULL)
|
|
break;
|
|
|
|
return phy_mii_ioctl(ag->phy_dev, data, cmd);
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
static void ag71xx_oom_timer_handler(unsigned long data)
|
|
{
|
|
struct net_device *dev = (struct net_device *) data;
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
|
|
netif_rx_schedule(dev, &ag->napi);
|
|
}
|
|
|
|
static void ag71xx_tx_timeout(struct net_device *dev)
|
|
{
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
|
|
if (netif_msg_tx_err(ag))
|
|
printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
|
|
|
|
schedule_work(&ag->restart_work);
|
|
}
|
|
|
|
static void ag71xx_restart_work_func(struct work_struct *work)
|
|
{
|
|
struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
|
|
|
|
ag71xx_stop(ag->dev);
|
|
ag71xx_open(ag->dev);
|
|
}
|
|
|
|
static void ag71xx_tx_packets(struct ag71xx *ag)
|
|
{
|
|
struct ag71xx_ring *ring = &ag->tx_ring;
|
|
unsigned int sent;
|
|
|
|
DBG("%s: processing TX ring\n", ag->dev->name);
|
|
|
|
sent = 0;
|
|
while (ring->dirty != ring->curr) {
|
|
unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
|
|
struct ag71xx_desc *desc = &ring->descs[i];
|
|
struct sk_buff *skb = ring->buf[i].skb;
|
|
|
|
if (!ag71xx_desc_empty(desc))
|
|
break;
|
|
|
|
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
|
|
|
|
ag->dev->stats.tx_bytes += skb->len;
|
|
ag->dev->stats.tx_packets++;
|
|
|
|
dev_kfree_skb_any(skb);
|
|
ring->buf[i].skb = NULL;
|
|
|
|
ring->dirty++;
|
|
sent++;
|
|
}
|
|
|
|
DBG("%s: %d packets sent out\n", ag->dev->name, sent);
|
|
|
|
if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
|
|
netif_wake_queue(ag->dev);
|
|
|
|
}
|
|
|
|
static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
|
|
{
|
|
struct net_device *dev = ag->dev;
|
|
struct ag71xx_ring *ring = &ag->rx_ring;
|
|
int done = 0;
|
|
|
|
DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
|
|
dev->name, limit, ring->curr, ring->dirty);
|
|
|
|
while (done < limit) {
|
|
unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
|
|
struct ag71xx_desc *desc = &ring->descs[i];
|
|
struct sk_buff *skb;
|
|
int pktlen;
|
|
|
|
if (ag71xx_desc_empty(desc))
|
|
break;
|
|
|
|
if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
|
|
ag71xx_assert(0);
|
|
break;
|
|
}
|
|
|
|
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
|
|
|
|
skb = ring->buf[i].skb;
|
|
pktlen = ag71xx_desc_pktlen(desc);
|
|
pktlen -= ETH_FCS_LEN;
|
|
|
|
skb_put(skb, pktlen);
|
|
|
|
skb->dev = dev;
|
|
skb->ip_summed = CHECKSUM_NONE;
|
|
|
|
dev->last_rx = jiffies;
|
|
dev->stats.rx_packets++;
|
|
dev->stats.rx_bytes += pktlen;
|
|
|
|
if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
|
|
dev->stats.rx_dropped++;
|
|
kfree_skb(skb);
|
|
} else {
|
|
skb->protocol = eth_type_trans(skb, dev);
|
|
netif_receive_skb(skb);
|
|
}
|
|
|
|
ring->buf[i].skb = NULL;
|
|
done++;
|
|
|
|
ring->curr++;
|
|
}
|
|
|
|
ag71xx_ring_rx_refill(ag);
|
|
|
|
DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
|
|
dev->name, ring->curr, ring->dirty, done);
|
|
|
|
return done;
|
|
}
|
|
|
|
static int ag71xx_poll(struct napi_struct *napi, int limit)
|
|
{
|
|
struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
|
|
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
|
|
struct net_device *dev = ag->dev;
|
|
struct ag71xx_ring *rx_ring;
|
|
unsigned long flags;
|
|
u32 status;
|
|
int done;
|
|
|
|
pdata->ddr_flush();
|
|
ag71xx_tx_packets(ag);
|
|
|
|
DBG("%s: processing RX ring\n", dev->name);
|
|
done = ag71xx_rx_packets(ag, limit);
|
|
|
|
rx_ring = &ag->rx_ring;
|
|
if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
|
|
goto oom;
|
|
|
|
status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
|
|
if (unlikely(status & RX_STATUS_OF)) {
|
|
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
|
|
dev->stats.rx_fifo_errors++;
|
|
|
|
/* restart RX */
|
|
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
|
|
}
|
|
|
|
if (done < limit) {
|
|
if (status & RX_STATUS_PR)
|
|
goto more;
|
|
|
|
status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
|
|
if (status & TX_STATUS_PS)
|
|
goto more;
|
|
|
|
DBG("%s: disable polling mode, done=%d, limit=%d\n",
|
|
dev->name, done, limit);
|
|
|
|
netif_rx_complete(dev, napi);
|
|
|
|
/* enable interrupts */
|
|
spin_lock_irqsave(&ag->lock, flags);
|
|
ag71xx_int_enable(ag, AG71XX_INT_POLL);
|
|
spin_unlock_irqrestore(&ag->lock, flags);
|
|
return done;
|
|
}
|
|
|
|
more:
|
|
DBG("%s: stay in polling mode, done=%d, limit=%d\n",
|
|
dev->name, done, limit);
|
|
return done;
|
|
|
|
oom:
|
|
if (netif_msg_rx_err(ag))
|
|
printk(KERN_DEBUG "%s: out of memory\n", dev->name);
|
|
|
|
mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
|
|
netif_rx_complete(dev, napi);
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct net_device *dev = dev_id;
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
u32 status;
|
|
|
|
status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
|
|
ag71xx_dump_intr(ag, "raw", status);
|
|
|
|
if (unlikely(!status))
|
|
return IRQ_NONE;
|
|
|
|
if (unlikely(status & AG71XX_INT_ERR)) {
|
|
if (status & AG71XX_INT_TX_BE) {
|
|
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
|
|
dev_err(&dev->dev, "TX BUS error\n");
|
|
}
|
|
if (status & AG71XX_INT_RX_BE) {
|
|
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
|
|
dev_err(&dev->dev, "RX BUS error\n");
|
|
}
|
|
}
|
|
|
|
if (likely(status & AG71XX_INT_POLL)) {
|
|
ag71xx_int_disable(ag, AG71XX_INT_POLL);
|
|
DBG("%s: enable polling mode\n", dev->name);
|
|
netif_rx_schedule(dev, &ag->napi);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void ag71xx_set_multicast_list(struct net_device *dev)
|
|
{
|
|
/* TODO */
|
|
}
|
|
|
|
static int __init ag71xx_probe(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev;
|
|
struct resource *res;
|
|
struct ag71xx *ag;
|
|
struct ag71xx_platform_data *pdata;
|
|
int err;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "no platform data specified\n");
|
|
err = -ENXIO;
|
|
goto err_out;
|
|
}
|
|
|
|
dev = alloc_etherdev(sizeof(*ag));
|
|
if (!dev) {
|
|
dev_err(&pdev->dev, "alloc_etherdev failed\n");
|
|
err = -ENOMEM;
|
|
goto err_out;
|
|
}
|
|
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
ag = netdev_priv(dev);
|
|
ag->pdev = pdev;
|
|
ag->dev = dev;
|
|
ag->mii_bus = ag71xx_mdio_bus->mii_bus;
|
|
ag->msg_enable = netif_msg_init(ag71xx_debug,
|
|
AG71XX_DEFAULT_MSG_ENABLE);
|
|
spin_lock_init(&ag->lock);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "no mac_base resource found\n");
|
|
err = -ENXIO;
|
|
goto err_out;
|
|
}
|
|
|
|
ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
|
|
if (!ag->mac_base) {
|
|
dev_err(&pdev->dev, "unable to ioremap mac_base\n");
|
|
err = -ENOMEM;
|
|
goto err_free_dev;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "no mac_base2 resource found\n");
|
|
err = -ENXIO;
|
|
goto err_unmap_base1;
|
|
}
|
|
|
|
ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
|
|
if (!ag->mac_base) {
|
|
dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
|
|
err = -ENOMEM;
|
|
goto err_unmap_base1;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "no mii_ctrl resource found\n");
|
|
err = -ENXIO;
|
|
goto err_unmap_base2;
|
|
}
|
|
|
|
ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
|
|
if (!ag->mii_ctrl) {
|
|
dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
|
|
err = -ENOMEM;
|
|
goto err_unmap_base2;
|
|
}
|
|
|
|
dev->irq = platform_get_irq(pdev, 0);
|
|
err = request_irq(dev->irq, ag71xx_interrupt,
|
|
IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
|
|
dev->name, dev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
|
|
goto err_unmap_mii_ctrl;
|
|
}
|
|
|
|
dev->base_addr = (unsigned long)ag->mac_base;
|
|
dev->open = ag71xx_open;
|
|
dev->stop = ag71xx_stop;
|
|
dev->hard_start_xmit = ag71xx_hard_start_xmit;
|
|
dev->set_multicast_list = ag71xx_set_multicast_list;
|
|
dev->do_ioctl = ag71xx_do_ioctl;
|
|
dev->ethtool_ops = &ag71xx_ethtool_ops;
|
|
|
|
dev->tx_timeout = ag71xx_tx_timeout;
|
|
INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
|
|
|
|
init_timer(&ag->oom_timer);
|
|
ag->oom_timer.data = (unsigned long) dev;
|
|
ag->oom_timer.function = ag71xx_oom_timer_handler;
|
|
|
|
memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
|
|
|
|
netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
|
|
|
|
err = register_netdev(dev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "unable to register net device\n");
|
|
goto err_free_irq;
|
|
}
|
|
|
|
printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
|
|
dev->name, dev->base_addr, dev->irq);
|
|
|
|
ag71xx_dump_regs(ag);
|
|
|
|
ag71xx_hw_init(ag);
|
|
|
|
ag71xx_dump_regs(ag);
|
|
|
|
/* Reset the mdio bus explicitly */
|
|
if (ag->mii_bus) {
|
|
mutex_lock(&ag->mii_bus->mdio_lock);
|
|
ag->mii_bus->reset(ag->mii_bus);
|
|
mutex_unlock(&ag->mii_bus->mdio_lock);
|
|
}
|
|
|
|
err = ag71xx_phy_connect(ag);
|
|
if (err)
|
|
goto err_unregister_netdev;
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
return 0;
|
|
|
|
err_unregister_netdev:
|
|
unregister_netdev(dev);
|
|
err_free_irq:
|
|
free_irq(dev->irq, dev);
|
|
err_unmap_mii_ctrl:
|
|
iounmap(ag->mii_ctrl);
|
|
err_unmap_base2:
|
|
iounmap(ag->mac_base2);
|
|
err_unmap_base1:
|
|
iounmap(ag->mac_base);
|
|
err_free_dev:
|
|
kfree(dev);
|
|
err_out:
|
|
platform_set_drvdata(pdev, NULL);
|
|
return err;
|
|
}
|
|
|
|
static int __exit ag71xx_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
|
|
|
if (dev) {
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
|
|
ag71xx_phy_disconnect(ag);
|
|
unregister_netdev(dev);
|
|
free_irq(dev->irq, dev);
|
|
iounmap(ag->mii_ctrl);
|
|
iounmap(ag->mac_base2);
|
|
iounmap(ag->mac_base);
|
|
kfree(dev);
|
|
platform_set_drvdata(pdev, NULL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ag71xx_driver = {
|
|
.probe = ag71xx_probe,
|
|
.remove = __exit_p(ag71xx_remove),
|
|
.driver = {
|
|
.name = AG71XX_DRV_NAME,
|
|
}
|
|
};
|
|
|
|
static int __init ag71xx_module_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = ag71xx_mdio_driver_init();
|
|
if (ret)
|
|
goto err_out;
|
|
|
|
ret = platform_driver_register(&ag71xx_driver);
|
|
if (ret)
|
|
goto err_mdio_exit;
|
|
|
|
return 0;
|
|
|
|
err_mdio_exit:
|
|
ag71xx_mdio_driver_exit();
|
|
err_out:
|
|
return ret;
|
|
}
|
|
|
|
static void __exit ag71xx_module_exit(void)
|
|
{
|
|
platform_driver_unregister(&ag71xx_driver);
|
|
ag71xx_mdio_driver_exit();
|
|
}
|
|
|
|
module_init(ag71xx_module_init);
|
|
module_exit(ag71xx_module_exit);
|
|
|
|
MODULE_VERSION(AG71XX_DRV_VERSION);
|
|
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
|
|
MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
|