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0814097081
* fixes spi flash for ar9 * adds limited support for netgear dgn3500 (enough for others to start working with) git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27137 3c298f89-4303-0410-b956-a3cf2f4a3e73
74 lines
2.2 KiB
Diff
74 lines
2.2 KiB
Diff
From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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Date: Thu, 3 Mar 2011 20:42:26 +0000 (+0100)
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Subject: MIPS: lantiq: Add device register helper for SPI controller and devices
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X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=b35b07062b718ece9b9cb7b23b12d83a087eafb0;hp=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90
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MIPS: lantiq: Add device register helper for SPI controller and devices
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Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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---
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--- a/arch/mips/lantiq/xway/devices.c
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+++ b/arch/mips/lantiq/xway/devices.c
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@@ -21,6 +21,7 @@
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/leds.h>
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+#include <linux/spi/spi.h>
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#include <asm/bootinfo.h>
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#include <asm/irq.h>
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@@ -119,3 +120,41 @@
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platform_device_register(<q_etop);
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}
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}
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+
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+static struct resource ltq_spi_resources[] = {
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+ {
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+ .start = LTQ_SSC_BASE_ADDR,
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+ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ IRQ_RES(spi_tx, LTQ_SSC_TIR),
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+ IRQ_RES(spi_rx, LTQ_SSC_RIR),
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+ IRQ_RES(spi_err, LTQ_SSC_EIR),
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+};
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+
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+static struct resource ltq_spi_resources_ar9[] = {
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+ {
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+ .start = LTQ_SSC_BASE_ADDR,
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+ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9),
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+ IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9),
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+ IRQ_RES(spi_err, LTQ_SSC_EIR),
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+};
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+
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+static struct platform_device ltq_spi = {
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+ .name = "ltq-spi",
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+ .resource = ltq_spi_resources,
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+ .num_resources = ARRAY_SIZE(ltq_spi_resources),
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+};
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+
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+void __init ltq_register_spi(struct ltq_spi_platform_data *pdata,
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+ struct spi_board_info const *info, unsigned n)
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+{
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+ if(ltq_is_ar9())
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+ ltq_spi.resource = ltq_spi_resources_ar9;
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+ spi_register_board_info(info, n);
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+ ltq_spi.dev.platform_data = pdata;
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+ platform_device_register(<q_spi);
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+}
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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@@ -27,6 +27,8 @@
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#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
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#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
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+#define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14)
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+#define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15)
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#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
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#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
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