mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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f46a1cc756
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17201 3c298f89-4303-0410-b956-a3cf2f4a3e73
187 lines
5.0 KiB
C
187 lines
5.0 KiB
C
/*
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* Copyright (C) 2009 Christian Daniel <cd@maintech.de>
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* TRX flash partition table.
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* Based on ar7 map by Felix Fietkau <nbd@openwrt.org>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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struct cybertan_header {
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char magic[4];
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u8 res1[4];
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char fw_date[3];
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char fw_ver[3];
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char id[4];
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char hw_ver;
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char unused;
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u8 flags[2];
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u8 res2[10];
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};
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#define TRX_PARTS 6
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#define TRX_MAGIC 0x30524448
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#define TRX_MAX_OFFSET 3
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struct trx_header {
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uint32_t magic; /* "HDR0" */
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uint32_t len; /* Length of file including header */
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uint32_t crc32; /* 32-bit CRC from flag_version to end of file */
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uint32_t flag_version; /* 0:15 flags, 16:31 version */
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uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
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};
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#define IH_MAGIC 0x27051956 /* Image Magic Number */
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#define IH_NMLEN 32 /* Image Name Length */
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struct uimage_header {
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uint32_t ih_magic; /* Image Header Magic Number */
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uint32_t ih_hcrc; /* Image Header CRC Checksum */
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uint32_t ih_time; /* Image Creation Timestamp */
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uint32_t ih_size; /* Image Data Size */
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uint32_t ih_load; /* Data» Load Address */
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uint32_t ih_ep; /* Entry Point Address */
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uint32_t ih_dcrc; /* Image Data CRC Checksum */
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uint8_t ih_os; /* Operating System */
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uint8_t ih_arch; /* CPU architecture */
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uint8_t ih_type; /* Image Type */
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uint8_t ih_comp; /* Compression Type */
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uint8_t ih_name[IH_NMLEN]; /* Image Name */
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};
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struct wrt160nl_header {
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struct cybertan_header cybertan;
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struct trx_header trx;
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struct uimage_header uimage;
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} __attribute__ ((packed));
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static struct mtd_partition trx_parts[TRX_PARTS];
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static int wrt160nl_parse_partitions(struct mtd_info *master,
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struct mtd_partition **pparts,
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unsigned long origin)
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{
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struct wrt160nl_header *header;
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struct trx_header *theader;
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struct uimage_header *uheader;
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size_t retlen;
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unsigned int kernel_len;
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int ret;
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header = vmalloc(sizeof(*header));
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if (!header) {
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return -ENOMEM;
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goto out;
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}
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ret = master->read(master, 4 * master->erasesize, sizeof(*header),
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&retlen, (void *) header);
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if (ret)
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goto free_hdr;
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if (retlen != sizeof(*header)) {
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ret = -EIO;
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goto free_hdr;
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}
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if (strncmp(header->cybertan.magic, "NL16", 4) != 0) {
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printk(KERN_NOTICE "%s: no WRT160NL signature found\n",
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master->name);
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goto free_hdr;
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}
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theader = &header->trx;
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if (le32_to_cpu(theader->magic) != TRX_MAGIC) {
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printk(KERN_NOTICE "%s: no TRX header found\n", master->name);
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goto free_hdr;
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}
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uheader = &header->uimage;
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if (uheader->ih_magic != IH_MAGIC) {
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printk(KERN_NOTICE "%s: no uImage found\n", master->name);
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goto free_hdr;
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}
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kernel_len = uheader->ih_size / master->erasesize;
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if (uheader->ih_size % master->erasesize)
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kernel_len++;
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kernel_len++;
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kernel_len *= master->erasesize;
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trx_parts[0].name = "u-boot";
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trx_parts[0].offset = 0;
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trx_parts[0].size = 4 * master->erasesize;
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trx_parts[0].mask_flags = MTD_WRITEABLE;
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trx_parts[1].name = "kernel";
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trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size;
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trx_parts[1].size = kernel_len;
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trx_parts[1].mask_flags = 0;
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trx_parts[2].name = "rootfs";
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trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;
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trx_parts[2].size = master->size - 6 * master->erasesize - trx_parts[1].size;
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trx_parts[2].mask_flags = 0;
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trx_parts[3].name = "nvram";
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trx_parts[3].offset = master->size - 2 * master->erasesize;
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trx_parts[3].size = master->erasesize;
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trx_parts[3].mask_flags = MTD_WRITEABLE;
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trx_parts[4].name = "art";
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trx_parts[4].offset = master->size - master->erasesize;
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trx_parts[4].size = master->erasesize;
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trx_parts[4].mask_flags = MTD_WRITEABLE;
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trx_parts[5].name = "firmware";
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trx_parts[5].offset = 4 * master->erasesize;
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trx_parts[5].size = master->size - 6 * master->erasesize;
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trx_parts[5].mask_flags = 0;
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*pparts = trx_parts;
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ret = TRX_PARTS;
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free_hdr:
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vfree(header);
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out:
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return ret;
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}
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static struct mtd_part_parser wrt160nl_parser = {
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.owner = THIS_MODULE,
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.parse_fn = wrt160nl_parse_partitions,
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.name = "wrt160nl",
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};
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static int __init wrt160nl_parser_init(void)
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{
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return register_mtd_parser(&wrt160nl_parser);
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}
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module_init(wrt160nl_parser_init);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Christian Daniel <cd@maintech.de>");
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