mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 23:07:43 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21783 3c298f89-4303-0410-b956-a3cf2f4a3e73
1232 lines
46 KiB
Diff
1232 lines
46 KiB
Diff
--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
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{
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if (!cc->dev)
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return; /* We don't have a ChipCommon */
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+ if (cc->dev->id.revision >= 11)
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+ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
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ssb_pmu_init(cc);
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chipco_powercontrol_init(cc);
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ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
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@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
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{
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return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
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}
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+EXPORT_SYMBOL(ssb_chipco_gpio_control);
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u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
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case 0x5354:
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ssb_pmu0_pllinit_r0(cc, crystalfreq);
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break;
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+ case 0x4322:
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+ if (cc->pmu.rev == 2) {
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+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
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+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
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+ }
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+ break;
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default:
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ssb_printk(KERN_ERR PFX
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"ERROR: PLL init unknown for device %04X\n",
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@@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
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switch (bus->chip_id) {
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case 0x4312:
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+ case 0x4322:
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/* We keep the default settings:
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* min_msk = 0xCBB
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* max_msk = 0x7FFFF
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--- a/drivers/ssb/driver_gige.c
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+++ b/drivers/ssb/driver_gige.c
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@@ -12,6 +12,7 @@
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#include <linux/ssb/ssb_driver_gige.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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+#include <linux/slab.h>
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/*
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
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set_irq(dev, irq++);
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}
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break;
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- /* fallthrough */
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case SSB_DEV_PCI:
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case SSB_DEV_ETHERNET:
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case SSB_DEV_ETHERNET_GBIT:
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@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
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set_irq(dev, irq++);
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break;
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}
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+ /* fallthrough */
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+ case SSB_DEV_EXTIF:
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+ set_irq(dev, 0);
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+ break;
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}
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}
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ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
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--- a/drivers/ssb/driver_pcicore.c
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+++ b/drivers/ssb/driver_pcicore.c
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@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
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.pci_ops = &ssb_pcicore_pciops,
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.io_resource = &ssb_pcicore_io_resource,
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.mem_resource = &ssb_pcicore_mem_resource,
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- .mem_offset = 0x24000000,
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};
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-static u32 ssb_pcicore_pcibus_iobase = 0x100;
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-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
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-
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/* This function is called when doing a pci_enable_device().
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* We must first check if the device is a device on the PCI-core bridge. */
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int ssb_pcicore_plat_dev_init(struct pci_dev *d)
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{
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- struct resource *res;
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- int pos, size;
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- u32 *base;
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-
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if (d->bus->ops != &ssb_pcicore_pciops) {
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/* This is not a device on the PCI-core bridge. */
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return -ENODEV;
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@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
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ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
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pci_name(d));
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- /* Fix up resource bases */
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- for (pos = 0; pos < 6; pos++) {
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- res = &d->resource[pos];
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- if (res->flags & IORESOURCE_IO)
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- base = &ssb_pcicore_pcibus_iobase;
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- else
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- base = &ssb_pcicore_pcibus_membase;
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- res->flags |= IORESOURCE_PCI_FIXED;
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- if (res->end) {
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- size = res->end - res->start + 1;
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- if (*base & (size - 1))
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- *base = (*base + size) & ~(size - 1);
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- res->start = *base;
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- res->end = res->start + size - 1;
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- *base += size;
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- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
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- }
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- /* Fix up PCI bridge BAR0 only */
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- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
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- break;
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- }
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/* Fix up interrupt lines */
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d->irq = ssb_mips_irq(extpci_core->dev) + 2;
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pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
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@@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
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might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
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/* Enable interrupts for this device. */
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- if (bus->host_pci &&
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- ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
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+ if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
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u32 coremask;
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/* Calculate the "coremask" for the device. */
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coremask = (1 << dev->core_index);
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+ SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
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err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
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if (err)
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goto out;
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -18,6 +18,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/pci.h>
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#include <linux/mmc/sdio_func.h>
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+#include <linux/slab.h>
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#include <pcmcia/cs_types.h>
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#include <pcmcia/cs.h>
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@@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de
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put_device(dev->dev);
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}
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+static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
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+{
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+ if (drv)
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+ get_driver(&drv->drv);
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+ return drv;
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+}
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+
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+static inline void ssb_driver_put(struct ssb_driver *drv)
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+{
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+ if (drv)
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+ put_driver(&drv->drv);
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+}
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+
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static int ssb_device_resume(struct device *dev)
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{
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struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
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@@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
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EXPORT_SYMBOL(ssb_bus_suspend);
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#ifdef CONFIG_SSB_SPROM
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-int ssb_devices_freeze(struct ssb_bus *bus)
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+/** ssb_devices_freeze - Freeze all devices on the bus.
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+ *
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+ * After freezing no device driver will be handling a device
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+ * on this bus anymore. ssb_devices_thaw() must be called after
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+ * a successful freeze to reactivate the devices.
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+ *
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+ * @bus: The bus.
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+ * @ctx: Context structure. Pass this to ssb_devices_thaw().
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+ */
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+int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
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{
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- struct ssb_device *dev;
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- struct ssb_driver *drv;
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- int err = 0;
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- int i;
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- pm_message_t state = PMSG_FREEZE;
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+ struct ssb_device *sdev;
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+ struct ssb_driver *sdrv;
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+ unsigned int i;
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+
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+ memset(ctx, 0, sizeof(*ctx));
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+ ctx->bus = bus;
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+ SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
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- /* First check that we are capable to freeze all devices. */
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for (i = 0; i < bus->nr_devices; i++) {
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- dev = &(bus->devices[i]);
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- if (!dev->dev ||
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- !dev->dev->driver ||
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- !device_is_registered(dev->dev))
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- continue;
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- drv = drv_to_ssb_drv(dev->dev->driver);
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- if (!drv)
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+ sdev = ssb_device_get(&bus->devices[i]);
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+
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+ if (!sdev->dev || !sdev->dev->driver ||
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+ !device_is_registered(sdev->dev)) {
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+ ssb_device_put(sdev);
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continue;
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- if (!drv->suspend) {
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- /* Nope, can't suspend this one. */
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- return -EOPNOTSUPP;
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}
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- }
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- /* Now suspend all devices */
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- for (i = 0; i < bus->nr_devices; i++) {
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- dev = &(bus->devices[i]);
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- if (!dev->dev ||
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- !dev->dev->driver ||
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- !device_is_registered(dev->dev))
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+ sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
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+ if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
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+ ssb_device_put(sdev);
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continue;
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- drv = drv_to_ssb_drv(dev->dev->driver);
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- if (!drv)
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- continue;
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- err = drv->suspend(dev, state);
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- if (err) {
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- ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
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- dev_name(dev->dev));
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- goto err_unwind;
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}
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+ sdrv->remove(sdev);
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+ ctx->device_frozen[i] = 1;
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}
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return 0;
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-err_unwind:
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- for (i--; i >= 0; i--) {
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- dev = &(bus->devices[i]);
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- if (!dev->dev ||
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- !dev->dev->driver ||
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- !device_is_registered(dev->dev))
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- continue;
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- drv = drv_to_ssb_drv(dev->dev->driver);
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- if (!drv)
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- continue;
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- if (drv->resume)
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- drv->resume(dev);
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- }
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- return err;
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}
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-int ssb_devices_thaw(struct ssb_bus *bus)
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+/** ssb_devices_thaw - Unfreeze all devices on the bus.
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+ *
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+ * This will re-attach the device drivers and re-init the devices.
|
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+ *
|
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+ * @ctx: The context structure from ssb_devices_freeze()
|
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+ */
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+int ssb_devices_thaw(struct ssb_freeze_context *ctx)
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{
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- struct ssb_device *dev;
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- struct ssb_driver *drv;
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- int err;
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- int i;
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+ struct ssb_bus *bus = ctx->bus;
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+ struct ssb_device *sdev;
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+ struct ssb_driver *sdrv;
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+ unsigned int i;
|
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+ int err, result = 0;
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|
|
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for (i = 0; i < bus->nr_devices; i++) {
|
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- dev = &(bus->devices[i]);
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- if (!dev->dev ||
|
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- !dev->dev->driver ||
|
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- !device_is_registered(dev->dev))
|
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+ if (!ctx->device_frozen[i])
|
|
continue;
|
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- drv = drv_to_ssb_drv(dev->dev->driver);
|
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- if (!drv)
|
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+ sdev = &bus->devices[i];
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+
|
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+ if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
|
|
continue;
|
|
- if (SSB_WARN_ON(!drv->resume))
|
|
+ sdrv = drv_to_ssb_drv(sdev->dev->driver);
|
|
+ if (SSB_WARN_ON(!sdrv || !sdrv->probe))
|
|
continue;
|
|
- err = drv->resume(dev);
|
|
+
|
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+ err = sdrv->probe(sdev, &sdev->id);
|
|
if (err) {
|
|
ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
|
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- dev_name(dev->dev));
|
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+ dev_name(sdev->dev));
|
|
+ result = err;
|
|
}
|
|
+ ssb_driver_put(sdrv);
|
|
+ ssb_device_put(sdev);
|
|
}
|
|
|
|
- return 0;
|
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+ return result;
|
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}
|
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#endif /* CONFIG_SSB_SPROM */
|
|
|
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@@ -490,8 +495,7 @@ static int ssb_devices_register(struct s
|
|
#endif
|
|
break;
|
|
case SSB_BUSTYPE_SDIO:
|
|
-#ifdef CONFIG_SSB_SDIO
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- sdev->irq = bus->host_sdio->dev.irq;
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|
+#ifdef CONFIG_SSB_SDIOHOST
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|
dev->parent = &bus->host_sdio->dev;
|
|
#endif
|
|
break;
|
|
@@ -830,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
|
|
if (!err) {
|
|
ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
|
|
"PCI device %s\n", dev_name(&host_pci->dev));
|
|
+ } else {
|
|
+ ssb_printk(KERN_ERR PFX "Failed to register PCI version"
|
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+ " of SSB with error %d\n", err);
|
|
}
|
|
|
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return err;
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
|
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@@ -17,6 +17,7 @@
|
|
|
|
#include <linux/ssb/ssb.h>
|
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#include <linux/ssb/ssb_regs.h>
|
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+#include <linux/slab.h>
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#include <linux/pci.h>
|
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#include <linux/delay.h>
|
|
|
|
@@ -167,7 +168,7 @@ err_pci:
|
|
}
|
|
|
|
/* Get the word-offset for a SSB_SPROM_XXX define. */
|
|
-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
|
|
+#define SPOFF(offset) ((offset) / sizeof(u16))
|
|
/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
|
|
#define SPEX16(_outvar, _offset, _mask, _shift) \
|
|
out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
|
|
@@ -253,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
|
|
int i;
|
|
|
|
for (i = 0; i < bus->sprom_size; i++)
|
|
- sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
|
|
+ sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
|
|
|
|
return 0;
|
|
}
|
|
@@ -284,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
|
|
ssb_printk("75%%");
|
|
else if (i % 2)
|
|
ssb_printk(".");
|
|
- writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
|
|
+ writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
|
|
mmiowb();
|
|
msleep(20);
|
|
}
|
|
@@ -620,6 +621,14 @@ static int ssb_pci_sprom_get(struct ssb_
|
|
int err = -ENOMEM;
|
|
u16 *buf;
|
|
|
|
+ if (!ssb_is_sprom_available(bus)) {
|
|
+ ssb_printk(KERN_ERR PFX "No SPROM available!\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
|
|
+ SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
|
|
+
|
|
buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
|
|
if (!buf)
|
|
goto out;
|
|
--- a/drivers/ssb/pcihost_wrapper.c
|
|
+++ b/drivers/ssb/pcihost_wrapper.c
|
|
@@ -12,6 +12,7 @@
|
|
*/
|
|
|
|
#include <linux/pci.h>
|
|
+#include <linux/slab.h>
|
|
#include <linux/ssb/ssb.h>
|
|
|
|
|
|
--- a/drivers/ssb/pcmcia.c
|
|
+++ b/drivers/ssb/pcmcia.c
|
|
@@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
|
|
} \
|
|
} while (0)
|
|
|
|
-int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
|
|
- struct ssb_init_invariants *iv)
|
|
+static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
|
|
+ tuple_t *tuple,
|
|
+ void *priv)
|
|
+{
|
|
+ struct ssb_sprom *sprom = priv;
|
|
+
|
|
+ if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
|
|
+ return -EINVAL;
|
|
+ if (tuple->TupleDataLen != ETH_ALEN + 2)
|
|
+ return -EINVAL;
|
|
+ if (tuple->TupleData[1] != ETH_ALEN)
|
|
+ return -EINVAL;
|
|
+ memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
|
|
+ return 0;
|
|
+};
|
|
+
|
|
+static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
|
|
+ tuple_t *tuple,
|
|
+ void *priv)
|
|
{
|
|
- tuple_t tuple;
|
|
- int res;
|
|
- unsigned char buf[32];
|
|
+ struct ssb_init_invariants *iv = priv;
|
|
struct ssb_sprom *sprom = &iv->sprom;
|
|
struct ssb_boardinfo *bi = &iv->boardinfo;
|
|
const char *error_description;
|
|
|
|
+ GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
|
|
+ switch (tuple->TupleData[0]) {
|
|
+ case SSB_PCMCIA_CIS_ID:
|
|
+ GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
|
|
+ (tuple->TupleDataLen != 7),
|
|
+ "id tpl size");
|
|
+ bi->vendor = tuple->TupleData[1] |
|
|
+ ((u16)tuple->TupleData[2] << 8);
|
|
+ break;
|
|
+ case SSB_PCMCIA_CIS_BOARDREV:
|
|
+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
|
|
+ "boardrev tpl size");
|
|
+ sprom->board_rev = tuple->TupleData[1];
|
|
+ break;
|
|
+ case SSB_PCMCIA_CIS_PA:
|
|
+ GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
|
|
+ (tuple->TupleDataLen != 10),
|
|
+ "pa tpl size");
|
|
+ sprom->pa0b0 = tuple->TupleData[1] |
|
|
+ ((u16)tuple->TupleData[2] << 8);
|
|
+ sprom->pa0b1 = tuple->TupleData[3] |
|
|
+ ((u16)tuple->TupleData[4] << 8);
|
|
+ sprom->pa0b2 = tuple->TupleData[5] |
|
|
+ ((u16)tuple->TupleData[6] << 8);
|
|
+ sprom->itssi_a = tuple->TupleData[7];
|
|
+ sprom->itssi_bg = tuple->TupleData[7];
|
|
+ sprom->maxpwr_a = tuple->TupleData[8];
|
|
+ sprom->maxpwr_bg = tuple->TupleData[8];
|
|
+ break;
|
|
+ case SSB_PCMCIA_CIS_OEMNAME:
|
|
+ /* We ignore this. */
|
|
+ break;
|
|
+ case SSB_PCMCIA_CIS_CCODE:
|
|
+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
|
|
+ "ccode tpl size");
|
|
+ sprom->country_code = tuple->TupleData[1];
|
|
+ break;
|
|
+ case SSB_PCMCIA_CIS_ANTENNA:
|
|
+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
|
|
+ "ant tpl size");
|
|
+ sprom->ant_available_a = tuple->TupleData[1];
|
|
+ sprom->ant_available_bg = tuple->TupleData[1];
|
|
+ break;
|
|
+ case SSB_PCMCIA_CIS_ANTGAIN:
|
|
+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
|
|
+ "antg tpl size");
|
|
+ sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
|
|
+ break;
|
|
+ case SSB_PCMCIA_CIS_BFLAGS:
|
|
+ GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
|
|
+ (tuple->TupleDataLen != 5),
|
|
+ "bfl tpl size");
|
|
+ sprom->boardflags_lo = tuple->TupleData[1] |
|
|
+ ((u16)tuple->TupleData[2] << 8);
|
|
+ break;
|
|
+ case SSB_PCMCIA_CIS_LEDS:
|
|
+ GOTO_ERROR_ON(tuple->TupleDataLen != 5,
|
|
+ "leds tpl size");
|
|
+ sprom->gpio0 = tuple->TupleData[1];
|
|
+ sprom->gpio1 = tuple->TupleData[2];
|
|
+ sprom->gpio2 = tuple->TupleData[3];
|
|
+ sprom->gpio3 = tuple->TupleData[4];
|
|
+ break;
|
|
+ }
|
|
+ return -ENOSPC; /* continue with next entry */
|
|
+
|
|
+error:
|
|
+ ssb_printk(KERN_ERR PFX
|
|
+ "PCMCIA: Failed to fetch device invariants: %s\n",
|
|
+ error_description);
|
|
+ return -ENODEV;
|
|
+}
|
|
+
|
|
+
|
|
+int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
|
|
+ struct ssb_init_invariants *iv)
|
|
+{
|
|
+ struct ssb_sprom *sprom = &iv->sprom;
|
|
+ int res;
|
|
+
|
|
memset(sprom, 0xFF, sizeof(*sprom));
|
|
sprom->revision = 1;
|
|
sprom->boardflags_lo = 0;
|
|
sprom->boardflags_hi = 0;
|
|
|
|
/* First fetch the MAC address. */
|
|
- memset(&tuple, 0, sizeof(tuple));
|
|
- tuple.DesiredTuple = CISTPL_FUNCE;
|
|
- tuple.TupleData = buf;
|
|
- tuple.TupleDataMax = sizeof(buf);
|
|
- res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
|
|
- GOTO_ERROR_ON(res != 0, "MAC first tpl");
|
|
- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
|
|
- GOTO_ERROR_ON(res != 0, "MAC first tpl data");
|
|
- while (1) {
|
|
- GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
|
|
- if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
|
|
- break;
|
|
- res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
|
|
- GOTO_ERROR_ON(res != 0, "MAC next tpl");
|
|
- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
|
|
- GOTO_ERROR_ON(res != 0, "MAC next tpl data");
|
|
+ res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
|
|
+ ssb_pcmcia_get_mac, sprom);
|
|
+ if (res != 0) {
|
|
+ ssb_printk(KERN_ERR PFX
|
|
+ "PCMCIA: Failed to fetch MAC address\n");
|
|
+ return -ENODEV;
|
|
}
|
|
- GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
|
|
- memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
|
|
|
|
/* Fetch the vendor specific tuples. */
|
|
- memset(&tuple, 0, sizeof(tuple));
|
|
- tuple.DesiredTuple = SSB_PCMCIA_CIS;
|
|
- tuple.TupleData = buf;
|
|
- tuple.TupleDataMax = sizeof(buf);
|
|
- res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
|
|
- GOTO_ERROR_ON(res != 0, "VEN first tpl");
|
|
- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
|
|
- GOTO_ERROR_ON(res != 0, "VEN first tpl data");
|
|
- while (1) {
|
|
- GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
|
|
- switch (tuple.TupleData[0]) {
|
|
- case SSB_PCMCIA_CIS_ID:
|
|
- GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
|
|
- (tuple.TupleDataLen != 7),
|
|
- "id tpl size");
|
|
- bi->vendor = tuple.TupleData[1] |
|
|
- ((u16)tuple.TupleData[2] << 8);
|
|
- break;
|
|
- case SSB_PCMCIA_CIS_BOARDREV:
|
|
- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
|
|
- "boardrev tpl size");
|
|
- sprom->board_rev = tuple.TupleData[1];
|
|
- break;
|
|
- case SSB_PCMCIA_CIS_PA:
|
|
- GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
|
|
- (tuple.TupleDataLen != 10),
|
|
- "pa tpl size");
|
|
- sprom->pa0b0 = tuple.TupleData[1] |
|
|
- ((u16)tuple.TupleData[2] << 8);
|
|
- sprom->pa0b1 = tuple.TupleData[3] |
|
|
- ((u16)tuple.TupleData[4] << 8);
|
|
- sprom->pa0b2 = tuple.TupleData[5] |
|
|
- ((u16)tuple.TupleData[6] << 8);
|
|
- sprom->itssi_a = tuple.TupleData[7];
|
|
- sprom->itssi_bg = tuple.TupleData[7];
|
|
- sprom->maxpwr_a = tuple.TupleData[8];
|
|
- sprom->maxpwr_bg = tuple.TupleData[8];
|
|
- break;
|
|
- case SSB_PCMCIA_CIS_OEMNAME:
|
|
- /* We ignore this. */
|
|
- break;
|
|
- case SSB_PCMCIA_CIS_CCODE:
|
|
- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
|
|
- "ccode tpl size");
|
|
- sprom->country_code = tuple.TupleData[1];
|
|
- break;
|
|
- case SSB_PCMCIA_CIS_ANTENNA:
|
|
- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
|
|
- "ant tpl size");
|
|
- sprom->ant_available_a = tuple.TupleData[1];
|
|
- sprom->ant_available_bg = tuple.TupleData[1];
|
|
- break;
|
|
- case SSB_PCMCIA_CIS_ANTGAIN:
|
|
- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
|
|
- "antg tpl size");
|
|
- sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
|
|
- break;
|
|
- case SSB_PCMCIA_CIS_BFLAGS:
|
|
- GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
|
|
- (tuple.TupleDataLen != 5),
|
|
- "bfl tpl size");
|
|
- sprom->boardflags_lo = tuple.TupleData[1] |
|
|
- ((u16)tuple.TupleData[2] << 8);
|
|
- break;
|
|
- case SSB_PCMCIA_CIS_LEDS:
|
|
- GOTO_ERROR_ON(tuple.TupleDataLen != 5,
|
|
- "leds tpl size");
|
|
- sprom->gpio0 = tuple.TupleData[1];
|
|
- sprom->gpio1 = tuple.TupleData[2];
|
|
- sprom->gpio2 = tuple.TupleData[3];
|
|
- sprom->gpio3 = tuple.TupleData[4];
|
|
- break;
|
|
- }
|
|
- res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
|
|
- if (res == -ENOSPC)
|
|
- break;
|
|
- GOTO_ERROR_ON(res != 0, "VEN next tpl");
|
|
- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
|
|
- GOTO_ERROR_ON(res != 0, "VEN next tpl data");
|
|
- }
|
|
+ res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
|
|
+ ssb_pcmcia_do_get_invariants, sprom);
|
|
+ if ((res == 0) || (res == -ENOSPC))
|
|
+ return 0;
|
|
|
|
- return 0;
|
|
-error:
|
|
ssb_printk(KERN_ERR PFX
|
|
- "PCMCIA: Failed to fetch device invariants: %s\n",
|
|
- error_description);
|
|
+ "PCMCIA: Failed to fetch device invariants\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
--- a/drivers/ssb/scan.c
|
|
+++ b/drivers/ssb/scan.c
|
|
@@ -354,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
|
|
dev->bus = bus;
|
|
dev->ops = bus->ops;
|
|
|
|
- ssb_dprintk(KERN_INFO PFX
|
|
+ printk(KERN_DEBUG PFX
|
|
"Core %d found: %s "
|
|
"(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
|
|
i, ssb_core_name(dev->id.coreid),
|
|
--- a/drivers/ssb/sprom.c
|
|
+++ b/drivers/ssb/sprom.c
|
|
@@ -14,6 +14,7 @@
|
|
#include "ssb_private.h"
|
|
|
|
#include <linux/ctype.h>
|
|
+#include <linux/slab.h>
|
|
|
|
|
|
static const struct ssb_sprom *fallback_sprom;
|
|
@@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
|
|
u16 *sprom;
|
|
int res = 0, err = -ENOMEM;
|
|
size_t sprom_size_words = bus->sprom_size;
|
|
+ struct ssb_freeze_context freeze;
|
|
|
|
sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
|
|
if (!sprom)
|
|
@@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
|
|
err = -ERESTARTSYS;
|
|
if (mutex_lock_interruptible(&bus->sprom_mutex))
|
|
goto out_kfree;
|
|
- err = ssb_devices_freeze(bus);
|
|
- if (err == -EOPNOTSUPP) {
|
|
- ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
|
|
- "No suspend support. Is CONFIG_PM enabled?\n");
|
|
- goto out_unlock;
|
|
- }
|
|
+ err = ssb_devices_freeze(bus, &freeze);
|
|
if (err) {
|
|
ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
|
|
goto out_unlock;
|
|
}
|
|
res = sprom_write(bus, sprom);
|
|
- err = ssb_devices_thaw(bus);
|
|
+ err = ssb_devices_thaw(&freeze);
|
|
if (err)
|
|
ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
|
|
out_unlock:
|
|
@@ -179,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
|
|
{
|
|
return fallback_sprom;
|
|
}
|
|
+
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
|
|
+bool ssb_is_sprom_available(struct ssb_bus *bus)
|
|
+{
|
|
+ /* status register only exists on chipcomon rev >= 11 and we need check
|
|
+ for >= 31 only */
|
|
+ /* this routine differs from specs as we do not access SPROM directly
|
|
+ on PCMCIA */
|
|
+ if (bus->bustype == SSB_BUSTYPE_PCI &&
|
|
+ bus->chipco.dev->id.revision >= 31)
|
|
+ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
|
|
+
|
|
+ return true;
|
|
+}
|
|
--- a/drivers/ssb/ssb_private.h
|
|
+++ b/drivers/ssb/ssb_private.h
|
|
@@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f
|
|
|
|
/* core.c */
|
|
extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
|
|
-extern int ssb_devices_freeze(struct ssb_bus *bus);
|
|
-extern int ssb_devices_thaw(struct ssb_bus *bus);
|
|
extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
|
|
int ssb_for_each_bus_call(unsigned long data,
|
|
int (*func)(struct ssb_bus *bus, unsigned long data));
|
|
extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
|
|
|
|
+struct ssb_freeze_context {
|
|
+ /* Pointer to the bus */
|
|
+ struct ssb_bus *bus;
|
|
+ /* Boolean list to indicate whether a device is frozen on this bus. */
|
|
+ bool device_frozen[SSB_MAX_NR_CORES];
|
|
+};
|
|
+extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
|
|
+extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
|
|
+
|
|
+
|
|
|
|
/* b43_pci_bridge.c */
|
|
#ifdef CONFIG_SSB_B43_PCI_BRIDGE
|
|
extern int __init b43_pci_ssb_bridge_init(void);
|
|
extern void __exit b43_pci_ssb_bridge_exit(void);
|
|
-#else /* CONFIG_SSB_B43_PCI_BRIDGR */
|
|
+#else /* CONFIG_SSB_B43_PCI_BRIDGE */
|
|
static inline int b43_pci_ssb_bridge_init(void)
|
|
{
|
|
return 0;
|
|
@@ -196,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
|
|
static inline void b43_pci_ssb_bridge_exit(void)
|
|
{
|
|
}
|
|
-#endif /* CONFIG_SSB_PCIHOST */
|
|
+#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
|
|
|
|
#endif /* LINUX_SSB_PRIVATE_H_ */
|
|
--- a/include/linux/ssb/ssb.h
|
|
+++ b/include/linux/ssb/ssb.h
|
|
@@ -269,7 +269,8 @@ struct ssb_bus {
|
|
|
|
const struct ssb_bus_ops *ops;
|
|
|
|
- /* The core in the basic address register window. (PCI bus only) */
|
|
+ /* The core currently mapped into the MMIO window.
|
|
+ * Not valid on all host-buses. So don't use outside of SSB. */
|
|
struct ssb_device *mapped_device;
|
|
union {
|
|
/* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
|
|
@@ -281,14 +282,17 @@ struct ssb_bus {
|
|
* On PCMCIA-host busses this is used to protect the whole MMIO access. */
|
|
spinlock_t bar_lock;
|
|
|
|
- /* The bus this backplane is running on. */
|
|
+ /* The host-bus this backplane is running on. */
|
|
enum ssb_bustype bustype;
|
|
- /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
|
|
- struct pci_dev *host_pci;
|
|
- /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
|
|
- struct pcmcia_device *host_pcmcia;
|
|
- /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
|
|
- struct sdio_func *host_sdio;
|
|
+ /* Pointers to the host-bus. Check bustype before using any of these pointers. */
|
|
+ union {
|
|
+ /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
|
|
+ struct pci_dev *host_pci;
|
|
+ /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
|
|
+ struct pcmcia_device *host_pcmcia;
|
|
+ /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
|
|
+ struct sdio_func *host_sdio;
|
|
+ };
|
|
|
|
/* See enum ssb_quirks */
|
|
unsigned int quirks;
|
|
@@ -301,6 +305,7 @@ struct ssb_bus {
|
|
/* ID information about the Chip. */
|
|
u16 chip_id;
|
|
u16 chip_rev;
|
|
+ u16 sprom_offset;
|
|
u16 sprom_size; /* number of words in sprom */
|
|
u8 chip_package;
|
|
|
|
@@ -390,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
|
|
|
|
extern void ssb_bus_unregister(struct ssb_bus *bus);
|
|
|
|
+/* Does the device have an SPROM? */
|
|
+extern bool ssb_is_sprom_available(struct ssb_bus *bus);
|
|
+
|
|
/* Set a fallback SPROM.
|
|
* See kdoc at the function definition for complete documentation. */
|
|
extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
|
|
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
|
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
|
@@ -53,6 +53,7 @@
|
|
#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
|
|
#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
|
|
#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
|
|
+#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
|
|
#define SSB_CHIPCO_CORECTL 0x0008
|
|
#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
|
|
#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
|
|
@@ -385,6 +386,7 @@
|
|
|
|
|
|
/** Chip specific Chip-Status register contents. */
|
|
+#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
|
|
#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
|
|
#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
|
|
#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
|
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@@ -398,6 +400,18 @@
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#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
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#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
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+/** Macros to determine SPROM presence based on Chip-Status register. */
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+#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
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+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
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+ SSB_CHIPCO_CHST_4325_OTP_SEL)
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+#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
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+ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
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+#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
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+ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
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+ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
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+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
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+ SSB_CHIPCO_CHST_4325_OTP_SEL))
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+
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/** Clockcontrol masks and values **/
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@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
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struct ssb_chipcommon {
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struct ssb_device *dev;
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u32 capabilities;
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+ u32 status;
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/* Fast Powerup Delay constant */
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u16 fast_pwrup_delay;
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struct ssb_chipcommon_pmu pmu;
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -170,26 +170,27 @@
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#define SSB_SPROMSIZE_WORDS_R4 220
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#define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
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#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
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-#define SSB_SPROM_BASE 0x1000
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-#define SSB_SPROM_REVISION 0x107E
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+#define SSB_SPROM_BASE1 0x1000
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+#define SSB_SPROM_BASE31 0x0800
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+#define SSB_SPROM_REVISION 0x007E
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#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
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#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
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#define SSB_SPROM_REVISION_CRC_SHIFT 8
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/* SPROM Revision 1 */
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-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
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-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
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-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
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-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
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-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
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-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
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-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
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+#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
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+#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
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+#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
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+#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
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+#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
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+#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
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+#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
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#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
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#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
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#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
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#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
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#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
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-#define SSB_SPROM1_BINF 0x105C /* Board info */
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+#define SSB_SPROM1_BINF 0x005C /* Board info */
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#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
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#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
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#define SSB_SPROM1_BINF_CCODE_SHIFT 8
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@@ -197,63 +198,63 @@
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#define SSB_SPROM1_BINF_ANTBG_SHIFT 12
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#define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
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#define SSB_SPROM1_BINF_ANTA_SHIFT 14
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-#define SSB_SPROM1_PA0B0 0x105E
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-#define SSB_SPROM1_PA0B1 0x1060
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-#define SSB_SPROM1_PA0B2 0x1062
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-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
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+#define SSB_SPROM1_PA0B0 0x005E
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+#define SSB_SPROM1_PA0B1 0x0060
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+#define SSB_SPROM1_PA0B2 0x0062
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+#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
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#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
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#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
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#define SSB_SPROM1_GPIOA_P1_SHIFT 8
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-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
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+#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
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#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
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#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
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#define SSB_SPROM1_GPIOB_P3_SHIFT 8
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-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
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+#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
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#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
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#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
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#define SSB_SPROM1_MAXPWR_A_SHIFT 8
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-#define SSB_SPROM1_PA1B0 0x106A
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-#define SSB_SPROM1_PA1B1 0x106C
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-#define SSB_SPROM1_PA1B2 0x106E
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-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
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+#define SSB_SPROM1_PA1B0 0x006A
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+#define SSB_SPROM1_PA1B1 0x006C
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+#define SSB_SPROM1_PA1B2 0x006E
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+#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
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#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
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#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
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#define SSB_SPROM1_ITSSI_A_SHIFT 8
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-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
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-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
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+#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
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+#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
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#define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
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#define SSB_SPROM1_AGAIN_BG_SHIFT 0
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#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
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#define SSB_SPROM1_AGAIN_A_SHIFT 8
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/* SPROM Revision 2 (inherits from rev 1) */
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-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
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-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
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+#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
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+#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
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#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
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#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
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#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
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-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
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-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
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-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
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-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
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-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
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-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
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-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
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+#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
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+#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
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+#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
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+#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
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+#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
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+#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
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+#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
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#define SSB_SPROM2_OPO_VALUE 0x00FF
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#define SSB_SPROM2_OPO_UNUSED 0xFF00
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-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
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+#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
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/* SPROM Revision 3 (inherits most data from rev 2) */
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-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
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-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
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-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
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-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
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-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
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+#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
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+#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
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+#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
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+#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
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#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
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#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
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#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
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#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
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-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
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+#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
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+#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
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#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
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#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
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#define SSB_SPROM3_CCKPO_2M_SHIFT 4
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@@ -264,100 +265,100 @@
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#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
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/* SPROM Revision 4 */
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-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
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-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
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+#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
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+#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
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+#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
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+#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
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+#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
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+#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
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+#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
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+#define SSB_SPROM4_GPIOA_P1_SHIFT 8
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+#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
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+#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
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+#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
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+#define SSB_SPROM4_GPIOB_P3_SHIFT 8
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+#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
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#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
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#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
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#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
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#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
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#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
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-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
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-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
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-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
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-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
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-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
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-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
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-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
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-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
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+#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
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+#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
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+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
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+#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
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+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
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+#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
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#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
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#define SSB_SPROM4_AGAIN0_SHIFT 0
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#define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
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#define SSB_SPROM4_AGAIN1_SHIFT 8
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-#define SSB_SPROM4_AGAIN23 0x1060
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+#define SSB_SPROM4_AGAIN23 0x0060
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#define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
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#define SSB_SPROM4_AGAIN2_SHIFT 0
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#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
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#define SSB_SPROM4_AGAIN3_SHIFT 8
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-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
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-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
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+#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
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#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
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#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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#define SSB_SPROM4_ITSSI_BG_SHIFT 8
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-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
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+#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
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#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
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#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
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#define SSB_SPROM4_ITSSI_A_SHIFT 8
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-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
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-#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
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-#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
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-#define SSB_SPROM4_GPIOA_P1_SHIFT 8
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-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
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-#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
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-#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
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-#define SSB_SPROM4_GPIOB_P3_SHIFT 8
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-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
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-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
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-#define SSB_SPROM4_PA0B2 0x1086
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-#define SSB_SPROM4_PA1B0 0x108E
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-#define SSB_SPROM4_PA1B1 0x1090
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-#define SSB_SPROM4_PA1B2 0x1092
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+#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
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+#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
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+#define SSB_SPROM4_PA0B2 0x0086
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+#define SSB_SPROM4_PA1B0 0x008E
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+#define SSB_SPROM4_PA1B1 0x0090
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+#define SSB_SPROM4_PA1B2 0x0092
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/* SPROM Revision 5 (inherits most data from rev 4) */
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-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
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-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
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-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
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-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
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-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
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+#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
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+#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
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+#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
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+#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
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+#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
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#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
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#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
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#define SSB_SPROM5_GPIOA_P1_SHIFT 8
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-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
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+#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
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#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
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#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
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#define SSB_SPROM5_GPIOB_P3_SHIFT 8
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/* SPROM Revision 8 */
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-#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
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-#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
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-#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
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-#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
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-#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
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-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
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-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
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-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
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-#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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-#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
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-#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
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-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
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-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
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+#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
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+#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
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+#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
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+#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
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+#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
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+#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
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+#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
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+#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
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+#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
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+#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
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+#define SSB_SPROM8_GPIOA_P1_SHIFT 8
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+#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
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+#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
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+#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
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+#define SSB_SPROM8_GPIOB_P3_SHIFT 8
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+#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
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+#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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+#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
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+#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
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+#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
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+#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
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#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
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#define SSB_SPROM8_AGAIN0_SHIFT 0
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#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
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#define SSB_SPROM8_AGAIN1_SHIFT 8
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-#define SSB_SPROM8_AGAIN23 0x10A0
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+#define SSB_SPROM8_AGAIN23 0x00A0
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#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
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#define SSB_SPROM8_AGAIN2_SHIFT 0
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#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
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#define SSB_SPROM8_AGAIN3_SHIFT 8
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-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
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-#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
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-#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
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-#define SSB_SPROM8_GPIOA_P1_SHIFT 8
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-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
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-#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
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-#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
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-#define SSB_SPROM8_GPIOB_P3_SHIFT 8
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-#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
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+#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
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#define SSB_SPROM8_RSSISMF2G 0x000F
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#define SSB_SPROM8_RSSISMC2G 0x00F0
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#define SSB_SPROM8_RSSISMC2G_SHIFT 4
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@@ -365,7 +366,7 @@
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#define SSB_SPROM8_RSSISAV2G_SHIFT 8
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#define SSB_SPROM8_BXA2G 0x1800
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#define SSB_SPROM8_BXA2G_SHIFT 11
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-#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
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+#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
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#define SSB_SPROM8_RSSISMF5G 0x000F
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#define SSB_SPROM8_RSSISMC5G 0x00F0
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#define SSB_SPROM8_RSSISMC5G_SHIFT 4
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@@ -373,47 +374,47 @@
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#define SSB_SPROM8_RSSISAV5G_SHIFT 8
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#define SSB_SPROM8_BXA5G 0x1800
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#define SSB_SPROM8_BXA5G_SHIFT 11
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-#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
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+#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
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#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
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#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
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#define SSB_SPROM8_TRI5G_SHIFT 8
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-#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
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+#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
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#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
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#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
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#define SSB_SPROM8_TRI5GH_SHIFT 8
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-#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
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+#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
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#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
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#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
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#define SSB_SPROM8_RXPO5G_SHIFT 8
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-#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
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+#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
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#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
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#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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#define SSB_SPROM8_ITSSI_BG_SHIFT 8
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-#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
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-#define SSB_SPROM8_PA0B1 0x10C4
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-#define SSB_SPROM8_PA0B2 0x10C6
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-#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
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+#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
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+#define SSB_SPROM8_PA0B1 0x00C4
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+#define SSB_SPROM8_PA0B2 0x00C6
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+#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
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#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
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#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
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#define SSB_SPROM8_ITSSI_A_SHIFT 8
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-#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
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+#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
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#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
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#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
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#define SSB_SPROM8_MAXP_AL_SHIFT 8
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-#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
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-#define SSB_SPROM8_PA1B1 0x10CE
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-#define SSB_SPROM8_PA1B2 0x10D0
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-#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
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-#define SSB_SPROM8_PA1LOB1 0x10D4
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-#define SSB_SPROM8_PA1LOB2 0x10D6
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-#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
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-#define SSB_SPROM8_PA1HIB1 0x10DA
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-#define SSB_SPROM8_PA1HIB2 0x10DC
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-#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
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-#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
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-#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
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-#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
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-#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
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+#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
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+#define SSB_SPROM8_PA1B1 0x00CE
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+#define SSB_SPROM8_PA1B2 0x00D0
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+#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
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+#define SSB_SPROM8_PA1LOB1 0x00D4
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+#define SSB_SPROM8_PA1LOB2 0x00D6
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+#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
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+#define SSB_SPROM8_PA1HIB1 0x00DA
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+#define SSB_SPROM8_PA1HIB2 0x00DC
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+#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
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+#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
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+#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
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+#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
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+#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
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/* Values for SSB_SPROM1_BINF_CCODE */
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enum {
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