mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 12:24:04 +02:00
dc3d3f1c49
it's basically also provided by ingenic and nativly based on 2.6.27, adjusted to fit into the OpenWrt-environment
797 lines
21 KiB
C
797 lines
21 KiB
C
/*
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* linux/drivers/video/jz4750_lcd.h -- Ingenic Jz4750 On-Chip LCD frame buffer device
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*
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* Copyright (C) 2005-2008, Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __JZ4750_LCD_H__
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#define __JZ4750_LCD_H__
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//#include <asm/io.h>
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#define NR_PALETTE 256
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#define PALETTE_SIZE (NR_PALETTE*2)
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/* use new descriptor(8 words) */
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struct jz4750_lcd_dma_desc {
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unsigned int next_desc; /* LCDDAx */
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unsigned int databuf; /* LCDSAx */
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unsigned int frame_id; /* LCDFIDx */
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unsigned int cmd; /* LCDCMDx */
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unsigned int offsize; /* Stride Offsize(in word) */
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unsigned int page_width; /* Stride Pagewidth(in word) */
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unsigned int cmd_num; /* Command Number(for SLCD) */
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unsigned int desc_size; /* Foreground Size */
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};
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struct jz4750lcd_panel_t {
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unsigned int cfg; /* panel mode and pin usage etc. */
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unsigned int slcd_cfg; /* Smart lcd configurations */
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unsigned int ctrl; /* lcd controll register */
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unsigned int w; /* Panel Width(in pixel) */
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unsigned int h; /* Panel Height(in line) */
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unsigned int fclk; /* frame clk */
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unsigned int hsw; /* hsync width, in pclk */
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unsigned int vsw; /* vsync width, in line count */
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unsigned int elw; /* end of line, in pclk */
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unsigned int blw; /* begin of line, in pclk */
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unsigned int efw; /* end of frame, in line count */
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unsigned int bfw; /* begin of frame, in line count */
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};
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struct jz4750lcd_fg_t {
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int bpp; /* foreground bpp */
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int x; /* foreground start position x */
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int y; /* foreground start position y */
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int w; /* foreground width */
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int h; /* foreground height */
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};
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struct jz4750lcd_osd_t {
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unsigned int osd_cfg; /* OSDEN, ALHPAEN, F0EN, F1EN, etc */
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unsigned int osd_ctrl; /* IPUEN, OSDBPP, etc */
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unsigned int rgb_ctrl; /* RGB Dummy, RGB sequence, RGB to YUV */
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unsigned int bgcolor; /* background color(RGB888) */
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unsigned int colorkey0; /* foreground0's Colorkey enable, Colorkey value */
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unsigned int colorkey1; /* foreground1's Colorkey enable, Colorkey value */
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unsigned int alpha; /* ALPHAEN, alpha value */
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unsigned int ipu_restart; /* IPU Restart enable, ipu restart interval time */
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#define FG_NOCHANGE 0x0000
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#define FG0_CHANGE_SIZE 0x0001
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#define FG0_CHANGE_POSITION 0x0002
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#define FG1_CHANGE_SIZE 0x0010
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#define FG1_CHANGE_POSITION 0x0020
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#define FG_CHANGE_ALL ( FG0_CHANGE_SIZE | FG0_CHANGE_POSITION | \
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FG1_CHANGE_SIZE | FG1_CHANGE_POSITION )
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int fg_change;
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struct jz4750lcd_fg_t fg0; /* foreground 0 */
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struct jz4750lcd_fg_t fg1; /* foreground 1 */
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};
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struct jz4750lcd_info {
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struct jz4750lcd_panel_t panel;
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struct jz4750lcd_osd_t osd;
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};
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/* Jz LCDFB supported I/O controls. */
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#define FBIOSETBACKLIGHT 0x4688 /* set back light level */
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#define FBIODISPON 0x4689 /* display on */
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#define FBIODISPOFF 0x468a /* display off */
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#define FBIORESET 0x468b /* lcd reset */
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#define FBIOPRINT_REG 0x468c /* print lcd registers(debug) */
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#define FBIOROTATE 0x46a0 /* rotated fb */
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#define FBIOGETBUFADDRS 0x46a1 /* get buffers addresses */
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#define FBIO_GET_MODE 0x46a2 /* get lcd info */
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#define FBIO_SET_MODE 0x46a3 /* set osd mode */
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#define FBIO_DEEP_SET_MODE 0x46a4 /* set panel and osd mode */
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#define FBIO_MODE_SWITCH 0x46a5 /* switch mode between LCD and TVE */
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#define FBIO_GET_TVE_MODE 0x46a6 /* get tve info */
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#define FBIO_SET_TVE_MODE 0x46a7 /* set tve mode */
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#define FBIODISON_FG 0x46a8 /* FG display on */
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#define FBIODISOFF_FG 0x46a9 /* FG display on */
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#define FBIO_SET_LCD_TO_TVE 0x46b0 /* set lcd to tve mode */
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#define FBIO_SET_FRM_TO_LCD 0x46b1 /* set framebuffer to lcd */
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#define FBIO_SET_IPU_TO_LCD 0x46b2 /* set ipu to lcd directly */
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#define FBIO_CHANGE_SIZE 0x46b3 /* change FG size */
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#define FBIO_CHANGE_POSITION 0x46b4 /* change FG starts position */
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#define FBIO_SET_BG_COLOR 0x46b5 /* set background color */
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#define FBIO_SET_IPU_RESTART_VAL 0x46b6 /* set ipu restart value */
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#define FBIO_SET_IPU_RESTART_ON 0x46b7 /* set ipu restart on */
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#define FBIO_SET_IPU_RESTART_OFF 0x46b8 /* set ipu restart off */
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#define FBIO_ALPHA_ON 0x46b9 /* enable alpha */
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#define FBIO_ALPHA_OFF 0x46c0 /* disable alpha */
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#define FBIO_SET_ALPHA_VAL 0x46c1 /* set alpha value */
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/*
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* LCD panel specific definition
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*/
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/* AUO */
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#if defined(CONFIG_JZ4750_LCD_AUO_A043FL01V2)
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#if defined(CONFIG_JZ4750_APUS) /* board pavo */
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#define SPEN (32*3+29) /*LCD_CS*/
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#define SPCK (32*3+26) /*LCD_SCL*/
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#define SPDA (32*3+27) /*LCD_SDA*/
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#define LCD_RET (32*4+25) /*LCD_DISP_N use for lcd reset*/
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#elif defined(CONFIG_JZ4750_FUWA) /* board fuwa */
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#define SPEN (32*3+29) /*LCD_CS*/
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#define SPCK (32*3+26) /*LCD_SCL*/
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#define SPDA (32*3+27) /*LCD_SDA*/
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#define LCD_RET (32*5+2) /*LCD_DISP_N use for lcd reset*/
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#elif defined(CONFIG_JZ4750D_CETUS) /* board cetus */
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#define SPEN (32*5+13) /*LCD_CS*/
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#define SPCK (32*5+10) /*LCD_SCL*/
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#define SPDA (32*5+11) /*LCD_SDA*/
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#define LCD_RET (32*4+18) /*LCD_DISP_N use for lcd reset*/
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#else
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#error "driver/video/Jzlcd.h, please define SPI pins on your board."
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#endif
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#define __spi_write_reg(reg, val) \
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do { \
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unsigned char no; \
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unsigned short value; \
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unsigned char a=0; \
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unsigned char b=0; \
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__gpio_as_output(SPEN); /* use SPDA */ \
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__gpio_as_output(SPCK); /* use SPCK */ \
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__gpio_as_output(SPDA); /* use SPDA */ \
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a=reg; \
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b=val; \
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__gpio_set_pin(SPEN); \
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__gpio_clear_pin(SPCK); \
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udelay(50); \
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__gpio_clear_pin(SPDA); \
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__gpio_clear_pin(SPEN); \
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udelay(50); \
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value=((a<<8)|(b&0xFF)); \
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for(no=0;no<16;no++) \
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{ \
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if((value&0x8000)==0x8000){ \
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__gpio_set_pin(SPDA);} \
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else{ \
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__gpio_clear_pin(SPDA); } \
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udelay(50); \
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__gpio_set_pin(SPCK); \
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value=(value<<1); \
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udelay(50); \
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__gpio_clear_pin(SPCK); \
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} \
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__gpio_set_pin(SPEN); \
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udelay(400); \
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} while (0)
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#define __spi_read_reg(reg,val) \
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do{ \
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unsigned char no; \
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unsigned short value; \
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__gpio_as_output(SPEN); /* use SPDA */ \
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__gpio_as_output(SPCK); /* use SPCK */ \
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__gpio_as_output(SPDA); /* use SPDA */ \
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value = ((reg << 0) | (1 << 7)); \
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val = 0; \
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__gpio_as_output(SPDA); \
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__gpio_set_pin(SPEN); \
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__gpio_clear_pin(SPCK); \
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udelay(50); \
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__gpio_clear_pin(SPDA); \
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__gpio_clear_pin(SPEN); \
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udelay(50); \
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for (no = 0; no < 16; no++ ) { \
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udelay(50); \
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if(no < 8) \
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{ \
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if (value & 0x80) /* send data */ \
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__gpio_set_pin(SPDA); \
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else \
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__gpio_clear_pin(SPDA); \
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udelay(50); \
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__gpio_set_pin(SPCK); \
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value = (value << 1); \
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udelay(50); \
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__gpio_clear_pin(SPCK); \
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if(no == 7) \
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__gpio_as_input(SPDA); \
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} \
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else \
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{ \
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udelay(100); \
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__gpio_set_pin(SPCK); \
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udelay(50); \
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val = (val << 1); \
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val |= __gpio_get_pin(SPDA); \
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__gpio_clear_pin(SPCK); \
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} \
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} \
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__gpio_as_output(SPDA); \
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__gpio_set_pin(SPEN); \
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udelay(400); \
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} while(0)
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#define __lcd_special_pin_init() \
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do { \
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__gpio_as_output(SPEN); /* use SPDA */ \
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__gpio_as_output(SPCK); /* use SPCK */ \
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__gpio_as_output(SPDA); /* use SPDA */ \
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__gpio_as_output(LCD_RET); \
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udelay(50); \
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__gpio_clear_pin(LCD_RET); \
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udelay(100); \
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__gpio_set_pin(LCD_RET); \
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} while (0)
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#define __lcd_special_on() \
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do { \
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udelay(50); \
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__gpio_clear_pin(LCD_RET); \
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udelay(100); \
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__gpio_set_pin(LCD_RET); \
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} while (0)
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#define __lcd_special_off() \
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do { \
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__gpio_clear_pin(LCD_RET); \
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} while (0)
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#endif /* CONFIG_JZLCD_AUO_A030FL01_V1 */
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/* TRULY_TFTG320240DTSW */
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#if defined(CONFIG_JZ4750_LCD_TRULY_TFTG320240DTSW_16BIT) || defined(CONFIG_JZ4750_LCD_TRULY_TFTG320240DTSW_18BIT)
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#if defined(CONFIG_JZ4750_FUWA)
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#define LCD_RESET_PIN (32*3+25)// LCD_REV, GPD25
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#else
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#error "Define LCD_RESET_PIN on your board"
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#endif
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#define __lcd_special_on() \
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do { \
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__gpio_as_output(32*3+30);\
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__gpio_clear_pin(32*3+30);\
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__gpio_as_output(LCD_RESET_PIN); \
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__gpio_set_pin(LCD_RESET_PIN); \
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udelay(100); \
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__gpio_clear_pin(LCD_RESET_PIN); \
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udelay(100); \
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__gpio_set_pin(LCD_RESET_PIN); \
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} while (0)
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#endif /* CONFIG_JZ4750_LCD_TRULY_TFTG320240DTSW */
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// Wolfgang 2008.02.23
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#if defined(CONFIG_JZ4750_LCD_TOPPOLY_TD025THEA7_RGB_DELTA) || defined(CONFIG_JZ4750_LCD_TOPPOLY_TD025THEA7_RGB_DUMMY)
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#if defined(CONFIG_JZ4750_LCD_TOPPOLY_TD025THEA7_RGB_DELTA)
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#define PANEL_MODE 0x02 /* RGB Delta */
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#elif defined(CONFIG_JZ4750_LCD_TOPPOLY_TD025THEA7_RGB_DUMMY)
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#define PANEL_MODE 0x00 /* RGB Dummy */
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#endif
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#if defined(CONFIG_JZ4750_FUWA) /* board FuWa */
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#define SPEN (32*3+16) //LCD_D16 - GPD16
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#define SPCK (32*3+17) //LCD_D17 - GPD17
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#define SPDA (32*3+21) //LCD_DE - GPD21
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#define LCD_RET (32*3+25) //LCD_REV - GPD25 //use for lcd reset
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#else
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#error "please define SPI pins on your board."
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#endif
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#define __spi_write_reg1(reg, val) \
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do { \
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unsigned char no;\
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unsigned short value;\
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unsigned char a=0;\
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unsigned char b=0;\
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a=reg;\
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b=val;\
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__gpio_set_pin(SPEN);\
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udelay(100);\
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__gpio_clear_pin(SPCK);\
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__gpio_clear_pin(SPDA);\
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__gpio_clear_pin(SPEN);\
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udelay(25);\
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value=((a<<8)|(b&0xFF));\
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for(no=0;no<16;no++)\
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{\
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__gpio_clear_pin(SPCK);\
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if((value&0x8000)==0x8000)\
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__gpio_set_pin(SPDA);\
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else\
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__gpio_clear_pin(SPDA);\
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udelay(25);\
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__gpio_set_pin(SPCK);\
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value=(value<<1); \
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udelay(25);\
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}\
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__gpio_clear_pin(SPCK);\
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__gpio_set_pin(SPEN);\
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udelay(100);\
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} while (0)
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#define __spi_write_reg(reg, val) \
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do {\
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__spi_write_reg1((reg<<2), val); \
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udelay(100); \
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}while(0)
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#define __lcd_special_pin_init() \
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do { \
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__gpio_as_output(SPEN); /* use SPDA */\
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__gpio_as_output(SPCK); /* use SPCK */\
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__gpio_as_output(SPDA); /* use SPDA */\
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__gpio_as_output(SPDA); /* use reset */\
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__gpio_as_output(LCD_RET); /* use reset */\
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__gpio_set_pin(LCD_RET);\
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mdelay(15);\
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__gpio_clear_pin(LCD_RET);\
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mdelay(15);\
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__gpio_set_pin(LCD_RET);\
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} while (0)
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#define __lcd_special_on() \
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do { \
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mdelay(10); \
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__spi_write_reg(0x00, 0x10); \
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__spi_write_reg(0x01, 0xB1); \
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__spi_write_reg(0x00, 0x10); \
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__spi_write_reg(0x01, 0xB1); \
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__spi_write_reg(0x02, PANEL_MODE); /* RGBD MODE */ \
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__spi_write_reg(0x03, 0x01); /* Noninterlace*/ \
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mdelay(10); \
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} while (0)
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#define __lcd_special_off() \
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do { \
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} while (0)
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#endif /* CONFIG_JZ4750_LCD_TOPPOLY_TD025THEA7_RGB_DELTA */
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#if defined(CONFIG_JZ4750_LCD_FOXCONN_PT035TN01) || defined(CONFIG_JZ4750_LCD_INNOLUX_PT035TN01_SERIAL)
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#if defined(CONFIG_JZ4750_LCD_FOXCONN_PT035TN01) /* board FUWA */
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#define MODE 0xcd /* 24bit parellel RGB */
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#endif
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#if defined(CONFIG_JZ4750_LCD_INNOLUX_PT035TN01_SERIAL)
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#define MODE 0xc9 /* 8bit serial RGB */
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#endif
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#if defined(CONFIG_JZ4750_FUWA) /* board FuWa */
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#if 0
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#define SPEN (32*5+7) //LCD_SPL GPF7
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#define SPCK (32*5+6) //LCD_CLS GPF6
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#define SPDA (32*5+5) //LCD_PS GPF5
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#define LCD_RET (32*5+4) //LCD_REV GPF4 //use for lcd reset
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#endif
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#define SPEN (32*3+29) /*LCD_CS*/
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#define SPCK (32*3+26) /*LCD_SCL*/
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#define SPDA (32*3+27) /*LCD_SDA*/
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#define LCD_RET (32*4+25) /*LCD_DISP_N use for lcd reset*/
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#else
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#error "driver/video/Jzlcd.h, please define SPI pins on your board."
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#endif
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#define __spi_write_reg1(reg, val) \
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do { \
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unsigned char no;\
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unsigned short value;\
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unsigned char a=0;\
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unsigned char b=0;\
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a=reg;\
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b=val;\
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__gpio_set_pin(SPEN);\
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__gpio_set_pin(SPCK);\
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__gpio_clear_pin(SPDA);\
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__gpio_clear_pin(SPEN);\
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udelay(25);\
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value=((a<<8)|(b&0xFF));\
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for(no=0;no<16;no++)\
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{\
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__gpio_clear_pin(SPCK);\
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if((value&0x8000)==0x8000)\
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__gpio_set_pin(SPDA);\
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else\
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__gpio_clear_pin(SPDA);\
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udelay(25);\
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__gpio_set_pin(SPCK);\
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value=(value<<1); \
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udelay(25);\
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}\
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__gpio_set_pin(SPEN);\
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udelay(100);\
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} while (0)
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#define __spi_write_reg(reg, val) \
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do {\
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__spi_write_reg1((reg<<2|2), val); \
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udelay(100); \
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}while(0)
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#define __lcd_special_pin_init() \
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do { \
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__gpio_as_output(SPEN); /* use SPDA */\
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__gpio_as_output(SPCK); /* use SPCK */\
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__gpio_as_output(SPDA); /* use SPDA */\
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__gpio_as_output(LCD_RET);\
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udelay(50);\
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__gpio_clear_pin(LCD_RET);\
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mdelay(150);\
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__gpio_set_pin(LCD_RET);\
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} while (0)
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#define __lcd_special_on() \
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do { \
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udelay(50);\
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__gpio_clear_pin(LCD_RET);\
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mdelay(150);\
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__gpio_set_pin(LCD_RET);\
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mdelay(10);\
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__spi_write_reg(0x00, 0x03); \
|
|
__spi_write_reg(0x01, 0x40); \
|
|
__spi_write_reg(0x02, 0x11); \
|
|
__spi_write_reg(0x03, MODE); /* mode */ \
|
|
__spi_write_reg(0x04, 0x32); \
|
|
__spi_write_reg(0x05, 0x0e); \
|
|
__spi_write_reg(0x07, 0x03); \
|
|
__spi_write_reg(0x08, 0x08); \
|
|
__spi_write_reg(0x09, 0x32); \
|
|
__spi_write_reg(0x0A, 0x88); \
|
|
__spi_write_reg(0x0B, 0xc6); \
|
|
__spi_write_reg(0x0C, 0x20); \
|
|
__spi_write_reg(0x0D, 0x20); \
|
|
} while (0) //reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level
|
|
|
|
/* __spi_write_reg(0x02, 0x03); \
|
|
__spi_write_reg(0x06, 0x40); \
|
|
__spi_write_reg(0x0a, 0x11); \
|
|
__spi_write_reg(0x0e, 0xcd); \
|
|
__spi_write_reg(0x12, 0x32); \
|
|
__spi_write_reg(0x16, 0x0e); \
|
|
__spi_write_reg(0x1e, 0x03); \
|
|
__spi_write_reg(0x22, 0x08); \
|
|
__spi_write_reg(0x26, 0x40); \
|
|
__spi_write_reg(0x2a, 0x88); \
|
|
__spi_write_reg(0x2e, 0x88); \
|
|
__spi_write_reg(0x32, 0x20); \
|
|
__spi_write_reg(0x36, 0x20); \
|
|
*/
|
|
// } while (0) //reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level
|
|
|
|
#define __lcd_special_off() \
|
|
do { \
|
|
__spi_write_reg(0x00, 0x03); \
|
|
} while (0)
|
|
|
|
#endif /* CONFIG_JZ4750_LCD_FOXCONN_PT035TN01 or CONFIG_JZ4750_LCD_INNOLUX_PT035TN01_SERIAL */
|
|
|
|
#if defined(CONFIG_JZ4750_LCD_TRULY_TFT_GG1P0319LTSW_W)
|
|
static inline void CmdWrite(unsigned int cmd)
|
|
{
|
|
while (REG_SLCD_STATE & SLCD_STATE_BUSY); /* wait slcd ready */
|
|
udelay(30);
|
|
REG_SLCD_DATA = SLCD_DATA_RS_COMMAND | cmd;
|
|
}
|
|
|
|
static inline void DataWrite(unsigned int data)
|
|
{
|
|
while (REG_SLCD_STATE & SLCD_STATE_BUSY); /* wait slcd ready */
|
|
// udelay(30);
|
|
REG_SLCD_DATA = SLCD_DATA_RS_DATA | data;
|
|
}
|
|
|
|
|
|
static inline void delay(long delay_time)
|
|
{
|
|
long cnt;
|
|
|
|
// delay_time *= (384/8);
|
|
delay_time *= (43/8);
|
|
|
|
for (cnt=0;cnt<delay_time;cnt++)
|
|
{
|
|
asm("nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
"nop\n"
|
|
);
|
|
}
|
|
}
|
|
|
|
|
|
/*---- LCD Initial ----*/
|
|
static void SlcdInit(void)
|
|
{
|
|
delay(10000);
|
|
CmdWrite(0x0301); //reset
|
|
delay(10000);
|
|
CmdWrite(0x0101);
|
|
CmdWrite(0x0301);
|
|
CmdWrite(0x0008);
|
|
CmdWrite(0x2201); //reset
|
|
CmdWrite(0x0000);
|
|
CmdWrite(0x0080); //0x0020
|
|
delay(10000);
|
|
|
|
CmdWrite(0x2809);
|
|
CmdWrite(0x1900);
|
|
CmdWrite(0x2110);
|
|
CmdWrite(0x1805);
|
|
CmdWrite(0x1E01);
|
|
CmdWrite(0x1847);
|
|
delay(1000);
|
|
CmdWrite(0x1867);
|
|
delay(10000);
|
|
CmdWrite(0x18F7);
|
|
delay(10000);
|
|
CmdWrite(0x2100);
|
|
CmdWrite(0x2809);
|
|
CmdWrite(0x1a05);
|
|
CmdWrite(0x1900);
|
|
CmdWrite(0x1f64);
|
|
CmdWrite(0x2070);
|
|
CmdWrite(0x1e81);
|
|
CmdWrite(0x1b01);
|
|
|
|
CmdWrite(0x0200);
|
|
CmdWrite(0x0504); //y address increcement
|
|
CmdWrite(0x0D00); //*240
|
|
CmdWrite(0x1D08);
|
|
CmdWrite(0x2300);
|
|
CmdWrite(0x2D01);
|
|
CmdWrite(0x337F);
|
|
CmdWrite(0x3400);
|
|
CmdWrite(0x3501);
|
|
CmdWrite(0x3700);
|
|
CmdWrite(0x42ef); //x start from 239
|
|
CmdWrite(0x4300);
|
|
CmdWrite(0x4400); //y start from 0
|
|
CmdWrite(0x4500);
|
|
CmdWrite(0x46EF);
|
|
CmdWrite(0x4700);
|
|
CmdWrite(0x4800);
|
|
CmdWrite(0x4901);
|
|
CmdWrite(0x4A3F);
|
|
CmdWrite(0x4B00);
|
|
CmdWrite(0x4C00);
|
|
CmdWrite(0x4D00);
|
|
CmdWrite(0x4E00);
|
|
CmdWrite(0x4F00);
|
|
CmdWrite(0x5000);
|
|
CmdWrite(0x7600);
|
|
CmdWrite(0x8600);
|
|
CmdWrite(0x8720);
|
|
CmdWrite(0x8802);
|
|
CmdWrite(0x8903);
|
|
CmdWrite(0x8D40);
|
|
CmdWrite(0x8F05);
|
|
CmdWrite(0x9005);
|
|
CmdWrite(0x9144);
|
|
CmdWrite(0x9244);
|
|
CmdWrite(0x9344);
|
|
CmdWrite(0x9433);
|
|
CmdWrite(0x9505);
|
|
CmdWrite(0x9605);
|
|
CmdWrite(0x9744);
|
|
CmdWrite(0x9844);
|
|
CmdWrite(0x9944);
|
|
CmdWrite(0x9A33);
|
|
CmdWrite(0x9B33);
|
|
CmdWrite(0x9C33);
|
|
//==> SETP 3
|
|
CmdWrite(0x0000);
|
|
CmdWrite(0x01A0);
|
|
CmdWrite(0x3B01);
|
|
|
|
CmdWrite(0x2809);
|
|
delay(1000);
|
|
CmdWrite(0x1900);
|
|
delay(1000);
|
|
CmdWrite(0x2110);
|
|
delay(1000);
|
|
CmdWrite(0x1805);
|
|
delay(1000);
|
|
CmdWrite(0x1E01);
|
|
delay(1000);
|
|
CmdWrite(0x1847);
|
|
delay(1000);
|
|
CmdWrite(0x1867);
|
|
delay(1000);
|
|
CmdWrite(0x18F7);
|
|
delay(1000);
|
|
CmdWrite(0x2100);
|
|
delay(1000);
|
|
CmdWrite(0x2809);
|
|
delay(1000);
|
|
CmdWrite(0x1A05);
|
|
delay(1000);
|
|
CmdWrite(0x19E8);
|
|
delay(1000);
|
|
CmdWrite(0x1F64);
|
|
delay(1000);
|
|
CmdWrite(0x2045);
|
|
delay(1000);
|
|
CmdWrite(0x1E81);
|
|
delay(1000);
|
|
CmdWrite(0x1B09);
|
|
delay(1000);
|
|
CmdWrite(0x0020);
|
|
delay(1000);
|
|
CmdWrite(0x0120);
|
|
delay(1000);
|
|
|
|
CmdWrite(0x3B01);
|
|
delay(1000);
|
|
|
|
/* Set Window(239,319), Set Cursor(239,319) */
|
|
CmdWrite(0x0510);
|
|
CmdWrite(0x01C0);
|
|
CmdWrite(0x4500);
|
|
CmdWrite(0x46EF);
|
|
CmdWrite(0x4800);
|
|
CmdWrite(0x4700);
|
|
CmdWrite(0x4A3F);
|
|
CmdWrite(0x4901);
|
|
CmdWrite(0x42EF);
|
|
CmdWrite(0x443F);
|
|
CmdWrite(0x4301);
|
|
|
|
}
|
|
|
|
#if defined(CONFIG_JZ4750_FUWA)
|
|
//#define PIN_CS_N (32*2+xx) /* a low voltage */
|
|
#define PIN_RD_N (32*3+21) /* LCD_DE: GP D21, a high voltage */
|
|
#define PIN_RESET_N (32*3+25) /* LCD_REV GP D25 */
|
|
#else
|
|
#error "Define special lcd pins for your platform."
|
|
#endif
|
|
|
|
#define __lcd_slcd_pin_init() \
|
|
do { \
|
|
__gpio_as_output(PIN_RD_N); /* RD#: LCD_REV */ \
|
|
__gpio_as_output(PIN_RESET_N); /* RESET#: LCD_SPL */ \
|
|
__gpio_set_pin(PIN_RD_N); /*set read signal high */ \
|
|
__gpio_set_pin(PIN_RESET_N); \
|
|
mdelay(100); \
|
|
__gpio_clear_pin(PIN_RESET_N); \
|
|
mdelay(100); \
|
|
__gpio_set_pin(PIN_RESET_N); \
|
|
/* Configure SLCD module */ \
|
|
REG_LCD_CTRL &= ~(LCD_CTRL_ENA|LCD_CTRL_DIS); /* disable lcdc */ \
|
|
REG_LCD_CFG = LCD_CFG_LCDPIN_SLCD | 0x0D; /* LCM */ \
|
|
REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; /* disable slcd dma */ \
|
|
REG_SLCD_CFG = SLCD_CFG_DWIDTH_16BIT | SLCD_CFG_CWIDTH_16BIT | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | SLCD_CFG_TYPE_PARALLEL; \
|
|
REG_LCD_REV = 0x04; /* lcd clock??? */ \
|
|
printk("Fuwa test, pixclk divide REG_LCD_REV=0x%08x\n", REG_LCD_REV); \
|
|
}while (0)
|
|
|
|
#define __lcd_slcd_special_on() \
|
|
do { \
|
|
__lcd_slcd_pin_init(); \
|
|
SlcdInit(); \
|
|
REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN; /* slcdc dma enable */ \
|
|
} while (0)
|
|
|
|
#endif /* #if CONFIG_JZ4750_LCD_TRULY_TFT_GG1P0319LTSW_W */
|
|
|
|
#ifndef __lcd_special_pin_init
|
|
#define __lcd_special_pin_init()
|
|
#endif
|
|
#ifndef __lcd_special_on
|
|
#define __lcd_special_on()
|
|
#endif
|
|
#ifndef __lcd_special_off
|
|
#define __lcd_special_off()
|
|
#endif
|
|
|
|
|
|
/*
|
|
* Platform specific definition
|
|
*/
|
|
#if defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
|
|
|
|
#if defined(CONFIG_JZ4750_APUS) /* board apus */
|
|
#define __lcd_display_pin_init() \
|
|
do { \
|
|
__gpio_as_output(GPIO_LCD_VCC_EN_N); \
|
|
__lcd_special_pin_init(); \
|
|
} while (0)
|
|
#define __lcd_display_on() \
|
|
do { \
|
|
__gpio_clear_pin(GPIO_LCD_VCC_EN_N); \
|
|
__lcd_special_on(); \
|
|
mdelay(200); \
|
|
__lcd_set_backlight_level(80); \
|
|
} while (0)
|
|
|
|
#define __lcd_display_off() \
|
|
do { \
|
|
__lcd_close_backlight(); \
|
|
__lcd_special_off(); \
|
|
} while (0)
|
|
|
|
#elif defined(CONFIG_JZ4750D_CETUS)/* board apus */
|
|
|
|
#define __lcd_display_pin_init() \
|
|
do { \
|
|
__gpio_as_output(GPIO_LCD_VCC_EN_N); \
|
|
__lcd_special_pin_init(); \
|
|
} while (0)
|
|
#define __lcd_display_on() \
|
|
do { \
|
|
__gpio_set_pin(GPIO_LCD_VCC_EN_N); \
|
|
__lcd_special_on(); \
|
|
__lcd_set_backlight_level(80); \
|
|
} while (0)
|
|
|
|
#define __lcd_display_off() \
|
|
do { \
|
|
__lcd_close_backlight(); \
|
|
__lcd_special_off(); \
|
|
} while (0)
|
|
|
|
#else /* other boards */
|
|
|
|
#define __lcd_display_pin_init() \
|
|
do { \
|
|
__lcd_special_pin_init(); \
|
|
} while (0)
|
|
#define __lcd_display_on() \
|
|
do { \
|
|
__lcd_special_on(); \
|
|
__lcd_set_backlight_level(80); \
|
|
} while (0)
|
|
|
|
#define __lcd_display_off() \
|
|
do { \
|
|
__lcd_close_backlight(); \
|
|
__lcd_special_off(); \
|
|
} while (0)
|
|
#endif /* APUS */
|
|
#endif /* CONFIG_SOC_JZ4750 */
|
|
|
|
|
|
/*****************************************************************************
|
|
* LCD display pin dummy macros
|
|
*****************************************************************************/
|
|
|
|
#ifndef __lcd_display_pin_init
|
|
#define __lcd_display_pin_init()
|
|
#endif
|
|
#ifndef __lcd_slcd_special_on
|
|
#define __lcd_slcd_special_on()
|
|
#endif
|
|
#ifndef __lcd_display_on
|
|
#define __lcd_display_on()
|
|
#endif
|
|
#ifndef __lcd_display_off
|
|
#define __lcd_display_off()
|
|
#endif
|
|
#ifndef __lcd_set_backlight_level
|
|
#define __lcd_set_backlight_level(n)
|
|
#endif
|
|
|
|
#endif /* __JZ4750_LCD_H__ */
|