mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 10:42:49 +02:00
85ec5ce98d
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29007 3c298f89-4303-0410-b956-a3cf2f4a3e73
254 lines
8.1 KiB
Diff
254 lines
8.1 KiB
Diff
From e2d5b4ba92289cb0fcc9db741d159ef5eb852d9f Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 27 Aug 2011 20:08:14 +0200
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Subject: [PATCH 16/24] MIPS: lantiq: adds xway nand driver
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This patch adds a nand driver for XWAY SoCs. The patch makes use of the
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plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the
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endianess swap problem on read. To workaround this problem we make the
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read_byte() callback available via the plat_nand driver causing the nand
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layer to do byte reads.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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TODO : memory ranges
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cs lines
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plat dev
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ebu2 and not ebu1 ?
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +
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arch/mips/lantiq/xway/Makefile | 2 +-
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arch/mips/lantiq/xway/nand.c | 185 ++++++++++++++++++++
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drivers/mtd/nand/plat_nand.c | 1 +
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include/linux/mtd/nand.h | 1 +
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5 files changed, 190 insertions(+), 1 deletions(-)
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create mode 100644 arch/mips/lantiq/xway/nand.c
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -138,6 +138,8 @@
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/* register access macros for EBU and CGU */
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#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
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#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
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+#define ltq_ebu_w32_mask(x, y, z) \
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+ ltq_w32_mask(x, y, ltq_ebu_membase + (z))
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#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
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#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
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--- a/arch/mips/lantiq/xway/Makefile
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+++ b/arch/mips/lantiq/xway/Makefile
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@@ -1,4 +1,4 @@
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-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
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+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o
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obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
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obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/nand.c
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@@ -0,0 +1,185 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/mtd/physmap.h>
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+#include <linux/mtd/nand.h>
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+#include <linux/platform_device.h>
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+
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+#include <lantiq_soc.h>
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+#include <lantiq_irq.h>
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+#include <lantiq_platform.h>
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+
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+#include "devices.h"
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+
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+/* nand registers */
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+#define LTQ_EBU_NAND_WAIT 0xB4
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+#define LTQ_EBU_NAND_ECC0 0xB8
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+#define LTQ_EBU_NAND_ECC_AC 0xBC
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+#define LTQ_EBU_NAND_CON 0xB0
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+#define LTQ_EBU_ADDSEL1 0x24
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+
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+/* gpio definitions */
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+#define PIN_ALE 13
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+#define PIN_CLE 24
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+#define PIN_CS1 23
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+#define PIN_RDY 48 /* NFLASH_READY */
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+#define PIN_RD 49 /* NFLASH_READ_N */
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+
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+#define NAND_CMD_ALE (1 << 2)
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+#define NAND_CMD_CLE (1 << 3)
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+#define NAND_CMD_CS (1 << 4)
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+#define NAND_WRITE_CMD_RESET 0xff
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+#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
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+#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
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+#define NAND_WRITE_DATA (NAND_CMD_CS)
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+#define NAND_READ_DATA (NAND_CMD_CS)
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+#define NAND_WAIT_WR_C (1 << 3)
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+#define NAND_WAIT_RD (0x1)
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+
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+#define ADDSEL1_MASK(x) (x << 4)
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+#define ADDSEL1_REGEN 1
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+#define BUSCON1_SETUP (1 << 22)
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+#define BUSCON1_BCGEN_RES (0x3 << 12)
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+#define BUSCON1_WAITWRC2 (2 << 8)
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+#define BUSCON1_WAITRDC2 (2 << 6)
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+#define BUSCON1_HOLDC1 (1 << 4)
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+#define BUSCON1_RECOVC1 (1 << 2)
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+#define BUSCON1_CMULT4 1
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+#define NAND_CON_NANDM 1
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+#define NAND_CON_CSMUX (1 << 1)
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+#define NAND_CON_CS_P (1 << 4)
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+#define NAND_CON_SE_P (1 << 5)
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+#define NAND_CON_WP_P (1 << 6)
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+#define NAND_CON_PRE_P (1 << 7)
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+#define NAND_CON_IN_CS0 0
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+#define NAND_CON_OUT_CS0 0
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+#define NAND_CON_IN_CS1 (1 << 8)
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+#define NAND_CON_OUT_CS1 (1 << 10)
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+#define NAND_CON_CE (1 << 20)
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+
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+#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000)
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+
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+static const char *part_probes[] = { "cmdlinepart", NULL };
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+
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+static void
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+xway_select_chip(struct mtd_info *mtd, int chip)
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+{
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+ switch (chip) {
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+ case -1:
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+ ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON);
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+ ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON);
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+ break;
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+ case 0:
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+ ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON);
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+ ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON);
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+ /* reset the nand chip */
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+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
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+ ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
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+ break;
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+ default:
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+ BUG();
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+ }
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+}
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+
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+static void
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+xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
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+{
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+ struct nand_chip *this = mtd->priv;
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+
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+ if (ctrl & NAND_CTRL_CHANGE) {
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+ if(ctrl & NAND_CLE)
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+ this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_CMD);
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+ else if(ctrl & NAND_ALE)
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+ this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_ADDR);
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+ }
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+
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+ if(data != NAND_CMD_NONE) {
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+ *(volatile u8*)((u32)this->IO_ADDR_W) = data;
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+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
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+ }
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+}
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+
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+static int
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+xway_dev_ready(struct mtd_info *mtd)
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+{
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+ return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD;
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+}
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+
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+void
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+nand_write(unsigned int addr, unsigned int val)
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+{
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+ ltq_w32(val, ((u32*)(NAND_BASE_ADDRESS | addr)));
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+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
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+}
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+
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+unsigned char
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+ltq_nand_read_byte(struct mtd_info *mtd)
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+{
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+ return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
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+}
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+
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+int xway_nand_probe(struct platform_device *pdev)
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+{
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+// ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1");
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+ ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE");
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+ ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE");
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+ if (ltq_is_ar9() || ltq_is_vr9()) {
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+ ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY");
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+ ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD");
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+ }
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+
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+ ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
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+ | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
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+
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+ ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
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+ | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
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+ | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
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+
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+ ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
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+ | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
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+ | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
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+
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+ ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
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+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
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+
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+ return 0;
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+}
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+
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+static struct platform_nand_data falcon_flash_nand_data = {
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+ .chip = {
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+ .nr_chips = 1,
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+ .chip_delay = 30,
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+ .part_probe_types = part_probes,
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+ },
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+ .ctrl = {
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+ .probe = xway_nand_probe,
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+ .cmd_ctrl = xway_cmd_ctrl,
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+ .dev_ready = xway_dev_ready,
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+ .select_chip = xway_select_chip,
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+ .read_byte = ltq_nand_read_byte,
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+ }
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+};
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+
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+static struct resource ltq_nand_res =
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+ MEM_RES("nand", 0x14000000, 0x3ffffff);
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+
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+static struct platform_device ltq_flash_nand = {
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+ .name = "gen_nand",
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+ .id = -1,
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+ .num_resources = 1,
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+ .resource = <q_nand_res,
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+ .dev = {
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+ .platform_data = &falcon_flash_nand_data,
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+ },
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+};
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+
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+void __init
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+xway_register_nand(void)
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+{
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+ platform_device_register(<q_flash_nand);
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+}
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--- a/drivers/mtd/nand/plat_nand.c
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+++ b/drivers/mtd/nand/plat_nand.c
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@@ -77,6 +77,7 @@ static int __devinit plat_nand_probe(str
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data->chip.select_chip = pdata->ctrl.select_chip;
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data->chip.write_buf = pdata->ctrl.write_buf;
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data->chip.read_buf = pdata->ctrl.read_buf;
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+ data->chip.read_byte = pdata->ctrl.read_byte;
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data->chip.chip_delay = pdata->chip.chip_delay;
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data->chip.options |= pdata->chip.options;
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--- a/include/linux/mtd/nand.h
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+++ b/include/linux/mtd/nand.h
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@@ -657,6 +657,7 @@ struct platform_nand_ctrl {
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void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
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void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
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void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
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+ unsigned char (*read_byte)(struct mtd_info *mtd);
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void *priv;
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};
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