mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 21:16:27 +02:00
bbb153176f
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31222 3c298f89-4303-0410-b956-a3cf2f4a3e73
352 lines
11 KiB
Diff
352 lines
11 KiB
Diff
From 27ff621cd9a5347efda4be502abbef13a99146ce Mon Sep 17 00:00:00 2001
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From: Maarten ter Huurne <maarten@treewalker.org>
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Date: Sun, 29 Aug 2010 08:11:00 +0200
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Subject: [PATCH 11/21] MIPS: JZ4740: Added setting of PLL rate and main
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dividers.
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This functionality makes a cpufreq driver possible.
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Squashed version of the development done in the jz-2.6.39 branch.
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---
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arch/mips/jz4740/clock.c | 230 ++++++++++++++++++++++++++++++++++++++++++++--
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arch/mips/jz4740/clock.h | 4 +
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2 files changed, 224 insertions(+), 10 deletions(-)
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--- a/arch/mips/jz4740/clock.c
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+++ b/arch/mips/jz4740/clock.c
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@@ -1,5 +1,8 @@
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/*
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+ * Copyright (c) 2006-2007, Ingenic Semiconductor Inc.
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * Copyright (c) 2010, Ulrich Hecht <ulrich.hecht@gmail.com>
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+ * Copyright (c) 2010, Maarten ter Huurne <maarten@treewalker.org>
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* JZ4740 SoC clock support
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*
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* This program is free software; you can redistribute it and/or modify it
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@@ -41,16 +44,20 @@
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#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31)
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#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30)
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#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29)
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-#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000
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#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22)
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#define JZ_CLOCK_CTRL_PLL_HALF BIT(21)
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-#define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000
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#define JZ_CLOCK_CTRL_UDIV_OFFSET 23
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#define JZ_CLOCK_CTRL_LDIV_OFFSET 16
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#define JZ_CLOCK_CTRL_MDIV_OFFSET 12
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#define JZ_CLOCK_CTRL_PDIV_OFFSET 8
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#define JZ_CLOCK_CTRL_HDIV_OFFSET 4
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#define JZ_CLOCK_CTRL_CDIV_OFFSET 0
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+#define JZ_CLOCK_CTRL_UDIV_MASK (0x3f << JZ_CLOCK_CTRL_UDIV_OFFSET)
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+#define JZ_CLOCK_CTRL_LDIV_MASK (0x1f << JZ_CLOCK_CTRL_LDIV_OFFSET)
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+#define JZ_CLOCK_CTRL_MDIV_MASK (0x0f << JZ_CLOCK_CTRL_MDIV_OFFSET)
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+#define JZ_CLOCK_CTRL_PDIV_MASK (0x0f << JZ_CLOCK_CTRL_PDIV_OFFSET)
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+#define JZ_CLOCK_CTRL_HDIV_MASK (0x0f << JZ_CLOCK_CTRL_HDIV_OFFSET)
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+#define JZ_CLOCK_CTRL_CDIV_MASK (0x0f << JZ_CLOCK_CTRL_CDIV_OFFSET)
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#define JZ_CLOCK_GATE_UART0 BIT(0)
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#define JZ_CLOCK_GATE_TCU BIT(1)
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@@ -90,6 +97,7 @@
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#define JZ_CLOCK_PLL_M_OFFSET 23
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#define JZ_CLOCK_PLL_N_OFFSET 18
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#define JZ_CLOCK_PLL_OD_OFFSET 16
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+#define JZ_CLOCK_PLL_STABILIZE_OFFSET 0
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#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
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#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
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@@ -97,10 +105,15 @@
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#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7)
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#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6)
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+#define JZ_REG_EMC_RTCNT 0x88
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+#define JZ_REG_EMC_RTCOR 0x8C
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+
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static void __iomem *jz_clock_base;
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static spinlock_t jz_clock_lock;
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static LIST_HEAD(jz_clocks);
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+static void __iomem *jz_emc_base;
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+
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struct main_clk {
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struct clk clk;
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uint32_t div_offset;
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@@ -204,25 +217,88 @@ static int jz_clk_ko_is_enabled(struct c
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return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
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}
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+static struct static_clk jz_clk_ext;
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+
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+static unsigned long jz_clk_pll_calc_rate(
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+ unsigned int in_div, unsigned int feedback, unsigned int out_div)
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+{
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+ return ((jz_clk_ext.rate / in_div) * feedback) / out_div;
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+}
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+
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+static void jz_clk_pll_calc_dividers(unsigned long rate,
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+ unsigned int *in_div, unsigned int *feedback, unsigned int *out_div)
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+{
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+ unsigned int target;
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+
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+ /* The frequency after the input divider must be between 1 and 15 MHz.
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+ The highest divider yields the best resolution. */
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+ *in_div = jz_clk_ext.rate / 1000000;
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+ if (*in_div >= 34)
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+ *in_div = 33;
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+
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+ /* The frequency before the output divider must be between 100 and
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+ 500 MHz. The lowest target rate is more energy efficient. */
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+ if (rate < 25000000) {
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+ *out_div = 4;
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+ target = 25000000 * 4;
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+ } else if (rate <= 50000000) {
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+ *out_div = 4;
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+ target = rate * 4;
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+ } else if (rate <= 100000000) {
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+ *out_div = 2;
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+ target = rate * 2;
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+ } else if (rate <= 500000000) {
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+ *out_div = 1;
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+ target = rate;
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+ } else {
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+ *out_div = 1;
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+ target = 500000000;
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+ }
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+
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+ /* Compute the feedback divider.
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+ Since the divided input is at least 1 MHz and the target frequency
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+ at most 500 MHz, the feedback will be at most 500 and will therefore
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+ always fit in the 9-bit register.
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+ Similarly, the divided input is at most 15 MHz and the target
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+ frequency at least 100 MHz, so the feedback will be at least 6
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+ where the minimum supported value is 2. */
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+ *feedback = ((target / 1000) * *in_div) / (jz_clk_ext.rate / 1000);
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+}
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+
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+static unsigned long jz_clk_pll_round_rate(struct clk *clk, unsigned long rate)
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+{
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+ unsigned int in_div, feedback, out_div;
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+ /* The PLL frequency must be a multiple of 24 MHz, since the LCD pixel
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+ * clock must be exactly 12 MHz for the TV-out to work.
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+ * TODO: A multiple of 12 MHz for the PLL would work if the PLL would
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+ * not be divided by 2 before being passed to the set of derived
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+ * clocks that includes the LCD pixel clock.
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+ * TODO: Systemwide decisions like this should be made by the board
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+ * support code, so add some kind of hook for that.
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+ */
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+ unsigned long rate24 = (rate / 24000000) * 24000000;
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+
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+ jz_clk_pll_calc_dividers(rate24, &in_div, &feedback, &out_div);
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+ return jz_clk_pll_calc_rate(in_div, feedback, out_div);
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+}
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+
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static const int pllno[] = {1, 2, 2, 4};
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static unsigned long jz_clk_pll_get_rate(struct clk *clk)
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{
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uint32_t val;
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- int m;
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- int n;
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- int od;
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+ unsigned int in_div, feedback, out_div;
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val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
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if (val & JZ_CLOCK_PLL_BYPASS)
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return clk_get_rate(clk->parent);
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- m = ((val >> 23) & 0x1ff) + 2;
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- n = ((val >> 18) & 0x1f) + 2;
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- od = (val >> 16) & 0x3;
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+ feedback = ((val >> 23) & 0x1ff) + 2;
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+ in_div = ((val >> 18) & 0x1f) + 2;
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+ out_div = pllno[(val >> 16) & 0x3];
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- return ((clk_get_rate(clk->parent) / n) * m) / pllno[od];
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+ return jz_clk_pll_calc_rate(in_div, feedback, out_div);
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}
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static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
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@@ -235,7 +311,77 @@ static unsigned long jz_clk_pll_half_get
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return jz_clk_pll_get_rate(clk->parent) >> 1;
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}
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-static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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+#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
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+
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+static void sdram_set_pll(unsigned int pllin)
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+{
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+ unsigned int ns, sdramclock;
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+
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+ ns = 1000000000 / pllin;
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+ sdramclock = (SDRAM_TREF / ns) / 64 + 1;
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+ if (sdramclock > 0xff) sdramclock = 0xff;
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+ /* Set refresh registers */
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+ writew(sdramclock, jz_emc_base + JZ_REG_EMC_RTCOR);
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+ writew(sdramclock, jz_emc_base + JZ_REG_EMC_RTCNT);
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+}
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+
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+static int jz_clk_pll_set_rate(struct clk *clk, unsigned long rate)
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+{
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+ unsigned int ctrl, plcr1;
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+ unsigned int feedback, in_div, out_div, pllout, pllout2;
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+
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+ jz_clk_pll_calc_dividers(rate, &in_div, &feedback, &out_div);
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+
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+ ctrl = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
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+ pllout = jz_clk_pll_calc_rate(in_div, feedback, out_div);
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+ pllout2 = (ctrl & JZ_CLOCK_CTRL_PLL_HALF) ? pllout : (pllout / 2);
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+
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+ /* Init UHC clock */
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+ writel(pllout2 / 48000000 - 1, jz_clock_base + JZ_REG_CLOCK_UHC);
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+
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+ plcr1 = ((feedback - 2) << JZ_CLOCK_PLL_M_OFFSET) |
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+ ((in_div - 2) << JZ_CLOCK_PLL_N_OFFSET) |
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+ ((out_div - 1) << JZ_CLOCK_PLL_OD_OFFSET) |
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+ (0x20 << JZ_CLOCK_PLL_STABILIZE_OFFSET) |
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+ JZ_CLOCK_PLL_ENABLED;
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+
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+ sdram_set_pll(pllout);
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+
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+ /* LCD pixclock */
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+ writel(pllout2 / 12000000 - 1, jz_clock_base + JZ_REG_CLOCK_LCD);
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+
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+ /* configure PLL */
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+ __asm__ __volatile__(
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+ ".set noreorder\n\t"
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+ ".align 5\n"
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+ "sw %1,0(%0)\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ ".set reorder\n\t"
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+ :
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+ : "r" (jz_clock_base + JZ_REG_CLOCK_PLL), "r" (plcr1));
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+
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+ /* MtH: For some reason the MSC will have problems if this flag is not
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+ restored, even though the MSC is supposedly the only divider
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+ that is not affected by this flag. */
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+ jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_CHANGE_ENABLE);
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+
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+ return 0;
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+}
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+
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+static const unsigned int jz_clk_main_divs[] = {
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+ 1, 2, 3, 4, 6, 8, 12, 16, 24, 32
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+};
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+static const unsigned int jz_clk_main_divs_inv[] = {
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+ -1, 0, 1, 2, 3, -1, 4, -1, 5, -1, -1, -1, 6, -1, -1, -1,
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+ 7, -1, -1, -1, -1, -1, -1, -1, 8, -1, -1, -1, -1, -1, -1, -1,
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+ 9
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+};
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static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
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{
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@@ -290,6 +436,64 @@ static int jz_clk_main_set_rate(struct c
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return 0;
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}
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+static struct main_clk jz_clk_cpu;
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+
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+int clk_main_set_dividers(bool immediate, unsigned int cdiv, unsigned int hdiv,
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+ unsigned int mdiv, unsigned int pdiv)
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+{
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+ unsigned int cdiv_enc, hdiv_enc, mdiv_enc, pdiv_enc;
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+ unsigned int ctrl;
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+ unsigned int tmp, wait;
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+
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+ if (cdiv >= ARRAY_SIZE(jz_clk_main_divs_inv) ||
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+ hdiv >= ARRAY_SIZE(jz_clk_main_divs_inv) ||
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+ mdiv >= ARRAY_SIZE(jz_clk_main_divs_inv) ||
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+ pdiv >= ARRAY_SIZE(jz_clk_main_divs_inv))
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+ return -EINVAL;
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+ cdiv_enc = jz_clk_main_divs_inv[cdiv];
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+ hdiv_enc = jz_clk_main_divs_inv[hdiv];
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+ mdiv_enc = jz_clk_main_divs_inv[mdiv];
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+ pdiv_enc = jz_clk_main_divs_inv[pdiv];
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+ if (cdiv_enc == (unsigned int)-1 ||
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+ hdiv_enc == (unsigned int)-1 ||
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+ mdiv_enc == (unsigned int)-1 ||
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+ pdiv_enc == (unsigned int)-1)
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+ return -EINVAL;
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+
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+ ctrl = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
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+ ctrl &= ~(JZ_CLOCK_CTRL_CHANGE_ENABLE |
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+ JZ_CLOCK_CTRL_CDIV_MASK | JZ_CLOCK_CTRL_HDIV_MASK |
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+ JZ_CLOCK_CTRL_MDIV_MASK | JZ_CLOCK_CTRL_PDIV_MASK);
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+ if (immediate) ctrl |= JZ_CLOCK_CTRL_CHANGE_ENABLE;
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+ ctrl |= (cdiv_enc << JZ_CLOCK_CTRL_CDIV_OFFSET) |
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+ (hdiv_enc << JZ_CLOCK_CTRL_HDIV_OFFSET) |
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+ (mdiv_enc << JZ_CLOCK_CTRL_MDIV_OFFSET) |
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+ (pdiv_enc << JZ_CLOCK_CTRL_PDIV_OFFSET);
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+
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+ /* set dividers */
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+ /* delay loops lifted from the old Ingenic cpufreq driver */
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+ wait = ((clk_get_rate(&jz_clk_cpu.clk) / 1000000) * 500) / 1000;
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+ __asm__ __volatile__(
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+ ".set noreorder\n\t"
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+ ".align 5\n"
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+ "sw %2,0(%1)\n\t"
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+ "li %0,0\n\t"
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+ "1:\n\t"
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+ "bne %0,%3,1b\n\t"
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+ "addi %0, 1\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ "nop\n\t"
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+ ".set reorder\n\t"
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+ : "=r" (tmp)
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+ : "r" (jz_clock_base + JZ_REG_CLOCK_CTRL), "r" (ctrl),
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+ "r" (wait));
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(clk_main_set_dividers);
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+
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static struct clk_ops jz_clk_static_ops = {
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.get_rate = jz_clk_static_get_rate,
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.enable = jz_clk_enable_gating,
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@@ -307,6 +511,8 @@ static struct static_clk jz_clk_ext = {
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static struct clk_ops jz_clk_pll_ops = {
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.get_rate = jz_clk_pll_get_rate,
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+ .set_rate = jz_clk_pll_set_rate,
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+ .round_rate = jz_clk_pll_round_rate,
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};
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static struct clk jz_clk_pll = {
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@@ -897,6 +1103,10 @@ static int jz4740_clock_init(void)
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if (!jz_clock_base)
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return -EBUSY;
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+ jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
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+ if (!jz_emc_base)
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+ return -EBUSY;
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+
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spin_lock_init(&jz_clock_lock);
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jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
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--- a/arch/mips/jz4740/clock.h
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+++ b/arch/mips/jz4740/clock.h
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@@ -17,6 +17,7 @@
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#define __MIPS_JZ4740_CLOCK_H__
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#include <linux/list.h>
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+#include <linux/types.h>
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struct jz4740_clock_board_data {
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unsigned long ext_rate;
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@@ -63,6 +64,9 @@ struct clk {
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int clk_is_enabled(struct clk *clk);
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+int clk_main_set_dividers(bool immediate, unsigned int cdiv, unsigned int hdiv,
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+ unsigned int mdiv, unsigned int pdiv);
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+
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#ifdef CONFIG_DEBUG_FS
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void jz4740_clock_debugfs_init(void);
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void jz4740_clock_debugfs_add_clk(struct clk *clk);
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