mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 00:30:37 +02:00
414e59d258
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19358 3c298f89-4303-0410-b956-a3cf2f4a3e73
658 lines
18 KiB
Diff
658 lines
18 KiB
Diff
From 42789dfb077bb7b640ee19d0e3f7808dc5318adf Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Mon, 11 Jan 2010 04:29:35 +0100
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Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-core.patch
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---
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arch/mips/Kconfig | 29 ++++
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arch/mips/Makefile | 18 +++
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arch/mips/boot/Makefile | 23 +++-
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arch/mips/include/asm/bootinfo.h | 6 +
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arch/mips/include/asm/cpu.h | 13 ++-
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arch/mips/include/asm/mach-generic/irq.h | 2 +-
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arch/mips/include/asm/r4kcache.h | 231 ++++++++++++++++++++++++++++++
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arch/mips/include/asm/suspend.h | 3 +
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arch/mips/kernel/cpu-probe.c | 21 +++
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arch/mips/mm/c-r4k.c | 30 ++++
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arch/mips/mm/cache.c | 2 +
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arch/mips/mm/tlbex.c | 5 +
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12 files changed, 379 insertions(+), 4 deletions(-)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -174,6 +174,9 @@ config MACH_JAZZ
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Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
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Olivetti M700-10 workstations.
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+config MACH_JZ
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+ bool "Ingenic JZ4720/JZ4740 based machines"
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+
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config LASAT
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bool "LASAT Networks platforms"
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select CEVT_R4K
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@@ -677,6 +680,7 @@ source "arch/mips/alchemy/Kconfig"
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source "arch/mips/basler/excite/Kconfig"
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source "arch/mips/bcm63xx/Kconfig"
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source "arch/mips/jazz/Kconfig"
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+source "arch/mips/jz4740/Kconfig"
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source "arch/mips/lasat/Kconfig"
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source "arch/mips/pmc-sierra/Kconfig"
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source "arch/mips/sgi-ip27/Kconfig"
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@@ -1913,6 +1917,14 @@ config NR_CPUS
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source "kernel/time/Kconfig"
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+# the value of (max order + 1)
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+config FORCE_MAX_ZONEORDER
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+ prompt "MAX_ZONEORDER"
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+ int
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+ default "12"
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+ help
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+ The max memory that can be allocated = 4KB * 2^(CONFIG_FORCE_MAX_ZONEORDER - 1)
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+
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#
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# Timer Interrupt Frequency Configuration
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#
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -184,6 +184,14 @@ cflags-$(CONFIG_AR7) += -I$(srctree)/ar
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load-$(CONFIG_AR7) += 0xffffffff94100000
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#
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+# Commond Ingenic JZ4740 series
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+#
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+
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+core-$(CONFIG_SOC_JZ4740) += arch/mips/jz4740/
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+cflags-$(CONFIG_SOC_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
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+load-$(CONFIG_SOC_JZ4740) += 0xffffffff80010000
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+
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+#
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# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
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#
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core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
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@@ -705,6 +713,12 @@ makeboot =$(Q)$(MAKE) $(build)=arch/mips
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all: $(all-y)
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+uImage: $(vmlinux-32)
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+ +@$(call makeboot,$@)
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+
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+zImage: $(vmlinux-32)
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+ +@$(call makeboot,$@)
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+
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vmlinux.bin: $(vmlinux-32)
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+@$(call makeboot,$@)
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@@ -734,6 +748,7 @@ install:
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archclean:
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@$(MAKE) $(clean)=arch/mips/boot
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+ @$(MAKE) $(clean)=arch/mips/boot/compressed
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@$(MAKE) $(clean)=arch/mips/lasat
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define archhelp
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@@ -741,6 +756,9 @@ define archhelp
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echo ' vmlinux.ecoff - ECOFF boot image'
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echo ' vmlinux.bin - Raw binary boot image'
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echo ' vmlinux.srec - SREC boot image'
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+ echo ' uImage - u-boot format image (arch/$(ARCH)/boot/uImage)'
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+ echo ' zImage - Compressed binary image (arch/$(ARCH)/boot/compressed/zImage)'
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+ echo ' vmlinux.bin - Uncompressed binary image (arch/$(ARCH)/boot/vmlinux.bin)'
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echo
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echo ' These will be default as apropriate for a configured platform.'
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endef
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--- a/arch/mips/boot/Makefile
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+++ b/arch/mips/boot/Makefile
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@@ -7,6 +7,9 @@
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# Copyright (C) 2004 Maciej W. Rozycki
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#
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+# This one must match the LOADADDR in arch/mips/Makefile!
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+LOADADDR=0x80010000
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+
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#
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# Some DECstations need all possible sections of an ECOFF executable
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#
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@@ -25,7 +28,7 @@ strip-flags = $(addprefix --remove-secti
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VMLINUX = vmlinux
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-all: vmlinux.ecoff vmlinux.srec addinitrd
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+all: vmlinux.ecoff vmlinux.srec addinitrd uImage zImage
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vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
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$(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
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@@ -42,8 +45,24 @@ vmlinux.srec: $(VMLINUX)
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$(obj)/addinitrd: $(obj)/addinitrd.c
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$(HOSTCC) -o $@ $^
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+uImage: $(VMLINUX) vmlinux.bin
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+ rm -f $(obj)/vmlinux.bin.gz
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+ gzip -9 $(obj)/vmlinux.bin
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+ mkimage -A mips -O linux -T kernel -C gzip \
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+ -a $(LOADADDR) -e $(shell sh ./$(obj)/tools/entry $(NM) $(VMLINUX) ) \
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+ -n 'Linux-$(KERNELRELEASE)' \
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+ -d $(obj)/vmlinux.bin.gz $(obj)/uImage
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+ @echo ' Kernel: arch/mips/boot/$@ is ready'
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+
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+zImage:
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+ $(Q)$(MAKE) $(build)=$(obj)/compressed loadaddr=$(LOADADDR) $@
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+ @echo ' Kernel: arch/mips/boot/compressed/$@ is ready'
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+
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clean-files += addinitrd \
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elf2ecoff \
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vmlinux.bin \
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vmlinux.ecoff \
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- vmlinux.srec
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+ vmlinux.srec \
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+ vmlinux.bin.gz \
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+ uImage \
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+ zImage
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--- a/arch/mips/include/asm/bootinfo.h
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+++ b/arch/mips/include/asm/bootinfo.h
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@@ -69,6 +69,12 @@
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#define MACH_DEXXON_GDIUM2F10 5
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#define MACH_LOONGSON_END 6
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+/*
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+ * Valid machtype for group INGENIC
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+ */
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+#define MACH_INGENIC_JZ4720 0 /* JZ4730 SOC */
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+#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
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+
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#define CL_SIZE COMMAND_LINE_SIZE
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extern char *system_type;
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--- a/arch/mips/include/asm/cpu.h
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+++ b/arch/mips/include/asm/cpu.h
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@@ -34,7 +34,7 @@
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#define PRID_COMP_LSI 0x080000
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#define PRID_COMP_LEXRA 0x0b0000
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#define PRID_COMP_CAVIUM 0x0d0000
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-
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+#define PRID_COMP_INGENIC 0xd00000
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/*
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* Assigned values for the product ID register. In order to detect a
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@@ -133,6 +133,12 @@
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#define PRID_IMP_CAVIUM_CN52XX 0x0700
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/*
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+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
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+ */
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+
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+#define PRID_IMP_JZRISC 0x0200
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+
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+/*
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* Definitions for 7:0 on legacy processors
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*/
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@@ -224,6 +230,11 @@ enum cpu_type_enum {
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CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
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CPU_CAVIUM_OCTEON,
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+ /*
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+ * Ingenic class processors
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+ */
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+ CPU_JZRISC, CPU_XBURST,
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+
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CPU_LAST
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};
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--- a/arch/mips/include/asm/mach-generic/irq.h
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+++ b/arch/mips/include/asm/mach-generic/irq.h
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@@ -9,7 +9,7 @@
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#define __ASM_MACH_GENERIC_IRQ_H
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#ifndef NR_IRQS
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-#define NR_IRQS 128
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+#define NR_IRQS 256
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#endif
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#ifdef CONFIG_I8259
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--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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@@ -17,6 +17,58 @@
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#include <asm/cpu-features.h>
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#include <asm/mipsmtregs.h>
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+#ifdef CONFIG_JZRISC
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+
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+#define K0_TO_K1() \
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+do { \
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+ unsigned long __k0_addr; \
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+ \
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+ __asm__ __volatile__( \
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+ "la %0, 1f\n\t" \
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+ "or %0, %0, %1\n\t" \
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+ "jr %0\n\t" \
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+ "nop\n\t" \
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+ "1: nop\n" \
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+ : "=&r"(__k0_addr) \
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+ : "r" (0x20000000) ); \
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+} while(0)
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+
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+#define K1_TO_K0() \
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+do { \
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+ unsigned long __k0_addr; \
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+ __asm__ __volatile__( \
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+ "nop;nop;nop;nop;nop;nop;nop\n\t" \
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+ "la %0, 1f\n\t" \
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+ "jr %0\n\t" \
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+ "nop\n\t" \
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+ "1: nop\n" \
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+ : "=&r" (__k0_addr)); \
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+} while (0)
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+
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+#define INVALIDATE_BTB() \
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+do { \
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+ unsigned long tmp; \
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+ __asm__ __volatile__( \
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+ ".set mips32\n\t" \
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+ "mfc0 %0, $16, 7\n\t" \
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+ "nop\n\t" \
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+ "ori %0, 2\n\t" \
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+ "mtc0 %0, $16, 7\n\t" \
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+ "nop\n\t" \
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+ : "=&r" (tmp)); \
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+} while (0)
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+
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+#define SYNC_WB() __asm__ __volatile__ ("sync")
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+
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+#else /* CONFIG_JZRISC */
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+
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+#define K0_TO_K1() do { } while (0)
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+#define K1_TO_K0() do { } while (0)
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+#define INVALIDATE_BTB() do { } while (0)
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+#define SYNC_WB() do { } while (0)
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+
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+#endif /* CONFIG_JZRISC */
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+
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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@@ -144,6 +196,7 @@ static inline void flush_icache_line_ind
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{
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__iflush_prologue
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cache_op(Index_Invalidate_I, addr);
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+ INVALIDATE_BTB();
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__iflush_epilogue
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}
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@@ -151,6 +204,7 @@ static inline void flush_dcache_line_ind
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{
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__dflush_prologue
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cache_op(Index_Writeback_Inv_D, addr);
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+ SYNC_WB();
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__dflush_epilogue
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}
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@@ -163,6 +217,7 @@ static inline void flush_icache_line(uns
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{
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__iflush_prologue
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cache_op(Hit_Invalidate_I, addr);
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+ INVALIDATE_BTB();
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__iflush_epilogue
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}
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@@ -170,6 +225,7 @@ static inline void flush_dcache_line(uns
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{
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__dflush_prologue
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cache_op(Hit_Writeback_Inv_D, addr);
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+ SYNC_WB();
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__dflush_epilogue
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}
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@@ -177,6 +233,7 @@ static inline void invalidate_dcache_lin
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{
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__dflush_prologue
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cache_op(Hit_Invalidate_D, addr);
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+ SYNC_WB();
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__dflush_epilogue
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}
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@@ -209,6 +266,7 @@ static inline void flush_scache_line(uns
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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protected_cache_op(Hit_Invalidate_I, addr);
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+ INVALIDATE_BTB();
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}
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/*
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@@ -220,6 +278,7 @@ static inline void protected_flush_icach
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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protected_cache_op(Hit_Writeback_Inv_D, addr);
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+ SYNC_WB();
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}
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static inline void protected_writeback_scache_line(unsigned long addr)
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@@ -396,8 +455,10 @@ static inline void blast_##pfx##cache##l
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
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+#ifndef CONFIG_JZRISC
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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+#endif
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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@@ -405,12 +466,122 @@ __BUILD_BLAST_CACHE(s, scache, Index_Wri
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
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+#ifndef CONFIG_JZRISC
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
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+#endif
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
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+#ifdef CONFIG_JZRISC
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+
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+static inline void blast_dcache32(void)
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+{
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+ unsigned long start = INDEX_BASE;
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+ unsigned long end = start + current_cpu_data.dcache.waysize;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc)
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+ for (addr = start; addr < end; addr += 0x400)
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+ cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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+
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+ SYNC_WB();
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+}
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+
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+static inline void blast_dcache32_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = page + PAGE_SIZE;
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+
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+ do {
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+ cache32_unroll32(start,Hit_Writeback_Inv_D);
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+ start += 0x400;
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+ } while (start < end);
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+
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+ SYNC_WB();
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+}
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+
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+static inline void blast_dcache32_page_indexed(unsigned long page)
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+{
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+ unsigned long indexmask = current_cpu_data.dcache.waysize - 1;
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+ unsigned long start = INDEX_BASE + (page & indexmask);
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc)
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+ for (addr = start; addr < end; addr += 0x400)
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+ cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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+
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+ SYNC_WB();
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+}
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+
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+static inline void blast_icache32(void)
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+{
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+ unsigned long start = INDEX_BASE;
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+ unsigned long end = start + current_cpu_data.icache.waysize;
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+ unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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+ unsigned long ws_end = current_cpu_data.icache.ways <<
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+ current_cpu_data.icache.waybit;
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+ unsigned long ws, addr;
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+
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+ K0_TO_K1();
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc)
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+ for (addr = start; addr < end; addr += 0x400)
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+ cache32_unroll32(addr|ws,Index_Invalidate_I);
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+
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+ INVALIDATE_BTB();
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+
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+ K1_TO_K0();
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+}
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+
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+static inline void blast_icache32_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = page + PAGE_SIZE;
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+
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+ K0_TO_K1();
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+
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+ do {
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+ cache32_unroll32(start,Hit_Invalidate_I);
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+ start += 0x400;
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+ } while (start < end);
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+
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+ INVALIDATE_BTB();
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+
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+ K1_TO_K0();
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+}
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+
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+static inline void blast_icache32_page_indexed(unsigned long page)
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+{
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+ unsigned long indexmask = current_cpu_data.icache.waysize - 1;
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+ unsigned long start = INDEX_BASE + (page & indexmask);
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
|
|
+ unsigned long ws_end = current_cpu_data.icache.ways <<
|
|
+ current_cpu_data.icache.waybit;
|
|
+ unsigned long ws, addr;
|
|
+
|
|
+ K0_TO_K1();
|
|
+
|
|
+ for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
+ for (addr = start; addr < end; addr += 0x400)
|
|
+ cache32_unroll32(addr|ws,Index_Invalidate_I);
|
|
+
|
|
+ INVALIDATE_BTB();
|
|
+
|
|
+ K1_TO_K0();
|
|
+}
|
|
+
|
|
+#endif /* CONFIG_JZRISC */
|
|
+
|
|
/* build blast_xxx_range, protected_blast_xxx_range */
|
|
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
|
|
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
|
|
@@ -432,13 +603,73 @@ static inline void prot##blast_##pfx##ca
|
|
__##pfx##flush_epilogue \
|
|
}
|
|
|
|
+#ifndef CONFIG_JZRISC
|
|
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
|
|
+#endif
|
|
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
|
|
+#ifndef CONFIG_JZRISC
|
|
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
|
|
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
|
|
+#endif
|
|
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
|
|
/* blast_inv_dcache_range */
|
|
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
|
|
__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
|
|
|
|
+#ifdef CONFIG_JZRISC
|
|
+
|
|
+static inline void protected_blast_dcache_range(unsigned long start,
|
|
+ unsigned long end)
|
|
+{
|
|
+ unsigned long lsize = cpu_dcache_line_size();
|
|
+ unsigned long addr = start & ~(lsize - 1);
|
|
+ unsigned long aend = (end - 1) & ~(lsize - 1);
|
|
+
|
|
+ while (1) {
|
|
+ protected_cache_op(Hit_Writeback_Inv_D, addr);
|
|
+ if (addr == aend)
|
|
+ break;
|
|
+ addr += lsize;
|
|
+ }
|
|
+ SYNC_WB();
|
|
+}
|
|
+
|
|
+static inline void protected_blast_icache_range(unsigned long start,
|
|
+ unsigned long end)
|
|
+{
|
|
+ unsigned long lsize = cpu_icache_line_size();
|
|
+ unsigned long addr = start & ~(lsize - 1);
|
|
+ unsigned long aend = (end - 1) & ~(lsize - 1);
|
|
+
|
|
+ K0_TO_K1();
|
|
+
|
|
+ while (1) {
|
|
+ protected_cache_op(Hit_Invalidate_I, addr);
|
|
+ if (addr == aend)
|
|
+ break;
|
|
+ addr += lsize;
|
|
+ }
|
|
+ INVALIDATE_BTB();
|
|
+
|
|
+ K1_TO_K0();
|
|
+}
|
|
+
|
|
+static inline void blast_dcache_range(unsigned long start,
|
|
+ unsigned long end)
|
|
+{
|
|
+ unsigned long lsize = cpu_dcache_line_size();
|
|
+ unsigned long addr = start & ~(lsize - 1);
|
|
+ unsigned long aend = (end - 1) & ~(lsize - 1);
|
|
+
|
|
+ while (1) {
|
|
+ cache_op(Hit_Writeback_Inv_D, addr);
|
|
+ if (addr == aend)
|
|
+ break;
|
|
+ addr += lsize;
|
|
+ }
|
|
+ SYNC_WB();
|
|
+}
|
|
+
|
|
+#endif /* CONFIG_JZRISC */
|
|
+
|
|
#endif /* _ASM_R4KCACHE_H */
|
|
--- a/arch/mips/include/asm/suspend.h
|
|
+++ b/arch/mips/include/asm/suspend.h
|
|
@@ -2,6 +2,9 @@
|
|
#define __ASM_SUSPEND_H
|
|
|
|
static inline int arch_prepare_suspend(void) { return 0; }
|
|
+#if defined(CONFIG_PM) && defined(CONFIG_JZSOC)
|
|
+extern int jz_pm_init(void);
|
|
+#endif
|
|
|
|
/* References to section boundaries */
|
|
extern const void __nosave_begin, __nosave_end;
|
|
--- a/arch/mips/kernel/cpu-probe.c
|
|
+++ b/arch/mips/kernel/cpu-probe.c
|
|
@@ -160,6 +160,7 @@ void __init check_wait(void)
|
|
case CPU_BCM6348:
|
|
case CPU_BCM6358:
|
|
case CPU_CAVIUM_OCTEON:
|
|
+ case CPU_JZRISC:
|
|
cpu_wait = r4k_wait;
|
|
break;
|
|
|
|
@@ -902,6 +903,23 @@ static inline void cpu_probe_cavium(stru
|
|
}
|
|
}
|
|
|
|
+static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
|
|
+{
|
|
+ decode_configs(c);
|
|
+ c->options &= ~MIPS_CPU_COUNTER; /* JZRISC does not implement the CP0 counter. */
|
|
+ switch (c->processor_id & 0xff00) {
|
|
+ case PRID_IMP_JZRISC:
|
|
+ c->cputype = CPU_JZRISC;
|
|
+ c->isa_level = MIPS_CPU_ISA_M32R1;
|
|
+ c->tlbsize = 32;
|
|
+ __cpu_name[cpu] = "Ingenic JZRISC";
|
|
+ break;
|
|
+ default:
|
|
+ panic("Unknown Ingenic Processor ID!");
|
|
+ break;
|
|
+ }
|
|
+}
|
|
+
|
|
const char *__cpu_name[NR_CPUS];
|
|
|
|
__cpuinit void cpu_probe(void)
|
|
@@ -939,6 +957,9 @@ __cpuinit void cpu_probe(void)
|
|
case PRID_COMP_CAVIUM:
|
|
cpu_probe_cavium(c, cpu);
|
|
break;
|
|
+ case PRID_COMP_INGENIC:
|
|
+ cpu_probe_ingenic(c, cpu);
|
|
+ break;
|
|
}
|
|
|
|
BUG_ON(!__cpu_name[cpu]);
|
|
--- a/arch/mips/mm/c-r4k.c
|
|
+++ b/arch/mips/mm/c-r4k.c
|
|
@@ -928,6 +928,36 @@ static void __cpuinit probe_pcache(void)
|
|
c->dcache.waybit = 0;
|
|
break;
|
|
|
|
+ case CPU_JZRISC:
|
|
+ config1 = read_c0_config1();
|
|
+ config1 = (config1 >> 22) & 0x07;
|
|
+ if (config1 == 0x07)
|
|
+ config1 = 10;
|
|
+ else
|
|
+ config1 = config1 + 11;
|
|
+ config1 += 2;
|
|
+ icache_size = (1 << config1);
|
|
+ c->icache.linesz = 32;
|
|
+ c->icache.ways = 4;
|
|
+ c->icache.waybit = __ffs(icache_size / c->icache.ways);
|
|
+
|
|
+ config1 = read_c0_config1();
|
|
+ config1 = (config1 >> 13) & 0x07;
|
|
+ if (config1 == 0x07)
|
|
+ config1 = 10;
|
|
+ else
|
|
+ config1 = config1 + 11;
|
|
+ config1 += 2;
|
|
+ dcache_size = (1 << config1);
|
|
+ c->dcache.linesz = 32;
|
|
+ c->dcache.ways = 4;
|
|
+ c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
|
|
+
|
|
+ c->dcache.flags = 0;
|
|
+ c->options |= MIPS_CPU_PREFETCH;
|
|
+
|
|
+ break;
|
|
+
|
|
default:
|
|
if (!(config & MIPS_CONF_M))
|
|
panic("Don't know how to probe P-caches on this cpu.");
|
|
--- a/arch/mips/mm/cache.c
|
|
+++ b/arch/mips/mm/cache.c
|
|
@@ -52,6 +52,8 @@ void (*_dma_cache_wback)(unsigned long s
|
|
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
|
|
|
|
EXPORT_SYMBOL(_dma_cache_wback_inv);
|
|
+EXPORT_SYMBOL(_dma_cache_wback);
|
|
+EXPORT_SYMBOL(_dma_cache_inv);
|
|
|
|
#endif /* CONFIG_DMA_NONCOHERENT */
|
|
|
|
--- a/arch/mips/mm/tlbex.c
|
|
+++ b/arch/mips/mm/tlbex.c
|
|
@@ -389,6 +389,11 @@ static void __cpuinit build_tlb_write_en
|
|
tlbw(p);
|
|
break;
|
|
|
|
+ case CPU_JZRISC:
|
|
+ tlbw(p);
|
|
+ uasm_i_nop(p);
|
|
+ break;
|
|
+
|
|
default:
|
|
panic("No TLB refill handler yet (CPU type: %d)",
|
|
current_cpu_data.cputype);
|