mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-27 20:58:59 +02:00
809c03fe4c
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19098 3c298f89-4303-0410-b956-a3cf2f4a3e73
419 lines
10 KiB
C
419 lines
10 KiB
C
/*
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* Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4720/JZ4740 SoC NAND controller driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/jz4740_nand.h>
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#include <linux/gpio.h>
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#define JZ_REG_NAND_CTRL 0x50
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#define JZ_REG_NAND_ECC_CTRL 0x100
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#define JZ_REG_NAND_DATA 0x104
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#define JZ_REG_NAND_PAR0 0x108
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#define JZ_REG_NAND_PAR1 0x10C
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#define JZ_REG_NAND_PAR2 0x110
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#define JZ_REG_NAND_IRQ_STAT 0x114
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#define JZ_REG_NAND_IRQ_CTRL 0x118
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#define JZ_REG_NAND_ERR(x) (0x11C + (x << 2))
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#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
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#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
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#define JZ_NAND_ECC_CTRL_RS BIT(2)
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#define JZ_NAND_ECC_CTRL_RESET BIT(1)
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#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
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#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
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#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
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#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
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#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
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#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
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#define JZ_NAND_STATUS_ERROR BIT(0)
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#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT(x << 1)
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#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT((x << 1) + 1)
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#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
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#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
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#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
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struct jz_nand {
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struct mtd_info mtd;
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struct nand_chip chip;
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void __iomem *base;
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struct resource *mem;
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struct jz_nand_platform_data *pdata;
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};
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static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
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{
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return container_of(mtd, struct jz_nand, mtd);
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}
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static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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struct nand_chip *chip = mtd->priv;
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uint32_t reg;
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if (ctrl & NAND_CTRL_CHANGE) {
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BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
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if (ctrl & NAND_ALE)
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chip->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
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else if (ctrl & NAND_CLE)
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chip->IO_ADDR_W = JZ_NAND_CMD_ADDR;
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else
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chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
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reg = readl(nand->base + JZ_REG_NAND_CTRL);
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if ( ctrl & NAND_NCE )
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reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
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else
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reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
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writel(reg, nand->base + JZ_REG_NAND_CTRL);
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}
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if (dat != NAND_CMD_NONE)
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writeb(dat, chip->IO_ADDR_W);
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}
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static int jz_nand_dev_ready(struct mtd_info *mtd)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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return gpio_get_value_cansleep(nand->pdata->busy_gpio);
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}
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static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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uint32_t reg;
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writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg |= JZ_NAND_ECC_CTRL_RESET;
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reg |= JZ_NAND_ECC_CTRL_ENABLE;
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reg |= JZ_NAND_ECC_CTRL_RS;
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switch(mode) {
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case NAND_ECC_READ:
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reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
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break;
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case NAND_ECC_WRITE:
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reg |= JZ_NAND_ECC_CTRL_ENCODING;
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break;
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default:
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break;
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}
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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}
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static int jz_nand_calculate_ecc_rs(struct mtd_info* mtd, const uint8_t* dat,
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uint8_t *ecc_code)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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uint32_t reg, status;
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int i;
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do {
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status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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} while(!(status & JZ_NAND_STATUS_ENC_FINISH));
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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for (i = 0; i < 9; ++i) {
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ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
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}
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return 0;
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}
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static void correct_data(uint8_t *dat, int index, int mask)
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{
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int offset = index & 0x7;
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uint16_t data;
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printk("correct: ");
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index += (index >> 3);
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data = dat[index];
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data |= dat[index+1] << 8;
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printk("0x%x -> ", data);
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mask ^= (data >> offset) & 0x1ff;
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data &= ~(0x1ff << offset);
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data |= (mask << offset);
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printk("0x%x\n", data);
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dat[index] = data & 0xff;
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dat[index+1] = (data >> 8) & 0xff;
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}
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static int jz_nand_correct_ecc_rs(struct mtd_info* mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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int i, error_count, index;
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uint32_t reg, status, error;
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for(i = 0; i < 9; ++i) {
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if (read_ecc[i] != 0xff)
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break;
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}
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if (i == 9) {
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for (i = 0; i < nand->chip.ecc.size; ++i) {
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if (dat[i] != 0xff)
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break;
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}
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if (i == nand->chip.ecc.size)
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return 0;
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}
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for(i = 0; i < 9; ++i)
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writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg |= JZ_NAND_ECC_CTRL_PAR_READY;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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do {
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status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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} while (!(status & JZ_NAND_STATUS_DEC_FINISH));
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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if (status & JZ_NAND_STATUS_ERROR) {
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if (status & JZ_NAND_STATUS_UNCOR_ERROR) {
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printk("uncorrectable ecc:");
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for(i = 0; i < 9; ++i)
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printk(" 0x%x", read_ecc[i]);
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printk("\n");
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printk("uncorrectable data:");
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for(i = 0; i < 32; ++i)
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printk(" 0x%x", dat[i]);
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printk("\n");
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return -1;
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}
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error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
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printk("error_count: %d %x\n", error_count, status);
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for(i = 0; i < error_count; ++i) {
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error = readl(nand->base + JZ_REG_NAND_ERR(i));
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index = ((error >> 16) & 0x1ff) - 1;
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if (index >= 0 && index < 512) {
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correct_data(dat, index, error & 0x1ff);
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}
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}
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return error_count;
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}
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return 0;
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}
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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static const char *part_probes[] = {"cmdline", NULL};
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#endif
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static int __devinit jz_nand_probe(struct platform_device *pdev)
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{
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int ret;
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struct jz_nand *nand;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
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#ifdef CONFIG_MTD_PARTITIONS
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struct mtd_partition *partition_info;
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int num_partitions = 0;
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#endif
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nand = kzalloc(sizeof(*nand), GFP_KERNEL);
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if (!nand) {
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dev_err(&pdev->dev, "Failed to allocate device structure.\n");
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return -ENOMEM;
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}
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nand->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!nand->mem) {
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dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
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ret = -ENOENT;
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goto err_free;
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}
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nand->mem = request_mem_region(nand->mem->start, resource_size(nand->mem),
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pdev->name);
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if (!nand->mem) {
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dev_err(&pdev->dev, "Failed to request mmio memory region\n");
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ret = -EBUSY;
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goto err_free;
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}
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nand->base = ioremap(nand->mem->start, resource_size(nand->mem));
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if (!nand->base) {
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dev_err(&pdev->dev, "Faild to ioremap mmio memory region\n");
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ret = -EBUSY;
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goto err_release_mem;
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}
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if (pdata && gpio_is_valid(pdata->busy_gpio)) {
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ret = gpio_request(pdata->busy_gpio, "jz nand busy line");
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if (ret) {
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dev_err(&pdev->dev, "Failed to request busy gpio %d: %d\n",
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pdata->busy_gpio, ret);
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goto err_iounmap;
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}
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}
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mtd = &nand->mtd;
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chip = &nand->chip;
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mtd->priv = chip;
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mtd->owner = THIS_MODULE;
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mtd->name = "jz4740-nand";
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chip->ecc.hwctl = jz_nand_hwctl;
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chip->ecc.calculate = jz_nand_calculate_ecc_rs;
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chip->ecc.correct = jz_nand_correct_ecc_rs;
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = 512;
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chip->ecc.bytes = 9;
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if (pdata)
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chip->ecc.layout = pdata->ecc_layout;
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chip->chip_delay = 50;
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chip->cmd_ctrl = jz_nand_cmd_ctrl;
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if (pdata && gpio_is_valid(pdata->busy_gpio))
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chip->dev_ready = jz_nand_dev_ready;
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chip->IO_ADDR_R = JZ_NAND_DATA_ADDR;
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chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
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nand->pdata = pdata;
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platform_set_drvdata(pdev, nand);
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ret = nand_scan_ident(mtd, 1);
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if (ret) {
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dev_err(&pdev->dev, "Failed to scan nand\n");
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goto err_gpio_free;
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}
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if (pdata && pdata->ident_callback) {
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pdata->ident_callback(pdev, chip, &pdata->partitions, &pdata->num_partitions);
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}
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ret = nand_scan_tail(mtd);
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if (ret) {
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dev_err(&pdev->dev, "Failed to scan nand\n");
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goto err_gpio_free;
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}
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#ifdef CONFIG_MTD_PARTITIONS
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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num_partitions = parse_mtd_partitions(mtd, part_probes,
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&partition_info, 0);
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#endif
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if (num_partitions <= 0 && pdata) {
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num_partitions = pdata->num_partitions;
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partition_info = pdata->partitions;
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}
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if (num_partitions > 0)
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ret = add_mtd_partitions(mtd, partition_info, num_partitions);
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else
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#endif
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ret = add_mtd_device(mtd);
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if (ret) {
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dev_err(&pdev->dev, "Failed to add mtd device\n");
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goto err_nand_release;
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}
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dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
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return 0;
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err_nand_release:
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nand_release(&nand->mtd);
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err_gpio_free:
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platform_set_drvdata(pdev, NULL);
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gpio_free(pdata->busy_gpio);
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err_iounmap:
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iounmap(nand->base);
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err_release_mem:
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release_mem_region(nand->mem->start, resource_size(nand->mem));
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err_free:
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kfree(nand);
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return ret;
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}
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static void __devexit jz_nand_remove(struct platform_device *pdev)
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{
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struct jz_nand *nand = platform_get_drvdata(pdev);
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nand_release(&nand->mtd);
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iounmap(nand->base);
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release_mem_region(nand->mem->start, resource_size(nand->mem));
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platform_set_drvdata(pdev, NULL);
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kfree(nand);
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}
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struct platform_driver jz_nand_driver = {
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.probe = jz_nand_probe,
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.remove = __devexit_p(jz_nand_probe),
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.driver = {
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.name = "jz4740-nand",
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.owner = THIS_MODULE,
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},
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};
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static int __init jz_nand_init(void)
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{
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return platform_driver_register(&jz_nand_driver);
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}
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module_init(jz_nand_init);
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static void __exit jz_nand_exit(void)
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{
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platform_driver_unregister(&jz_nand_driver);
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}
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module_exit(jz_nand_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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MODULE_DESCRIPTION("NAND controller driver for JZ4720/JZ4740 SoC");
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MODULE_ALIAS("platform:jz4740-nand");
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MODULE_ALIAS("platform:jz4720-nand");
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