mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-01 22:25:20 +02:00
4ad28d6429
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31278 3c298f89-4303-0410-b956-a3cf2f4a3e73
731 lines
25 KiB
Diff
731 lines
25 KiB
Diff
--- a/drivers/ssb/driver_pcicore.c
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+++ b/drivers/ssb/driver_pcicore.c
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@@ -74,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
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u32 tmp;
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/* We do only have one cardbus device behind the bridge. */
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- if (pc->cardbusmode && (dev >= 1))
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+ if (pc->cardbusmode && (dev > 1))
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goto out;
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if (bus == 0) {
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--- a/drivers/ssb/b43_pci_bridge.c
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+++ b/drivers/ssb/b43_pci_bridge.c
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@@ -11,6 +11,7 @@
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*/
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#include <linux/pci.h>
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+#include <linux/module.h>
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#include <linux/ssb/ssb.h>
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#include "ssb_private.h"
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -12,6 +12,9 @@
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#include <linux/ssb/ssb_regs.h>
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#include <linux/ssb/ssb_driver_chipcommon.h>
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#include <linux/delay.h>
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+#ifdef CONFIG_BCM47XX
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+#include <asm/mach-bcm47xx/nvram.h>
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+#endif
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#include "ssb_private.h"
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@@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
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u32 pmuctl, tmp, pllctl;
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unsigned int i;
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- if ((bus->chip_id == 0x5354) && !crystalfreq) {
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- /* The 5354 crystal freq is 25MHz */
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- crystalfreq = 25000;
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- }
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if (crystalfreq)
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e = pmu0_plltab_find_entry(crystalfreq);
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if (!e)
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@@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
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u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
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if (bus->bustype == SSB_BUSTYPE_SSB) {
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- /* TODO: The user may override the crystal frequency. */
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+#ifdef CONFIG_BCM47XX
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+ char buf[20];
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+ if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
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+ crystalfreq = simple_strtoul(buf, NULL, 0);
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+#endif
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}
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switch (bus->chip_id) {
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@@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
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ssb_pmu1_pllinit_r0(cc, crystalfreq);
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break;
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case 0x4328:
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+ ssb_pmu0_pllinit_r0(cc, crystalfreq);
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+ break;
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case 0x5354:
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+ if (crystalfreq == 0)
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+ crystalfreq = 25000;
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ssb_pmu0_pllinit_r0(cc, crystalfreq);
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break;
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case 0x4322:
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@@ -606,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
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EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
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EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
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+
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+u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
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+ return 240000000;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU cpu clock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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+
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+u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ return 120000000;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU controlclock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
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struct ssb_bus *bus = mcore->dev->bus;
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u32 pll_type, n, m, rate = 0;
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+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_cpu_clock(&bus->chipco);
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+
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if (bus->extif.dev) {
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ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
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} else if (bus->chipco.dev) {
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -12,6 +12,7 @@
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#include <linux/delay.h>
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#include <linux/io.h>
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+#include <linux/module.h>
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_regs.h>
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#include <linux/ssb/ssb_driver_gige.h>
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@@ -139,19 +140,6 @@ static void ssb_device_put(struct ssb_de
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put_device(dev->dev);
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}
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-static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
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-{
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- if (drv)
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- get_driver(&drv->drv);
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- return drv;
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-}
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-
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-static inline void ssb_driver_put(struct ssb_driver *drv)
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-{
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- if (drv)
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- put_driver(&drv->drv);
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-}
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-
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static int ssb_device_resume(struct device *dev)
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{
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struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
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@@ -249,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
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ssb_device_put(sdev);
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continue;
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}
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- sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
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- if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
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- ssb_device_put(sdev);
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+ sdrv = drv_to_ssb_drv(sdev->dev->driver);
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+ if (SSB_WARN_ON(!sdrv->remove))
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continue;
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- }
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sdrv->remove(sdev);
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ctx->device_frozen[i] = 1;
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}
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@@ -292,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
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dev_name(sdev->dev));
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result = err;
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}
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- ssb_driver_put(sdrv);
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ssb_device_put(sdev);
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}
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@@ -1093,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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u32 plltype;
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u32 clkctl_n, clkctl_m;
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+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_controlclock(&bus->chipco);
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+
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if (ssb_extif_available(&bus->extif))
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ssb_extif_get_clockcontrol(&bus->extif, &plltype,
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&clkctl_n, &clkctl_m);
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@@ -1260,16 +1248,34 @@ void ssb_device_disable(struct ssb_devic
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}
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EXPORT_SYMBOL(ssb_device_disable);
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+/* Some chipsets need routing known for PCIe and 64-bit DMA */
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+static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
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+{
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+ u16 chip_id = dev->bus->chip_id;
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+
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+ if (dev->id.coreid == SSB_DEV_80211) {
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+ return (chip_id == 0x4322 || chip_id == 43221 ||
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+ chip_id == 43231 || chip_id == 43222);
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+ }
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+
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+ return 0;
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+}
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+
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u32 ssb_dma_translation(struct ssb_device *dev)
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{
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switch (dev->bus->bustype) {
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case SSB_BUSTYPE_SSB:
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return 0;
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case SSB_BUSTYPE_PCI:
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- if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
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+ if (pci_is_pcie(dev->bus->host_pci) &&
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+ ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
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return SSB_PCIE_DMA_H32;
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- else
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- return SSB_PCI_DMA;
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+ } else {
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+ if (ssb_dma_translation_special_bit(dev))
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+ return SSB_PCIE_DMA_H32;
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+ else
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+ return SSB_PCI_DMA;
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+ }
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default:
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__ssb_dma_not_implemented(dev);
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}
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
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{
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int i;
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u16 v;
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- s8 gain;
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u16 loc[3];
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if (out->revision == 3) /* rev 3 moved MAC */
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@@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ss
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SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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/* Extract the antenna gain values. */
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- gain = r123_extract_antgain(out->revision, in,
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- SSB_SPROM1_AGAIN_BG,
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- SSB_SPROM1_AGAIN_BG_SHIFT);
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- out->antenna_gain.ghz24.a0 = gain;
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- out->antenna_gain.ghz24.a1 = gain;
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- out->antenna_gain.ghz24.a2 = gain;
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- out->antenna_gain.ghz24.a3 = gain;
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- gain = r123_extract_antgain(out->revision, in,
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- SSB_SPROM1_AGAIN_A,
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- SSB_SPROM1_AGAIN_A_SHIFT);
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- out->antenna_gain.ghz5.a0 = gain;
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- out->antenna_gain.ghz5.a1 = gain;
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- out->antenna_gain.ghz5.a2 = gain;
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- out->antenna_gain.ghz5.a3 = gain;
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+ out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
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+ SSB_SPROM1_AGAIN_BG,
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+ SSB_SPROM1_AGAIN_BG_SHIFT);
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+ out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
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+ SSB_SPROM1_AGAIN_A,
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+ SSB_SPROM1_AGAIN_A_SHIFT);
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}
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/* Revs 4 5 and 8 have partially shared layout */
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@@ -504,16 +495,14 @@ static void sprom_extract_r45(struct ssb
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}
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/* Extract the antenna gain values. */
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- SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
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+ SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
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SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
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- SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
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+ SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
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SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
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- SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
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+ SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
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SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
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- SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
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+ SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
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SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
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- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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- sizeof(out->antenna_gain.ghz5));
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sprom_extract_r458(out, in);
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@@ -523,7 +512,13 @@ static void sprom_extract_r45(struct ssb
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static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
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{
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int i;
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- u16 v;
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+ u16 v, o;
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+ u16 pwr_info_offset[] = {
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+ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
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+ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
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+ };
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+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
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+ ARRAY_SIZE(out->core_pwr_info));
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/* extract the MAC address */
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for (i = 0; i < 3; i++) {
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@@ -596,16 +591,69 @@ static void sprom_extract_r8(struct ssb_
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SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
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/* Extract the antenna gain values. */
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- SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
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+ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
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SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
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- SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
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+ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
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SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
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- SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
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+ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
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SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
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- SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
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+ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
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SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
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- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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- sizeof(out->antenna_gain.ghz5));
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+
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+ /* Extract cores power info info */
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+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
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+ o = pwr_info_offset[i];
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+ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
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+ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
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+ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
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+ SSB_SPROM8_2G_MAXP, 0);
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+
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+ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
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+
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+ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
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+ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
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+ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
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+ SSB_SPROM8_5G_MAXP, 0);
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+ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
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+ SSB_SPROM8_5GH_MAXP, 0);
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+ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
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+ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
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+
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+ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
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+ }
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+
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+ /* Extract FEM info */
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+ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
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+ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
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+ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
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+ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
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+ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
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+
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+ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
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+ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
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+ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
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+ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
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+ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
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|
sprom_extract_r458(out, in);
|
|
|
|
--- a/drivers/ssb/pcmcia.c
|
|
+++ b/drivers/ssb/pcmcia.c
|
|
@@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
|
|
case SSB_PCMCIA_CIS_ANTGAIN:
|
|
GOTO_ERROR_ON(tuple->TupleDataLen != 2,
|
|
"antg tpl size");
|
|
- sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.a0 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.a1 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.a2 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.a3 = tuple->TupleData[1];
|
|
break;
|
|
case SSB_PCMCIA_CIS_BFLAGS:
|
|
GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
|
|
--- a/drivers/ssb/scan.c
|
|
+++ b/drivers/ssb/scan.c
|
|
@@ -318,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
|
|
bus->chip_package = 0;
|
|
}
|
|
}
|
|
+ ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
|
|
+ "package 0x%02X\n", bus->chip_id, bus->chip_rev,
|
|
+ bus->chip_package);
|
|
if (!bus->nr_devices)
|
|
bus->nr_devices = chipid_to_nrcores(bus->chip_id);
|
|
if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
|
|
--- a/drivers/ssb/sdio.c
|
|
+++ b/drivers/ssb/sdio.c
|
|
@@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
|
|
case SSB_SDIO_CIS_ANTGAIN:
|
|
GOTO_ERROR_ON(tuple->size != 2,
|
|
"antg tpl size");
|
|
- sprom->antenna_gain.ghz24.a0 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz24.a1 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz24.a2 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz24.a3 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz5.a0 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz5.a1 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz5.a2 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz5.a3 = tuple->data[1];
|
|
+ sprom->antenna_gain.a0 = tuple->data[1];
|
|
+ sprom->antenna_gain.a1 = tuple->data[1];
|
|
+ sprom->antenna_gain.a2 = tuple->data[1];
|
|
+ sprom->antenna_gain.a3 = tuple->data[1];
|
|
break;
|
|
case SSB_SDIO_CIS_BFLAGS:
|
|
GOTO_ERROR_ON((tuple->size != 3) &&
|
|
--- a/drivers/ssb/ssb_private.h
|
|
+++ b/drivers/ssb/ssb_private.h
|
|
@@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
|
|
}
|
|
#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
|
|
|
|
+/* driver_chipcommon_pmu.c */
|
|
+extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
|
|
+extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
|
|
+
|
|
#endif /* LINUX_SSB_PRIVATE_H_ */
|
|
--- a/include/linux/ssb/ssb.h
|
|
+++ b/include/linux/ssb/ssb.h
|
|
@@ -16,6 +16,12 @@ struct pcmcia_device;
|
|
struct ssb_bus;
|
|
struct ssb_driver;
|
|
|
|
+struct ssb_sprom_core_pwr_info {
|
|
+ u8 itssi_2g, itssi_5g;
|
|
+ u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
|
|
+ u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
|
|
+};
|
|
+
|
|
struct ssb_sprom {
|
|
u8 revision;
|
|
u8 il0mac[6]; /* MAC address for 802.11b/g */
|
|
@@ -25,10 +31,13 @@ struct ssb_sprom {
|
|
u8 et1phyaddr; /* MII address for enet1 */
|
|
u8 et0mdcport; /* MDIO for enet0 */
|
|
u8 et1mdcport; /* MDIO for enet1 */
|
|
- u8 board_rev; /* Board revision number from SPROM. */
|
|
+ u16 board_rev; /* Board revision number from SPROM. */
|
|
+ u16 board_num; /* Board number from SPROM. */
|
|
+ u16 board_type; /* Board type from SPROM. */
|
|
u8 country_code; /* Country Code */
|
|
- u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
|
|
- u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
|
|
+ char alpha2[2]; /* Country Code as two chars like EU or US */
|
|
+ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
|
|
+ u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
|
|
u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
|
|
u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
|
|
u16 pa0b0;
|
|
@@ -47,10 +56,10 @@ struct ssb_sprom {
|
|
u8 gpio1; /* GPIO pin 1 */
|
|
u8 gpio2; /* GPIO pin 2 */
|
|
u8 gpio3; /* GPIO pin 3 */
|
|
- u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
|
|
- u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
|
|
- u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
|
|
- u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
|
|
+ u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
|
|
+ u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
|
|
+ u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
|
|
+ u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
|
|
u8 itssi_a; /* Idle TSSI Target for A-PHY */
|
|
u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
|
|
u8 tri2g; /* 2.4GHz TX isolation */
|
|
@@ -61,8 +70,8 @@ struct ssb_sprom {
|
|
u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
|
|
u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
|
|
u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
|
|
- u8 rxpo2g; /* 2GHz RX power offset */
|
|
- u8 rxpo5g; /* 5GHz RX power offset */
|
|
+ s8 rxpo2g; /* 2GHz RX power offset */
|
|
+ s8 rxpo5g; /* 5GHz RX power offset */
|
|
u8 rssisav2g; /* 2GHz RSSI params */
|
|
u8 rssismc2g;
|
|
u8 rssismf2g;
|
|
@@ -82,19 +91,97 @@ struct ssb_sprom {
|
|
u16 boardflags2_hi; /* Board flags (bits 48-63) */
|
|
/* TODO store board flags in a single u64 */
|
|
|
|
+ struct ssb_sprom_core_pwr_info core_pwr_info[4];
|
|
+
|
|
/* Antenna gain values for up to 4 antennas
|
|
* on each band. Values in dBm/4 (Q5.2). Negative gain means the
|
|
* loss in the connectors is bigger than the gain. */
|
|
struct {
|
|
- struct {
|
|
- s8 a0, a1, a2, a3;
|
|
- } ghz24; /* 2.4GHz band */
|
|
- struct {
|
|
- s8 a0, a1, a2, a3;
|
|
- } ghz5; /* 5GHz band */
|
|
+ s8 a0, a1, a2, a3;
|
|
} antenna_gain;
|
|
|
|
- /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
|
|
+ struct {
|
|
+ struct {
|
|
+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
|
|
+ } ghz2;
|
|
+ struct {
|
|
+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
|
|
+ } ghz5;
|
|
+ } fem;
|
|
+
|
|
+ u16 mcs2gpo[8];
|
|
+ u16 mcs5gpo[8];
|
|
+ u16 mcs5glpo[8];
|
|
+ u16 mcs5ghpo[8];
|
|
+ u8 opo;
|
|
+
|
|
+ u8 rxgainerr2ga[3];
|
|
+ u8 rxgainerr5gla[3];
|
|
+ u8 rxgainerr5gma[3];
|
|
+ u8 rxgainerr5gha[3];
|
|
+ u8 rxgainerr5gua[3];
|
|
+
|
|
+ u8 noiselvl2ga[3];
|
|
+ u8 noiselvl5gla[3];
|
|
+ u8 noiselvl5gma[3];
|
|
+ u8 noiselvl5gha[3];
|
|
+ u8 noiselvl5gua[3];
|
|
+
|
|
+ u8 regrev;
|
|
+ u8 txchain;
|
|
+ u8 rxchain;
|
|
+ u8 antswitch;
|
|
+ u16 cddpo;
|
|
+ u16 stbcpo;
|
|
+ u16 bw40po;
|
|
+ u16 bwduppo;
|
|
+
|
|
+ u8 tempthresh;
|
|
+ u8 tempoffset;
|
|
+ u16 rawtempsense;
|
|
+ u8 measpower;
|
|
+ u8 tempsense_slope;
|
|
+ u8 tempcorrx;
|
|
+ u8 tempsense_option;
|
|
+ u8 freqoffset_corr;
|
|
+ u8 iqcal_swp_dis;
|
|
+ u8 hw_iqcal_en;
|
|
+ u8 elna2g;
|
|
+ u8 elna5g;
|
|
+ u8 phycal_tempdelta;
|
|
+ u8 temps_period;
|
|
+ u8 temps_hysteresis;
|
|
+ u8 measpower1;
|
|
+ u8 measpower2;
|
|
+ u8 pcieingress_war;
|
|
+
|
|
+ /* power per rate from sromrev 9 */
|
|
+ u16 cckbw202gpo;
|
|
+ u16 cckbw20ul2gpo;
|
|
+ u32 legofdmbw202gpo;
|
|
+ u32 legofdmbw20ul2gpo;
|
|
+ u32 legofdmbw205glpo;
|
|
+ u32 legofdmbw20ul5glpo;
|
|
+ u32 legofdmbw205gmpo;
|
|
+ u32 legofdmbw20ul5gmpo;
|
|
+ u32 legofdmbw205ghpo;
|
|
+ u32 legofdmbw20ul5ghpo;
|
|
+ u32 mcsbw202gpo;
|
|
+ u32 mcsbw20ul2gpo;
|
|
+ u32 mcsbw402gpo;
|
|
+ u32 mcsbw205glpo;
|
|
+ u32 mcsbw20ul5glpo;
|
|
+ u32 mcsbw405glpo;
|
|
+ u32 mcsbw205gmpo;
|
|
+ u32 mcsbw20ul5gmpo;
|
|
+ u32 mcsbw405gmpo;
|
|
+ u32 mcsbw205ghpo;
|
|
+ u32 mcsbw20ul5ghpo;
|
|
+ u32 mcsbw405ghpo;
|
|
+ u16 mcs32po;
|
|
+ u16 legofdm40duppo;
|
|
+ u8 sar2g;
|
|
+ u8 sar5g;
|
|
};
|
|
|
|
/* Information about the PCB the circuitry is soldered on. */
|
|
@@ -231,10 +318,9 @@ struct ssb_driver {
|
|
#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
|
|
|
|
extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
|
|
-static inline int ssb_driver_register(struct ssb_driver *drv)
|
|
-{
|
|
- return __ssb_driver_register(drv, THIS_MODULE);
|
|
-}
|
|
+#define ssb_driver_register(drv) \
|
|
+ __ssb_driver_register(drv, THIS_MODULE)
|
|
+
|
|
extern void ssb_driver_unregister(struct ssb_driver *drv);
|
|
|
|
|
|
--- a/include/linux/ssb/ssb_driver_gige.h
|
|
+++ b/include/linux/ssb/ssb_driver_gige.h
|
|
@@ -2,6 +2,7 @@
|
|
#define LINUX_SSB_DRIVER_GIGE_H_
|
|
|
|
#include <linux/ssb/ssb.h>
|
|
+#include <linux/bug.h>
|
|
#include <linux/pci.h>
|
|
#include <linux/spinlock.h>
|
|
|
|
--- a/include/linux/ssb/ssb_regs.h
|
|
+++ b/include/linux/ssb/ssb_regs.h
|
|
@@ -432,6 +432,56 @@
|
|
#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
|
|
#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
|
|
#define SSB_SPROM8_RXPO5G_SHIFT 8
|
|
+#define SSB_SPROM8_FEM2G 0x00AE
|
|
+#define SSB_SPROM8_FEM5G 0x00B0
|
|
+#define SSB_SROM8_FEM_TSSIPOS 0x0001
|
|
+#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
|
|
+#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
|
|
+#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
|
|
+#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
|
|
+#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
|
|
+#define SSB_SROM8_FEM_TR_ISO 0x0700
|
|
+#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
|
|
+#define SSB_SROM8_FEM_ANTSWLUT 0xF800
|
|
+#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
|
|
+#define SSB_SPROM8_THERMAL 0x00B2
|
|
+#define SSB_SPROM8_MPWR_RAWTS 0x00B4
|
|
+#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
|
|
+#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
|
|
+#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
|
|
+
|
|
+/* There are 4 blocks with power info sharing the same layout */
|
|
+#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
|
|
+#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
|
|
+#define SSB_SROM8_PWR_INFO_CORE2 0x0100
|
|
+#define SSB_SROM8_PWR_INFO_CORE3 0x0120
|
|
+
|
|
+#define SSB_SROM8_2G_MAXP_ITSSI 0x00
|
|
+#define SSB_SPROM8_2G_MAXP 0x00FF
|
|
+#define SSB_SPROM8_2G_ITSSI 0xFF00
|
|
+#define SSB_SPROM8_2G_ITSSI_SHIFT 8
|
|
+#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
|
|
+#define SSB_SROM8_2G_PA_1 0x04
|
|
+#define SSB_SROM8_2G_PA_2 0x06
|
|
+#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
|
|
+#define SSB_SPROM8_5G_MAXP 0x00FF
|
|
+#define SSB_SPROM8_5G_ITSSI 0xFF00
|
|
+#define SSB_SPROM8_5G_ITSSI_SHIFT 8
|
|
+#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
|
|
+#define SSB_SPROM8_5GH_MAXP 0x00FF
|
|
+#define SSB_SPROM8_5GL_MAXP 0xFF00
|
|
+#define SSB_SPROM8_5GL_MAXP_SHIFT 8
|
|
+#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
|
|
+#define SSB_SROM8_5G_PA_1 0x0E
|
|
+#define SSB_SROM8_5G_PA_2 0x10
|
|
+#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
|
|
+#define SSB_SROM8_5GL_PA_1 0x14
|
|
+#define SSB_SROM8_5GL_PA_2 0x16
|
|
+#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
|
|
+#define SSB_SROM8_5GH_PA_1 0x1A
|
|
+#define SSB_SROM8_5GH_PA_2 0x1C
|
|
+
|
|
+/* TODO: Make it deprecated */
|
|
#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
|
|
#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
|
|
#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
|
|
@@ -456,12 +506,53 @@
|
|
#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
|
|
#define SSB_SPROM8_PA1HIB1 0x00DA
|
|
#define SSB_SPROM8_PA1HIB2 0x00DC
|
|
+
|
|
#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
|
|
#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
|
|
#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
|
|
#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
|
|
#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
|
|
|
|
+/* Values for boardflags_lo read from SPROM */
|
|
+#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
|
|
+#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
|
|
+#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
|
|
+#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
|
|
+#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
|
|
+#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
|
|
+#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
|
|
+#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
|
|
+#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
|
|
+#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
|
|
+#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
|
|
+#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
|
|
+#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
|
|
+#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
|
|
+#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
|
|
+#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
|
|
+
|
|
+/* Values for boardflags_hi read from SPROM */
|
|
+#define SSB_BFH_NOPA 0x0001 /* has no PA */
|
|
+#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
|
|
+#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
|
|
+#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
|
|
+#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
|
|
+#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
|
|
+#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
|
|
+
|
|
+/* Values for boardflags2_lo read from SPROM */
|
|
+#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
|
|
+#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
|
|
+#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
|
|
+#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
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+#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
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+#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
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+#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
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+#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
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+#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
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+#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
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+#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
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+
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/* Values for SSB_SPROM1_BINF_CCODE */
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enum {
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SSB_SPROM1CCODE_WORLD = 0,
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