mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-01 13:29:41 +02:00
17bba1a8f6
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11200 3c298f89-4303-0410-b956-a3cf2f4a3e73
66 lines
2.4 KiB
Diff
66 lines
2.4 KiB
Diff
Index: linux-2.6.23.17/drivers/ssb/driver_pcicore.c
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===================================================================
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--- linux-2.6.23.17.orig/drivers/ssb/driver_pcicore.c
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+++ linux-2.6.23.17/drivers/ssb/driver_pcicore.c
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@@ -66,6 +66,7 @@ int pcibios_plat_dev_init(struct pci_dev
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base = &ssb_pcicore_pcibus_iobase;
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else
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base = &ssb_pcicore_pcibus_membase;
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+ res->flags |= IORESOURCE_PCI_FIXED;
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if (res->end) {
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size = res->end - res->start + 1;
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if (*base & (size - 1))
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@@ -88,10 +89,12 @@ int pcibios_plat_dev_init(struct pci_dev
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static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
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{
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+ u8 lat;
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+
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if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
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return;
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- ssb_printk(KERN_INFO "PCI: fixing up bridge\n");
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+ ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
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/* Enable PCI bridge bus mastering and memory space */
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pci_set_master(dev);
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@@ -101,7 +104,10 @@ static void __init ssb_fixup_pcibridge(s
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pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
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/* Make sure our latency is high enough to handle the devices behind us */
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- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
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+ lat = 168;
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+ ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
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+ pci_name(dev), lat);
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+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
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@@ -279,14 +285,14 @@ static struct resource ssb_pcicore_mem_r
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.name = "SSB PCIcore external memory",
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.start = SSB_PCI_DMA,
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.end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
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- .flags = IORESOURCE_MEM,
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+ .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
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};
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static struct resource ssb_pcicore_io_resource = {
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.name = "SSB PCIcore external I/O",
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.start = 0x100,
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.end = 0x7FF,
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- .flags = IORESOURCE_IO,
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+ .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
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};
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static struct pci_controller ssb_pcicore_controller = {
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@@ -344,7 +350,8 @@ static void ssb_pcicore_init_hostmode(st
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/* Ok, ready to run, register it to the system.
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* The following needs change, if we want to port hostmode
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* to non-MIPS platform. */
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- set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
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+ ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
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+ set_io_port_base(ssb_pcicore_controller.io_map_base);
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/* Give some time to the PCI controller to configure itself with the new
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* values. Not waiting at this point causes crashes of the machine. */
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mdelay(10);
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