Release 12.2 Map M.63c (lin64)
Xilinx Map Application Log File for Design 'beta'

Design Information
------------------
Command Line   : map -pr b -p xc3s500e-VQ100-4 project.ngd 
Target Device  : xc3s500e
Target Package : vq100
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.52 $
Mapped Date    : Sun Oct 31 20:56:29 2010

Mapping design into LUTs...
Writing file project.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Writing design file "project.ncd"...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:           131 out of   9,312    1%
  Number of 4 input LUTs:               112 out of   9,312    1%
Logic Distribution:
  Number of occupied Slices:            118 out of   4,656    2%
    Number of Slices containing only related logic:     118 out of     118 100%
    Number of Slices containing unrelated logic:          0 out of     118   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         140 out of   9,312    1%
    Number used as logic:               112
    Number used as a route-thru:         28

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 34 out of      66   51%
    IOB Flip Flops:                      27
  Number of RAMB16s:                      4 out of      20   20%
  Number of BUFGMUXs:                     1 out of      24    4%

Average Fanout of Non-Clock Nets:                2.51

Peak Memory Usage:  367 MB
Total REAL time to MAP completion:  5 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "project.mrp" for details.
