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Code

Pins corrected again

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This commit is contained in:
Erwin Lopez 2010-10-31 14:13:54 -05:00
parent 551a96ecc3
commit 03456560f3
39 changed files with 860 additions and 854 deletions
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BIN
Examples/Beta1/logic/beta.bit
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32
Examples/Beta1/logic/beta.ucf
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@ -5,22 +5,22 @@ NET reset LOC = "P30"; #WARNING change to another pin
#NET led2 LOC = "P71"; #Pin superior izquierdo
#NET OD2 LOC = "P66";
#NET OD3 LOC = "P63";
#NET quadA LOC = "P67";
#NET quadB LOC = "P68";
#NET quadC LOC = "P70";
#NET quadD LOC = "P71";
NET quadA LOC = "P36"; #PINES DE PRUEBA
NET quadB LOC = "P35"; #PINES DE PRUEBA
NET quadC LOC = "P34"; #PINES DE PRUEBA
NET quadD LOC = "P33"; #PINES DE PRUEBA
#NET "hbridge<3>" LOC = "P53";
#NET "hbridge<2>" LOC = "P54";
#NET "hbridge<1>" LOC = "P49";
#NET "hbridge<0>" LOC = "P48";
NET "hbridge<3>" LOC = "P71";#PINES DE PRUEBA
NET "hbridge<2>" LOC = "P70"; #PINES DE PRUEBA
NET "hbridge<1>" LOC = "P68"; #PINES DE PRUEBA
NET "hbridge<0>" LOC = "P66"; #PINES DE PRUEBA
NET quadA LOC = "P71";
NET quadB LOC = "P68";
NET quadC LOC = "P70";
NET quadD LOC = "P66";
#NET quadA LOC = "P36"; #PINES DE PRUEBA
#NET quadB LOC = "P35"; #PINES DE PRUEBA
#NET quadC LOC = "P34"; #PINES DE PRUEBA
#NET quadD LOC = "P33"; #PINES DE PRUEBA
NET "hbridge<3>" LOC = "P53";
NET "hbridge<2>" LOC = "P57";
NET "hbridge<1>" LOC = "P27";
NET "hbridge<0>" LOC = "P49";
#NET "hbridge<3>" LOC = "P71";#PINES DE PRUEBA
#NET "hbridge<2>" LOC = "P70"; #PINES DE PRUEBA
#NET "hbridge<1>" LOC = "P68"; #PINES DE PRUEBA
#NET "hbridge<0>" LOC = "P66"; #PINES DE PRUEBA
#ADDRESS BUS
NET "addr<12>" LOC = "P90";

2
Examples/Beta1/logic/build/_xmsgs/bitgen.xmsgs
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@ -5,7 +5,7 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Bitgen" num="275" delta="old" >Spartan-3E devices do not support bitstream readback of the Blockram resources in the -4C speedgrade. If Blockram readback functionality is desired, it is suggested to target the -5C or -4I speedgrades.
<msg type="info" file="Bitgen" num="275" delta="new" >Spartan-3E devices do not support bitstream readback of the Blockram resources in the -4C speedgrade. If Blockram readback functionality is desired, it is suggested to target the -5C or -4I speedgrades.
</msg>
</messages>

8
Examples/Beta1/logic/build/_xmsgs/par.xmsgs
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@ -5,12 +5,14 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
</messages>

10
Examples/Beta1/logic/build/_xmsgs/trce.xmsgs
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@ -5,15 +5,15 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3390" delta="old" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
<msg type="info" file="Timing" num="3390" delta="new" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
<msg type="info" file="Timing" num="3389" delta="old" >This architecture does not support &apos;Discrete Jitter&apos; and &apos;Phase Error&apos; calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
<msg type="info" file="Timing" num="3389" delta="new" >This architecture does not support &apos;Discrete Jitter&apos; and &apos;Phase Error&apos; calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
</messages>

4
Examples/Beta1/logic/build/_xmsgs/xst.xmsgs
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@ -5,10 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompilers" num="259" delta="old" ><arg fmt="%s" index="1">&quot;../enco.v&quot; line 65 </arg>Connection to input port &apos;<arg fmt="%s" index="2">ADDRB</arg>&apos; does not match port size
<msg type="warning" file="HDLCompilers" num="259" delta="new" ><arg fmt="%s" index="1">&quot;../enco.v&quot; line 65 </arg>Connection to input port &apos;<arg fmt="%s" index="2">ADDRB</arg>&apos; does not match port size
</msg>
<msg type="warning" file="HDLCompilers" num="259" delta="old" ><arg fmt="%s" index="1">&quot;../enco.v&quot; line 65 </arg>Connection to input port &apos;<arg fmt="%s" index="2">ADDRB</arg>&apos; does not match port size
<msg type="warning" file="HDLCompilers" num="259" delta="new" ><arg fmt="%s" index="1">&quot;../enco.v&quot; line 65 </arg>Connection to input port &apos;<arg fmt="%s" index="2">ADDRB</arg>&apos; does not match port size
</msg>
</messages>

4
Examples/Beta1/logic/build/beta_map.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Sun Oct 31 12:20:39 2010">
<application stringID="Map" timeStamp="Sun Oct 31 14:11:34 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -54,7 +54,7 @@
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="375984"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="4 secs "/>
<item stringID="MAP_TOTAL_REAL_TIME" value="5 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="2 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">

144
Examples/Beta1/logic/build/beta_par.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Sun Oct 31 12:20:43 2010">
<application stringID="par" timeStamp="Sun Oct 31 14:11:36 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -48,11 +48,11 @@
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="23 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="21 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="22 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="24 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="21 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="22 secs "/>
</section>
</task>
<task stringID="PAR_par">
@ -72,7 +72,7 @@
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y1"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="99.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.082000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.075000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.204000"/>
</row>
</table>
@ -344,10 +344,18 @@
</row>
<row stringID="row" value="27">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P27"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;1>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L02N_2/MOSI/CSI_B"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="28">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P28"/>
@ -386,55 +394,31 @@
</row>
<row stringID="row" value="33">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P33"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadD"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L03N_2/D6/GCLK13"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="34">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P34"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadC"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO/D5"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="35">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P35"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadB"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L04P_2/D4/GCLK14"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="36">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P36"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadA"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L04N_2/D3/GCLK15"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="37">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P37"/>
@ -522,10 +506,18 @@
</row>
<row stringID="row" value="49">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P49"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;0>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L09P_2/VS0"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="50">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P50"/>
@ -544,10 +536,18 @@
</row>
<row stringID="row" value="53">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P53"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;3>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L01P_1"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="54">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P54"/>
@ -569,10 +569,18 @@
</row>
<row stringID="row" value="57">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P57"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;2>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L02P_1"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="58">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P58"/>
@ -626,17 +634,15 @@
</row>
<row stringID="row" value="66">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P66"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;0>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadD"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L05N_1/RHCLK5"/>
<item stringID="Direction" value="OUTPUT"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="67">
@ -648,17 +654,15 @@
</row>
<row stringID="row" value="68">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P68"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;1>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadB"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L06N_1/RHCLK7"/>
<item stringID="Direction" value="OUTPUT"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="69">
@ -676,32 +680,28 @@
</row>
<row stringID="row" value="70">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P70"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;2>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadC"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L07P_1"/>
<item stringID="Direction" value="OUTPUT"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="71">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P71"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;3>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadA"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L07N_1"/>
<item stringID="Direction" value="OUTPUT"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="72">

2
Examples/Beta1/logic/build/netlist.lst
View File

@ -1,2 +1,2 @@
/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build/project.ngc 1288492403
/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build/project.ngc 1288551154
OK

2
Examples/Beta1/logic/build/project.bld
View File

@ -27,7 +27,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 235700 kilobytes
Total memory usage is 235688 kilobytes
Writing NGD file "project.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec

6
Examples/Beta1/logic/build/project.log
View File

@ -644,13 +644,13 @@ Delay: 6.573ns (Levels of Logic = 3)
=========================================================================
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.71 secs
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 6.36 secs
-->
Total memory usage is 336112 kilobytes
Total memory usage is 336212 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)

4
Examples/Beta1/logic/build/project.map
View File

@ -8,7 +8,7 @@ Target Device : xc3s500e
Target Package : vq100
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.52 $
Mapped Date : Sun Oct 31 12:20:35 2010
Mapped Date : Sun Oct 31 14:11:28 2010
Mapping design into LUTs...
Writing file project.ngm...
@ -47,7 +47,7 @@ Logic Distribution:
Average Fanout of Non-Clock Nets: 2.51
Peak Memory Usage: 367 MB
Total REAL time to MAP completion: 4 secs
Total REAL time to MAP completion: 5 secs
Total CPU time to MAP completion: 2 secs
NOTES:

4
Examples/Beta1/logic/build/project.mrp
View File

@ -8,7 +8,7 @@ Target Device : xc3s500e
Target Package : vq100
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.52 $
Mapped Date : Sun Oct 31 12:20:35 2010
Mapped Date : Sun Oct 31 14:11:28 2010
Design Summary
--------------
@ -37,7 +37,7 @@ Logic Distribution:
Average Fanout of Non-Clock Nets: 2.51
Peak Memory Usage: 367 MB
Total REAL time to MAP completion: 4 secs
Total REAL time to MAP completion: 5 secs
Total CPU time to MAP completion: 2 secs
NOTES:

2
Examples/Beta1/logic/build/project.ncd
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File diff suppressed because one or more lines are too long

2
Examples/Beta1/logic/build/project.ngc
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File diff suppressed because one or more lines are too long

2
Examples/Beta1/logic/build/project.ngc_xst.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Oct 30 21:33:16 2010">
<application stringID="Xst" timeStamp="Sun Oct 31 13:52:26 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>

2
Examples/Beta1/logic/build/project.ngd
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File diff suppressed because one or more lines are too long

2
Examples/Beta1/logic/build/project.ngm
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File diff suppressed because one or more lines are too long

2
Examples/Beta1/logic/build/project.ngr
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File diff suppressed because one or more lines are too long

18
Examples/Beta1/logic/build/project.pcf
View File

@ -1,5 +1,5 @@
//! **************************************************************************
// Written by: Map M.63c on Sun Oct 31 12:20:38 2010
// Written by: Map M.63c on Sun Oct 31 14:11:32 2010
//! **************************************************************************
SCHEMATIC START;
@ -25,14 +25,14 @@ COMP "addr<11>" LOCATE = SITE "P91" LEVEL 1;
COMP "addr<12>" LOCATE = SITE "P90" LEVEL 1;
COMP "ncs" LOCATE = SITE "P69" LEVEL 1;
COMP "noe" LOCATE = SITE "P86" LEVEL 1;
COMP "hbridge<0>" LOCATE = SITE "P66" LEVEL 1;
COMP "hbridge<1>" LOCATE = SITE "P68" LEVEL 1;
COMP "hbridge<2>" LOCATE = SITE "P70" LEVEL 1;
COMP "hbridge<3>" LOCATE = SITE "P71" LEVEL 1;
COMP "quadA" LOCATE = SITE "P36" LEVEL 1;
COMP "quadB" LOCATE = SITE "P35" LEVEL 1;
COMP "quadC" LOCATE = SITE "P34" LEVEL 1;
COMP "quadD" LOCATE = SITE "P33" LEVEL 1;
COMP "hbridge<0>" LOCATE = SITE "P49" LEVEL 1;
COMP "hbridge<1>" LOCATE = SITE "P27" LEVEL 1;
COMP "hbridge<2>" LOCATE = SITE "P57" LEVEL 1;
COMP "hbridge<3>" LOCATE = SITE "P53" LEVEL 1;
COMP "quadA" LOCATE = SITE "P71" LEVEL 1;
COMP "quadB" LOCATE = SITE "P68" LEVEL 1;
COMP "quadC" LOCATE = SITE "P70" LEVEL 1;
COMP "quadD" LOCATE = SITE "P66" LEVEL 1;
COMP "nwe" LOCATE = SITE "P88" LEVEL 1;
COMP "reset" LOCATE = SITE "P30" LEVEL 1;
COMP "addr<0>" LOCATE = SITE "P84" LEVEL 1;

4
Examples/Beta1/logic/build/project_ngdbuild.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sun Oct 31 12:20:33 2010">
<application stringID="NgdBuild" timeStamp="Sun Oct 31 14:11:24 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -33,7 +33,7 @@
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz"/>
<item stringID="speed" value="2201.000 MHz"/>
<item stringID="speed" value="1200.000 MHz"/>
</row>
</table>
</section>

2
Examples/Beta1/logic/build/project_r.bgn
View File

@ -4,7 +4,7 @@ Loading device for application Rf_Device from file '3s500e.nph' in environment
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/.
"beta" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4
Sun Oct 31 12:21:10 2010
Sun Oct 31 14:12:04 2010
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -l -w -g TdoPin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpClk:CCLK project_r.ncd

2
Examples/Beta1/logic/build/project_r.drc
View File

@ -1,7 +1,7 @@
Release 12.2 Drc M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sun Oct 31 12:21:10 2010
Sun Oct 31 14:12:04 2010
drc -z project_r.ncd

336
Examples/Beta1/logic/build/project_r.ll
View File

@ -1,5 +1,5 @@
Revision 3
; Created by bitgen M.63c at Sun Oct 31 12:21:12 2010
; Created by bitgen M.63c at Sun Oct 31 14:12:05 2010
; Bit lines have the following form:
; <offset> <frame address> <frame offset> <information>
; <information> may be zero or more <kw>=<value> pairs
@ -58,34 +58,34 @@ Bit 17000 0x00020200 1480 Block=P11 Latch=IQ1 Net=buffer_data<3>
Bit 17103 0x00020200 1583 Block=P16 Latch=IQ1 Net=buffer_data<0>
Bit 17128 0x00020200 1608 Block=P15 Latch=IQ1 Net=buffer_data<1>
Bit 74568 0x00042400 72 Block=P98 Latch=IQ1 Net=buffer_addr<6>
Bit 186669 0x00082000 429 Block=RAMB16_X0Y9 Latch=DOA6 Net=rdBus3<6>
Bit 186683 0x00082000 443 Block=RAMB16_X0Y9 Latch=DOA5 Net=rdBus3<5>
Bit 186697 0x00082000 457 Block=RAMB16_X0Y9 Latch=DOA4 Net=rdBus3<4>
Bit 186725 0x00082000 485 Block=RAMB16_X0Y9 Latch=DOA3 Net=rdBus3<3>
Bit 186739 0x00082000 499 Block=RAMB16_X0Y9 Latch=DOA2 Net=rdBus3<2>
Bit 186753 0x00082000 513 Block=RAMB16_X0Y9 Latch=DOA1 Net=rdBus3<1>
Bit 186767 0x00082000 527 Block=RAMB16_X0Y9 Latch=DOA0 Net=rdBus3<0>
Bit 186925 0x00082000 685 Block=RAMB16_X0Y8 Latch=DOA6 Net=rdBus2<6>
Bit 186939 0x00082000 699 Block=RAMB16_X0Y8 Latch=DOA5 Net=rdBus2<5>
Bit 186953 0x00082000 713 Block=RAMB16_X0Y8 Latch=DOA4 Net=rdBus2<4>
Bit 186981 0x00082000 741 Block=RAMB16_X0Y8 Latch=DOA3 Net=rdBus2<3>
Bit 186995 0x00082000 755 Block=RAMB16_X0Y8 Latch=DOA2 Net=rdBus2<2>
Bit 187009 0x00082000 769 Block=RAMB16_X0Y8 Latch=DOA1 Net=rdBus2<1>
Bit 187023 0x00082000 783 Block=RAMB16_X0Y8 Latch=DOA0 Net=rdBus2<0>
Bit 187181 0x00082000 941 Block=RAMB16_X0Y7 Latch=DOA6 Net=rdBus0<6>
Bit 187195 0x00082000 955 Block=RAMB16_X0Y7 Latch=DOA5 Net=rdBus0<5>
Bit 187209 0x00082000 969 Block=RAMB16_X0Y7 Latch=DOA4 Net=rdBus0<4>
Bit 187237 0x00082000 997 Block=RAMB16_X0Y7 Latch=DOA3 Net=rdBus0<3>
Bit 187251 0x00082000 1011 Block=RAMB16_X0Y7 Latch=DOA2 Net=rdBus0<2>
Bit 187265 0x00082000 1025 Block=RAMB16_X0Y7 Latch=DOA1 Net=rdBus0<1>
Bit 187279 0x00082000 1039 Block=RAMB16_X0Y7 Latch=DOA0 Net=rdBus0<0>
Bit 187437 0x00082000 1197 Block=RAMB16_X0Y6 Latch=DOA6 Net=rdBus1<6>
Bit 187451 0x00082000 1211 Block=RAMB16_X0Y6 Latch=DOA5 Net=rdBus1<5>
Bit 187465 0x00082000 1225 Block=RAMB16_X0Y6 Latch=DOA4 Net=rdBus1<4>
Bit 187493 0x00082000 1253 Block=RAMB16_X0Y6 Latch=DOA3 Net=rdBus1<3>
Bit 187507 0x00082000 1267 Block=RAMB16_X0Y6 Latch=DOA2 Net=rdBus1<2>
Bit 187521 0x00082000 1281 Block=RAMB16_X0Y6 Latch=DOA1 Net=rdBus1<1>
Bit 187535 0x00082000 1295 Block=RAMB16_X0Y6 Latch=DOA0 Net=rdBus1<0>
Bit 186669 0x00082000 429 Block=RAMB16_X0Y9 Latch=DOA6 Net=rdBus0<6>
Bit 186683 0x00082000 443 Block=RAMB16_X0Y9 Latch=DOA5 Net=rdBus0<5>
Bit 186697 0x00082000 457 Block=RAMB16_X0Y9 Latch=DOA4 Net=rdBus0<4>
Bit 186725 0x00082000 485 Block=RAMB16_X0Y9 Latch=DOA3 Net=rdBus0<3>
Bit 186739 0x00082000 499 Block=RAMB16_X0Y9 Latch=DOA2 Net=rdBus0<2>
Bit 186753 0x00082000 513 Block=RAMB16_X0Y9 Latch=DOA1 Net=rdBus0<1>
Bit 186767 0x00082000 527 Block=RAMB16_X0Y9 Latch=DOA0 Net=rdBus0<0>
Bit 186925 0x00082000 685 Block=RAMB16_X0Y8 Latch=DOA6 Net=rdBus1<6>
Bit 186939 0x00082000 699 Block=RAMB16_X0Y8 Latch=DOA5 Net=rdBus1<5>
Bit 186953 0x00082000 713 Block=RAMB16_X0Y8 Latch=DOA4 Net=rdBus1<4>
Bit 186981 0x00082000 741 Block=RAMB16_X0Y8 Latch=DOA3 Net=rdBus1<3>
Bit 186995 0x00082000 755 Block=RAMB16_X0Y8 Latch=DOA2 Net=rdBus1<2>
Bit 187009 0x00082000 769 Block=RAMB16_X0Y8 Latch=DOA1 Net=rdBus1<1>
Bit 187023 0x00082000 783 Block=RAMB16_X0Y8 Latch=DOA0 Net=rdBus1<0>
Bit 187181 0x00082000 941 Block=RAMB16_X0Y7 Latch=DOA6 Net=rdBus3<6>
Bit 187195 0x00082000 955 Block=RAMB16_X0Y7 Latch=DOA5 Net=rdBus3<5>
Bit 187209 0x00082000 969 Block=RAMB16_X0Y7 Latch=DOA4 Net=rdBus3<4>
Bit 187237 0x00082000 997 Block=RAMB16_X0Y7 Latch=DOA3 Net=rdBus3<3>
Bit 187251 0x00082000 1011 Block=RAMB16_X0Y7 Latch=DOA2 Net=rdBus3<2>
Bit 187265 0x00082000 1025 Block=RAMB16_X0Y7 Latch=DOA1 Net=rdBus3<1>
Bit 187279 0x00082000 1039 Block=RAMB16_X0Y7 Latch=DOA0 Net=rdBus3<0>
Bit 187437 0x00082000 1197 Block=RAMB16_X0Y6 Latch=DOA6 Net=rdBus2<6>
Bit 187451 0x00082000 1211 Block=RAMB16_X0Y6 Latch=DOA5 Net=rdBus2<5>
Bit 187465 0x00082000 1225 Block=RAMB16_X0Y6 Latch=DOA4 Net=rdBus2<4>
Bit 187493 0x00082000 1253 Block=RAMB16_X0Y6 Latch=DOA3 Net=rdBus2<3>
Bit 187507 0x00082000 1267 Block=RAMB16_X0Y6 Latch=DOA2 Net=rdBus2<2>
Bit 187521 0x00082000 1281 Block=RAMB16_X0Y6 Latch=DOA1 Net=rdBus2<1>
Bit 187535 0x00082000 1295 Block=RAMB16_X0Y6 Latch=DOA0 Net=rdBus2<0>
Bit 245488 0x000a2000 272 Block=RAMB16_X0Y9 Ram=B:BIT31
Bit 245489 0x000a2000 273 Block=RAMB16_X0Y9 Ram=B:BIT159
Bit 245490 0x000a2000 274 Block=RAMB16_X0Y9 Ram=B:BIT287
@ -2102,6 +2102,7 @@ Bit 249612 0x000a2200 1292 Block=RAMB16_X0Y6 Ram=B:BIT416
Bit 249613 0x000a2200 1293 Block=RAMB16_X0Y6 Ram=B:BIT544
Bit 249614 0x000a2200 1294 Block=RAMB16_X0Y6 Ram=B:BIT672
Bit 249615 0x000a2200 1295 Block=RAMB16_X0Y6 Ram=B:BIT800
Bit 251376 0x000a2200 3056 Block=P27 Latch=O2 Net=puente/OUT1B/Mcompar_PWM_out_cy<7>
Bit 251696 0x000a2400 272 Block=RAMB16_X0Y9 Ram=B:BIT95
Bit 251697 0x000a2400 273 Block=RAMB16_X0Y9 Ram=B:BIT223
Bit 251698 0x000a2400 274 Block=RAMB16_X0Y9 Ram=B:BIT351
@ -73814,158 +73815,157 @@ Bit 479298 0x00121e00 1282 Block=RAMB16_X0Y6 Ram=B:BIT16240
Bit 479299 0x00121e00 1283 Block=RAMB16_X0Y6 Ram=B:BIT16368
Bit 479305 0x00121e00 1289 Block=RAMB16_X0Y6 Ram=B:BIT16224
Bit 479306 0x00121e00 1290 Block=RAMB16_X0Y6 Ram=B:BIT16352
Bit 485434 0x00122200 1210 Block=SLICE_X12Y56 Latch=YQ Net=wrBus<4>
Bit 485437 0x00122200 1213 Block=SLICE_X12Y56 Latch=XQ Net=wrBus<5>
Bit 488506 0x00122400 1178 Block=SLICE_X13Y57 Latch=YQ Net=wrBus<2>
Bit 488509 0x00122400 1181 Block=SLICE_X13Y57 Latch=XQ Net=wrBus<3>
Bit 488538 0x00122400 1210 Block=SLICE_X13Y56 Latch=YQ Net=wrBus<0>
Bit 488541 0x00122400 1213 Block=SLICE_X13Y56 Latch=XQ Net=wrBus<1>
Bit 547130 0x00142400 826 Block=SLICE_X15Y68 Latch=YQ Net=wrBus<6>
Bit 547133 0x00142400 829 Block=SLICE_X15Y68 Latch=XQ Net=wrBus<7>
Bit 488538 0x00122400 1210 Block=SLICE_X13Y56 Latch=YQ Net=wrBus<6>
Bit 488541 0x00122400 1213 Block=SLICE_X13Y56 Latch=XQ Net=wrBus<7>
Bit 547610 0x00142400 1306 Block=SLICE_X15Y53 Latch=YQ Net=wrBus<4>
Bit 547613 0x00142400 1309 Block=SLICE_X15Y53 Latch=XQ Net=wrBus<5>
Bit 547802 0x00142400 1498 Block=SLICE_X15Y47 Latch=YQ Net=wrBus<0>
Bit 547805 0x00142400 1501 Block=SLICE_X15Y47 Latch=XQ Net=wrBus<1>
Bit 606714 0x00162400 1434 Block=SLICE_X17Y49 Latch=YQ Net=wrBus<2>
Bit 606717 0x00162400 1437 Block=SLICE_X17Y49 Latch=XQ Net=wrBus<3>
Bit 665594 0x00182400 1338 Block=SLICE_X18Y52 Latch=YQ Net=puente/OUT1B/PWM_in_reg<0>
Bit 665597 0x00182400 1341 Block=SLICE_X18Y52 Latch=XQ Net=puente/OUT1B/PWM_in_reg<1>
Bit 667407 0x001a0000 47 Block=P95 Latch=IQ1 Net=buffer_addr<7>
Bit 667432 0x001a0000 72 Block=P94 Latch=IQ1 Net=buffer_addr<8>
Bit 668922 0x001a0000 1562 Block=SLICE_X19Y45 Latch=YQ Net=enco2/count<7>
Bit 668925 0x001a0000 1565 Block=SLICE_X19Y45 Latch=XQ Net=enco2/count<6>
Bit 668954 0x001a0000 1594 Block=SLICE_X19Y44 Latch=YQ Net=enco2/count<5>
Bit 668957 0x001a0000 1597 Block=SLICE_X19Y44 Latch=XQ Net=enco2/count<4>
Bit 668986 0x001a0000 1626 Block=SLICE_X19Y43 Latch=YQ Net=enco2/count<3>
Bit 668989 0x001a0000 1629 Block=SLICE_X19Y43 Latch=XQ Net=enco2/count<2>
Bit 669018 0x001a0000 1658 Block=SLICE_X19Y42 Latch=YQ Net=enco2/count<1>
Bit 669021 0x001a0000 1661 Block=SLICE_X19Y42 Latch=XQ Net=enco2/count<0>
Bit 727354 0x001c0000 1018 Block=SLICE_X21Y62 Latch=YQ Net=puente/we1
Bit 727674 0x001c0000 1338 Block=SLICE_X21Y52 Latch=YQ Net=enco1/count<7>
Bit 727677 0x001c0000 1341 Block=SLICE_X21Y52 Latch=XQ Net=enco1/count<6>
Bit 727706 0x001c0000 1370 Block=SLICE_X21Y51 Latch=YQ Net=enco1/count<5>
Bit 727709 0x001c0000 1373 Block=SLICE_X21Y51 Latch=XQ Net=enco1/count<4>
Bit 727738 0x001c0000 1402 Block=SLICE_X21Y50 Latch=YQ Net=enco1/count<3>
Bit 727741 0x001c0000 1405 Block=SLICE_X21Y50 Latch=XQ Net=enco1/count<2>
Bit 727770 0x001c0000 1434 Block=SLICE_X21Y49 Latch=YQ Net=enco1/count<1>
Bit 727773 0x001c0000 1437 Block=SLICE_X21Y49 Latch=XQ Net=enco1/count<0>
Bit 728250 0x001c0000 1914 Block=SLICE_X21Y34 Latch=YQ Net=enco2/quadA_delayed<1>
Bit 728253 0x001c0000 1917 Block=SLICE_X21Y34 Latch=XQ Net=enco2/quadA_delayed<2>
Bit 787194 0x001e0000 1882 Block=SLICE_X23Y35 Latch=YQ Net=enco1/quadB_delayed<1>
Bit 787197 0x001e0000 1885 Block=SLICE_X23Y35 Latch=XQ Net=enco1/quadB_delayed<2>
Bit 787226 0x001e0000 1914 Block=SLICE_X23Y34 Latch=YQ Net=enco1/quadA_delayed<1>
Bit 787229 0x001e0000 1917 Block=SLICE_X23Y34 Latch=XQ Net=enco1/quadA_delayed<2>
Bit 842362 0x001e2400 1178 Block=SLICE_X24Y57 Latch=YQ Net=puente/PWM_3<2>
Bit 842365 0x001e2400 1181 Block=SLICE_X24Y57 Latch=XQ Net=puente/PWM_3<3>
Bit 842394 0x001e2400 1210 Block=SLICE_X24Y56 Latch=YQ Net=puente/OUT2A/PWM_in_reg<2>
Bit 842397 0x001e2400 1213 Block=SLICE_X24Y56 Latch=XQ Net=puente/OUT2A/PWM_in_reg<3>
Bit 845498 0x00200000 1210 Block=SLICE_X25Y56 Latch=YQ Net=puente/OUT2A/PWM_in_reg<0>
Bit 845501 0x00200000 1213 Block=SLICE_X25Y56 Latch=XQ Net=puente/OUT2A/PWM_in_reg<1>
Bit 846170 0x00200000 1882 Block=SLICE_X25Y35 Latch=YQ Net=enco2/quadB_delayed<1>
Bit 846173 0x00200000 1885 Block=SLICE_X25Y35 Latch=XQ Net=enco2/quadB_delayed<2>
Bit 901274 0x00202400 1114 Block=SLICE_X26Y59 Latch=YQ Net=puente/OUT2A/PWM_in_reg<4>
Bit 901277 0x00202400 1117 Block=SLICE_X26Y59 Latch=XQ Net=puente/OUT2A/PWM_in_reg<5>
Bit 904378 0x00220000 1114 Block=SLICE_X27Y59 Latch=YQ Net=puente/PWM_3<0>
Bit 904381 0x00220000 1117 Block=SLICE_X27Y59 Latch=XQ Net=puente/PWM_3<1>
Bit 904474 0x00220000 1210 Block=SLICE_X27Y56 Latch=YQ Net=puente/PWM_3<4>
Bit 904477 0x00220000 1213 Block=SLICE_X27Y56 Latch=XQ Net=puente/PWM_3<5>
Bit 668730 0x001a0000 1370 Block=SLICE_X19Y51 Latch=YQ Net=puente/OUT1B/PWM_in_reg<2>
Bit 668733 0x001a0000 1373 Block=SLICE_X19Y51 Latch=XQ Net=puente/OUT1B/PWM_in_reg<3>
Bit 724474 0x001a2400 1242 Block=SLICE_X20Y55 Latch=YQ Net=puente/PWM_2<2>
Bit 724477 0x001a2400 1245 Block=SLICE_X20Y55 Latch=XQ Net=puente/PWM_2<3>
Bit 724506 0x001a2400 1274 Block=SLICE_X20Y54 Latch=YQ Net=puente/PWM_2<4>
Bit 724509 0x001a2400 1277 Block=SLICE_X20Y54 Latch=XQ Net=puente/PWM_2<5>
Bit 724634 0x001a2400 1402 Block=SLICE_X20Y50 Latch=YQ Net=puente/PWM_2<0>
Bit 724637 0x001a2400 1405 Block=SLICE_X20Y50 Latch=XQ Net=puente/PWM_2<1>
Bit 724666 0x001a2400 1434 Block=SLICE_X20Y49 Latch=YQ Net=puente/OUT1B/PWM_in_reg<6>
Bit 724669 0x001a2400 1437 Block=SLICE_X20Y49 Latch=XQ Net=puente/OUT1B/PWM_in_reg<7>
Bit 727642 0x001c0000 1306 Block=SLICE_X21Y53 Latch=YQ Net=puente/OUT1B/PWM_accum<7>
Bit 727645 0x001c0000 1309 Block=SLICE_X21Y53 Latch=XQ Net=puente/OUT1B/PWM_accum<6>
Bit 727674 0x001c0000 1338 Block=SLICE_X21Y52 Latch=YQ Net=puente/OUT1B/PWM_accum<5>
Bit 727677 0x001c0000 1341 Block=SLICE_X21Y52 Latch=XQ Net=puente/OUT1B/PWM_accum<4>
Bit 727706 0x001c0000 1370 Block=SLICE_X21Y51 Latch=YQ Net=puente/OUT1B/PWM_accum<3>
Bit 727709 0x001c0000 1373 Block=SLICE_X21Y51 Latch=XQ Net=puente/OUT1B/PWM_accum<2>
Bit 727738 0x001c0000 1402 Block=SLICE_X21Y50 Latch=YQ Net=puente/OUT1B/PWM_accum<1>
Bit 727741 0x001c0000 1405 Block=SLICE_X21Y50 Latch=XQ Net=puente/OUT1B/PWM_accum<0>
Bit 783610 0x001c2400 1402 Block=SLICE_X22Y50 Latch=YQ Net=puente/PWM_2<6>
Bit 783613 0x001c2400 1405 Block=SLICE_X22Y50 Latch=XQ Net=puente/PWM_2<7>
Bit 786714 0x001e0000 1402 Block=SLICE_X23Y50 Latch=YQ Net=puente/OUT1B/PWM_in_reg<4>
Bit 786717 0x001e0000 1405 Block=SLICE_X23Y50 Latch=XQ Net=puente/OUT1B/PWM_in_reg<5>
Bit 845370 0x00200000 1082 Block=SLICE_X25Y60 Latch=YQ Net=puente/we1
Bit 904154 0x00220000 890 Block=SLICE_X27Y66 Latch=YQ Net=enco1/count<7>
Bit 904157 0x00220000 893 Block=SLICE_X27Y66 Latch=XQ Net=enco1/count<6>
Bit 904186 0x00220000 922 Block=SLICE_X27Y65 Latch=YQ Net=enco1/count<5>
Bit 904189 0x00220000 925 Block=SLICE_X27Y65 Latch=XQ Net=enco1/count<4>
Bit 904218 0x00220000 954 Block=SLICE_X27Y64 Latch=YQ Net=enco1/count<3>
Bit 904221 0x00220000 957 Block=SLICE_X27Y64 Latch=XQ Net=enco1/count<2>
Bit 904250 0x00220000 986 Block=SLICE_X27Y63 Latch=YQ Net=enco1/count<1>
Bit 904253 0x00220000 989 Block=SLICE_X27Y63 Latch=XQ Net=enco1/count<0>
Bit 904346 0x00220000 1082 Block=SLICE_X27Y60 Latch=YQ Net=enco2/count<7>
Bit 904349 0x00220000 1085 Block=SLICE_X27Y60 Latch=XQ Net=enco2/count<6>
Bit 904378 0x00220000 1114 Block=SLICE_X27Y59 Latch=YQ Net=enco2/count<5>
Bit 904381 0x00220000 1117 Block=SLICE_X27Y59 Latch=XQ Net=enco2/count<4>
Bit 904410 0x00220000 1146 Block=SLICE_X27Y58 Latch=YQ Net=enco2/count<3>
Bit 904413 0x00220000 1149 Block=SLICE_X27Y58 Latch=XQ Net=enco2/count<2>
Bit 904442 0x00220000 1178 Block=SLICE_X27Y57 Latch=YQ Net=enco2/count<1>
Bit 904445 0x00220000 1181 Block=SLICE_X27Y57 Latch=XQ Net=enco2/count<0>
Bit 909416 0x00220200 3048 Block=P30 Latch=I Net=reset_IBUF
Bit 960314 0x00222400 1178 Block=SLICE_X28Y57 Latch=YQ Net=puente/OUT2A/PWM_in_reg<6>
Bit 960317 0x00222400 1181 Block=SLICE_X28Y57 Latch=XQ Net=puente/OUT2A/PWM_in_reg<7>
Bit 960346 0x00222400 1210 Block=SLICE_X28Y56 Latch=YQ Net=puente/PWM_3<6>
Bit 960349 0x00222400 1213 Block=SLICE_X28Y56 Latch=XQ Net=puente/PWM_3<7>
Bit 960474 0x00222400 1338 Block=SLICE_X28Y52 Latch=YQ Net=puente/PWM_1<0>
Bit 960477 0x00222400 1341 Block=SLICE_X28Y52 Latch=XQ Net=puente/PWM_1<1>
Bit 960538 0x00222400 1402 Block=SLICE_X28Y50 Latch=YQ Net=puente/PWM_1<2>
Bit 960541 0x00222400 1405 Block=SLICE_X28Y50 Latch=XQ Net=puente/PWM_1<3>
Bit 960602 0x00222400 1466 Block=SLICE_X28Y48 Latch=YQ Net=puente/PWM_1<6>
Bit 960605 0x00222400 1469 Block=SLICE_X28Y48 Latch=XQ Net=puente/PWM_1<7>
Bit 960730 0x00222400 1594 Block=SLICE_X28Y44 Latch=YQ Net=puente/OUT1A/PWM_in_reg<0>
Bit 960733 0x00222400 1597 Block=SLICE_X28Y44 Latch=XQ Net=puente/OUT1A/PWM_in_reg<1>
Bit 962272 0x00240000 32 Block=P92 Latch=IQ1 Net=buffer_addr<9>
Bit 963290 0x00240000 1050 Block=SLICE_X29Y61 Latch=YQ Net=puente/OUT2A/PWM_accum<7>
Bit 963293 0x00240000 1053 Block=SLICE_X29Y61 Latch=XQ Net=puente/OUT2A/PWM_accum<6>
Bit 963322 0x00240000 1082 Block=SLICE_X29Y60 Latch=YQ Net=puente/OUT2A/PWM_accum<5>
Bit 963325 0x00240000 1085 Block=SLICE_X29Y60 Latch=XQ Net=puente/OUT2A/PWM_accum<4>
Bit 963354 0x00240000 1114 Block=SLICE_X29Y59 Latch=YQ Net=puente/OUT2A/PWM_accum<3>
Bit 963357 0x00240000 1117 Block=SLICE_X29Y59 Latch=XQ Net=puente/OUT2A/PWM_accum<2>
Bit 963386 0x00240000 1146 Block=SLICE_X29Y58 Latch=YQ Net=puente/OUT2A/PWM_accum<1>
Bit 963389 0x00240000 1149 Block=SLICE_X29Y58 Latch=XQ Net=puente/OUT2A/PWM_accum<0>
Bit 965295 0x00240000 3055 Block=P33 Latch=IQ1 Net=enco2/quadB_delayed<0>
Bit 1019194 0x00242400 1082 Block=SLICE_X30Y60 Latch=YQ Net=puente/PWM_1<4>
Bit 1019197 0x00242400 1085 Block=SLICE_X30Y60 Latch=XQ Net=puente/PWM_1<5>
Bit 1019354 0x00242400 1242 Block=SLICE_X30Y55 Latch=YQ Net=puente/PWM_1<2>
Bit 1019357 0x00242400 1245 Block=SLICE_X30Y55 Latch=XQ Net=puente/PWM_1<3>
Bit 1019514 0x00242400 1402 Block=SLICE_X30Y50 Latch=YQ Net=puente/OUT1A/PWM_in_reg<4>
Bit 1019517 0x00242400 1405 Block=SLICE_X30Y50 Latch=XQ Net=puente/OUT1A/PWM_in_reg<5>
Bit 963610 0x00240000 1370 Block=SLICE_X29Y51 Latch=YQ Net=puente/PWM_1<4>
Bit 963613 0x00240000 1373 Block=SLICE_X29Y51 Latch=XQ Net=puente/PWM_1<5>
Bit 963674 0x00240000 1434 Block=SLICE_X29Y49 Latch=YQ Net=puente/OUT1A/PWM_accum<7>
Bit 963677 0x00240000 1437 Block=SLICE_X29Y49 Latch=XQ Net=puente/OUT1A/PWM_accum<6>
Bit 963706 0x00240000 1466 Block=SLICE_X29Y48 Latch=YQ Net=puente/OUT1A/PWM_accum<5>
Bit 963709 0x00240000 1469 Block=SLICE_X29Y48 Latch=XQ Net=puente/OUT1A/PWM_accum<4>
Bit 963738 0x00240000 1498 Block=SLICE_X29Y47 Latch=YQ Net=puente/OUT1A/PWM_accum<3>
Bit 963741 0x00240000 1501 Block=SLICE_X29Y47 Latch=XQ Net=puente/OUT1A/PWM_accum<2>
Bit 963770 0x00240000 1530 Block=SLICE_X29Y46 Latch=YQ Net=puente/OUT1A/PWM_accum<1>
Bit 963773 0x00240000 1533 Block=SLICE_X29Y46 Latch=XQ Net=puente/OUT1A/PWM_accum<0>
Bit 963834 0x00240000 1594 Block=SLICE_X29Y44 Latch=YQ Net=puente/OUT1A/PWM_in_reg<2>
Bit 963837 0x00240000 1597 Block=SLICE_X29Y44 Latch=XQ Net=puente/OUT1A/PWM_in_reg<3>
Bit 1019482 0x00242400 1370 Block=SLICE_X30Y51 Latch=YQ Net=puente/OUT2B/PWM_in_reg<2>
Bit 1019485 0x00242400 1373 Block=SLICE_X30Y51 Latch=XQ Net=puente/OUT2B/PWM_in_reg<3>
Bit 1019514 0x00242400 1402 Block=SLICE_X30Y50 Latch=YQ Net=puente/PWM_4<2>
Bit 1019517 0x00242400 1405 Block=SLICE_X30Y50 Latch=XQ Net=puente/PWM_4<3>
Bit 1019674 0x00242400 1562 Block=SLICE_X30Y45 Latch=YQ Net=puente/PWM_4<0>
Bit 1019677 0x00242400 1565 Block=SLICE_X30Y45 Latch=XQ Net=puente/PWM_4<1>
Bit 1019706 0x00242400 1594 Block=SLICE_X30Y44 Latch=YQ Net=puente/OUT1A/PWM_in_reg<6>
Bit 1019709 0x00242400 1597 Block=SLICE_X30Y44 Latch=XQ Net=puente/OUT1A/PWM_in_reg<7>
Bit 1021263 0x00260000 47 Block=P91 Latch=IQ1 Net=buffer_addr<11>
Bit 1021288 0x00260000 72 Block=P90 Latch=IQ1 Net=buffer_addr<12>
Bit 1022298 0x00260000 1082 Block=SLICE_X31Y60 Latch=YQ Net=puente/OUT1A/PWM_in_reg<0>
Bit 1022301 0x00260000 1085 Block=SLICE_X31Y60 Latch=XQ Net=puente/OUT1A/PWM_in_reg<1>
Bit 1022330 0x00260000 1114 Block=SLICE_X31Y59 Latch=YQ Net=puente/PWM_1<0>
Bit 1022333 0x00260000 1117 Block=SLICE_X31Y59 Latch=XQ Net=puente/PWM_1<1>
Bit 1022362 0x00260000 1146 Block=SLICE_X31Y58 Latch=YQ Net=puente/PWM_1<6>
Bit 1022365 0x00260000 1149 Block=SLICE_X31Y58 Latch=XQ Net=puente/PWM_1<7>
Bit 1022394 0x00260000 1178 Block=SLICE_X31Y57 Latch=YQ Net=puente/OUT1A/PWM_accum<7>
Bit 1022397 0x00260000 1181 Block=SLICE_X31Y57 Latch=XQ Net=puente/OUT1A/PWM_accum<6>
Bit 1022426 0x00260000 1210 Block=SLICE_X31Y56 Latch=YQ Net=puente/OUT1A/PWM_accum<5>
Bit 1022429 0x00260000 1213 Block=SLICE_X31Y56 Latch=XQ Net=puente/OUT1A/PWM_accum<4>
Bit 1022458 0x00260000 1242 Block=SLICE_X31Y55 Latch=YQ Net=puente/OUT1A/PWM_accum<3>
Bit 1022461 0x00260000 1245 Block=SLICE_X31Y55 Latch=XQ Net=puente/OUT1A/PWM_accum<2>
Bit 1022490 0x00260000 1274 Block=SLICE_X31Y54 Latch=YQ Net=puente/OUT1A/PWM_accum<1>
Bit 1022493 0x00260000 1277 Block=SLICE_X31Y54 Latch=XQ Net=puente/OUT1A/PWM_accum<0>
Bit 1024256 0x00260000 3040 Block=P34 Latch=IQ1 Net=enco2/quadA_delayed<0>
Bit 1078010 0x00262400 922 Block=SLICE_X32Y65 Latch=YQ Net=puente/PWM_2<4>
Bit 1078013 0x00262400 925 Block=SLICE_X32Y65 Latch=XQ Net=puente/PWM_2<5>
Bit 1078042 0x00262400 954 Block=SLICE_X32Y64 Latch=YQ Net=puente/PWM_4<2>
Bit 1078045 0x00262400 957 Block=SLICE_X32Y64 Latch=XQ Net=puente/PWM_4<3>
Bit 1078074 0x00262400 986 Block=SLICE_X32Y63 Latch=YQ Net=puente/PWM_2<6>
Bit 1078077 0x00262400 989 Block=SLICE_X32Y63 Latch=XQ Net=puente/PWM_2<7>
Bit 1078106 0x00262400 1018 Block=SLICE_X32Y62 Latch=YQ Net=puente/PWM_4<4>
Bit 1078109 0x00262400 1021 Block=SLICE_X32Y62 Latch=XQ Net=puente/PWM_4<5>
Bit 1078138 0x00262400 1050 Block=SLICE_X32Y61 Latch=YQ Net=puente/OUT2B/PWM_in_reg<2>
Bit 1078141 0x00262400 1053 Block=SLICE_X32Y61 Latch=XQ Net=puente/OUT2B/PWM_in_reg<3>
Bit 1078490 0x00262400 1402 Block=SLICE_X32Y50 Latch=YQ Net=puente/OUT1A/PWM_in_reg<6>
Bit 1078493 0x00262400 1405 Block=SLICE_X32Y50 Latch=XQ Net=puente/OUT1A/PWM_in_reg<7>
Bit 1022554 0x00260000 1338 Block=SLICE_X31Y52 Latch=YQ Net=enco2/quadB_delayed<1>
Bit 1022557 0x00260000 1341 Block=SLICE_X31Y52 Latch=XQ Net=enco2/quadB_delayed<2>
Bit 1022618 0x00260000 1402 Block=SLICE_X31Y50 Latch=YQ Net=puente/OUT1A/PWM_in_reg<4>
Bit 1022621 0x00260000 1405 Block=SLICE_X31Y50 Latch=XQ Net=puente/OUT1A/PWM_in_reg<5>
Bit 1022650 0x00260000 1434 Block=SLICE_X31Y49 Latch=YQ Net=puente/PWM_4<4>
Bit 1022653 0x00260000 1437 Block=SLICE_X31Y49 Latch=XQ Net=puente/PWM_4<5>
Bit 1022682 0x00260000 1466 Block=SLICE_X31Y48 Latch=YQ Net=puente/OUT2B/PWM_accum<7>
Bit 1022685 0x00260000 1469 Block=SLICE_X31Y48 Latch=XQ Net=puente/OUT2B/PWM_accum<6>
Bit 1022714 0x00260000 1498 Block=SLICE_X31Y47 Latch=YQ Net=puente/OUT2B/PWM_accum<5>
Bit 1022717 0x00260000 1501 Block=SLICE_X31Y47 Latch=XQ Net=puente/OUT2B/PWM_accum<4>
Bit 1022746 0x00260000 1530 Block=SLICE_X31Y46 Latch=YQ Net=puente/OUT2B/PWM_accum<3>
Bit 1022749 0x00260000 1533 Block=SLICE_X31Y46 Latch=XQ Net=puente/OUT2B/PWM_accum<2>
Bit 1022778 0x00260000 1562 Block=SLICE_X31Y45 Latch=YQ Net=puente/OUT2B/PWM_accum<1>
Bit 1022781 0x00260000 1565 Block=SLICE_X31Y45 Latch=XQ Net=puente/OUT2B/PWM_accum<0>
Bit 1022810 0x00260000 1594 Block=SLICE_X31Y44 Latch=YQ Net=puente/OUT2B/PWM_in_reg<4>
Bit 1022813 0x00260000 1597 Block=SLICE_X31Y44 Latch=XQ Net=puente/OUT2B/PWM_in_reg<5>
Bit 1078170 0x00262400 1082 Block=SLICE_X32Y60 Latch=YQ Net=we
Bit 1078173 0x00262400 1085 Block=SLICE_X32Y60 Latch=XQ Net=w_st
Bit 1078394 0x00262400 1306 Block=SLICE_X32Y53 Latch=YQ Net=puente/PWM_3<4>
Bit 1078397 0x00262400 1309 Block=SLICE_X32Y53 Latch=XQ Net=puente/PWM_3<5>
Bit 1078426 0x00262400 1338 Block=SLICE_X32Y52 Latch=YQ Net=puente/PWM_3<2>
Bit 1078429 0x00262400 1341 Block=SLICE_X32Y52 Latch=XQ Net=puente/PWM_3<3>
Bit 1078586 0x00262400 1498 Block=SLICE_X32Y47 Latch=YQ Net=puente/PWM_4<6>
Bit 1078589 0x00262400 1501 Block=SLICE_X32Y47 Latch=XQ Net=puente/PWM_4<7>
Bit 1080264 0x00280000 72 Block=P88 Latch=IQ1 Net=snwe
Bit 1081146 0x00280000 954 Block=SLICE_X33Y64 Latch=YQ Net=we
Bit 1081149 0x00280000 957 Block=SLICE_X33Y64 Latch=XQ Net=w_st
Bit 1081210 0x00280000 1018 Block=SLICE_X33Y62 Latch=YQ Net=puente/PWM_2<2>
Bit 1081213 0x00280000 1021 Block=SLICE_X33Y62 Latch=XQ Net=puente/PWM_2<3>
Bit 1081242 0x00280000 1050 Block=SLICE_X33Y61 Latch=YQ Net=puente/PWM_4<6>
Bit 1081245 0x00280000 1053 Block=SLICE_X33Y61 Latch=XQ Net=puente/PWM_4<7>
Bit 1081274 0x00280000 1082 Block=SLICE_X33Y60 Latch=YQ Net=puente/OUT2B/PWM_accum<7>
Bit 1081277 0x00280000 1085 Block=SLICE_X33Y60 Latch=XQ Net=puente/OUT2B/PWM_accum<6>
Bit 1081306 0x00280000 1114 Block=SLICE_X33Y59 Latch=YQ Net=puente/OUT2B/PWM_accum<5>
Bit 1081309 0x00280000 1117 Block=SLICE_X33Y59 Latch=XQ Net=puente/OUT2B/PWM_accum<4>
Bit 1081338 0x00280000 1146 Block=SLICE_X33Y58 Latch=YQ Net=puente/OUT2B/PWM_accum<3>
Bit 1081341 0x00280000 1149 Block=SLICE_X33Y58 Latch=XQ Net=puente/OUT2B/PWM_accum<2>
Bit 1081370 0x00280000 1178 Block=SLICE_X33Y57 Latch=YQ Net=puente/OUT2B/PWM_accum<1>
Bit 1081373 0x00280000 1181 Block=SLICE_X33Y57 Latch=XQ Net=puente/OUT2B/PWM_accum<0>
Bit 1081402 0x00280000 1210 Block=SLICE_X33Y56 Latch=YQ Net=puente/PWM_4<0>
Bit 1081405 0x00280000 1213 Block=SLICE_X33Y56 Latch=XQ Net=puente/PWM_4<1>
Bit 1083247 0x00280000 3055 Block=P36 Latch=IQ1 Net=enco1/quadA_delayed<0>
Bit 1083272 0x00280000 3080 Block=P35 Latch=IQ1 Net=enco1/quadB_delayed<0>
Bit 1140058 0x002a0000 890 Block=SLICE_X34Y66 Latch=YQ Net=puente/OUT1B/PWM_in_reg<4>
Bit 1140061 0x002a0000 893 Block=SLICE_X34Y66 Latch=XQ Net=puente/OUT1B/PWM_in_reg<5>
Bit 1140122 0x002a0000 954 Block=SLICE_X34Y64 Latch=YQ Net=puente/PWM_2<0>
Bit 1140125 0x002a0000 957 Block=SLICE_X34Y64 Latch=XQ Net=puente/PWM_2<1>
Bit 1140250 0x002a0000 1082 Block=SLICE_X34Y60 Latch=YQ Net=puente/OUT2B/PWM_in_reg<0>
Bit 1140253 0x002a0000 1085 Block=SLICE_X34Y60 Latch=XQ Net=puente/OUT2B/PWM_in_reg<1>
Bit 1140506 0x002a0000 1338 Block=SLICE_X34Y52 Latch=YQ Net=puente/OUT1A/PWM_in_reg<2>
Bit 1140509 0x002a0000 1341 Block=SLICE_X34Y52 Latch=XQ Net=puente/OUT1A/PWM_in_reg<3>
Bit 1081370 0x00280000 1178 Block=SLICE_X33Y57 Latch=YQ Net=puente/OUT2A/PWM_in_reg<4>
Bit 1081373 0x00280000 1181 Block=SLICE_X33Y57 Latch=XQ Net=puente/OUT2A/PWM_in_reg<5>
Bit 1081466 0x00280000 1274 Block=SLICE_X33Y54 Latch=YQ Net=puente/OUT2A/PWM_accum<7>
Bit 1081469 0x00280000 1277 Block=SLICE_X33Y54 Latch=XQ Net=puente/OUT2A/PWM_accum<6>
Bit 1081498 0x00280000 1306 Block=SLICE_X33Y53 Latch=YQ Net=puente/OUT2A/PWM_accum<5>
Bit 1081501 0x00280000 1309 Block=SLICE_X33Y53 Latch=XQ Net=puente/OUT2A/PWM_accum<4>
Bit 1081530 0x00280000 1338 Block=SLICE_X33Y52 Latch=YQ Net=puente/OUT2A/PWM_accum<3>
Bit 1081533 0x00280000 1341 Block=SLICE_X33Y52 Latch=XQ Net=puente/OUT2A/PWM_accum<2>
Bit 1081562 0x00280000 1370 Block=SLICE_X33Y51 Latch=YQ Net=puente/OUT2A/PWM_accum<1>
Bit 1081565 0x00280000 1373 Block=SLICE_X33Y51 Latch=XQ Net=puente/OUT2A/PWM_accum<0>
Bit 1140442 0x002a0000 1274 Block=SLICE_X34Y54 Latch=YQ Net=puente/OUT2A/PWM_in_reg<0>
Bit 1140445 0x002a0000 1277 Block=SLICE_X34Y54 Latch=XQ Net=puente/OUT2A/PWM_in_reg<1>
Bit 1140538 0x002a0000 1370 Block=SLICE_X34Y51 Latch=YQ Net=puente/PWM_3<0>
Bit 1140541 0x002a0000 1373 Block=SLICE_X34Y51 Latch=XQ Net=puente/PWM_3<1>
Bit 1140570 0x002a0000 1402 Block=SLICE_X34Y50 Latch=YQ Net=puente/PWM_3<6>
Bit 1140573 0x002a0000 1405 Block=SLICE_X34Y50 Latch=XQ Net=puente/PWM_3<7>
Bit 1140762 0x002a0000 1594 Block=SLICE_X34Y44 Latch=YQ Net=puente/OUT2B/PWM_in_reg<6>
Bit 1140765 0x002a0000 1597 Block=SLICE_X34Y44 Latch=XQ Net=puente/OUT2B/PWM_in_reg<7>
Bit 1142344 0x002a0200 72 Block=P85 Latch=IQ1 Net=buffer_addr<10>
Bit 1143162 0x002a0200 890 Block=SLICE_X35Y66 Latch=YQ Net=puente/OUT1B/PWM_in_reg<0>
Bit 1143165 0x002a0200 893 Block=SLICE_X35Y66 Latch=XQ Net=puente/OUT1B/PWM_in_reg<1>
Bit 1143226 0x002a0200 954 Block=SLICE_X35Y64 Latch=YQ Net=puente/OUT2B/PWM_in_reg<6>
Bit 1143229 0x002a0200 957 Block=SLICE_X35Y64 Latch=XQ Net=puente/OUT2B/PWM_in_reg<7>
Bit 1143258 0x002a0200 986 Block=SLICE_X35Y63 Latch=YQ Net=puente/OUT1B/PWM_accum<7>
Bit 1143261 0x002a0200 989 Block=SLICE_X35Y63 Latch=XQ Net=puente/OUT1B/PWM_accum<6>
Bit 1143290 0x002a0200 1018 Block=SLICE_X35Y62 Latch=YQ Net=puente/OUT1B/PWM_accum<5>
Bit 1143293 0x002a0200 1021 Block=SLICE_X35Y62 Latch=XQ Net=puente/OUT1B/PWM_accum<4>
Bit 1143322 0x002a0200 1050 Block=SLICE_X35Y61 Latch=YQ Net=puente/OUT1B/PWM_accum<3>
Bit 1143325 0x002a0200 1053 Block=SLICE_X35Y61 Latch=XQ Net=puente/OUT1B/PWM_accum<2>
Bit 1143354 0x002a0200 1082 Block=SLICE_X35Y60 Latch=YQ Net=puente/OUT1B/PWM_accum<1>
Bit 1143357 0x002a0200 1085 Block=SLICE_X35Y60 Latch=XQ Net=puente/OUT1B/PWM_accum<0>
Bit 1143450 0x002a0200 1178 Block=SLICE_X35Y57 Latch=YQ Net=puente/OUT2A/PWM_in_reg<6>
Bit 1143453 0x002a0200 1181 Block=SLICE_X35Y57 Latch=XQ Net=puente/OUT2A/PWM_in_reg<7>
Bit 1143482 0x002a0200 1210 Block=SLICE_X35Y56 Latch=YQ Net=puente/OUT2A/PWM_in_reg<2>
Bit 1143485 0x002a0200 1213 Block=SLICE_X35Y56 Latch=XQ Net=puente/OUT2A/PWM_in_reg<3>
Bit 1143898 0x002a0200 1626 Block=SLICE_X35Y43 Latch=YQ Net=puente/OUT2B/PWM_in_reg<0>
Bit 1143901 0x002a0200 1629 Block=SLICE_X35Y43 Latch=XQ Net=puente/OUT2B/PWM_in_reg<1>
Bit 1145416 0x002a0400 40 Block=P86 Latch=I Net=noe_IBUF
Bit 1148463 0x002a0400 3087 Block=P38 Latch=I Net=clk_BUFGP/IBUFG
Bit 1199194 0x002c0000 1050 Block=SLICE_X36Y61 Latch=YQ Net=puente/OUT2B/PWM_in_reg<4>
Bit 1199197 0x002c0000 1053 Block=SLICE_X36Y61 Latch=XQ Net=puente/OUT2B/PWM_in_reg<5>
Bit 1202490 0x002c0200 1242 Block=SLICE_X37Y55 Latch=YQ Net=enco2/quadA_delayed<1>
Bit 1202493 0x002c0200 1245 Block=SLICE_X37Y55 Latch=XQ Net=enco2/quadA_delayed<2>
Bit 1260271 0x002e0200 47 Block=P84 Latch=IQ1 Net=buffer_addr<0>
Bit 1260296 0x002e0200 72 Block=P83 Latch=IQ1 Net=buffer_addr<1>
Bit 1320122 0x00300200 922 Block=SLICE_X41Y65 Latch=YQ Net=puente/OUT1B/PWM_in_reg<2>
Bit 1320125 0x00300200 925 Block=SLICE_X41Y65 Latch=XQ Net=puente/OUT1B/PWM_in_reg<3>
Bit 1379130 0x00320200 954 Block=SLICE_X43Y64 Latch=YQ Net=puente/OUT1B/PWM_in_reg<6>
Bit 1379133 0x00320200 957 Block=SLICE_X43Y64 Latch=XQ Net=puente/OUT1B/PWM_in_reg<7>
Bit 1261466 0x002e0200 1242 Block=SLICE_X39Y55 Latch=YQ Net=enco1/quadB_delayed<1>
Bit 1261469 0x002e0200 1245 Block=SLICE_X39Y55 Latch=XQ Net=enco1/quadB_delayed<2>
Bit 1261498 0x002e0200 1274 Block=SLICE_X39Y54 Latch=YQ Net=enco1/quadA_delayed<1>
Bit 1261501 0x002e0200 1277 Block=SLICE_X39Y54 Latch=XQ Net=enco1/quadA_delayed<2>
Bit 2089039 0x02027200 47 Block=P79 Latch=IQ1 Net=buffer_addr<2>
Bit 2089064 0x02027200 72 Block=P78 Latch=IQ1 Net=buffer_addr<3>
Bit 2205104 0x04002400 1264 Block=P71 Latch=O2 Net=puente/OUT2B/Mcompar_PWM_out_cy<7>
Bit 2205127 0x04002400 1287 Block=P70 Latch=O2 Net=puente/OUT2A/Mcompar_PWM_out_cy<7>
Bit 2205232 0x04002400 1392 Block=P68 Latch=O2 Net=puente/OUT1B/Mcompar_PWM_out_cy<7>
Bit 2205360 0x04002400 1520 Block=P66 Latch=O2 Net=puente/OUT1A/Mcompar_PWM_out_cy<7>
Bit 2147943 0x02029600 3079 Block=P49 Latch=O2 Net=puente/OUT1A/Mcompar_PWM_out_cy<7>
Bit 2205895 0x04002400 2055 Block=P57 Latch=O2 Net=puente/OUT2A/Mcompar_PWM_out_cy<7>
Bit 2206855 0x04002400 3015 Block=P53 Latch=O2 Net=puente/OUT2B/Mcompar_PWM_out_cy<7>
Bit 2208207 0x04020000 1263 Block=P71 Latch=IQ1 Net=enco1/quadA_delayed<0>
Bit 2208232 0x04020000 1288 Block=P70 Latch=IQ1 Net=enco2/quadA_delayed<0>
Bit 2208256 0x04020000 1312 Block=P69 Latch=IQ1 Net=sncs
Bit 2208335 0x04020000 1391 Block=P68 Latch=IQ1 Net=enco1/quadB_delayed<0>
Bit 2208463 0x04020000 1519 Block=P66 Latch=IQ1 Net=enco2/quadB_delayed<0>
Bit 2211367 0x04020200 1319 Block=P69 Latch=I Net=ncs_IBUF

2
Examples/Beta1/logic/build/project_r.ncd
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26
Examples/Beta1/logic/build/project_r.pad
View File

@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sun Oct 31 12:21:06 2010
Sun Oct 31 14:11:59 2010
# NOTE: This file is designed to be imported into a spreadsheet program
@ -45,16 +45,16 @@ P23||DIFFS|IO_L07N_3|UNUSED||3|||||||||
P24||DIFFM|IO_L01P_2/CSO_B|UNUSED||2|||||||||
P25||DIFFS|IO_L01N_2/INIT_B|UNUSED||2|||||||||
P26||DIFFM|IO_L02P_2/DOUT/BUSY|UNUSED||2|||||||||
P27||DIFFS|IO_L02N_2/MOSI/CSI_B|UNUSED||2|||||||||
P27|hbridge<1>|IOB|IO_L02N_2/MOSI/CSI_B|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P28|||VCCINT||||||||1.2||||
P29|||GND||||||||||||
P30|reset|IBUF|IP/VREF_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
P31|||VCCO_2|||2|||||2.50||||
P32||DIFFM|IO_L03P_2/D7/GCLK12|UNUSED||2|||||||||
P33|quadD|IBUF|IO_L03N_2/D6/GCLK13|INPUT|LVCMOS25*|2||||IFD||LOCATED|YES|NONE|
P34|quadC|IBUF|IO/D5|INPUT|LVCMOS25*|2||||IFD||LOCATED|YES|NONE|
P35|quadB|IBUF|IO_L04P_2/D4/GCLK14|INPUT|LVCMOS25*|2||||IFD||LOCATED|YES|NONE|
P36|quadA|IBUF|IO_L04N_2/D3/GCLK15|INPUT|LVCMOS25*|2||||IFD||LOCATED|YES|NONE|
P33||DIFFS|IO_L03N_2/D6/GCLK13|UNUSED||2|||||||||
P34||IOB|IO/D5|UNUSED||2|||||||||
P35||DIFFM|IO_L04P_2/D4/GCLK14|UNUSED||2|||||||||
P36||DIFFS|IO_L04N_2/D3/GCLK15|UNUSED||2|||||||||
P37|||GND||||||||||||
P38|clk|IBUF|IP_L05P_2/RDWR_B/GCLK0|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
P39||DIFFSI|IP_L05N_2/M2/GCLK1|UNUSED||2|||||||||
@ -67,15 +67,15 @@ P45|||VCCO_2|||2|||||2.50||||
P46|||VCCAUX||||||||2.5||||
P47||DIFFM|IO_L08P_2/VS2|UNUSED||2|||||||||
P48||DIFFS|IO_L08N_2/VS1|UNUSED||2|||||||||
P49||DIFFM|IO_L09P_2/VS0|UNUSED||2|||||||||
P49|hbridge<0>|IOB|IO_L09P_2/VS0|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P50||DIFFS|IO_L09N_2/CCLK|UNUSED||2|||||||||
P51|||DONE||||||||||||
P52|||GND||||||||||||
P53||DIFFM|IO_L01P_1|UNUSED||1|||||||||
P53|hbridge<3>|IOB|IO_L01P_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P54||DIFFS|IO_L01N_1|UNUSED||1|||||||||
P55|||VCCO_1|||1|||||2.50||||
P56|||VCCINT||||||||1.2||||
P57||DIFFM|IO_L02P_1|UNUSED||1|||||||||
P57|hbridge<2>|IOB|IO_L02P_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P58||DIFFS|IO_L02N_1|UNUSED||1|||||||||
P59|||GND||||||||||||
P60||DIFFM|IO_L03P_1/RHCLK0|UNUSED||1|||||||||
@ -84,12 +84,12 @@ P62||DIFFM|IO_L04P_1/RHCLK2|UNUSED||1|||||||||
P63||DIFFS|IO_L04N_1/RHCLK3/TRDY1|UNUSED||1|||||||||
P64|||GND||||||||||||
P65||DIFFM|IO_L05P_1/RHCLK4/IRDY1|UNUSED||1|||||||||
P66|hbridge<0>|IOB|IO_L05N_1/RHCLK5|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P66|quadD|IBUF|IO_L05N_1/RHCLK5|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
P67||DIFFM|IO_L06P_1/RHCLK6|UNUSED||1|||||||||
P68|hbridge<1>|IOB|IO_L06N_1/RHCLK7|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P68|quadB|IBUF|IO_L06N_1/RHCLK7|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
P69|ncs|IBUF|IP/VREF_1|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
P70|hbridge<2>|IOB|IO_L07P_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P71|hbridge<3>|IOB|IO_L07N_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P70|quadC|IBUF|IO_L07P_1|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
P71|quadA|IBUF|IO_L07N_1|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
P72|||GND||||||||||||
P73|||VCCO_1|||1|||||2.50||||
P74|||VCCAUX||||||||2.5||||

60
Examples/Beta1/logic/build/project_r.par
View File

@ -1,7 +1,7 @@
Release 12.2 par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
dellerwin:: Sun Oct 31 12:20:42 2010
dellerwin:: Sun Oct 31 14:11:35 2010
par -w project.ncd project_r.ncd
@ -65,43 +65,43 @@ Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:cb32ae9e) REAL time: 3 secs
Phase 1.1 Initial Placement Analysis (Checksum:f088b6e2) REAL time: 3 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:cb32ae9e) REAL time: 3 secs
Phase 2.7 Design Feasibility Check (Checksum:f088b6e2) REAL time: 3 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:cb32ae9e) REAL time: 3 secs
Phase 3.31 Local Placement Optimization (Checksum:f088b6e2) REAL time: 3 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:534cc618) REAL time: 4 secs
Phase 4.2 Initial Clock and IO Placement (Checksum:78a2ce5c) REAL time: 3 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:534cc618) REAL time: 4 secs
Phase 5.30 Global Clock Region Assignment (Checksum:78a2ce5c) REAL time: 3 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:534cc618) REAL time: 4 secs
Phase 6.36 Local Placement Optimization (Checksum:78a2ce5c) REAL time: 3 secs
Phase 7.8 Global Placement
....
...
...
...
......
....
Phase 7.8 Global Placement (Checksum:b10264e) REAL time: 11 secs
...
...
Phase 7.8 Global Placement (Checksum:93fddddd) REAL time: 10 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b10264e) REAL time: 11 secs
Phase 8.5 Local Placement Optimization (Checksum:93fddddd) REAL time: 10 secs
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:a0b1bc3c) REAL time: 12 secs
Phase 9.18 Placement Optimization (Checksum:b650a32c) REAL time: 11 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:a0b1bc3c) REAL time: 12 secs
Phase 10.5 Local Placement Optimization (Checksum:b650a32c) REAL time: 11 secs
Total REAL time to Placer completion: 12 secs
Total CPU time to Placer completion: 10 secs
Total REAL time to Placer completion: 11 secs
Total CPU time to Placer completion: 9 secs
Writing design to file project_r.ncd
@ -109,21 +109,23 @@ Writing design to file project_r.ncd
Starting Router
Phase 1 : 776 unrouted; REAL time: 17 secs
Phase 1 : 776 unrouted; REAL time: 16 secs
Phase 2 : 652 unrouted; REAL time: 17 secs
Phase 2 : 652 unrouted; REAL time: 16 secs
Phase 3 : 110 unrouted; REAL time: 17 secs
Phase 3 : 117 unrouted; REAL time: 16 secs
Phase 4 : 129 unrouted; (Par is working to improve performance) REAL time: 18 secs
Phase 4 : 153 unrouted; (Par is working to improve performance) REAL time: 17 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 18 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 17 secs
Updating file: project_r.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 17 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 22 secs
Updating file: project_r.ncd with current fully routed design.
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
@ -133,8 +135,10 @@ Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 2
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Total REAL time to Router completion: 23 secs
Total CPU time to Router completion: 21 secs
Total CPU time to Router completion: 22 secs
Partition Implementation Status
-------------------------------
@ -152,7 +156,7 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX_X2Y1| No | 99 | 0.082 | 0.204 |
| clk_BUFGP | BUFGMUX_X2Y1| No | 99 | 0.075 | 0.204 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
@ -169,7 +173,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 9.173ns| N/A| 0
Autotimespec constraint for clock net clk | SETUP | N/A| 9.302ns| N/A| 0
_BUFGP | HOLD | 0.968ns| | 0| 0
----------------------------------------------------------------------------------------------------------
@ -187,9 +191,9 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 24 secs
Total CPU time to PAR completion: 21 secs
Total CPU time to PAR completion: 22 secs
Peak Memory Usage: 366 MB
Peak Memory Usage: 357 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.

2
Examples/Beta1/logic/build/project_r.ptwx
View File

@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_BUFGP</twConstName><twConstData type="SETUP" best="9.173" units="ns" score="0"/><twConstData type="HOLD" slack="0.968" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">0</twUnmetConstCnt><twInfo anchorID="4">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_BUFGP</twConstName><twConstData type="SETUP" best="9.302" units="ns" score="0"/><twConstData type="HOLD" slack="0.968" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="5">0</twUnmetConstCnt><twInfo anchorID="6">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>

82
Examples/Beta1/logic/build/project_r.twr
View File

@ -56,14 +56,14 @@ addr<9> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
addr<10> | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
addr<11> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
addr<12> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
ncs | 4.667(F)| -0.793(F)|clk_BUFGP | 0.000|
ncs | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
nwe | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
quadA | 4.665(R)| -0.791(R)|clk_BUFGP | 0.000|
quadB | 4.665(R)| -0.791(R)|clk_BUFGP | 0.000|
quadC | 4.667(R)| -0.793(R)|clk_BUFGP | 0.000|
quadD | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
reset | 3.577(R)| -0.297(R)|clk_BUFGP | 0.000|
| 4.083(F)| 0.032(F)|clk_BUFGP | 0.000|
quadA | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
quadB | 4.665(R)| -0.790(R)|clk_BUFGP | 0.000|
quadC | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
quadD | 4.663(R)| -0.788(R)|clk_BUFGP | 0.000|
reset | 3.422(R)| -0.258(R)|clk_BUFGP | 0.000|
| 3.958(F)| -0.175(F)|clk_BUFGP | 0.000|
sram_data<0>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
sram_data<1>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
sram_data<2>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
@ -79,22 +79,22 @@ Clock clk to Pad
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
hbridge<0> | 11.827(R)|clk_BUFGP | 0.000|
| 11.992(F)|clk_BUFGP | 0.000|
hbridge<1> | 11.508(R)|clk_BUFGP | 0.000|
| 11.284(F)|clk_BUFGP | 0.000|
hbridge<2> | 11.647(R)|clk_BUFGP | 0.000|
| 11.564(F)|clk_BUFGP | 0.000|
hbridge<3> | 11.465(R)|clk_BUFGP | 0.000|
| 11.334(F)|clk_BUFGP | 0.000|
sram_data<0>| 12.695(F)|clk_BUFGP | 0.000|
sram_data<1>| 13.050(F)|clk_BUFGP | 0.000|
sram_data<2>| 12.938(F)|clk_BUFGP | 0.000|
sram_data<3>| 12.388(F)|clk_BUFGP | 0.000|
sram_data<4>| 12.405(F)|clk_BUFGP | 0.000|
sram_data<5>| 12.539(F)|clk_BUFGP | 0.000|
sram_data<6>| 13.285(F)|clk_BUFGP | 0.000|
sram_data<7>| 13.367(F)|clk_BUFGP | 0.000|
hbridge<0> | 12.986(R)|clk_BUFGP | 0.000|
| 12.791(F)|clk_BUFGP | 0.000|
hbridge<1> | 12.097(R)|clk_BUFGP | 0.000|
| 12.323(F)|clk_BUFGP | 0.000|
hbridge<2> | 12.361(R)|clk_BUFGP | 0.000|
| 12.576(F)|clk_BUFGP | 0.000|
hbridge<3> | 12.249(R)|clk_BUFGP | 0.000|
| 12.533(F)|clk_BUFGP | 0.000|
sram_data<0>| 13.558(F)|clk_BUFGP | 0.000|
sram_data<1>| 13.456(F)|clk_BUFGP | 0.000|
sram_data<2>| 13.303(F)|clk_BUFGP | 0.000|
sram_data<3>| 13.306(F)|clk_BUFGP | 0.000|
sram_data<4>| 13.100(F)|clk_BUFGP | 0.000|
sram_data<5>| 12.982(F)|clk_BUFGP | 0.000|
sram_data<6>| 13.549(F)|clk_BUFGP | 0.000|
sram_data<7>| 14.331(F)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
@ -102,33 +102,33 @@ Clock to Setup on destination clock clk
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 5.315| 4.587| 4.326| 9.106|
clk | 5.484| 4.651| 4.353| 8.989|
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
ncs |sram_data<0> | 9.780|
ncs |sram_data<1> | 9.525|
ncs |sram_data<2> | 9.790|
ncs |sram_data<3> | 9.796|
ncs |sram_data<4> | 10.045|
ncs |sram_data<5> | 9.192|
ncs |sram_data<6> | 10.035|
ncs |sram_data<7> | 10.294|
noe |sram_data<0> | 8.726|
noe |sram_data<1> | 8.471|
noe |sram_data<2> | 8.736|
noe |sram_data<3> | 8.742|
noe |sram_data<4> | 8.991|
noe |sram_data<5> | 8.138|
noe |sram_data<6> | 8.981|
noe |sram_data<7> | 9.240|
ncs |sram_data<0> | 9.401|
ncs |sram_data<1> | 9.145|
ncs |sram_data<2> | 9.411|
ncs |sram_data<3> | 9.425|
ncs |sram_data<4> | 9.674|
ncs |sram_data<5> | 9.658|
ncs |sram_data<6> | 11.147|
ncs |sram_data<7> | 11.413|
noe |sram_data<0> | 9.064|
noe |sram_data<1> | 8.808|
noe |sram_data<2> | 9.074|
noe |sram_data<3> | 9.088|
noe |sram_data<4> | 9.337|
noe |sram_data<5> | 9.321|
noe |sram_data<6> | 10.810|
noe |sram_data<7> | 11.076|
---------------+---------------+---------+
Analysis completed Sun Oct 31 12:21:08 2010
Analysis completed Sun Oct 31 14:12:02 2010
--------------------------------------------------------------------------------
Trace Settings:

2
Examples/Beta1/logic/build/project_r.twx
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2
Examples/Beta1/logic/build/project_r.unroutes
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@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sun Oct 31 12:21:06 2010
Sun Oct 31 14:11:59 2010
All signals are completely routed.

26
Examples/Beta1/logic/build/project_r_pad.csv
View File

@ -1,7 +1,7 @@
#Release 12.2 - par M.63c (lin64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Sun Oct 31 12:21:06 2010
#Sun Oct 31 14:11:59 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program
@ -45,16 +45,16 @@ P23,,DIFFS,IO_L07N_3,UNUSED,,3,,,,,,,,,
P24,,DIFFM,IO_L01P_2/CSO_B,UNUSED,,2,,,,,,,,,
P25,,DIFFS,IO_L01N_2/INIT_B,UNUSED,,2,,,,,,,,,
P26,,DIFFM,IO_L02P_2/DOUT/BUSY,UNUSED,,2,,,,,,,,,
P27,,DIFFS,IO_L02N_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,,
P27,hbridge<1>,IOB,IO_L02N_2/MOSI/CSI_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P28,,,VCCINT,,,,,,,,1.2,,,,
P29,,,GND,,,,,,,,,,,,
P30,reset,IBUF,IP/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
P31,,,VCCO_2,,,2,,,,,2.50,,,,
P32,,DIFFM,IO_L03P_2/D7/GCLK12,UNUSED,,2,,,,,,,,,
P33,quadD,IBUF,IO_L03N_2/D6/GCLK13,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
P34,quadC,IBUF,IO/D5,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
P35,quadB,IBUF,IO_L04P_2/D4/GCLK14,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
P36,quadA,IBUF,IO_L04N_2/D3/GCLK15,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
P33,,DIFFS,IO_L03N_2/D6/GCLK13,UNUSED,,2,,,,,,,,,
P34,,IOB,IO/D5,UNUSED,,2,,,,,,,,,
P35,,DIFFM,IO_L04P_2/D4/GCLK14,UNUSED,,2,,,,,,,,,
P36,,DIFFS,IO_L04N_2/D3/GCLK15,UNUSED,,2,,,,,,,,,
P37,,,GND,,,,,,,,,,,,
P38,clk,IBUF,IP_L05P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
P39,,DIFFSI,IP_L05N_2/M2/GCLK1,UNUSED,,2,,,,,,,,,
@ -67,15 +67,15 @@ P45,,,VCCO_2,,,2,,,,,2.50,,,,
P46,,,VCCAUX,,,,,,,,2.5,,,,
P47,,DIFFM,IO_L08P_2/VS2,UNUSED,,2,,,,,,,,,
P48,,DIFFS,IO_L08N_2/VS1,UNUSED,,2,,,,,,,,,
P49,,DIFFM,IO_L09P_2/VS0,UNUSED,,2,,,,,,,,,
P49,hbridge<0>,IOB,IO_L09P_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P50,,DIFFS,IO_L09N_2/CCLK,UNUSED,,2,,,,,,,,,
P51,,,DONE,,,,,,,,,,,,
P52,,,GND,,,,,,,,,,,,
P53,,DIFFM,IO_L01P_1,UNUSED,,1,,,,,,,,,
P53,hbridge<3>,IOB,IO_L01P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P54,,DIFFS,IO_L01N_1,UNUSED,,1,,,,,,,,,
P55,,,VCCO_1,,,1,,,,,2.50,,,,
P56,,,VCCINT,,,,,,,,1.2,,,,
P57,,DIFFM,IO_L02P_1,UNUSED,,1,,,,,,,,,
P57,hbridge<2>,IOB,IO_L02P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P58,,DIFFS,IO_L02N_1,UNUSED,,1,,,,,,,,,
P59,,,GND,,,,,,,,,,,,
P60,,DIFFM,IO_L03P_1/RHCLK0,UNUSED,,1,,,,,,,,,
@ -84,12 +84,12 @@ P62,,DIFFM,IO_L04P_1/RHCLK2,UNUSED,,1,,,,,,,,,
P63,,DIFFS,IO_L04N_1/RHCLK3/TRDY1,UNUSED,,1,,,,,,,,,
P64,,,GND,,,,,,,,,,,,
P65,,DIFFM,IO_L05P_1/RHCLK4/IRDY1,UNUSED,,1,,,,,,,,,
P66,hbridge<0>,IOB,IO_L05N_1/RHCLK5,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P66,quadD,IBUF,IO_L05N_1/RHCLK5,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
P67,,DIFFM,IO_L06P_1/RHCLK6,UNUSED,,1,,,,,,,,,
P68,hbridge<1>,IOB,IO_L06N_1/RHCLK7,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P68,quadB,IBUF,IO_L06N_1/RHCLK7,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
P69,ncs,IBUF,IP/VREF_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
P70,hbridge<2>,IOB,IO_L07P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P71,hbridge<3>,IOB,IO_L07N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P70,quadC,IBUF,IO_L07P_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
P71,quadA,IBUF,IO_L07N_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
P72,,,GND,,,,,,,,,,,,
P73,,,VCCO_1,,,1,,,,,2.50,,,,
P74,,,VCCAUX,,,,,,,,2.5,,,,

1 #Release 12.2 - par M.63c (lin64)
2 #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
3 #Sun Oct 31 12:21:06 2010 #Sun Oct 31 14:11:59 2010
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
45 P26,,DIFFM,IO_L02P_2/DOUT/BUSY,UNUSED,,2,,,,,,,,,
46 P27,,DIFFS,IO_L02N_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,, P27,hbridge<1>,IOB,IO_L02N_2/MOSI/CSI_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
47 P28,,,VCCINT,,,,,,,,1.2,,,,
48 P29,,,GND,,,,,,,,,,,,
49 P30,reset,IBUF,IP/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
50 P31,,,VCCO_2,,,2,,,,,2.50,,,,
51 P32,,DIFFM,IO_L03P_2/D7/GCLK12,UNUSED,,2,,,,,,,,,
52 P33,quadD,IBUF,IO_L03N_2/D6/GCLK13,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE, P33,,DIFFS,IO_L03N_2/D6/GCLK13,UNUSED,,2,,,,,,,,,
53 P34,quadC,IBUF,IO/D5,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE, P34,,IOB,IO/D5,UNUSED,,2,,,,,,,,,
54 P35,quadB,IBUF,IO_L04P_2/D4/GCLK14,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE, P35,,DIFFM,IO_L04P_2/D4/GCLK14,UNUSED,,2,,,,,,,,,
55 P36,quadA,IBUF,IO_L04N_2/D3/GCLK15,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE, P36,,DIFFS,IO_L04N_2/D3/GCLK15,UNUSED,,2,,,,,,,,,
56 P37,,,GND,,,,,,,,,,,,
57 P38,clk,IBUF,IP_L05P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
58 P39,,DIFFSI,IP_L05N_2/M2/GCLK1,UNUSED,,2,,,,,,,,,
59 P40,,DIFFM,IO_L06P_2/D2/GCLK2,UNUSED,,2,,,,,,,,,
60 P41,,DIFFS,IO_L06N_2/D1/GCLK3,UNUSED,,2,,,,,,,,,
67 P48,,DIFFS,IO_L08N_2/VS1,UNUSED,,2,,,,,,,,,
68 P49,,DIFFM,IO_L09P_2/VS0,UNUSED,,2,,,,,,,,, P49,hbridge<0>,IOB,IO_L09P_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
69 P50,,DIFFS,IO_L09N_2/CCLK,UNUSED,,2,,,,,,,,,
70 P51,,,DONE,,,,,,,,,,,,
71 P52,,,GND,,,,,,,,,,,,
72 P53,,DIFFM,IO_L01P_1,UNUSED,,1,,,,,,,,, P53,hbridge<3>,IOB,IO_L01P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
73 P54,,DIFFS,IO_L01N_1,UNUSED,,1,,,,,,,,,
74 P55,,,VCCO_1,,,1,,,,,2.50,,,,
75 P56,,,VCCINT,,,,,,,,1.2,,,,
76 P57,,DIFFM,IO_L02P_1,UNUSED,,1,,,,,,,,, P57,hbridge<2>,IOB,IO_L02P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
77 P58,,DIFFS,IO_L02N_1,UNUSED,,1,,,,,,,,,
78 P59,,,GND,,,,,,,,,,,,
79 P60,,DIFFM,IO_L03P_1/RHCLK0,UNUSED,,1,,,,,,,,,
80 P61,,DIFFS,IO_L03N_1/RHCLK1,UNUSED,,1,,,,,,,,,
81 P62,,DIFFM,IO_L04P_1/RHCLK2,UNUSED,,1,,,,,,,,,
84 P65,,DIFFM,IO_L05P_1/RHCLK4/IRDY1,UNUSED,,1,,,,,,,,,
85 P66,hbridge<0>,IOB,IO_L05N_1/RHCLK5,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, P66,quadD,IBUF,IO_L05N_1/RHCLK5,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
86 P67,,DIFFM,IO_L06P_1/RHCLK6,UNUSED,,1,,,,,,,,,
87 P68,hbridge<1>,IOB,IO_L06N_1/RHCLK7,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, P68,quadB,IBUF,IO_L06N_1/RHCLK7,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
88 P69,ncs,IBUF,IP/VREF_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
89 P70,hbridge<2>,IOB,IO_L07P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, P70,quadC,IBUF,IO_L07P_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
90 P71,hbridge<3>,IOB,IO_L07N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, P71,quadA,IBUF,IO_L07N_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
91 P72,,,GND,,,,,,,,,,,,
92 P73,,,VCCO_1,,,1,,,,,2.50,,,,
93 P74,,,VCCAUX,,,,,,,,2.5,,,,
94 P75,,,TMS,,,,,,,,,,,,
95 P76,,,TDO,,,,,,,,,,,,

26
Examples/Beta1/logic/build/project_r_pad.txt
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@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sun Oct 31 12:21:06 2010
Sun Oct 31 14:11:59 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@ -46,16 +46,16 @@ Pinout by Pin Number:
|P24 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | |
|P25 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | |
|P26 | |DIFFM |IO_L02P_2/DOUT/BUSY |UNUSED | |2 | | | | | | | | |
|P27 | |DIFFS |IO_L02N_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | |
|P27 |hbridge<1> |IOB |IO_L02N_2/MOSI/CSI_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P28 | | |VCCINT | | | | | | | |1.2 | | | |
|P29 | | |GND | | | | | | | | | | | |
|P30 |reset |IBUF |IP/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|P31 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|P32 | |DIFFM |IO_L03P_2/D7/GCLK12 |UNUSED | |2 | | | | | | | | |
|P33 |quadD |IBUF |IO_L03N_2/D6/GCLK13 |INPUT |LVCMOS25* |2 | | | |IFD | |LOCATED |YES |NONE |
|P34 |quadC |IBUF |IO/D5 |INPUT |LVCMOS25* |2 | | | |IFD | |LOCATED |YES |NONE |
|P35 |quadB |IBUF |IO_L04P_2/D4/GCLK14 |INPUT |LVCMOS25* |2 | | | |IFD | |LOCATED |YES |NONE |
|P36 |quadA |IBUF |IO_L04N_2/D3/GCLK15 |INPUT |LVCMOS25* |2 | | | |IFD | |LOCATED |YES |NONE |
|P33 | |DIFFS |IO_L03N_2/D6/GCLK13 |UNUSED | |2 | | | | | | | | |
|P34 | |IOB |IO/D5 |UNUSED | |2 | | | | | | | | |
|P35 | |DIFFM |IO_L04P_2/D4/GCLK14 |UNUSED | |2 | | | | | | | | |
|P36 | |DIFFS |IO_L04N_2/D3/GCLK15 |UNUSED | |2 | | | | | | | | |
|P37 | | |GND | | | | | | | | | | | |
|P38 |clk |IBUF |IP_L05P_2/RDWR_B/GCLK0|INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|P39 | |DIFFSI |IP_L05N_2/M2/GCLK1 |UNUSED | |2 | | | | | | | | |
@ -68,15 +68,15 @@ Pinout by Pin Number:
|P46 | | |VCCAUX | | | | | | | |2.5 | | | |
|P47 | |DIFFM |IO_L08P_2/VS2 |UNUSED | |2 | | | | | | | | |
|P48 | |DIFFS |IO_L08N_2/VS1 |UNUSED | |2 | | | | | | | | |
|P49 | |DIFFM |IO_L09P_2/VS0 |UNUSED | |2 | | | | | | | | |
|P49 |hbridge<0> |IOB |IO_L09P_2/VS0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P50 | |DIFFS |IO_L09N_2/CCLK |UNUSED | |2 | | | | | | | | |
|P51 | | |DONE | | | | | | | | | | | |
|P52 | | |GND | | | | | | | | | | | |
|P53 | |DIFFM |IO_L01P_1 |UNUSED | |1 | | | | | | | | |
|P53 |hbridge<3> |IOB |IO_L01P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P54 | |DIFFS |IO_L01N_1 |UNUSED | |1 | | | | | | | | |
|P55 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|P56 | | |VCCINT | | | | | | | |1.2 | | | |
|P57 | |DIFFM |IO_L02P_1 |UNUSED | |1 | | | | | | | | |
|P57 |hbridge<2> |IOB |IO_L02P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P58 | |DIFFS |IO_L02N_1 |UNUSED | |1 | | | | | | | | |
|P59 | | |GND | | | | | | | | | | | |
|P60 | |DIFFM |IO_L03P_1/RHCLK0 |UNUSED | |1 | | | | | | | | |
@ -85,12 +85,12 @@ Pinout by Pin Number:
|P63 | |DIFFS |IO_L04N_1/RHCLK3/TRDY1|UNUSED | |1 | | | | | | | | |
|P64 | | |GND | | | | | | | | | | | |
|P65 | |DIFFM |IO_L05P_1/RHCLK4/IRDY1|UNUSED | |1 | | | | | | | | |
|P66 |hbridge<0> |IOB |IO_L05N_1/RHCLK5 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P66 |quadD |IBUF |IO_L05N_1/RHCLK5 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P67 | |DIFFM |IO_L06P_1/RHCLK6 |UNUSED | |1 | | | | | | | | |
|P68 |hbridge<1> |IOB |IO_L06N_1/RHCLK7 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P68 |quadB |IBUF |IO_L06N_1/RHCLK7 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P69 |ncs |IBUF |IP/VREF_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P70 |hbridge<2> |IOB |IO_L07P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P71 |hbridge<3> |IOB |IO_L07N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P70 |quadC |IBUF |IO_L07P_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P71 |quadA |IBUF |IO_L07N_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P72 | | |GND | | | | | | | | | | | |
|P73 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|P74 | | |VCCAUX | | | | | | | |2.5 | | | |

2
Examples/Beta1/logic/build/project_summary.xml
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@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="20">
<DesignSummary rev="2">
<CmdHistory>
</CmdHistory>
</DesignSummary>

806
Examples/Beta1/logic/build/project_usage.xml
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File diff suppressed because it is too large Load Diff

70
Examples/Beta1/logic/build/usage_statistics_webtalk.html
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@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">3e658027d9514d018043b63a2e613df7</xtag-property>.<xtag-property name="ProjectIteration">10</xtag-property></TD>
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">9f5f0d2df28148bcb47e901093f9d1d1</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">vq100</xtag-property></TD>
</TR>
@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2010-10-31T12:21:16</xtag-property></TD>
<TD><xtag-property name="Date Generated">2010-10-31T14:12:09</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">CommandLine</xtag-property></TD>
</TR>
@ -85,30 +85,30 @@
<LI><xtag-item1>NumNodesOfType_Active_BRAMDUMMY=70</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=99</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=71</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=679</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=730</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMY=359</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYBANK=51</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYBANK=50</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYESC=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=54</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HFULLHEX=18</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HLONG=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=85</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=51</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HFULLHEX=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HLONG=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=98</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=590</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=31</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OMUX=281</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OMUX=290</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=218</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=210</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=43</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VLONG=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=85</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=220</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=32</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VLONG=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=64</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMADDR=22</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMDUMMY=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DUMMYBANK=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=16</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DUMMYBANK=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=38</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=16</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=9</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_VFULLHEX=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_BRAMDUMMY=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI>
@ -121,12 +121,12 @@
<UL>
<LI><xtag-item1>IBUF-DIFFM=8</xtag-item1></LI>
<LI><xtag-item1>IBUF-DIFFMI=2</xtag-item1></LI>
<LI><xtag-item1>IBUF-DIFFS=8</xtag-item1></LI>
<LI><xtag-item1>IBUF-DIFFS=9</xtag-item1></LI>
<LI><xtag-item1>IBUF-DIFFSI=1</xtag-item1></LI>
<LI><xtag-item1>IBUF-IOB=2</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFM=5</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFS=7</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=43</xtag-item1></LI>
<LI><xtag-item1>IBUF-IOB=1</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFM=7</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFS=5</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=42</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@ -696,8 +696,8 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>92</xtag-total-run-started></td>
<td><xtag-total-run-finished>92</xtag-total-run-finished></td>
<td><xtag-total-run-started>93</xtag-total-run-started></td>
<td><xtag-total-run-finished>93</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -706,8 +706,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>113</xtag-total-run-started></td>
<td><xtag-total-run-finished>111</xtag-total-run-finished></td>
<td><xtag-total-run-started>116</xtag-total-run-started></td>
<td><xtag-total-run-finished>112</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -716,8 +716,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>117</xtag-total-run-started></td>
<td><xtag-total-run-finished>117</xtag-total-run-finished></td>
<td><xtag-total-run-started>120</xtag-total-run-started></td>
<td><xtag-total-run-finished>120</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -726,8 +726,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>110</xtag-total-run-started></td>
<td><xtag-total-run-finished>110</xtag-total-run-finished></td>
<td><xtag-total-run-started>111</xtag-total-run-started></td>
<td><xtag-total-run-finished>111</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -736,8 +736,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>110</xtag-total-run-started></td>
<td><xtag-total-run-finished>110</xtag-total-run-finished></td>
<td><xtag-total-run-started>111</xtag-total-run-started></td>
<td><xtag-total-run-finished>111</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -746,8 +746,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>212</xtag-total-run-started></td>
<td><xtag-total-run-finished>209</xtag-total-run-finished></td>
<td><xtag-total-run-started>213</xtag-total-run-started></td>
<td><xtag-total-run-finished>210</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>

4
Examples/Beta1/logic/build/webtalk.log
View File

@ -3,8 +3,8 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=3e658027d9514d018043b63a2e613df7
ProjectIteration=11
ProjectID=9f5f0d2df28148bcb47e901093f9d1d1
ProjectIteration=2
WebTalk Summary
----------------

BIN
Examples/Beta1/logic/build/xlnx_auto_0_xdb/cst.xbcd
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Binary file not shown.

8
Examples/Beta1/logic/build/xst/work/hdllib.ref
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@ -1,4 +1,4 @@
MO PWM NULL ../PWM.v vlg50/_p_w_m.bin 1288492397
MO beta NULL ../beta.v vlg5C/beta.bin 1288492397
MO PuenteH NULL ../PuenteH.v vlg69/_puente_h.bin 1288492397
MO enco NULL ../enco.v vlg6D/enco.bin 1288492397
MO PWM NULL ../PWM.v vlg50/_p_w_m.bin 1288551148
MO beta NULL ../beta.v vlg5C/beta.bin 1288551148
MO PuenteH NULL ../PuenteH.v vlg69/_puente_h.bin 1288551148
MO enco NULL ../enco.v vlg6D/enco.bin 1288551148