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Code

Changed src in Beta with example to all 4 PWM at 100%

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This commit is contained in:
Erwin Lopez 2010-10-30 22:27:00 -05:00
parent 8f2a9cc1d6
commit cc225fc088
49 changed files with 38495 additions and 19983 deletions
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BIN
Examples/Beta1/logic/beta.bit
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Binary file not shown.

11
Examples/Beta1/logic/beta.ucf
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@ -7,11 +7,20 @@ NET reset LOC = "P30"; #WARNING change to another pin
#NET OD3 LOC = "P63";
NET quadA LOC = "P67";
NET quadB LOC = "P68";
NET quadC LOC = "P70";
NET quadD LOC = "P71";
NET quadA LOC = "P36"; #PINES DE PRUEBA
NET quadB LOC = "P35"; #PINES DE PRUEBA
NET quadC LOC = "P34"; #PINES DE PRUEBA
NET quadD LOC = "P33"; #PINES DE PRUEBA
NET "hbridge<3>" LOC = "P53";
NET "hbridge<2>" LOC = "P54";
NET "hbridge<1>" LOC = "P49";
NET "hbridge<0>" LOC = "P48";
#NET "hbridge<3>" LOC = "P71";#PINES DE PRUEBA
#NET "hbridge<2>" LOC = "P70"; #PINES DE PRUEBA
#NET "hbridge<1>" LOC = "P68"; #PINES DE PRUEBA
#NET "hbridge<0>" LOC = "P66"; #PINES DE PRUEBA
#ADDRESS BUS
NET "addr<12>" LOC = "P90";

33
Examples/Beta1/logic/beta.v
View File

@ -2,7 +2,7 @@
/*module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART, led2);
*/
module beta(clk, sram_data, quadA, quadB, addr, nwe, ncs, noe, reset, hbridge);
module beta(clk, sram_data, quadA, quadB, quadC, quadD, addr, nwe, ncs, noe, reset, hbridge);
parameter B = (7);
@ -12,7 +12,7 @@ module beta(clk, sram_data, quadA, quadB, addr, nwe, ncs, noe, reset, hbridge);
// inout ADC_SDIN, ADC_SDOUT;
input clk, addr, nwe, ncs, noe, reset;
output [3:0] hbridge;
input quadA,quadB;
input quadA,quadB, quadC, quadD;
// External conection
//wire led, led2;
@ -110,16 +110,15 @@ enco enco1(
.buffer_addr(buffer_addr[10:0])
);
RAMB16_S9 ba0( .CLK(~clk),
.EN(csN[1]),
.DOP(),
.SSR(1'b0),
.ADDR(buffer_addr[10:0]),
.WE(we),
.DI(wrBus),
.DIP(1'b0),
.DO(rdBus1));
enco enco2(
.clk(clk),
.enable(csN[1]),
.quadA(quadC),
.quadB(quadD),
.out(rdBus1),
.buffer_addr(buffer_addr[10:0])
);
PuenteH puente (
.clk(clk),
.reset(~reset),
@ -131,7 +130,15 @@ PuenteH puente (
.ram_read(rdBus2)
);
RAMB16_S9 ba0( .CLK(~clk),
.EN(csN[3]),
.DOP(),
.SSR(1'b0),
.ADDR(buffer_addr[10:0]),
.WE(we),
.DI(wrBus),
.DIP(1'b0),
.DO(rdBus3));
endmodule

2
Examples/Beta1/logic/build/_xmsgs/bitgen.xmsgs
View File

@ -5,7 +5,7 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Bitgen" num="275" delta="new" >Spartan-3E devices do not support bitstream readback of the Blockram resources in the -4C speedgrade. If Blockram readback functionality is desired, it is suggested to target the -5C or -4I speedgrades.
<msg type="info" file="Bitgen" num="275" delta="old" >Spartan-3E devices do not support bitstream readback of the Blockram resources in the -4C speedgrade. If Blockram readback functionality is desired, it is suggested to target the -5C or -4I speedgrades.
</msg>
</messages>

4
Examples/Beta1/logic/build/_xmsgs/map.xmsgs
View File

@ -5,10 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
</messages>

6
Examples/Beta1/logic/build/_xmsgs/par.xmsgs
View File

@ -5,12 +5,12 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
</messages>

10
Examples/Beta1/logic/build/_xmsgs/trce.xmsgs
View File

@ -5,15 +5,15 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3390" delta="new" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
<msg type="info" file="Timing" num="3390" delta="old" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
<msg type="info" file="Timing" num="3389" delta="new" >This architecture does not support &apos;Discrete Jitter&apos; and &apos;Phase Error&apos; calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
<msg type="info" file="Timing" num="3389" delta="old" >This architecture does not support &apos;Discrete Jitter&apos; and &apos;Phase Error&apos; calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
</messages>

7
Examples/Beta1/logic/build/_xmsgs/xst.xmsgs
View File

@ -5,13 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompilers" num="259" delta="new" ><arg fmt="%s" index="1">&quot;../enco.v&quot; line 65 </arg>Connection to input port &apos;<arg fmt="%s" index="2">ADDRB</arg>&apos; does not match port size
<msg type="warning" file="HDLCompilers" num="259" delta="old" ><arg fmt="%s" index="1">&quot;../enco.v&quot; line 65 </arg>Connection to input port &apos;<arg fmt="%s" index="2">ADDRB</arg>&apos; does not match port size
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">rdBus3</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">00000000</arg>.
</msg>
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">csN&lt;3&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="HDLCompilers" num="259" delta="old" ><arg fmt="%s" index="1">&quot;../enco.v&quot; line 65 </arg>Connection to input port &apos;<arg fmt="%s" index="2">ADDRB</arg>&apos; does not match port size
</msg>
</messages>

48
Examples/Beta1/logic/build/beta_map.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Sat Oct 30 18:30:54 2010">
<application stringID="Map" timeStamp="Sat Oct 30 21:33:32 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -53,12 +53,12 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="375808"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="375988"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="2 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="2 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="118"/>
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="131"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE_SLICEL" value="2328"/>
<item dataType="int" stringID="MAP_AVAILABLE_SLICEM" value="2328"/>
@ -66,8 +66,8 @@
<item dataType="int" stringID="MAP_LUTS_PER_SLICE" value="2"/>
<item AVAILABLE="2328" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
<item AVAILABLE="2328" dataType="int" stringID="MAP_NUM_SLICEL" value="0"/>
<item dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="130"/>
<item dataType="int" label="Number of occupied Slices" stringID="MAP_AGG_SLICE" value="112"/>
<item dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="140"/>
<item dataType="int" label="Number of occupied Slices" stringID="MAP_AGG_SLICE" value="118"/>
<item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/>
<item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="28"/>
<item dataType="int" stringID="MAP_NUM_DP_RAM" value="0"/>
@ -83,7 +83,7 @@
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPADAGG_BONDED_IO" value="0"/>
<item AVAILABLE="414" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="25"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="27"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
<item AVAILABLE="116" dataType="int" stringID="MAP_NUM_DIFFM" value="0"/>
<item AVAILABLE="44" dataType="int" stringID="MAP_NUM_DIFFMI" value="0"/>
@ -95,7 +95,7 @@
</section>
</section>
<section stringID="MAP_HARD_IP_REPORTING">
<item AVAILABLE="20" dataType="int" stringID="MAP_NUM_RAMB16" value="3"/>
<item AVAILABLE="20" dataType="int" stringID="MAP_NUM_RAMB16" value="4"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_MULT18X18" value="0"/>
<item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="1"/>
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_DCM" value="0"/>
@ -310,13 +310,29 @@
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="24">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="quadC"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="25">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="quadD"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="26">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="reset"/>
<item stringID="Type" value="IBUF"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="25">
<row stringID="row" value="27">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sram_data&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
@ -326,7 +342,7 @@
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="26">
<row stringID="row" value="28">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sram_data&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
@ -336,7 +352,7 @@
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="27">
<row stringID="row" value="29">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sram_data&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
@ -346,7 +362,7 @@
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="28">
<row stringID="row" value="30">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sram_data&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
@ -356,7 +372,7 @@
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="29">
<row stringID="row" value="31">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sram_data&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
@ -366,7 +382,7 @@
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="30">
<row stringID="row" value="32">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sram_data&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
@ -376,7 +392,7 @@
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="31">
<row stringID="row" value="33">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sram_data&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
@ -386,7 +402,7 @@
<item label="Reg&#xA;(s)" stringID="REGS" value="IFF1"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 3"/>
</row>
<row stringID="row" value="32">
<row stringID="row" value="34">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="sram_data&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
@ -400,7 +416,7 @@
</section>
<section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="8"/>
<item dataType="int" stringID="MAP_NUM_SHAPE" value="10"/>
</section>
</section>
<section stringID="MAP_GUIDE_REPORT"/>

160
Examples/Beta1/logic/build/beta_par.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Sat Oct 30 18:30:57 2010">
<application stringID="par" timeStamp="Sat Oct 30 21:33:35 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -47,12 +47,12 @@
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="19 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="18 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="26 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="22 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="19 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="19 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="27 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="22 secs "/>
</section>
</task>
<task stringID="PAR_par">
@ -71,8 +71,8 @@
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y1"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="90.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.078000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="99.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.082000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.204000"/>
</row>
</table>
@ -386,31 +386,55 @@
</row>
<row stringID="row" value="33">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P33"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadD"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L03N_2/D6/GCLK13"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="34">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P34"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadC"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO/D5"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="35">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P35"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadB"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L04P_2/D4/GCLK14"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="36">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P36"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadA"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L04N_2/D3/GCLK15"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="37">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P37"/>
@ -491,33 +515,17 @@
</row>
<row stringID="row" value="48">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P48"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;0>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L08N_2/VS1"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="49">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P49"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;1>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L09P_2/VS0"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="50">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P50"/>
@ -536,33 +544,17 @@
</row>
<row stringID="row" value="53">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P53"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;3>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L01P_1"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="54">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P54"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;2>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L01N_1"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="55">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P55"/>
@ -634,35 +626,39 @@
</row>
<row stringID="row" value="66">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P66"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;0>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L05N_1/RHCLK5"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="67">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P67"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadA"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L06P_1/RHCLK6"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="68">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P68"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="quadB"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IBUF"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;1>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L06N_1/RHCLK7"/>
<item stringID="Direction" value="INPUT"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="IOB&#xA;Delay" stringID="IOB_Delay" value="IFD"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="69">
@ -680,17 +676,33 @@
</row>
<row stringID="row" value="70">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P70"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;2>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L07P_1"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="71">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P71"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="hbridge&lt;3>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L07N_1"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="72">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P72"/>

2
Examples/Beta1/logic/build/netlist.lst
View File

@ -1,2 +1,2 @@
/home/erwin/sie-ceimtun/Examples/Beta1/logic/build/project.ngc 1288481444
/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build/project.ngc 1288492403
OK

6
Examples/Beta1/logic/build/project.bld
View File

@ -4,8 +4,8 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: /home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
-p xc3s500e-VQ100-4 project.ngc -uc ../beta.ucf
Reading NGO file
"/home/erwin/sie-ceimtun/Examples/Beta1/logic/build/project.ngc" ...
Reading NGO file "/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso
Embebidos/Test_Video/Beta1/logic/build/project.ngc" ...
Gathering constraint information from source properties...
Done.
@ -27,7 +27,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 235524 kilobytes
Total memory usage is 235692 kilobytes
Writing NGD file "project.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec

108
Examples/Beta1/logic/build/project.log
View File

@ -338,7 +338,7 @@ Unit <PWM> synthesized.
Synthesizing Unit <enco>.
Related source file is "../enco.v".
Found 7-bit updown counter for signal <count>.
Found 8-bit updown counter for signal <count>.
Found 1-bit xor2 for signal <count_direction>.
Found 1-bit xor3 for signal <count_enable>.
Found 3-bit register for signal <quadA_delayed>.
@ -364,8 +364,6 @@ Unit <PuenteH> synthesized.
Synthesizing Unit <beta>.
Related source file is "../beta.v".
WARNING:Xst:653 - Signal <rdBus3> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
WARNING:Xst:646 - Signal <csN<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 8-bit tristate buffer for signal <sram_data>.
Found 13-bit register for signal <buffer_addr>.
Found 8-bit register for signal <buffer_data>.
@ -384,22 +382,22 @@ Unit <beta> synthesized.
HDL Synthesis Report
Macro Statistics
# Counters : 5
7-bit updown counter : 1
# Counters : 6
8-bit up counter : 4
# Registers : 18
8-bit updown counter : 2
# Registers : 20
1-bit register : 5
13-bit register : 1
3-bit register : 2
3-bit register : 4
8-bit register : 10
# Comparators : 8
8-bit comparator equal : 4
8-bit comparator less : 4
# Tristates : 1
8-bit tristate buffer : 1
# Xors : 2
1-bit xor2 : 1
1-bit xor3 : 1
# Xors : 4
1-bit xor2 : 2
1-bit xor3 : 2
=========================================================================
@ -412,17 +410,17 @@ Macro Statistics
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 5
7-bit updown counter : 1
# Counters : 6
8-bit up counter : 4
# Registers : 104
Flip-Flops : 104
8-bit updown counter : 2
# Registers : 110
Flip-Flops : 110
# Comparators : 8
8-bit comparator equal : 4
8-bit comparator less : 4
# Xors : 2
1-bit xor2 : 1
1-bit xor3 : 1
# Xors : 4
1-bit xor2 : 2
1-bit xor3 : 2
=========================================================================
@ -447,8 +445,8 @@ Final Macro Processing ...
Final Register Report
Macro Statistics
# Registers : 143
Flip-Flops : 143
# Registers : 158
Flip-Flops : 158
=========================================================================
@ -474,33 +472,33 @@ Optimization Goal : Area
Keep Hierarchy : no
Design Statistics
# IOs : 32
# IOs : 34
Cell Usage :
# BELS : 239
# BELS : 278
# GND : 1
# INV : 11
# INV : 10
# LUT1 : 28
# LUT2 : 38
# LUT3 : 3
# LUT4 : 55
# MUXCY : 60
# LUT2 : 40
# LUT3 : 35
# LUT4 : 31
# MUXCY : 74
# MUXF5 : 10
# VCC : 1
# XORCY : 32
# FlipFlops/Latches : 143
# FD : 38
# XORCY : 48
# FlipFlops/Latches : 158
# FD : 44
# FD_1 : 23
# FDE : 7
# FDE : 16
# FDR : 42
# FDRE_1 : 33
# RAMS : 3
# RAMS : 4
# RAMB16_S9 : 2
# RAMB16_S9_S9 : 1
# RAMB16_S9_S9 : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 31
# IBUF : 19
# IO Buffers : 33
# IBUF : 21
# IOBUF : 8
# OBUF : 4
=========================================================================
@ -510,13 +508,13 @@ Device utilization summary:
Selected Device : 3s500evq100-4
Number of Slices: 108 out of 4656 2%
Number of Slice Flip Flops: 119 out of 9312 1%
Number of 4 input LUTs: 135 out of 9312 1%
Number of IOs: 32
Number of bonded IOBs: 32 out of 66 48%
IOB Flip Flops: 24
Number of BRAMs: 3 out of 20 15%
Number of Slices: 114 out of 4656 2%
Number of Slice Flip Flops: 132 out of 9312 1%
Number of 4 input LUTs: 144 out of 9312 1%
Number of IOs: 34
Number of bonded IOBs: 34 out of 66 51%
IOB Flip Flops: 26
Number of BRAMs: 4 out of 20 20%
Number of GCLKs: 1 out of 24 4%
---------------------------
@ -540,7 +538,7 @@ Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 146 |
clk | BUFGP | 162 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
@ -553,7 +551,7 @@ Speed Grade: -4
Minimum period: 9.656ns (Maximum Frequency: 103.563MHz)
Minimum input arrival time before clock: 4.545ns
Maximum output required time after clock: 8.043ns
Maximum output required time after clock: 8.016ns
Maximum combinational path delay: 6.573ns
Timing Detail:
@ -563,7 +561,7 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 9.656ns (frequency: 103.563MHz)
Total number of paths / destination ports: 1347 / 251
Total number of paths / destination ports: 1655 / 294
-------------------------------------------------------------------------
Delay: 4.828ns (Levels of Logic = 2)
Source: puente/PWM_1_1 (FF)
@ -585,7 +583,7 @@ Delay: 4.828ns (Levels of Logic = 2)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 68 / 68
Total number of paths / destination ports: 70 / 70
-------------------------------------------------------------------------
Offset: 4.545ns (Levels of Logic = 2)
Source: reset (PAD)
@ -605,9 +603,9 @@ Offset: 4.545ns (Levels of Logic = 2)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 168 / 12
Total number of paths / destination ports: 152 / 12
-------------------------------------------------------------------------
Offset: 8.043ns (Levels of Logic = 3)
Offset: 8.016ns (Levels of Logic = 3)
Source: enco1/ba0 (RAM)
Destination: sram_data<7> (PAD)
Source Clock: clk falling
@ -616,13 +614,13 @@ Offset: 8.043ns (Levels of Logic = 3)
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
RAMB16_S9_S9:CLKA->DOA7 2 2.800 0.526 enco1/ba0 (rdBus0<7>)
LUT4:I1->O 1 0.704 0.000 rdBus<7>1 (rdBus<7>1)
MUXF5:I1->O 1 0.321 0.420 rdBus<7>_f5 (rdBus<7>)
RAMB16_S9_S9:CLKA->DOA7 1 2.800 0.499 enco1/ba0 (rdBus0<7>)
LUT3:I1->O 1 0.704 0.000 rdBus<7>31_F (N22)
MUXF5:I0->O 1 0.321 0.420 rdBus<7>31 (rdBus<7>)
IOBUF:I->IO 3.272 sram_data_7_IOBUF (sram_data<7>)
----------------------------------------
Total 8.043ns (7.097ns logic, 0.946ns route)
(88.2% logic, 11.8% route)
Total 8.016ns (7.097ns logic, 0.919ns route)
(88.5% logic, 11.5% route)
=========================================================================
Timing constraint: Default path analysis
@ -647,14 +645,14 @@ Delay: 6.573ns (Levels of Logic = 3)
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.07 secs
Total CPU time to Xst completion: 6.71 secs
-->
Total memory usage is 335836 kilobytes
Total memory usage is 336112 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 3 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

24
Examples/Beta1/logic/build/project.map
View File

@ -8,7 +8,7 @@ Target Device : xc3s500e
Target Package : vq100
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.52 $
Mapped Date : Sat Oct 30 18:30:51 2010
Mapped Date : Sat Oct 30 21:33:29 2010
Mapping design into LUTs...
Writing file project.ngm...
@ -25,26 +25,26 @@ Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 118 out of 9,312 1%
Number of 4 input LUTs: 102 out of 9,312 1%
Number of Slice Flip Flops: 131 out of 9,312 1%
Number of 4 input LUTs: 112 out of 9,312 1%
Logic Distribution:
Number of occupied Slices: 112 out of 4,656 2%
Number of Slices containing only related logic: 112 out of 112 100%
Number of Slices containing unrelated logic: 0 out of 112 0%
Number of occupied Slices: 118 out of 4,656 2%
Number of Slices containing only related logic: 118 out of 118 100%
Number of Slices containing unrelated logic: 0 out of 118 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 130 out of 9,312 1%
Number used as logic: 102
Total Number of 4 input LUTs: 140 out of 9,312 1%
Number used as logic: 112
Number used as a route-thru: 28
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 32 out of 66 48%
IOB Flip Flops: 25
Number of RAMB16s: 3 out of 20 15%
Number of bonded IOBs: 34 out of 66 51%
IOB Flip Flops: 27
Number of RAMB16s: 4 out of 20 20%
Number of BUFGMUXs: 1 out of 24 4%
Average Fanout of Non-Clock Nets: 2.62
Average Fanout of Non-Clock Nets: 2.51
Peak Memory Usage: 367 MB
Total REAL time to MAP completion: 2 secs

26
Examples/Beta1/logic/build/project.mrp
View File

@ -8,33 +8,33 @@ Target Device : xc3s500e
Target Package : vq100
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.52 $
Mapped Date : Sat Oct 30 18:30:51 2010
Mapped Date : Sat Oct 30 21:33:29 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 118 out of 9,312 1%
Number of 4 input LUTs: 102 out of 9,312 1%
Number of Slice Flip Flops: 131 out of 9,312 1%
Number of 4 input LUTs: 112 out of 9,312 1%
Logic Distribution:
Number of occupied Slices: 112 out of 4,656 2%
Number of Slices containing only related logic: 112 out of 112 100%
Number of Slices containing unrelated logic: 0 out of 112 0%
Number of occupied Slices: 118 out of 4,656 2%
Number of Slices containing only related logic: 118 out of 118 100%
Number of Slices containing unrelated logic: 0 out of 118 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 130 out of 9,312 1%
Number used as logic: 102
Total Number of 4 input LUTs: 140 out of 9,312 1%
Number used as logic: 112
Number used as a route-thru: 28
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 32 out of 66 48%
IOB Flip Flops: 25
Number of RAMB16s: 3 out of 20 15%
Number of bonded IOBs: 34 out of 66 51%
IOB Flip Flops: 27
Number of RAMB16s: 4 out of 20 20%
Number of BUFGMUXs: 1 out of 24 4%
Average Fanout of Non-Clock Nets: 2.62
Average Fanout of Non-Clock Nets: 2.51
Peak Memory Usage: 367 MB
Total REAL time to MAP completion: 2 secs
@ -132,6 +132,8 @@ Section 6 - IOB Properties
| nwe | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| quadA | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| quadB | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| quadC | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| quadD | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| reset | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| sram_data<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
| sram_data<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |

2
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Examples/Beta1/logic/build/project.ngc_xst.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Oct 30 18:30:37 2010">
<application stringID="Xst" timeStamp="Sat Oct 30 21:33:16 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -49,37 +49,37 @@
<item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="yes"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_COUNTERS" value="5"></item>
<item dataType="int" stringID="XST_REGISTERS" value="18">
<item dataType="int" stringID="XST_COUNTERS" value="6"></item>
<item dataType="int" stringID="XST_REGISTERS" value="20">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="5"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="4"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="10"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="8">
<item dataType="int" stringID="XST_8BIT_COMPARATOR_LESS" value="4"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="1"></item>
<item dataType="int" stringID="XST_XORS" value="2">
<item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
<item dataType="int" stringID="XST_1BIT_XOR3" value="1"/>
<item dataType="int" stringID="XST_XORS" value="4">
<item dataType="int" stringID="XST_1BIT_XOR2" value="2"/>
<item dataType="int" stringID="XST_1BIT_XOR3" value="2"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_COUNTERS" value="5"></item>
<item dataType="int" stringID="XST_REGISTERS" value="104">
<item dataType="int" stringID="XST_FLIPFLOPS" value="104"/>
<item dataType="int" stringID="XST_COUNTERS" value="6"></item>
<item dataType="int" stringID="XST_REGISTERS" value="110">
<item dataType="int" stringID="XST_FLIPFLOPS" value="110"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="8">
<item dataType="int" stringID="XST_8BIT_COMPARATOR_LESS" value="4"/>
</item>
<item dataType="int" stringID="XST_XORS" value="2">
<item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
<item dataType="int" stringID="XST_1BIT_XOR3" value="1"/>
<item dataType="int" stringID="XST_XORS" value="4">
<item dataType="int" stringID="XST_1BIT_XOR2" value="2"/>
<item dataType="int" stringID="XST_1BIT_XOR3" value="2"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="143">
<item dataType="int" stringID="XST_FLIPFLOPS" value="143"/>
<item dataType="int" stringID="XST_REGISTERS" value="158">
<item dataType="int" stringID="XST_FLIPFLOPS" value="158"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
@ -96,35 +96,35 @@
<item stringID="XST_KEEP_HIERARCHY" value="no"/>
</section>
<section stringID="XST_DESIGN_STATISTICS">
<item stringID="XST_IOS" value="32"/>
<item stringID="XST_IOS" value="34"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="239">
<item dataType="int" stringID="XST_BELS" value="278">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="11"/>
<item dataType="int" stringID="XST_INV" value="10"/>
<item dataType="int" stringID="XST_LUT1" value="28"/>
<item dataType="int" stringID="XST_LUT2" value="38"/>
<item dataType="int" stringID="XST_LUT3" value="3"/>
<item dataType="int" stringID="XST_LUT4" value="55"/>
<item dataType="int" stringID="XST_MUXCY" value="60"/>
<item dataType="int" stringID="XST_LUT2" value="40"/>
<item dataType="int" stringID="XST_LUT3" value="35"/>
<item dataType="int" stringID="XST_LUT4" value="31"/>
<item dataType="int" stringID="XST_MUXCY" value="74"/>
<item dataType="int" stringID="XST_MUXF5" value="10"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="32"/>
<item dataType="int" stringID="XST_XORCY" value="48"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="143">
<item dataType="int" stringID="XST_FD" value="38"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="158">
<item dataType="int" stringID="XST_FD" value="44"/>
<item dataType="int" stringID="XST_FD1" value="23"/>
<item dataType="int" stringID="XST_FDE" value="7"/>
<item dataType="int" stringID="XST_FDE" value="16"/>
<item dataType="int" stringID="XST_FDR" value="42"/>
</item>
<item dataType="int" stringID="XST_RAMS" value="3">
<item dataType="int" stringID="XST_RAMB16S9S9" value="1"/>
<item dataType="int" stringID="XST_RAMS" value="4">
<item dataType="int" stringID="XST_RAMB16S9S9" value="2"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
<item dataType="int" stringID="XST_BUFGP" value="1"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="31">
<item dataType="int" stringID="XST_IBUF" value="19"/>
<item dataType="int" stringID="XST_IO_BUFFERS" value="33">
<item dataType="int" stringID="XST_IBUF" value="21"/>
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="8"/>
<item dataType="int" stringID="XST_OBUF" value="4"/>
</item>
@ -132,12 +132,12 @@
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="3s500evq100-4"/>
<item AVAILABLE="4656" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="108"/>
<item AVAILABLE="9312" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="119"/>
<item AVAILABLE="9312" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="135"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="32"/>
<item AVAILABLE="66" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="32"/>
<item AVAILABLE="20" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="3"/>
<item AVAILABLE="4656" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="114"/>
<item AVAILABLE="9312" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="132"/>
<item AVAILABLE="9312" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="144"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="34"/>
<item AVAILABLE="66" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="34"/>
<item AVAILABLE="20" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="4"/>
<item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="1"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
@ -145,7 +145,7 @@
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="3"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="2"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
</section>
</application>

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Examples/Beta1/logic/build/project.pcf
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@ -1,5 +1,5 @@
//! **************************************************************************
// Written by: Map M.63c on Sat Oct 30 18:30:53 2010
// Written by: Map M.63c on Sat Oct 30 21:33:31 2010
//! **************************************************************************
SCHEMATIC START;
@ -25,12 +25,14 @@ COMP "addr<11>" LOCATE = SITE "P91" LEVEL 1;
COMP "addr<12>" LOCATE = SITE "P90" LEVEL 1;
COMP "ncs" LOCATE = SITE "P69" LEVEL 1;
COMP "noe" LOCATE = SITE "P86" LEVEL 1;
COMP "hbridge<0>" LOCATE = SITE "P48" LEVEL 1;
COMP "hbridge<1>" LOCATE = SITE "P49" LEVEL 1;
COMP "hbridge<2>" LOCATE = SITE "P54" LEVEL 1;
COMP "hbridge<3>" LOCATE = SITE "P53" LEVEL 1;
COMP "quadA" LOCATE = SITE "P67" LEVEL 1;
COMP "quadB" LOCATE = SITE "P68" LEVEL 1;
COMP "hbridge<0>" LOCATE = SITE "P66" LEVEL 1;
COMP "hbridge<1>" LOCATE = SITE "P68" LEVEL 1;
COMP "hbridge<2>" LOCATE = SITE "P70" LEVEL 1;
COMP "hbridge<3>" LOCATE = SITE "P71" LEVEL 1;
COMP "quadA" LOCATE = SITE "P36" LEVEL 1;
COMP "quadB" LOCATE = SITE "P35" LEVEL 1;
COMP "quadC" LOCATE = SITE "P34" LEVEL 1;
COMP "quadD" LOCATE = SITE "P33" LEVEL 1;
COMP "nwe" LOCATE = SITE "P88" LEVEL 1;
COMP "reset" LOCATE = SITE "P30" LEVEL 1;
COMP "addr<0>" LOCATE = SITE "P84" LEVEL 1;

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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sat Oct 30 18:30:49 2010">
<application stringID="NgdBuild" timeStamp="Sat Oct 30 21:33:27 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -53,50 +53,50 @@
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="38"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="16"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="42"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE_1" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="21"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="38"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="55"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="60"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="74"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9_S9" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9_S9" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="48"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="38"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="16"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="42"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE_1" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="27"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="38"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="55"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="60"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="74"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9_S9" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9_S9" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="48"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>

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Examples/Beta1/logic/build/project_r.bgn
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@ -4,7 +4,7 @@ Loading device for application Rf_Device from file '3s500e.nph' in environment
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/.
"beta" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4
Sat Oct 30 18:31:21 2010
Sat Oct 30 21:34:07 2010
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -l -w -g TdoPin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpClk:CCLK project_r.ncd

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Examples/Beta1/logic/build/project_r.drc
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@ -1,7 +1,7 @@
Release 12.2 Drc M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sat Oct 30 18:31:21 2010
Sat Oct 30 21:34:07 2010
drc -z project_r.ncd

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Examples/Beta1/logic/build/project_r.pad
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@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sat Oct 30 18:31:15 2010
Sat Oct 30 21:34:01 2010
# NOTE: This file is designed to be imported into a spreadsheet program
@ -51,10 +51,10 @@ P29|||GND||||||||||||
P30|reset|IBUF|IP/VREF_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
P31|||VCCO_2|||2|||||2.50||||
P32||DIFFM|IO_L03P_2/D7/GCLK12|UNUSED||2|||||||||
P33||DIFFS|IO_L03N_2/D6/GCLK13|UNUSED||2|||||||||
P34||IOB|IO/D5|UNUSED||2|||||||||
P35||DIFFM|IO_L04P_2/D4/GCLK14|UNUSED||2|||||||||
P36||DIFFS|IO_L04N_2/D3/GCLK15|UNUSED||2|||||||||
P33|quadD|IBUF|IO_L03N_2/D6/GCLK13|INPUT|LVCMOS25*|2||||IFD||LOCATED|YES|NONE|
P34|quadC|IBUF|IO/D5|INPUT|LVCMOS25*|2||||IFD||LOCATED|YES|NONE|
P35|quadB|IBUF|IO_L04P_2/D4/GCLK14|INPUT|LVCMOS25*|2||||IFD||LOCATED|YES|NONE|
P36|quadA|IBUF|IO_L04N_2/D3/GCLK15|INPUT|LVCMOS25*|2||||IFD||LOCATED|YES|NONE|
P37|||GND||||||||||||
P38|clk|IBUF|IP_L05P_2/RDWR_B/GCLK0|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
P39||DIFFSI|IP_L05N_2/M2/GCLK1|UNUSED||2|||||||||
@ -66,13 +66,13 @@ P44||DIFFS|IO_L07N_2/DIN/D0|UNUSED||2|||||||||
P45|||VCCO_2|||2|||||2.50||||
P46|||VCCAUX||||||||2.5||||
P47||DIFFM|IO_L08P_2/VS2|UNUSED||2|||||||||
P48|hbridge<0>|IOB|IO_L08N_2/VS1|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P49|hbridge<1>|IOB|IO_L09P_2/VS0|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P48||DIFFS|IO_L08N_2/VS1|UNUSED||2|||||||||
P49||DIFFM|IO_L09P_2/VS0|UNUSED||2|||||||||
P50||DIFFS|IO_L09N_2/CCLK|UNUSED||2|||||||||
P51|||DONE||||||||||||
P52|||GND||||||||||||
P53|hbridge<3>|IOB|IO_L01P_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P54|hbridge<2>|IOB|IO_L01N_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P53||DIFFM|IO_L01P_1|UNUSED||1|||||||||
P54||DIFFS|IO_L01N_1|UNUSED||1|||||||||
P55|||VCCO_1|||1|||||2.50||||
P56|||VCCINT||||||||1.2||||
P57||DIFFM|IO_L02P_1|UNUSED||1|||||||||
@ -84,12 +84,12 @@ P62||DIFFM|IO_L04P_1/RHCLK2|UNUSED||1|||||||||
P63||DIFFS|IO_L04N_1/RHCLK3/TRDY1|UNUSED||1|||||||||
P64|||GND||||||||||||
P65||DIFFM|IO_L05P_1/RHCLK4/IRDY1|UNUSED||1|||||||||
P66||DIFFS|IO_L05N_1/RHCLK5|UNUSED||1|||||||||
P67|quadA|IBUF|IO_L06P_1/RHCLK6|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
P68|quadB|IBUF|IO_L06N_1/RHCLK7|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
P66|hbridge<0>|IOB|IO_L05N_1/RHCLK5|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P67||DIFFM|IO_L06P_1/RHCLK6|UNUSED||1|||||||||
P68|hbridge<1>|IOB|IO_L06N_1/RHCLK7|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P69|ncs|IBUF|IP/VREF_1|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
P70||DIFFM|IO_L07P_1|UNUSED||1|||||||||
P71||DIFFS|IO_L07N_1|UNUSED||1|||||||||
P70|hbridge<2>|IOB|IO_L07P_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P71|hbridge<3>|IOB|IO_L07N_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P72|||GND||||||||||||
P73|||VCCO_1|||1|||||2.50||||
P74|||VCCAUX||||||||2.5||||

84
Examples/Beta1/logic/build/project_r.par
View File

@ -1,7 +1,7 @@
Release 12.2 par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
dellerwin:: Sat Oct 30 18:30:55 2010
dellerwin:: Sat Oct 30 21:33:34 2010
par -w project.ncd project_r.ncd
@ -24,12 +24,12 @@ Device speed data version: "PRODUCTION 1.27 2010-06-22".
Design Summary Report:
Number of External IOBs 32 out of 66 48%
Number of External IOBs 34 out of 66 51%
Number of External Input IOBs 20
Number of External Input IOBs 22
Number of External Input IBUFs 20
Number of LOCed External Input IBUFs 20 out of 20 100%
Number of External Input IBUFs 22
Number of LOCed External Input IBUFs 22 out of 22 100%
Number of External Output IOBs 4
@ -45,8 +45,8 @@ Design Summary Report:
Number of BUFGMUXs 1 out of 24 4%
Number of RAMB16s 3 out of 20 15%
Number of Slices 112 out of 4656 2%
Number of RAMB16s 4 out of 20 20%
Number of Slices 118 out of 4656 2%
Number of SLICEMs 0 out of 2328 0%
@ -56,52 +56,52 @@ Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 1 secs
Finished initial Timing Analysis. REAL time: 1 secs
Starting initial Timing Analysis. REAL time: 2 secs
Finished initial Timing Analysis. REAL time: 2 secs
Starting Placer
Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 2 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:1010e082) REAL time: 2 secs
Phase 1.1 Initial Placement Analysis (Checksum:cb32ae9e) REAL time: 3 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:1010e082) REAL time: 2 secs
Phase 2.7 Design Feasibility Check (Checksum:cb32ae9e) REAL time: 3 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:1010e082) REAL time: 2 secs
Phase 3.31 Local Placement Optimization (Checksum:cb32ae9e) REAL time: 3 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:40d1a052) REAL time: 2 secs
Phase 4.2 Initial Clock and IO Placement (Checksum:534cc618) REAL time: 3 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:40d1a052) REAL time: 2 secs
Phase 5.30 Global Clock Region Assignment (Checksum:534cc618) REAL time: 3 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:40d1a052) REAL time: 2 secs
Phase 6.36 Local Placement Optimization (Checksum:534cc618) REAL time: 3 secs
Phase 7.8 Global Placement
....
...
...
..........
...
...
Phase 7.8 Global Placement (Checksum:a2a5832f) REAL time: 9 secs
....
Phase 7.8 Global Placement (Checksum:b10264e) REAL time: 12 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a2a5832f) REAL time: 9 secs
Phase 8.5 Local Placement Optimization (Checksum:b10264e) REAL time: 12 secs
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:14df4917) REAL time: 10 secs
Phase 9.18 Placement Optimization (Checksum:a0b1bc3c) REAL time: 13 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:14df4917) REAL time: 10 secs
Phase 10.5 Local Placement Optimization (Checksum:a0b1bc3c) REAL time: 13 secs
Total REAL time to Placer completion: 10 secs
Total CPU time to Placer completion: 10 secs
Total REAL time to Placer completion: 13 secs
Total CPU time to Placer completion: 11 secs
Writing design to file project_r.ncd
@ -109,30 +109,32 @@ Writing design to file project_r.ncd
Starting Router
Phase 1 : 712 unrouted; REAL time: 15 secs
Phase 1 : 776 unrouted; REAL time: 19 secs
Phase 2 : 603 unrouted; REAL time: 15 secs
Phase 2 : 652 unrouted; REAL time: 19 secs
Phase 3 : 133 unrouted; REAL time: 16 secs
Phase 3 : 110 unrouted; REAL time: 19 secs
Phase 4 : 162 unrouted; (Par is working to improve performance) REAL time: 16 secs
Phase 4 : 129 unrouted; (Par is working to improve performance) REAL time: 20 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 17 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 20 secs
Updating file: project_r.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 17 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Total REAL time to Router completion: 19 secs
Total CPU time to Router completion: 18 secs
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Total REAL time to Router completion: 26 secs
Total CPU time to Router completion: 22 secs
Partition Implementation Status
-------------------------------
@ -150,7 +152,7 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX_X2Y1| No | 90 | 0.078 | 0.204 |
| clk_BUFGP | BUFGMUX_X2Y1| No | 99 | 0.082 | 0.204 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
@ -167,7 +169,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 9.582ns| N/A| 0
Autotimespec constraint for clock net clk | SETUP | N/A| 9.173ns| N/A| 0
_BUFGP | HOLD | 0.968ns| | 0| 0
----------------------------------------------------------------------------------------------------------
@ -184,10 +186,10 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 19 secs
Total CPU time to PAR completion: 19 secs
Total REAL time to PAR completion: 27 secs
Total CPU time to PAR completion: 22 secs
Peak Memory Usage: 365 MB
Peak Memory Usage: 366 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.

2
Examples/Beta1/logic/build/project_r.ptwx
View File

@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_BUFGP</twConstName><twConstData type="SETUP" best="9.582" units="ns" score="0"/><twConstData type="HOLD" slack="0.968" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">0</twUnmetConstCnt><twInfo anchorID="4">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_BUFGP</twConstName><twConstData type="SETUP" best="9.173" units="ns" score="0"/><twConstData type="HOLD" slack="0.968" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">0</twUnmetConstCnt><twInfo anchorID="4">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>

76
Examples/Beta1/logic/build/project_r.twr
View File

@ -56,12 +56,14 @@ addr<9> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
addr<10> | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
addr<11> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
addr<12> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
ncs | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
ncs | 4.667(F)| -0.793(F)|clk_BUFGP | 0.000|
nwe | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
quadA | 4.665(R)| -0.791(R)|clk_BUFGP | 0.000|
quadB | 4.665(R)| -0.791(R)|clk_BUFGP | 0.000|
reset | 3.592(R)| -0.849(R)|clk_BUFGP | 0.000|
| 3.855(F)| -0.185(F)|clk_BUFGP | 0.000|
quadC | 4.667(R)| -0.793(R)|clk_BUFGP | 0.000|
quadD | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
reset | 3.577(R)| -0.297(R)|clk_BUFGP | 0.000|
| 4.083(F)| 0.032(F)|clk_BUFGP | 0.000|
sram_data<0>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
sram_data<1>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
sram_data<2>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
@ -77,22 +79,22 @@ Clock clk to Pad
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
hbridge<0> | 13.931(R)|clk_BUFGP | 0.000|
| 14.353(F)|clk_BUFGP | 0.000|
hbridge<1> | 12.746(R)|clk_BUFGP | 0.000|
| 12.864(F)|clk_BUFGP | 0.000|
hbridge<2> | 13.504(R)|clk_BUFGP | 0.000|
| 13.837(F)|clk_BUFGP | 0.000|
hbridge<3> | 12.556(R)|clk_BUFGP | 0.000|
| 12.505(F)|clk_BUFGP | 0.000|
sram_data<0>| 12.178(F)|clk_BUFGP | 0.000|
sram_data<1>| 12.129(F)|clk_BUFGP | 0.000|
sram_data<2>| 11.885(F)|clk_BUFGP | 0.000|
sram_data<3>| 12.212(F)|clk_BUFGP | 0.000|
sram_data<4>| 11.613(F)|clk_BUFGP | 0.000|
sram_data<5>| 11.936(F)|clk_BUFGP | 0.000|
sram_data<6>| 12.842(F)|clk_BUFGP | 0.000|
sram_data<7>| 12.678(F)|clk_BUFGP | 0.000|
hbridge<0> | 11.827(R)|clk_BUFGP | 0.000|
| 11.992(F)|clk_BUFGP | 0.000|
hbridge<1> | 11.508(R)|clk_BUFGP | 0.000|
| 11.284(F)|clk_BUFGP | 0.000|
hbridge<2> | 11.647(R)|clk_BUFGP | 0.000|
| 11.564(F)|clk_BUFGP | 0.000|
hbridge<3> | 11.465(R)|clk_BUFGP | 0.000|
| 11.334(F)|clk_BUFGP | 0.000|
sram_data<0>| 12.695(F)|clk_BUFGP | 0.000|
sram_data<1>| 13.050(F)|clk_BUFGP | 0.000|
sram_data<2>| 12.938(F)|clk_BUFGP | 0.000|
sram_data<3>| 12.388(F)|clk_BUFGP | 0.000|
sram_data<4>| 12.405(F)|clk_BUFGP | 0.000|
sram_data<5>| 12.539(F)|clk_BUFGP | 0.000|
sram_data<6>| 13.285(F)|clk_BUFGP | 0.000|
sram_data<7>| 13.367(F)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
@ -100,33 +102,33 @@ Clock to Setup on destination clock clk
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 6.238| 4.791| 4.655| 9.476|
clk | 5.315| 4.587| 4.326| 9.106|
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
ncs |sram_data<0> | 8.523|
ncs |sram_data<1> | 9.355|
ncs |sram_data<2> | 8.852|
ncs |sram_data<3> | 9.607|
ncs |sram_data<4> | 8.850|
ncs |sram_data<5> | 8.354|
ncs |sram_data<6> | 9.662|
ncs |sram_data<7> | 9.907|
noe |sram_data<0> | 8.646|
noe |sram_data<1> | 9.478|
noe |sram_data<2> | 8.975|
noe |sram_data<3> | 9.730|
noe |sram_data<4> | 8.973|
noe |sram_data<5> | 8.477|
noe |sram_data<6> | 9.785|
noe |sram_data<7> | 10.030|
ncs |sram_data<0> | 9.780|
ncs |sram_data<1> | 9.525|
ncs |sram_data<2> | 9.790|
ncs |sram_data<3> | 9.796|
ncs |sram_data<4> | 10.045|
ncs |sram_data<5> | 9.192|
ncs |sram_data<6> | 10.035|
ncs |sram_data<7> | 10.294|
noe |sram_data<0> | 8.726|
noe |sram_data<1> | 8.471|
noe |sram_data<2> | 8.736|
noe |sram_data<3> | 8.742|
noe |sram_data<4> | 8.991|
noe |sram_data<5> | 8.138|
noe |sram_data<6> | 8.981|
noe |sram_data<7> | 9.240|
---------------+---------------+---------+
Analysis completed Sat Oct 30 18:31:18 2010
Analysis completed Sat Oct 30 21:34:04 2010
--------------------------------------------------------------------------------
Trace Settings:

2
Examples/Beta1/logic/build/project_r.twx
View File

File diff suppressed because one or more lines are too long

2
Examples/Beta1/logic/build/project_r.unroutes
View File

@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sat Oct 30 18:31:15 2010
Sat Oct 30 21:34:01 2010
All signals are completely routed.

6
Examples/Beta1/logic/build/project_r_bitgen.xwbt
View File

@ -1,7 +1,7 @@
INFILE=/home/erwin/sie-ceimtun/Examples/Beta1/logic/build/project_r.ncd
OUTFILE=/home/erwin/sie-ceimtun/Examples/Beta1/logic/build/project_r.bit
INFILE=/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build/project_r.ncd
OUTFILE=/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build/project_r.bit
FAMILY=Spartan3E
PART=xc3s500e-4vq100
WORKINGDIR=/home/erwin/sie-ceimtun/Examples/Beta1/logic/build
WORKINGDIR=/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build
LICENSE=WebPack
USER_INFO=0_0_674

28
Examples/Beta1/logic/build/project_r_pad.csv
View File

@ -1,7 +1,7 @@
#Release 12.2 - par M.63c (lin64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Sat Oct 30 18:31:15 2010
#Sat Oct 30 21:34:01 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program
@ -51,10 +51,10 @@ P29,,,GND,,,,,,,,,,,,
P30,reset,IBUF,IP/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
P31,,,VCCO_2,,,2,,,,,2.50,,,,
P32,,DIFFM,IO_L03P_2/D7/GCLK12,UNUSED,,2,,,,,,,,,
P33,,DIFFS,IO_L03N_2/D6/GCLK13,UNUSED,,2,,,,,,,,,
P34,,IOB,IO/D5,UNUSED,,2,,,,,,,,,
P35,,DIFFM,IO_L04P_2/D4/GCLK14,UNUSED,,2,,,,,,,,,
P36,,DIFFS,IO_L04N_2/D3/GCLK15,UNUSED,,2,,,,,,,,,
P33,quadD,IBUF,IO_L03N_2/D6/GCLK13,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
P34,quadC,IBUF,IO/D5,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
P35,quadB,IBUF,IO_L04P_2/D4/GCLK14,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
P36,quadA,IBUF,IO_L04N_2/D3/GCLK15,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
P37,,,GND,,,,,,,,,,,,
P38,clk,IBUF,IP_L05P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
P39,,DIFFSI,IP_L05N_2/M2/GCLK1,UNUSED,,2,,,,,,,,,
@ -66,13 +66,13 @@ P44,,DIFFS,IO_L07N_2/DIN/D0,UNUSED,,2,,,,,,,,,
P45,,,VCCO_2,,,2,,,,,2.50,,,,
P46,,,VCCAUX,,,,,,,,2.5,,,,
P47,,DIFFM,IO_L08P_2/VS2,UNUSED,,2,,,,,,,,,
P48,hbridge<0>,IOB,IO_L08N_2/VS1,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P49,hbridge<1>,IOB,IO_L09P_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P48,,DIFFS,IO_L08N_2/VS1,UNUSED,,2,,,,,,,,,
P49,,DIFFM,IO_L09P_2/VS0,UNUSED,,2,,,,,,,,,
P50,,DIFFS,IO_L09N_2/CCLK,UNUSED,,2,,,,,,,,,
P51,,,DONE,,,,,,,,,,,,
P52,,,GND,,,,,,,,,,,,
P53,hbridge<3>,IOB,IO_L01P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P54,hbridge<2>,IOB,IO_L01N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P53,,DIFFM,IO_L01P_1,UNUSED,,1,,,,,,,,,
P54,,DIFFS,IO_L01N_1,UNUSED,,1,,,,,,,,,
P55,,,VCCO_1,,,1,,,,,2.50,,,,
P56,,,VCCINT,,,,,,,,1.2,,,,
P57,,DIFFM,IO_L02P_1,UNUSED,,1,,,,,,,,,
@ -84,12 +84,12 @@ P62,,DIFFM,IO_L04P_1/RHCLK2,UNUSED,,1,,,,,,,,,
P63,,DIFFS,IO_L04N_1/RHCLK3/TRDY1,UNUSED,,1,,,,,,,,,
P64,,,GND,,,,,,,,,,,,
P65,,DIFFM,IO_L05P_1/RHCLK4/IRDY1,UNUSED,,1,,,,,,,,,
P66,,DIFFS,IO_L05N_1/RHCLK5,UNUSED,,1,,,,,,,,,
P67,quadA,IBUF,IO_L06P_1/RHCLK6,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
P68,quadB,IBUF,IO_L06N_1/RHCLK7,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
P66,hbridge<0>,IOB,IO_L05N_1/RHCLK5,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P67,,DIFFM,IO_L06P_1/RHCLK6,UNUSED,,1,,,,,,,,,
P68,hbridge<1>,IOB,IO_L06N_1/RHCLK7,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P69,ncs,IBUF,IP/VREF_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
P70,,DIFFM,IO_L07P_1,UNUSED,,1,,,,,,,,,
P71,,DIFFS,IO_L07N_1,UNUSED,,1,,,,,,,,,
P70,hbridge<2>,IOB,IO_L07P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P71,hbridge<3>,IOB,IO_L07N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
P72,,,GND,,,,,,,,,,,,
P73,,,VCCO_1,,,1,,,,,2.50,,,,
P74,,,VCCAUX,,,,,,,,2.5,,,,

1 #Release 12.2 - par M.63c (lin64)
2 #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
3 #Sat Oct 30 18:31:15 2010 #Sat Oct 30 21:34:01 2010
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
51 P32,,DIFFM,IO_L03P_2/D7/GCLK12,UNUSED,,2,,,,,,,,,
52 P33,,DIFFS,IO_L03N_2/D6/GCLK13,UNUSED,,2,,,,,,,,, P33,quadD,IBUF,IO_L03N_2/D6/GCLK13,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
53 P34,,IOB,IO/D5,UNUSED,,2,,,,,,,,, P34,quadC,IBUF,IO/D5,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
54 P35,,DIFFM,IO_L04P_2/D4/GCLK14,UNUSED,,2,,,,,,,,, P35,quadB,IBUF,IO_L04P_2/D4/GCLK14,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
55 P36,,DIFFS,IO_L04N_2/D3/GCLK15,UNUSED,,2,,,,,,,,, P36,quadA,IBUF,IO_L04N_2/D3/GCLK15,INPUT,LVCMOS25*,2,,,,IFD,,LOCATED,YES,NONE,
56 P37,,,GND,,,,,,,,,,,,
57 P38,clk,IBUF,IP_L05P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
58 P39,,DIFFSI,IP_L05N_2/M2/GCLK1,UNUSED,,2,,,,,,,,,
59 P40,,DIFFM,IO_L06P_2/D2/GCLK2,UNUSED,,2,,,,,,,,,
60 P41,,DIFFS,IO_L06N_2/D1/GCLK3,UNUSED,,2,,,,,,,,,
66 P47,,DIFFM,IO_L08P_2/VS2,UNUSED,,2,,,,,,,,,
67 P48,hbridge<0>,IOB,IO_L08N_2/VS1,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, P48,,DIFFS,IO_L08N_2/VS1,UNUSED,,2,,,,,,,,,
68 P49,hbridge<1>,IOB,IO_L09P_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, P49,,DIFFM,IO_L09P_2/VS0,UNUSED,,2,,,,,,,,,
69 P50,,DIFFS,IO_L09N_2/CCLK,UNUSED,,2,,,,,,,,,
70 P51,,,DONE,,,,,,,,,,,,
71 P52,,,GND,,,,,,,,,,,,
72 P53,hbridge<3>,IOB,IO_L01P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, P53,,DIFFM,IO_L01P_1,UNUSED,,1,,,,,,,,,
73 P54,hbridge<2>,IOB,IO_L01N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE, P54,,DIFFS,IO_L01N_1,UNUSED,,1,,,,,,,,,
74 P55,,,VCCO_1,,,1,,,,,2.50,,,,
75 P56,,,VCCINT,,,,,,,,1.2,,,,
76 P57,,DIFFM,IO_L02P_1,UNUSED,,1,,,,,,,,,
77 P58,,DIFFS,IO_L02N_1,UNUSED,,1,,,,,,,,,
78 P59,,,GND,,,,,,,,,,,,
84 P65,,DIFFM,IO_L05P_1/RHCLK4/IRDY1,UNUSED,,1,,,,,,,,,
85 P66,,DIFFS,IO_L05N_1/RHCLK5,UNUSED,,1,,,,,,,,, P66,hbridge<0>,IOB,IO_L05N_1/RHCLK5,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
86 P67,quadA,IBUF,IO_L06P_1/RHCLK6,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE, P67,,DIFFM,IO_L06P_1/RHCLK6,UNUSED,,1,,,,,,,,,
87 P68,quadB,IBUF,IO_L06N_1/RHCLK7,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE, P68,hbridge<1>,IOB,IO_L06N_1/RHCLK7,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
88 P69,ncs,IBUF,IP/VREF_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
89 P70,,DIFFM,IO_L07P_1,UNUSED,,1,,,,,,,,, P70,hbridge<2>,IOB,IO_L07P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
90 P71,,DIFFS,IO_L07N_1,UNUSED,,1,,,,,,,,, P71,hbridge<3>,IOB,IO_L07N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
91 P72,,,GND,,,,,,,,,,,,
92 P73,,,VCCO_1,,,1,,,,,2.50,,,,
93 P74,,,VCCAUX,,,,,,,,2.5,,,,
94 P75,,,TMS,,,,,,,,,,,,
95 P76,,,TDO,,,,,,,,,,,,

28
Examples/Beta1/logic/build/project_r_pad.txt
View File

@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sat Oct 30 18:31:15 2010
Sat Oct 30 21:34:01 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@ -52,10 +52,10 @@ Pinout by Pin Number:
|P30 |reset |IBUF |IP/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|P31 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|P32 | |DIFFM |IO_L03P_2/D7/GCLK12 |UNUSED | |2 | | | | | | | | |
|P33 | |DIFFS |IO_L03N_2/D6/GCLK13 |UNUSED | |2 | | | | | | | | |
|P34 | |IOB |IO/D5 |UNUSED | |2 | | | | | | | | |
|P35 | |DIFFM |IO_L04P_2/D4/GCLK14 |UNUSED | |2 | | | | | | | | |
|P36 | |DIFFS |IO_L04N_2/D3/GCLK15 |UNUSED | |2 | | | | | | | | |
|P33 |quadD |IBUF |IO_L03N_2/D6/GCLK13 |INPUT |LVCMOS25* |2 | | | |IFD | |LOCATED |YES |NONE |
|P34 |quadC |IBUF |IO/D5 |INPUT |LVCMOS25* |2 | | | |IFD | |LOCATED |YES |NONE |
|P35 |quadB |IBUF |IO_L04P_2/D4/GCLK14 |INPUT |LVCMOS25* |2 | | | |IFD | |LOCATED |YES |NONE |
|P36 |quadA |IBUF |IO_L04N_2/D3/GCLK15 |INPUT |LVCMOS25* |2 | | | |IFD | |LOCATED |YES |NONE |
|P37 | | |GND | | | | | | | | | | | |
|P38 |clk |IBUF |IP_L05P_2/RDWR_B/GCLK0|INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|P39 | |DIFFSI |IP_L05N_2/M2/GCLK1 |UNUSED | |2 | | | | | | | | |
@ -67,13 +67,13 @@ Pinout by Pin Number:
|P45 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|P46 | | |VCCAUX | | | | | | | |2.5 | | | |
|P47 | |DIFFM |IO_L08P_2/VS2 |UNUSED | |2 | | | | | | | | |
|P48 |hbridge<0> |IOB |IO_L08N_2/VS1 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P49 |hbridge<1> |IOB |IO_L09P_2/VS0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P48 | |DIFFS |IO_L08N_2/VS1 |UNUSED | |2 | | | | | | | | |
|P49 | |DIFFM |IO_L09P_2/VS0 |UNUSED | |2 | | | | | | | | |
|P50 | |DIFFS |IO_L09N_2/CCLK |UNUSED | |2 | | | | | | | | |
|P51 | | |DONE | | | | | | | | | | | |
|P52 | | |GND | | | | | | | | | | | |
|P53 |hbridge<3> |IOB |IO_L01P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P54 |hbridge<2> |IOB |IO_L01N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P53 | |DIFFM |IO_L01P_1 |UNUSED | |1 | | | | | | | | |
|P54 | |DIFFS |IO_L01N_1 |UNUSED | |1 | | | | | | | | |
|P55 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|P56 | | |VCCINT | | | | | | | |1.2 | | | |
|P57 | |DIFFM |IO_L02P_1 |UNUSED | |1 | | | | | | | | |
@ -85,12 +85,12 @@ Pinout by Pin Number:
|P63 | |DIFFS |IO_L04N_1/RHCLK3/TRDY1|UNUSED | |1 | | | | | | | | |
|P64 | | |GND | | | | | | | | | | | |
|P65 | |DIFFM |IO_L05P_1/RHCLK4/IRDY1|UNUSED | |1 | | | | | | | | |
|P66 | |DIFFS |IO_L05N_1/RHCLK5 |UNUSED | |1 | | | | | | | | |
|P67 |quadA |IBUF |IO_L06P_1/RHCLK6 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P68 |quadB |IBUF |IO_L06N_1/RHCLK7 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P66 |hbridge<0> |IOB |IO_L05N_1/RHCLK5 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P67 | |DIFFM |IO_L06P_1/RHCLK6 |UNUSED | |1 | | | | | | | | |
|P68 |hbridge<1> |IOB |IO_L06N_1/RHCLK7 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P69 |ncs |IBUF |IP/VREF_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|P70 | |DIFFM |IO_L07P_1 |UNUSED | |1 | | | | | | | | |
|P71 | |DIFFS |IO_L07N_1 |UNUSED | |1 | | | | | | | | |
|P70 |hbridge<2> |IOB |IO_L07P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P71 |hbridge<3> |IOB |IO_L07N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|P72 | | |GND | | | | | | | | | | | |
|P73 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|P74 | | |VCCAUX | | | | | | | |2.5 | | | |

2
Examples/Beta1/logic/build/project_summary.xml
View File

@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="2">
<DesignSummary rev="16">
<CmdHistory>
</CmdHistory>
</DesignSummary>

1320
Examples/Beta1/logic/build/project_usage.xml
View File

File diff suppressed because it is too large Load Diff

630
Examples/Beta1/logic/build/usage_statistics_webtalk.html
View File

@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">44f8cd23f23f4c7d956e087dfdda32fd</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">3e658027d9514d018043b63a2e613df7</xtag-property>.<xtag-property name="ProjectIteration">8</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">vq100</xtag-property></TD>
</TR>
@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2010-10-30T18:31:27</xtag-property></TD>
<TD><xtag-property name="Date Generated">2010-10-30T21:34:13</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">CommandLine</xtag-property></TD>
</TR>
@ -58,75 +58,75 @@
<TD>
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>AGG_BONDED_IO=32</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=32</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=112</xtag-item1></LI>
<LI><xtag-item1>NUM_4_INPUT_LUT=130</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IBUF=20</xtag-item1></LI>
<LI><xtag-item1>AGG_BONDED_IO=34</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=34</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=118</xtag-item1></LI>
<LI><xtag-item1>NUM_4_INPUT_LUT=140</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IBUF=22</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=12</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFGMUX=1</xtag-item1></LI>
<LI><xtag-item1>NUM_CYMUX=60</xtag-item1></LI>
<LI><xtag-item1>NUM_IOB_FF=25</xtag-item1></LI>
<LI><xtag-item1>NUM_CYMUX=74</xtag-item1></LI>
<LI><xtag-item1>NUM_IOB_FF=27</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT=28</xtag-item1></LI>
<LI><xtag-item1>NUM_RAMB16=3</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=112</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=118</xtag-item1></LI>
<LI><xtag-item1>NUM_XOR=32</xtag-item1></LI>
<LI><xtag-item1>NUM_RAMB16=4</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=118</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=131</xtag-item1></LI>
<LI><xtag-item1>NUM_XOR=48</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=280</xtag-item1></LI>
<LI><xtag-item1>NumNets_Active=311</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BRAMADDR=33</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BRAMDUMMY=52</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=90</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=68</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=634</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMY=353</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYBANK=42</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BRAMADDR=44</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BRAMDUMMY=70</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=99</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=71</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=679</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMY=359</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYBANK=51</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYESC=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=51</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HFULLHEX=11</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HLONG=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=68</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=546</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=29</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OMUX=263</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=199</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=235</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=37</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VLONG=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=65</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMADDR=11</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMDUMMY=9</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DUMMYBANK=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=24</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=54</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HFULLHEX=18</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HLONG=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=85</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=590</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=31</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OMUX=281</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=218</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=210</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=43</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VLONG=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=85</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMADDR=22</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMDUMMY=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DUMMYBANK=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=38</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=16</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=9</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_VFULLHEX=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_BRAMDUMMY=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_BRAMDUMMY=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_INPUT=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_INPUT=9</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PREBXBY=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_VCCOUT=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_VCCOUT=8</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>IBUF-DIFFM=8</xtag-item1></LI>
<LI><xtag-item1>IBUF-DIFFMI=2</xtag-item1></LI>
<LI><xtag-item1>IBUF-DIFFS=7</xtag-item1></LI>
<LI><xtag-item1>IBUF-DIFFS=8</xtag-item1></LI>
<LI><xtag-item1>IBUF-DIFFSI=1</xtag-item1></LI>
<LI><xtag-item1>IBUF-IOB=1</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFM=6</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFS=6</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=42</xtag-item1></LI>
<LI><xtag-item1>IBUF-IOB=2</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFM=5</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFS=7</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=43</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@ -138,34 +138,34 @@
<LI><xtag-item2>BUFGMUX=1</xtag-item2></LI>
<LI><xtag-item2>BUFGMUX_GCLKMUX=1</xtag-item2></LI>
<LI><xtag-item2>BUFGMUX_GCLK_BUFFER=1</xtag-item2></LI>
<LI><xtag-item2>IBUF=20</xtag-item2></LI>
<LI><xtag-item2>IBUF_IFD_DELAY=17</xtag-item2></LI>
<LI><xtag-item2>IBUF_IFF1=17</xtag-item2></LI>
<LI><xtag-item2>IBUF_INBUF=20</xtag-item2></LI>
<LI><xtag-item2>IBUF_PAD=20</xtag-item2></LI>
<LI><xtag-item2>IBUF=22</xtag-item2></LI>
<LI><xtag-item2>IBUF_IFD_DELAY=19</xtag-item2></LI>
<LI><xtag-item2>IBUF_IFF1=19</xtag-item2></LI>
<LI><xtag-item2>IBUF_INBUF=22</xtag-item2></LI>
<LI><xtag-item2>IBUF_PAD=22</xtag-item2></LI>
<LI><xtag-item2>IOB=12</xtag-item2></LI>
<LI><xtag-item2>IOB_IFD_DELAY=8</xtag-item2></LI>
<LI><xtag-item2>IOB_IFF1=8</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=8</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=12</xtag-item2></LI>
<LI><xtag-item2>IOB_PAD=12</xtag-item2></LI>
<LI><xtag-item2>RAMB16=3</xtag-item2></LI>
<LI><xtag-item2>RAMB16_RAMB16=3</xtag-item2></LI>
<LI><xtag-item2>RAMB16_RAMB16A=3</xtag-item2></LI>
<LI><xtag-item2>RAMB16_RAMB16B=1</xtag-item2></LI>
<LI><xtag-item2>SLICEL=112</xtag-item2></LI>
<LI><xtag-item2>RAMB16=4</xtag-item2></LI>
<LI><xtag-item2>RAMB16_RAMB16=4</xtag-item2></LI>
<LI><xtag-item2>RAMB16_RAMB16A=4</xtag-item2></LI>
<LI><xtag-item2>RAMB16_RAMB16B=2</xtag-item2></LI>
<LI><xtag-item2>SLICEL=118</xtag-item2></LI>
<LI><xtag-item2>SLICEL_C1VDD=4</xtag-item2></LI>
<LI><xtag-item2>SLICEL_CYMUXF=32</xtag-item2></LI>
<LI><xtag-item2>SLICEL_CYMUXG=28</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F=70</xtag-item2></LI>
<LI><xtag-item2>SLICEL_CYMUXF=40</xtag-item2></LI>
<LI><xtag-item2>SLICEL_CYMUXG=34</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F=76</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F5MUX=10</xtag-item2></LI>
<LI><xtag-item2>SLICEL_FFX=59</xtag-item2></LI>
<LI><xtag-item2>SLICEL_FFY=59</xtag-item2></LI>
<LI><xtag-item2>SLICEL_G=60</xtag-item2></LI>
<LI><xtag-item2>SLICEL_FFX=65</xtag-item2></LI>
<LI><xtag-item2>SLICEL_FFY=66</xtag-item2></LI>
<LI><xtag-item2>SLICEL_G=64</xtag-item2></LI>
<LI><xtag-item2>SLICEL_GNDF=12</xtag-item2></LI>
<LI><xtag-item2>SLICEL_GNDG=12</xtag-item2></LI>
<LI><xtag-item2>SLICEL_XORF=16</xtag-item2></LI>
<LI><xtag-item2>SLICEL_XORG=16</xtag-item2></LI>
<LI><xtag-item2>SLICEL_XORF=24</xtag-item2></LI>
<LI><xtag-item2>SLICEL_XORG=24</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
@ -188,24 +188,24 @@
</xtag-group>
<xtag-group><xtag-group-name name="IBUF">IBUF</xtag-group-name>
<UL>
<LI><xtag-item3>ICLK1=[ICLK1_INV:15] [ICLK1:2]</xtag-item3></LI>
<LI><xtag-item3>ICLK1=[ICLK1_INV:15] [ICLK1:4]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IBUF_IFF1">IBUF_IFF1</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:2] [CK_INV:15]</xtag-item3></LI>
<LI><xtag-item3>IFF1_INIT_ATTR=[INIT0:17]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:17]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:4] [CK_INV:15]</xtag-item3></LI>
<LI><xtag-item3>IFF1_INIT_ATTR=[INIT0:19]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:19]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IBUF_INBUF">IBUF_INBUF</xtag-group-name>
<UL>
<LI><xtag-item3>IFD_DELAY_VALUE=[DLY3:17]</xtag-item3></LI>
<LI><xtag-item3>IFD_DELAY_VALUE=[DLY3:19]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IBUF_PAD">IBUF_PAD</xtag-group-name>
<UL>
<LI><xtag-item3>IOATTRBOX=[LVCMOS25:20]</xtag-item3></LI>
<LI><xtag-item3>IOATTRBOX=[LVCMOS25:22]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
@ -244,57 +244,57 @@
</xtag-group>
<xtag-group><xtag-group-name name="RAMB16">RAMB16</xtag-group-name>
<UL>
<LI><xtag-item3>CLKA=[CLKA_INV:3] [CLKA:0]</xtag-item3></LI>
<LI><xtag-item3>CLKB=[CLKB_INV:1] [CLKB:0]</xtag-item3></LI>
<LI><xtag-item3>ENA=[ENA_INV:0] [ENA:3]</xtag-item3></LI>
<LI><xtag-item3>ENB=[ENB_INV:0] [ENB:1]</xtag-item3></LI>
<LI><xtag-item3>SSRA=[SSRA_INV:0] [SSRA:3]</xtag-item3></LI>
<LI><xtag-item3>SSRB=[SSRB_INV:0] [SSRB:1]</xtag-item3></LI>
<LI><xtag-item3>WEA=[WEA:3] [WEA_INV:0]</xtag-item3></LI>
<LI><xtag-item3>WEB=[WEB:1] [WEB_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLKA=[CLKA_INV:4] [CLKA:0]</xtag-item3></LI>
<LI><xtag-item3>CLKB=[CLKB_INV:2] [CLKB:0]</xtag-item3></LI>
<LI><xtag-item3>ENA=[ENA_INV:0] [ENA:4]</xtag-item3></LI>
<LI><xtag-item3>ENB=[ENB_INV:0] [ENB:2]</xtag-item3></LI>
<LI><xtag-item3>SSRA=[SSRA_INV:0] [SSRA:4]</xtag-item3></LI>
<LI><xtag-item3>SSRB=[SSRB_INV:0] [SSRB:2]</xtag-item3></LI>
<LI><xtag-item3>WEA=[WEA:4] [WEA_INV:0]</xtag-item3></LI>
<LI><xtag-item3>WEB=[WEB:2] [WEB_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="RAMB16_RAMB16A">RAMB16_RAMB16A</xtag-group-name>
<UL>
<LI><xtag-item3>CLKA=[CLKA_INV:3] [CLKA:0]</xtag-item3></LI>
<LI><xtag-item3>ENA=[ENA_INV:0] [ENA:3]</xtag-item3></LI>
<LI><xtag-item3>PORTA_ATTR=[2048X9:3]</xtag-item3></LI>
<LI><xtag-item3>SSRA=[SSRA_INV:0] [SSRA:3]</xtag-item3></LI>
<LI><xtag-item3>WEA=[WEA:3] [WEA_INV:0]</xtag-item3></LI>
<LI><xtag-item3>WRITEMODEA=[WRITE_FIRST:3]</xtag-item3></LI>
<LI><xtag-item3>CLKA=[CLKA_INV:4] [CLKA:0]</xtag-item3></LI>
<LI><xtag-item3>ENA=[ENA_INV:0] [ENA:4]</xtag-item3></LI>
<LI><xtag-item3>PORTA_ATTR=[2048X9:4]</xtag-item3></LI>
<LI><xtag-item3>SSRA=[SSRA_INV:0] [SSRA:4]</xtag-item3></LI>
<LI><xtag-item3>WEA=[WEA:4] [WEA_INV:0]</xtag-item3></LI>
<LI><xtag-item3>WRITEMODEA=[WRITE_FIRST:4]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="RAMB16_RAMB16B">RAMB16_RAMB16B</xtag-group-name>
<UL>
<LI><xtag-item3>CLKB=[CLKB_INV:1] [CLKB:0]</xtag-item3></LI>
<LI><xtag-item3>ENB=[ENB_INV:0] [ENB:1]</xtag-item3></LI>
<LI><xtag-item3>PORTB_ATTR=[2048X9:1]</xtag-item3></LI>
<LI><xtag-item3>SSRB=[SSRB_INV:0] [SSRB:1]</xtag-item3></LI>
<LI><xtag-item3>WEB=[WEB:1] [WEB_INV:0]</xtag-item3></LI>
<LI><xtag-item3>WRITEMODEB=[WRITE_FIRST:1]</xtag-item3></LI>
<LI><xtag-item3>CLKB=[CLKB_INV:2] [CLKB:0]</xtag-item3></LI>
<LI><xtag-item3>ENB=[ENB_INV:0] [ENB:2]</xtag-item3></LI>
<LI><xtag-item3>PORTB_ATTR=[2048X9:2]</xtag-item3></LI>
<LI><xtag-item3>SSRB=[SSRB_INV:0] [SSRB:2]</xtag-item3></LI>
<LI><xtag-item3>WEB=[WEB:2] [WEB_INV:0]</xtag-item3></LI>
<LI><xtag-item3>WRITEMODEB=[WRITE_FIRST:2]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>BX=[BX_INV:1] [BX:56]</xtag-item3></LI>
<LI><xtag-item3>BY=[BY:39] [BY_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CE=[CE:22] [CE_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CIN=[CIN_INV:0] [CIN:24]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:44] [CLK_INV:17]</xtag-item3></LI>
<LI><xtag-item3>BX=[BX_INV:0] [BX:60]</xtag-item3></LI>
<LI><xtag-item3>BY=[BY:41] [BY_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CE=[CE:25] [CE_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CIN=[CIN_INV:0] [CIN:30]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:49] [CLK_INV:17]</xtag-item3></LI>
<LI><xtag-item3>SR=[SR:17] [SR_INV:21]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXF">SLICEL_CYMUXF</xtag-group-name>
<UL>
<LI><xtag-item3>0=[0:32] [0_INV:0]</xtag-item3></LI>
<LI><xtag-item3>1=[1_INV:0] [1:32]</xtag-item3></LI>
<LI><xtag-item3>0=[0:40] [0_INV:0]</xtag-item3></LI>
<LI><xtag-item3>1=[1_INV:0] [1:40]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
<UL>
<LI><xtag-item3>0=[0:28] [0_INV:0]</xtag-item3></LI>
<LI><xtag-item3>0=[0:34] [0_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F5MUX">SLICEL_F5MUX</xtag-group-name>
@ -304,33 +304,33 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
<UL>
<LI><xtag-item3>CE=[CE:20] [CE_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:43] [CK_INV:16]</xtag-item3></LI>
<LI><xtag-item3>D=[D:58] [D_INV:1]</xtag-item3></LI>
<LI><xtag-item3>FFX_INIT_ATTR=[INIT0:59]</xtag-item3></LI>
<LI><xtag-item3>FFX_SR_ATTR=[SRLOW:59]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:59]</xtag-item3></LI>
<LI><xtag-item3>CE=[CE:24] [CE_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:49] [CK_INV:16]</xtag-item3></LI>
<LI><xtag-item3>D=[D:65] [D_INV:0]</xtag-item3></LI>
<LI><xtag-item3>FFX_INIT_ATTR=[INIT0:65]</xtag-item3></LI>
<LI><xtag-item3>FFX_SR_ATTR=[SRLOW:65]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:65]</xtag-item3></LI>
<LI><xtag-item3>SR=[SR:16] [SR_INV:21]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:22] [SYNC:37]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:28] [SYNC:37]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFY">SLICEL_FFY</xtag-group-name>
<UL>
<LI><xtag-item3>CE=[CE:20] [CE_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:42] [CK_INV:17]</xtag-item3></LI>
<LI><xtag-item3>D=[D:59] [D_INV:0]</xtag-item3></LI>
<LI><xtag-item3>FFY_INIT_ATTR=[INIT0:59]</xtag-item3></LI>
<LI><xtag-item3>FFY_SR_ATTR=[SRLOW:59]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:59]</xtag-item3></LI>
<LI><xtag-item3>CE=[CE:25] [CE_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:49] [CK_INV:17]</xtag-item3></LI>
<LI><xtag-item3>D=[D:66] [D_INV:0]</xtag-item3></LI>
<LI><xtag-item3>FFY_INIT_ATTR=[INIT0:66]</xtag-item3></LI>
<LI><xtag-item3>FFY_SR_ATTR=[SRLOW:66]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:66]</xtag-item3></LI>
<LI><xtag-item3>SR=[SR:17] [SR_INV:21]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:21] [SYNC:38]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:28] [SYNC:38]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_XORF">SLICEL_XORF</xtag-group-name>
<UL>
<LI><xtag-item3>1=[1_INV:0] [1:16]</xtag-item3></LI>
<LI><xtag-item3>1=[1_INV:0] [1:24]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
@ -363,33 +363,33 @@
<xtag-group><xtag-group-name name="IBUF">IBUF</xtag-group-name>
<UL>
<LI><xtag-item1>I=4</xtag-item1></LI>
<LI><xtag-item1>ICLK1=17</xtag-item1></LI>
<LI><xtag-item1>IQ1=17</xtag-item1></LI>
<LI><xtag-item1>PAD=20</xtag-item1></LI>
<LI><xtag-item1>ICLK1=19</xtag-item1></LI>
<LI><xtag-item1>IQ1=19</xtag-item1></LI>
<LI><xtag-item1>PAD=22</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IBUF_IFD_DELAY">IBUF_IFD_DELAY</xtag-group-name>
<UL>
<LI><xtag-item1>IN=17</xtag-item1></LI>
<LI><xtag-item1>OUT=17</xtag-item1></LI>
<LI><xtag-item1>IN=19</xtag-item1></LI>
<LI><xtag-item1>OUT=19</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IBUF_IFF1">IBUF_IFF1</xtag-group-name>
<UL>
<LI><xtag-item1>CK=17</xtag-item1></LI>
<LI><xtag-item1>D=17</xtag-item1></LI>
<LI><xtag-item1>Q=17</xtag-item1></LI>
<LI><xtag-item1>CK=19</xtag-item1></LI>
<LI><xtag-item1>D=19</xtag-item1></LI>
<LI><xtag-item1>Q=19</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IBUF_INBUF">IBUF_INBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=20</xtag-item1></LI>
<LI><xtag-item1>OUT=20</xtag-item1></LI>
<LI><xtag-item1>IN=22</xtag-item1></LI>
<LI><xtag-item1>OUT=22</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IBUF_PAD">IBUF_PAD</xtag-group-name>
<UL>
<LI><xtag-item1>PAD=20</xtag-item1></LI>
<LI><xtag-item1>PAD=22</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
@ -434,30 +434,30 @@
</xtag-group>
<xtag-group><xtag-group-name name="RAMB16">RAMB16</xtag-group-name>
<UL>
<LI><xtag-item1>ADDRA10=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA11=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA12=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA13=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA3=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA4=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA5=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA6=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA7=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA8=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA9=3</xtag-item1></LI>
<LI><xtag-item1>ADDRB10=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB11=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB12=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB13=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB3=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB4=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB5=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB6=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB7=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB8=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB9=1</xtag-item1></LI>
<LI><xtag-item1>CLKA=3</xtag-item1></LI>
<LI><xtag-item1>CLKB=1</xtag-item1></LI>
<LI><xtag-item1>ADDRA10=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA11=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA12=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA13=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA3=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA4=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA5=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA6=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA7=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA8=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA9=4</xtag-item1></LI>
<LI><xtag-item1>ADDRB10=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB11=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB12=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB13=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB3=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB4=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB5=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB6=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB7=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB8=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB9=2</xtag-item1></LI>
<LI><xtag-item1>CLKA=4</xtag-item1></LI>
<LI><xtag-item1>CLKB=2</xtag-item1></LI>
<LI><xtag-item1>DIA0=2</xtag-item1></LI>
<LI><xtag-item1>DIA1=2</xtag-item1></LI>
<LI><xtag-item1>DIA2=2</xtag-item1></LI>
@ -466,60 +466,60 @@
<LI><xtag-item1>DIA5=2</xtag-item1></LI>
<LI><xtag-item1>DIA6=2</xtag-item1></LI>
<LI><xtag-item1>DIA7=2</xtag-item1></LI>
<LI><xtag-item1>DIB0=1</xtag-item1></LI>
<LI><xtag-item1>DIB1=1</xtag-item1></LI>
<LI><xtag-item1>DIB2=1</xtag-item1></LI>
<LI><xtag-item1>DIB3=1</xtag-item1></LI>
<LI><xtag-item1>DIB4=1</xtag-item1></LI>
<LI><xtag-item1>DIB5=1</xtag-item1></LI>
<LI><xtag-item1>DIB6=1</xtag-item1></LI>
<LI><xtag-item1>DIB7=1</xtag-item1></LI>
<LI><xtag-item1>DIB0=2</xtag-item1></LI>
<LI><xtag-item1>DIB1=2</xtag-item1></LI>
<LI><xtag-item1>DIB2=2</xtag-item1></LI>
<LI><xtag-item1>DIB3=2</xtag-item1></LI>
<LI><xtag-item1>DIB4=2</xtag-item1></LI>
<LI><xtag-item1>DIB5=2</xtag-item1></LI>
<LI><xtag-item1>DIB6=2</xtag-item1></LI>
<LI><xtag-item1>DIB7=2</xtag-item1></LI>
<LI><xtag-item1>DIPA0=2</xtag-item1></LI>
<LI><xtag-item1>DIPB0=1</xtag-item1></LI>
<LI><xtag-item1>DOA0=3</xtag-item1></LI>
<LI><xtag-item1>DOA1=3</xtag-item1></LI>
<LI><xtag-item1>DOA2=3</xtag-item1></LI>
<LI><xtag-item1>DOA3=3</xtag-item1></LI>
<LI><xtag-item1>DOA4=3</xtag-item1></LI>
<LI><xtag-item1>DOA5=3</xtag-item1></LI>
<LI><xtag-item1>DOA6=3</xtag-item1></LI>
<LI><xtag-item1>DOA7=3</xtag-item1></LI>
<LI><xtag-item1>ENA=3</xtag-item1></LI>
<LI><xtag-item1>ENB=1</xtag-item1></LI>
<LI><xtag-item1>SSRA=3</xtag-item1></LI>
<LI><xtag-item1>SSRB=1</xtag-item1></LI>
<LI><xtag-item1>WEA=3</xtag-item1></LI>
<LI><xtag-item1>WEB=1</xtag-item1></LI>
<LI><xtag-item1>DIPB0=2</xtag-item1></LI>
<LI><xtag-item1>DOA0=4</xtag-item1></LI>
<LI><xtag-item1>DOA1=4</xtag-item1></LI>
<LI><xtag-item1>DOA2=4</xtag-item1></LI>
<LI><xtag-item1>DOA3=4</xtag-item1></LI>
<LI><xtag-item1>DOA4=4</xtag-item1></LI>
<LI><xtag-item1>DOA5=4</xtag-item1></LI>
<LI><xtag-item1>DOA6=4</xtag-item1></LI>
<LI><xtag-item1>DOA7=4</xtag-item1></LI>
<LI><xtag-item1>ENA=4</xtag-item1></LI>
<LI><xtag-item1>ENB=2</xtag-item1></LI>
<LI><xtag-item1>SSRA=4</xtag-item1></LI>
<LI><xtag-item1>SSRB=2</xtag-item1></LI>
<LI><xtag-item1>WEA=4</xtag-item1></LI>
<LI><xtag-item1>WEB=2</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="RAMB16_RAMB16">RAMB16_RAMB16</xtag-group-name>
<UL>
<LI><xtag-item1>ADDRA=3</xtag-item1></LI>
<LI><xtag-item1>ADDRB=1</xtag-item1></LI>
<LI><xtag-item1>DIA=3</xtag-item1></LI>
<LI><xtag-item1>DIB=1</xtag-item1></LI>
<LI><xtag-item1>DOA=3</xtag-item1></LI>
<LI><xtag-item1>DOB=1</xtag-item1></LI>
<LI><xtag-item1>ADDRA=4</xtag-item1></LI>
<LI><xtag-item1>ADDRB=2</xtag-item1></LI>
<LI><xtag-item1>DIA=4</xtag-item1></LI>
<LI><xtag-item1>DIB=2</xtag-item1></LI>
<LI><xtag-item1>DOA=4</xtag-item1></LI>
<LI><xtag-item1>DOB=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="RAMB16_RAMB16A">RAMB16_RAMB16A</xtag-group-name>
<UL>
<LI><xtag-item1>ADDRA=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA10=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA11=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA12=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA13=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA3=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA4=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA5=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA6=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA7=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA8=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA9=3</xtag-item1></LI>
<LI><xtag-item1>CLKA=3</xtag-item1></LI>
<LI><xtag-item1>DIA=3</xtag-item1></LI>
<LI><xtag-item1>ADDRA=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA10=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA11=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA12=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA13=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA3=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA4=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA5=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA6=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA7=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA8=4</xtag-item1></LI>
<LI><xtag-item1>ADDRA9=4</xtag-item1></LI>
<LI><xtag-item1>CLKA=4</xtag-item1></LI>
<LI><xtag-item1>DIA=4</xtag-item1></LI>
<LI><xtag-item1>DIA0=2</xtag-item1></LI>
<LI><xtag-item1>DIA1=2</xtag-item1></LI>
<LI><xtag-item1>DIA2=2</xtag-item1></LI>
@ -529,74 +529,74 @@
<LI><xtag-item1>DIA6=2</xtag-item1></LI>
<LI><xtag-item1>DIA7=2</xtag-item1></LI>
<LI><xtag-item1>DIPA0=2</xtag-item1></LI>
<LI><xtag-item1>DOA=3</xtag-item1></LI>
<LI><xtag-item1>DOA0=3</xtag-item1></LI>
<LI><xtag-item1>DOA1=3</xtag-item1></LI>
<LI><xtag-item1>DOA2=3</xtag-item1></LI>
<LI><xtag-item1>DOA3=3</xtag-item1></LI>
<LI><xtag-item1>DOA4=3</xtag-item1></LI>
<LI><xtag-item1>DOA5=3</xtag-item1></LI>
<LI><xtag-item1>DOA6=3</xtag-item1></LI>
<LI><xtag-item1>DOA7=3</xtag-item1></LI>
<LI><xtag-item1>ENA=3</xtag-item1></LI>
<LI><xtag-item1>SSRA=3</xtag-item1></LI>
<LI><xtag-item1>WEA=3</xtag-item1></LI>
<LI><xtag-item1>DOA=4</xtag-item1></LI>
<LI><xtag-item1>DOA0=4</xtag-item1></LI>
<LI><xtag-item1>DOA1=4</xtag-item1></LI>
<LI><xtag-item1>DOA2=4</xtag-item1></LI>
<LI><xtag-item1>DOA3=4</xtag-item1></LI>
<LI><xtag-item1>DOA4=4</xtag-item1></LI>
<LI><xtag-item1>DOA5=4</xtag-item1></LI>
<LI><xtag-item1>DOA6=4</xtag-item1></LI>
<LI><xtag-item1>DOA7=4</xtag-item1></LI>
<LI><xtag-item1>ENA=4</xtag-item1></LI>
<LI><xtag-item1>SSRA=4</xtag-item1></LI>
<LI><xtag-item1>WEA=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="RAMB16_RAMB16B">RAMB16_RAMB16B</xtag-group-name>
<UL>
<LI><xtag-item1>ADDRB=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB10=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB11=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB12=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB13=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB3=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB4=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB5=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB6=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB7=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB8=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB9=1</xtag-item1></LI>
<LI><xtag-item1>CLKB=1</xtag-item1></LI>
<LI><xtag-item1>DIB=1</xtag-item1></LI>
<LI><xtag-item1>DIB0=1</xtag-item1></LI>
<LI><xtag-item1>DIB1=1</xtag-item1></LI>
<LI><xtag-item1>DIB2=1</xtag-item1></LI>
<LI><xtag-item1>DIB3=1</xtag-item1></LI>
<LI><xtag-item1>DIB4=1</xtag-item1></LI>
<LI><xtag-item1>DIB5=1</xtag-item1></LI>
<LI><xtag-item1>DIB6=1</xtag-item1></LI>
<LI><xtag-item1>DIB7=1</xtag-item1></LI>
<LI><xtag-item1>DIPB0=1</xtag-item1></LI>
<LI><xtag-item1>DOB=1</xtag-item1></LI>
<LI><xtag-item1>ENB=1</xtag-item1></LI>
<LI><xtag-item1>SSRB=1</xtag-item1></LI>
<LI><xtag-item1>WEB=1</xtag-item1></LI>
<LI><xtag-item1>ADDRB=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB10=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB11=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB12=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB13=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB3=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB4=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB5=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB6=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB7=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB8=2</xtag-item1></LI>
<LI><xtag-item1>ADDRB9=2</xtag-item1></LI>
<LI><xtag-item1>CLKB=2</xtag-item1></LI>
<LI><xtag-item1>DIB=2</xtag-item1></LI>
<LI><xtag-item1>DIB0=2</xtag-item1></LI>
<LI><xtag-item1>DIB1=2</xtag-item1></LI>
<LI><xtag-item1>DIB2=2</xtag-item1></LI>
<LI><xtag-item1>DIB3=2</xtag-item1></LI>
<LI><xtag-item1>DIB4=2</xtag-item1></LI>
<LI><xtag-item1>DIB5=2</xtag-item1></LI>
<LI><xtag-item1>DIB6=2</xtag-item1></LI>
<LI><xtag-item1>DIB7=2</xtag-item1></LI>
<LI><xtag-item1>DIPB0=2</xtag-item1></LI>
<LI><xtag-item1>DOB=2</xtag-item1></LI>
<LI><xtag-item1>ENB=2</xtag-item1></LI>
<LI><xtag-item1>SSRB=2</xtag-item1></LI>
<LI><xtag-item1>WEB=2</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>BX=57</xtag-item1></LI>
<LI><xtag-item1>BY=39</xtag-item1></LI>
<LI><xtag-item1>CE=22</xtag-item1></LI>
<LI><xtag-item1>CIN=24</xtag-item1></LI>
<LI><xtag-item1>CLK=61</xtag-item1></LI>
<LI><xtag-item1>COUT=28</xtag-item1></LI>
<LI><xtag-item1>F1=68</xtag-item1></LI>
<LI><xtag-item1>F2=52</xtag-item1></LI>
<LI><xtag-item1>F3=33</xtag-item1></LI>
<LI><xtag-item1>F4=32</xtag-item1></LI>
<LI><xtag-item1>G1=60</xtag-item1></LI>
<LI><xtag-item1>G2=44</xtag-item1></LI>
<LI><xtag-item1>G3=25</xtag-item1></LI>
<LI><xtag-item1>G4=23</xtag-item1></LI>
<LI><xtag-item1>BX=60</xtag-item1></LI>
<LI><xtag-item1>BY=41</xtag-item1></LI>
<LI><xtag-item1>CE=25</xtag-item1></LI>
<LI><xtag-item1>CIN=30</xtag-item1></LI>
<LI><xtag-item1>CLK=66</xtag-item1></LI>
<LI><xtag-item1>COUT=34</xtag-item1></LI>
<LI><xtag-item1>F1=74</xtag-item1></LI>
<LI><xtag-item1>F2=58</xtag-item1></LI>
<LI><xtag-item1>F3=37</xtag-item1></LI>
<LI><xtag-item1>F4=20</xtag-item1></LI>
<LI><xtag-item1>G1=64</xtag-item1></LI>
<LI><xtag-item1>G2=48</xtag-item1></LI>
<LI><xtag-item1>G3=29</xtag-item1></LI>
<LI><xtag-item1>G4=11</xtag-item1></LI>
<LI><xtag-item1>SR=38</xtag-item1></LI>
<LI><xtag-item1>X=34</xtag-item1></LI>
<LI><xtag-item1>XQ=59</xtag-item1></LI>
<LI><xtag-item1>Y=14</xtag-item1></LI>
<LI><xtag-item1>YQ=59</xtag-item1></LI>
<LI><xtag-item1>X=35</xtag-item1></LI>
<LI><xtag-item1>XQ=65</xtag-item1></LI>
<LI><xtag-item1>Y=13</xtag-item1></LI>
<LI><xtag-item1>YQ=66</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_C1VDD">SLICEL_C1VDD</xtag-group-name>
@ -606,27 +606,27 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXF">SLICEL_CYMUXF</xtag-group-name>
<UL>
<LI><xtag-item1>0=32</xtag-item1></LI>
<LI><xtag-item1>1=32</xtag-item1></LI>
<LI><xtag-item1>OUT=32</xtag-item1></LI>
<LI><xtag-item1>S0=32</xtag-item1></LI>
<LI><xtag-item1>0=40</xtag-item1></LI>
<LI><xtag-item1>1=40</xtag-item1></LI>
<LI><xtag-item1>OUT=40</xtag-item1></LI>
<LI><xtag-item1>S0=40</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
<UL>
<LI><xtag-item1>0=28</xtag-item1></LI>
<LI><xtag-item1>1=28</xtag-item1></LI>
<LI><xtag-item1>OUT=28</xtag-item1></LI>
<LI><xtag-item1>S0=28</xtag-item1></LI>
<LI><xtag-item1>0=34</xtag-item1></LI>
<LI><xtag-item1>1=34</xtag-item1></LI>
<LI><xtag-item1>OUT=34</xtag-item1></LI>
<LI><xtag-item1>S0=34</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F">SLICEL_F</xtag-group-name>
<UL>
<LI><xtag-item1>A1=68</xtag-item1></LI>
<LI><xtag-item1>A2=52</xtag-item1></LI>
<LI><xtag-item1>A3=33</xtag-item1></LI>
<LI><xtag-item1>A4=32</xtag-item1></LI>
<LI><xtag-item1>D=70</xtag-item1></LI>
<LI><xtag-item1>A1=74</xtag-item1></LI>
<LI><xtag-item1>A2=58</xtag-item1></LI>
<LI><xtag-item1>A3=37</xtag-item1></LI>
<LI><xtag-item1>A4=20</xtag-item1></LI>
<LI><xtag-item1>D=76</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F5MUX">SLICEL_F5MUX</xtag-group-name>
@ -639,29 +639,29 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
<UL>
<LI><xtag-item1>CE=20</xtag-item1></LI>
<LI><xtag-item1>CK=59</xtag-item1></LI>
<LI><xtag-item1>D=59</xtag-item1></LI>
<LI><xtag-item1>Q=59</xtag-item1></LI>
<LI><xtag-item1>CE=24</xtag-item1></LI>
<LI><xtag-item1>CK=65</xtag-item1></LI>
<LI><xtag-item1>D=65</xtag-item1></LI>
<LI><xtag-item1>Q=65</xtag-item1></LI>
<LI><xtag-item1>SR=37</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFY">SLICEL_FFY</xtag-group-name>
<UL>
<LI><xtag-item1>CE=20</xtag-item1></LI>
<LI><xtag-item1>CK=59</xtag-item1></LI>
<LI><xtag-item1>D=59</xtag-item1></LI>
<LI><xtag-item1>Q=59</xtag-item1></LI>
<LI><xtag-item1>CE=25</xtag-item1></LI>
<LI><xtag-item1>CK=66</xtag-item1></LI>
<LI><xtag-item1>D=66</xtag-item1></LI>
<LI><xtag-item1>Q=66</xtag-item1></LI>
<LI><xtag-item1>SR=38</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_G">SLICEL_G</xtag-group-name>
<UL>
<LI><xtag-item1>A1=60</xtag-item1></LI>
<LI><xtag-item1>A2=44</xtag-item1></LI>
<LI><xtag-item1>A3=25</xtag-item1></LI>
<LI><xtag-item1>A4=23</xtag-item1></LI>
<LI><xtag-item1>D=60</xtag-item1></LI>
<LI><xtag-item1>A1=64</xtag-item1></LI>
<LI><xtag-item1>A2=48</xtag-item1></LI>
<LI><xtag-item1>A3=29</xtag-item1></LI>
<LI><xtag-item1>A4=11</xtag-item1></LI>
<LI><xtag-item1>D=64</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_GNDF">SLICEL_GNDF</xtag-group-name>
@ -676,18 +676,18 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_XORF">SLICEL_XORF</xtag-group-name>
<UL>
<LI><xtag-item1>0=16</xtag-item1></LI>
<LI><xtag-item1>1=16</xtag-item1></LI>
<LI><xtag-item1>O=16</xtag-item1></LI>
<LI><xtag-item1>0=24</xtag-item1></LI>
<LI><xtag-item1>1=24</xtag-item1></LI>
<LI><xtag-item1>O=24</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_XORG">SLICEL_XORG</xtag-group-name>
<UL>
<LI><xtag-item1>0=16</xtag-item1></LI>
<LI><xtag-item1>1=16</xtag-item1></LI>
<LI><xtag-item1>O=16</xtag-item1></LI>
<LI><xtag-item1>0=24</xtag-item1></LI>
<LI><xtag-item1>1=24</xtag-item1></LI>
<LI><xtag-item1>O=24</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@ -696,8 +696,8 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>82</xtag-total-run-started></td>
<td><xtag-total-run-finished>82</xtag-total-run-finished></td>
<td><xtag-total-run-started>90</xtag-total-run-started></td>
<td><xtag-total-run-finished>90</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -706,8 +706,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>98</xtag-total-run-started></td>
<td><xtag-total-run-finished>96</xtag-total-run-finished></td>
<td><xtag-total-run-started>110</xtag-total-run-started></td>
<td><xtag-total-run-finished>108</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -716,8 +716,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>102</xtag-total-run-started></td>
<td><xtag-total-run-finished>102</xtag-total-run-finished></td>
<td><xtag-total-run-started>114</xtag-total-run-started></td>
<td><xtag-total-run-finished>114</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -726,8 +726,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>95</xtag-total-run-started></td>
<td><xtag-total-run-finished>95</xtag-total-run-finished></td>
<td><xtag-total-run-started>107</xtag-total-run-started></td>
<td><xtag-total-run-finished>107</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -736,8 +736,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>95</xtag-total-run-started></td>
<td><xtag-total-run-finished>95</xtag-total-run-finished></td>
<td><xtag-total-run-started>107</xtag-total-run-started></td>
<td><xtag-total-run-finished>107</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -746,8 +746,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>200</xtag-total-run-started></td>
<td><xtag-total-run-finished>197</xtag-total-run-finished></td>
<td><xtag-total-run-started>211</xtag-total-run-started></td>
<td><xtag-total-run-finished>208</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -760,68 +760,68 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
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</BODY></HTML>

6
Examples/Beta1/logic/build/webtalk.log
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@ -3,8 +3,8 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=44f8cd23f23f4c7d956e087dfdda32fd
ProjectIteration=2
ProjectID=3e658027d9514d018043b63a2e613df7
ProjectIteration=9
WebTalk Summary
----------------
@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:5 - /home/erwin/sie-ceimtun/Examples/Beta1/logic/build/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at /home/erwin/Xilinxs/12.2/ISE_DS/ISE/data/reports/webtalk_introduction.html
INFO:WebTalk:5 - /home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at /home/erwin/Xilinxs/12.2/ISE_DS/ISE/data/reports/webtalk_introduction.html

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8
Examples/Beta1/logic/build/xst/work/hdllib.ref
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@ -1,4 +1,4 @@
MO PWM NULL ../PWM.v vlg50/_p_w_m.bin 1288481438
MO beta NULL ../beta.v vlg5C/beta.bin 1288481438
MO PuenteH NULL ../PuenteH.v vlg69/_puente_h.bin 1288481438
MO enco NULL ../enco.v vlg6D/enco.bin 1288481438
MO PWM NULL ../PWM.v vlg50/_p_w_m.bin 1288492397
MO beta NULL ../beta.v vlg5C/beta.bin 1288492397
MO PuenteH NULL ../PuenteH.v vlg69/_puente_h.bin 1288492397
MO enco NULL ../enco.v vlg6D/enco.bin 1288492397

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4
Examples/Beta1/logic/enco.v
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@ -17,7 +17,7 @@ wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ qua
wire count_direction = quadA_delayed[1] ^ quadB_delayed[2];
//Registro para almacenar el contador
reg [6:0] count=0; //Pendiente cambiar este, no sabemos que dato saldr al final
reg [7:0] count=0; //Pendiente cambiar este, no sabemos que dato saldr al final
always @(posedge clk)
begin
if(count_enable)
@ -53,7 +53,7 @@ pos_reg1<=pos_reg0;
end*/
//Fue cambiado!
assign vel_dir={1'b0,count[6:0]};
assign vel_dir={count[7:0]};
// Dual-port RAM instatiation
RAMB16_S9_S9 ba0(

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47
Examples/Beta1/src/UNROBOT_pwm_test.c
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@ -18,10 +18,15 @@ main ()
#endif
int i;
int pwm1=10; //PWM Led en SIE, entre 0 y 255
int pwm2=255; //PWM Led fuera SIE, entre 0 y 255
int pwm1=0xFF; //PWM Led en SIE, entre 0 y 255
int pwm2=0xFF; //PWM Led fuera SIE, entre 0 y 255
int pwm3=0xFF; //PWM Led en SIE, entre 0 y 255
int pwm4=0xFF; //PWM Led fuera SIE, entre 0 y 255
int dutycycle1; //PWM Led en SIE
int dutycycle2; //PWM Led fuera SIE
int dutycycle3; //PWM Led en SIE
int dutycycle4; //PWM Led fuera SIE
JZ_PIO *pio;
int *virt_addr;
@ -46,35 +51,41 @@ main ()
dutycycle1=(int)((float)((100.0/255.0)*pwm1));
dutycycle2=(int)((float)((100.0/255.0)*pwm2));
dutycycle3=(int)((float)((100.0/255.0)*pwm3));
dutycycle4=(int)((float)((100.0/255.0)*pwm4));
printf ("DUTY1:%d%% \n", dutycycle1);
printf ("DUTY2:%d%% \n", dutycycle2);
printf ("Setting PWM1..\n");
virt_addr[1024] = pwm1;
printf ("DUTY3:%d%% \n", dutycycle3);
printf ("DUTY4:%d%% \n", dutycycle4);
printf ("Setting PWM2..\n");
virt_addr[1536] = pwm2;
virt_addr[1537] = pwm2;
virt_addr[1535] = pwm2;
printf ("Setting PWM..\n");
virt_addr[1024] = pwm1+(pwm2<<8)+(pwm3<<16)+(pwm4<<24);//0xFFFFFFFF Cada dos digitos es un PWM
usleep (1000 * 1000);
printf ("Writing In Memory1 the Dutycycles and pwm references from 0x100 to 0x103..\n");
virt_addr[512] = pwm1;
virt_addr[513] = dutycycle1;
virt_addr[514] = pwm2;
virt_addr[515] = dutycycle2;
virt_addr[1536] = pwm1;
virt_addr[1537] = dutycycle1;
virt_addr[1538] = pwm2;
virt_addr[1539] = dutycycle2;
virt_addr[1540] = pwm3;
virt_addr[1541] = dutycycle3;
virt_addr[1542] = pwm4;
virt_addr[1543] = dutycycle4;
printf ("Reading from Memory1 the Dutycycles and pwm references..\n");
printf("1- PWM_REF:%d, Duty Cycle:%d%% \n", virt_addr[512], virt_addr[513]);
printf("2- PWM_REF:%d, Duty Cycle:%d%% \n", virt_addr[514], virt_addr[515]);
printf("1- PWM_REF:%d, Duty Cycle:%d%% \n", virt_addr[1536], virt_addr[1537]);
printf("2- PWM_REF:%d, Duty Cycle:%d%% \n", virt_addr[1538], virt_addr[1539]);
printf("1- PWM_REF:%d, Duty Cycle:%d%% \n", virt_addr[1540], virt_addr[1541]);
printf("2- PWM_REF:%d, Duty Cycle:%d%% \n", virt_addr[1542], virt_addr[1543]);
printf("1- Encoder:%d\n", virt_addr[0]);
printf("1- Encoder:%d\n", virt_addr[1]);
printf("1- Encoder1:%d\n", virt_addr[0]);
printf("1- Encoder2:%d\n", virt_addr[512]);
return 0;
}