diff --git a/Examples/Beta1/logic/beta.bit b/Examples/Beta1/logic/beta.bit
index cfa281b..a9bd9e8 100644
Binary files a/Examples/Beta1/logic/beta.bit and b/Examples/Beta1/logic/beta.bit differ
diff --git a/Examples/Beta1/logic/beta.ucf b/Examples/Beta1/logic/beta.ucf
index 6756123..785e425 100644
--- a/Examples/Beta1/logic/beta.ucf
+++ b/Examples/Beta1/logic/beta.ucf
@@ -7,11 +7,20 @@ NET reset LOC = "P30"; #WARNING change to another pin
#NET OD3 LOC = "P63";
NET quadA LOC = "P67";
NET quadB LOC = "P68";
+NET quadC LOC = "P70";
+NET quadD LOC = "P71";
+NET quadA LOC = "P36"; #PINES DE PRUEBA
+NET quadB LOC = "P35"; #PINES DE PRUEBA
+NET quadC LOC = "P34"; #PINES DE PRUEBA
+NET quadD LOC = "P33"; #PINES DE PRUEBA
NET "hbridge<3>" LOC = "P53";
NET "hbridge<2>" LOC = "P54";
NET "hbridge<1>" LOC = "P49";
NET "hbridge<0>" LOC = "P48";
-
+#NET "hbridge<3>" LOC = "P71";#PINES DE PRUEBA
+#NET "hbridge<2>" LOC = "P70"; #PINES DE PRUEBA
+#NET "hbridge<1>" LOC = "P68"; #PINES DE PRUEBA
+#NET "hbridge<0>" LOC = "P66"; #PINES DE PRUEBA
#ADDRESS BUS
NET "addr<12>" LOC = "P90";
diff --git a/Examples/Beta1/logic/beta.v b/Examples/Beta1/logic/beta.v
index 286ffd9..98f37af 100644
--- a/Examples/Beta1/logic/beta.v
+++ b/Examples/Beta1/logic/beta.v
@@ -2,7 +2,7 @@
/*module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART, led2);
*/
-module beta(clk, sram_data, quadA, quadB, addr, nwe, ncs, noe, reset, hbridge);
+module beta(clk, sram_data, quadA, quadB, quadC, quadD, addr, nwe, ncs, noe, reset, hbridge);
parameter B = (7);
@@ -12,7 +12,7 @@ module beta(clk, sram_data, quadA, quadB, addr, nwe, ncs, noe, reset, hbridge);
// inout ADC_SDIN, ADC_SDOUT;
input clk, addr, nwe, ncs, noe, reset;
output [3:0] hbridge;
-input quadA,quadB;
+input quadA,quadB, quadC, quadD;
// External conection
//wire led, led2;
@@ -110,16 +110,15 @@ enco enco1(
.buffer_addr(buffer_addr[10:0])
);
- RAMB16_S9 ba0( .CLK(~clk),
- .EN(csN[1]),
- .DOP(),
- .SSR(1'b0),
- .ADDR(buffer_addr[10:0]),
- .WE(we),
- .DI(wrBus),
- .DIP(1'b0),
- .DO(rdBus1));
-
+enco enco2(
+ .clk(clk),
+ .enable(csN[1]),
+ .quadA(quadC),
+ .quadB(quadD),
+ .out(rdBus1),
+ .buffer_addr(buffer_addr[10:0])
+ );
+
PuenteH puente (
.clk(clk),
.reset(~reset),
@@ -131,7 +130,15 @@ PuenteH puente (
.ram_read(rdBus2)
);
-
+ RAMB16_S9 ba0( .CLK(~clk),
+ .EN(csN[3]),
+ .DOP(),
+ .SSR(1'b0),
+ .ADDR(buffer_addr[10:0]),
+ .WE(we),
+ .DI(wrBus),
+ .DIP(1'b0),
+ .DO(rdBus3));
endmodule
diff --git a/Examples/Beta1/logic/build/_xmsgs/bitgen.xmsgs b/Examples/Beta1/logic/build/_xmsgs/bitgen.xmsgs
index 07b3041..bf3b095 100644
--- a/Examples/Beta1/logic/build/_xmsgs/bitgen.xmsgs
+++ b/Examples/Beta1/logic/build/_xmsgs/bitgen.xmsgs
@@ -5,7 +5,7 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-Spartan-3E devices do not support bitstream readback of the Blockram resources in the -4C speedgrade. If Blockram readback functionality is desired, it is suggested to target the -5C or -4I speedgrades.
+Spartan-3E devices do not support bitstream readback of the Blockram resources in the -4C speedgrade. If Blockram readback functionality is desired, it is suggested to target the -5C or -4I speedgrades.
diff --git a/Examples/Beta1/logic/build/_xmsgs/map.xmsgs b/Examples/Beta1/logic/build/_xmsgs/map.xmsgs
index fe94612..e5fea32 100644
--- a/Examples/Beta1/logic/build/_xmsgs/map.xmsgs
+++ b/Examples/Beta1/logic/build/_xmsgs/map.xmsgs
@@ -5,10 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-No environment variables are currently set.
+No environment variables are currently set.
-All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
+All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
diff --git a/Examples/Beta1/logic/build/_xmsgs/par.xmsgs b/Examples/Beta1/logic/build/_xmsgs/par.xmsgs
index 6a5a463..cf259f4 100644
--- a/Examples/Beta1/logic/build/_xmsgs/par.xmsgs
+++ b/Examples/Beta1/logic/build/_xmsgs/par.xmsgs
@@ -5,12 +5,12 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
+No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
-N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
+N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
-N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
+N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
diff --git a/Examples/Beta1/logic/build/_xmsgs/trce.xmsgs b/Examples/Beta1/logic/build/_xmsgs/trce.xmsgs
index d870781..332d17a 100644
--- a/Examples/Beta1/logic/build/_xmsgs/trce.xmsgs
+++ b/Examples/Beta1/logic/build/_xmsgs/trce.xmsgs
@@ -5,15 +5,15 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-No timing constraints found, doing default enumeration.
+No timing constraints found, doing default enumeration.
-To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.
+To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.
-The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.
+The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.
-This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.
+This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.
-This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.
+This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.
diff --git a/Examples/Beta1/logic/build/_xmsgs/xst.xmsgs b/Examples/Beta1/logic/build/_xmsgs/xst.xmsgs
index 1c2dcad..8e79694 100644
--- a/Examples/Beta1/logic/build/_xmsgs/xst.xmsgs
+++ b/Examples/Beta1/logic/build/_xmsgs/xst.xmsgs
@@ -5,13 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-"../enco.v" line 65 Connection to input port 'ADDRB' does not match port size
+"../enco.v" line 65 Connection to input port 'ADDRB' does not match port size
-Signal <rdBus3> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
-
-
-Signal <csN<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+"../enco.v" line 65 Connection to input port 'ADDRB' does not match port size
diff --git a/Examples/Beta1/logic/build/beta_map.xrpt b/Examples/Beta1/logic/build/beta_map.xrpt
index c68bf33..634c37a 100644
--- a/Examples/Beta1/logic/build/beta_map.xrpt
+++ b/Examples/Beta1/logic/build/beta_map.xrpt
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-
+
@@ -53,12 +53,12 @@
+
+
+
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
diff --git a/Examples/Beta1/logic/build/beta_par.xrpt b/Examples/Beta1/logic/build/beta_par.xrpt
index d3d45cf..3a582fa 100644
--- a/Examples/Beta1/logic/build/beta_par.xrpt
+++ b/Examples/Beta1/logic/build/beta_par.xrpt
@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-
+
@@ -47,12 +47,12 @@
@@ -71,8 +71,8 @@
@@ -386,31 +386,55 @@
@@ -680,17 +676,33 @@