Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.2 (WebPack) - M.63c Target Family: Spartan3E
OS Platform: LIN64 Target Device: xc3s500e
Project ID (random number) c2aacd1c16a742efb7b16ebde1b15f3a.44f8cd23f23f4c7d956e087dfdda32fd.1 Target Package: vq100
Registration ID 0_0_674 Target Speed: -4
Date Generated 2010-10-30T18:31:27 Tool Flow CommandLine
 
User Environment
OS Name unknown OS Release unknown
CPU Name Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz CPU Speed 2201.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=32
  • AGG_IO=32
  • AGG_SLICE=112
  • NUM_4_INPUT_LUT=130
  • NUM_BONDED_IBUF=20
  • NUM_BONDED_IOB=12
  • NUM_BUFGMUX=1
  • NUM_CYMUX=60
  • NUM_IOB_FF=25
  • NUM_LUT_RT=28
  • NUM_RAMB16=3
  • NUM_SLICEL=112
  • NUM_SLICE_FF=118
  • NUM_XOR=32
 		NetStatistics
  • NumNets_Active=280
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=33
  • NumNodesOfType_Active_BRAMDUMMY=52
  • NumNodesOfType_Active_CLKPIN=90
  • NumNodesOfType_Active_CNTRLPIN=68
  • NumNodesOfType_Active_DOUBLE=634
  • NumNodesOfType_Active_DUMMY=353
  • NumNodesOfType_Active_DUMMYBANK=42
  • NumNodesOfType_Active_DUMMYESC=4
  • NumNodesOfType_Active_GLOBAL=51
  • NumNodesOfType_Active_HFULLHEX=11
  • NumNodesOfType_Active_HLONG=4
  • NumNodesOfType_Active_HUNIHEX=68
  • NumNodesOfType_Active_INPUT=546
  • NumNodesOfType_Active_IOBOUTPUT=29
  • NumNodesOfType_Active_OMUX=263
  • NumNodesOfType_Active_OUTPUT=199
  • NumNodesOfType_Active_PREBXBY=235
  • NumNodesOfType_Active_VFULLHEX=37
  • NumNodesOfType_Active_VLONG=5
  • NumNodesOfType_Active_VUNIHEX=65
  • NumNodesOfType_Gnd_BRAMADDR=11
  • NumNodesOfType_Gnd_BRAMDUMMY=9
  • NumNodesOfType_Gnd_DOUBLE=8
  • NumNodesOfType_Gnd_DUMMYBANK=5
  • NumNodesOfType_Gnd_INPUT=24
  • NumNodesOfType_Gnd_OMUX=8
  • NumNodesOfType_Gnd_OUTPUT=7
  • NumNodesOfType_Gnd_PREBXBY=4
  • NumNodesOfType_Gnd_VFULLHEX=1
  • NumNodesOfType_Vcc_BRAMDUMMY=2
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=7
  • NumNodesOfType_Vcc_PREBXBY=5
  • NumNodesOfType_Vcc_VCCOUT=7
 SiteStatistics
  • IBUF-DIFFM=8
  • IBUF-DIFFMI=2
  • IBUF-DIFFS=7
  • IBUF-DIFFSI=1
  • IBUF-IOB=1
  • IOB-DIFFM=6
  • IOB-DIFFS=6
  • SLICEL-SLICEM=42
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=20
  • IBUF_IFD_DELAY=17
  • IBUF_IFF1=17
  • IBUF_INBUF=20
  • IBUF_PAD=20
  • IOB=12
  • IOB_IFD_DELAY=8
  • IOB_IFF1=8
  • IOB_INBUF=8
  • IOB_OUTBUF=12
  • IOB_PAD=12
  • RAMB16=3
  • RAMB16_RAMB16=3
  • RAMB16_RAMB16A=3
  • RAMB16_RAMB16B=1
  • SLICEL=112
  • SLICEL_C1VDD=4
  • SLICEL_CYMUXF=32
  • SLICEL_CYMUXG=28
  • SLICEL_F=70
  • SLICEL_F5MUX=10
  • SLICEL_FFX=59
  • SLICEL_FFY=59
  • SLICEL_G=60
  • SLICEL_GNDF=12
  • SLICEL_GNDG=12
  • SLICEL_XORF=16
  • SLICEL_XORG=16
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF
  • ICLK1=[ICLK1_INV:15] [ICLK1:2]
 IBUF_IFF1
  • CK=[CK:2] [CK_INV:15]
  • IFF1_INIT_ATTR=[INIT0:17]
  • LATCH_OR_FF=[FF:17]
 IBUF_INBUF
  • IFD_DELAY_VALUE=[DLY3:17]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:20]
 IOB
  • ICLK1=[ICLK1_INV:8] [ICLK1:0]
  • O1=[O1_INV:4] [O1:8]
  • T1=[T1_INV:0] [T1:8]
 IOB_IFF1
  • CK=[CK:0] [CK_INV:8]
  • IFF1_INIT_ATTR=[INIT0:8]
  • LATCH_OR_FF=[FF:8]
 IOB_INBUF
  • IFD_DELAY_VALUE=[DLY3:8]
 IOB_OUTBUF
  • IN=[IN_INV:4] [IN:8]
  • TRI=[TRI_INV:0] [TRI:8]
 IOB_PAD
  • DRIVEATTRBOX=[12:12]
  • IOATTRBOX=[LVCMOS25:12]
  • SLEW=[SLOW:12]
 RAMB16
  • CLKA=[CLKA_INV:3] [CLKA:0]
  • CLKB=[CLKB_INV:1] [CLKB:0]
  • ENA=[ENA_INV:0] [ENA:3]
  • ENB=[ENB_INV:0] [ENB:1]
  • SSRA=[SSRA_INV:0] [SSRA:3]
  • SSRB=[SSRB_INV:0] [SSRB:1]
  • WEA=[WEA:3] [WEA_INV:0]
  • WEB=[WEB:1] [WEB_INV:0]
 RAMB16_RAMB16A
  • CLKA=[CLKA_INV:3] [CLKA:0]
  • ENA=[ENA_INV:0] [ENA:3]
  • PORTA_ATTR=[2048X9:3]
  • SSRA=[SSRA_INV:0] [SSRA:3]
  • WEA=[WEA:3] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:3]
 RAMB16_RAMB16B
  • CLKB=[CLKB_INV:1] [CLKB:0]
  • ENB=[ENB_INV:0] [ENB:1]
  • PORTB_ATTR=[2048X9:1]
  • SSRB=[SSRB_INV:0] [SSRB:1]
  • WEB=[WEB:1] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:1]
 SLICEL
  • BX=[BX_INV:1] [BX:56]
  • BY=[BY:39] [BY_INV:0]
  • CE=[CE:22] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:24]
  • CLK=[CLK:44] [CLK_INV:17]
  • SR=[SR:17] [SR_INV:21]
 SLICEL_CYMUXF
  • 0=[0:32] [0_INV:0]
  • 1=[1_INV:0] [1:32]
 SLICEL_CYMUXG
  • 0=[0:28] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:10] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:20] [CE_INV:0]
  • CK=[CK:43] [CK_INV:16]
  • D=[D:58] [D_INV:1]
  • FFX_INIT_ATTR=[INIT0:59]
  • FFX_SR_ATTR=[SRLOW:59]
  • LATCH_OR_FF=[FF:59]
  • SR=[SR:16] [SR_INV:21]
  • SYNC_ATTR=[ASYNC:22] [SYNC:37]
 SLICEL_FFY
  • CE=[CE:20] [CE_INV:0]
  • CK=[CK:42] [CK_INV:17]
  • D=[D:59] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:59]
  • FFY_SR_ATTR=[SRLOW:59]
  • LATCH_OR_FF=[FF:59]
  • SR=[SR:17] [SR_INV:21]
  • SYNC_ATTR=[ASYNC:21] [SYNC:38]
 SLICEL_XORF
  • 1=[1_INV:0] [1:16]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=4
  • ICLK1=17
  • IQ1=17
  • PAD=20
 IBUF_IFD_DELAY
  • IN=17
  • OUT=17
 IBUF_IFF1
  • CK=17
  • D=17
  • Q=17
 IBUF_INBUF
  • IN=20
  • OUT=20
 IBUF_PAD
  • PAD=20
 IOB
  • ICLK1=8
  • IQ1=8
  • O1=12
  • PAD=12
  • T1=8
 IOB_IFD_DELAY
  • IN=8
  • OUT=8
 IOB_IFF1
  • CK=8
  • D=8
  • Q=8
 IOB_INBUF
  • IN=8
  • OUT=8
 IOB_OUTBUF
  • IN=12
  • OUT=12
  • TRI=8
 IOB_PAD
  • PAD=12
 RAMB16
  • ADDRA10=3
  • ADDRA11=3
  • ADDRA12=3
  • ADDRA13=3
  • ADDRA3=3
  • ADDRA4=3
  • ADDRA5=3
  • ADDRA6=3
  • ADDRA7=3
  • ADDRA8=3
  • ADDRA9=3
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=3
  • CLKB=1
  • DIA0=2
  • DIA1=2
  • DIA2=2
  • DIA3=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIB0=1
  • DIB1=1
  • DIB2=1
  • DIB3=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIPA0=2
  • DIPB0=1
  • DOA0=3
  • DOA1=3
  • DOA2=3
  • DOA3=3
  • DOA4=3
  • DOA5=3
  • DOA6=3
  • DOA7=3
  • ENA=3
  • ENB=1
  • SSRA=3
  • SSRB=1
  • WEA=3
  • WEB=1
 RAMB16_RAMB16
  • ADDRA=3
  • ADDRB=1
  • DIA=3
  • DIB=1
  • DOA=3
  • DOB=1
 RAMB16_RAMB16A
  • ADDRA=3
  • ADDRA10=3
  • ADDRA11=3
  • ADDRA12=3
  • ADDRA13=3
  • ADDRA3=3
  • ADDRA4=3
  • ADDRA5=3
  • ADDRA6=3
  • ADDRA7=3
  • ADDRA8=3
  • ADDRA9=3
  • CLKA=3
  • DIA=3
  • DIA0=2
  • DIA1=2
  • DIA2=2
  • DIA3=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIPA0=2
  • DOA=3
  • DOA0=3
  • DOA1=3
  • DOA2=3
  • DOA3=3
  • DOA4=3
  • DOA5=3
  • DOA6=3
  • DOA7=3
  • ENA=3
  • SSRA=3
  • WEA=3
 RAMB16_RAMB16B
  • ADDRB=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKB=1
  • DIB=1
  • DIB0=1
  • DIB1=1
  • DIB2=1
  • DIB3=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIPB0=1
  • DOB=1
  • ENB=1
  • SSRB=1
  • WEB=1
 SLICEL
  • BX=57
  • BY=39
  • CE=22
  • CIN=24
  • CLK=61
  • COUT=28
  • F1=68
  • F2=52
  • F3=33
  • F4=32
  • G1=60
  • G2=44
  • G3=25
  • G4=23
  • SR=38
  • X=34
  • XQ=59
  • Y=14
  • YQ=59
 SLICEL_C1VDD
  • 1=4
 SLICEL_CYMUXF
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
 SLICEL_CYMUXG
  • 0=28
  • 1=28
  • OUT=28
  • S0=28
 SLICEL_F
  • A1=68
  • A2=52
  • A3=33
  • A4=32
  • D=70
 SLICEL_F5MUX
  • F=10
  • G=10
  • OUT=10
  • S0=10
 SLICEL_FFX
  • CE=20
  • CK=59
  • D=59
  • Q=59
  • SR=37
 SLICEL_FFY
  • CE=20
  • CK=59
  • D=59
  • Q=59
  • SR=38
 SLICEL_G
  • A1=60
  • A2=44
  • A3=25
  • A4=23
  • D=60
 SLICEL_GNDF
  • 0=12
 SLICEL_GNDG
  • 0=12
 SLICEL_XORF
  • 0=16
  • 1=16
  • O=16
 SLICEL_XORG
  • 0=16
  • 1=16
  • O=16
 
Software Quality
Run Statistics
bitgen 82 82 0 0 0 0 0
map 98 96 0 0 0 0 0
ngdbuild 102 102 0 0 0 0 0
par 95 95 0 0 0 0 0
trce 95 95 0 0 0 0 0
xst 200 197 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=38 NGDBUILD_NUM_FDE=7 NGDBUILD_NUM_FDR=42
NGDBUILD_NUM_FDRE_1=33 NGDBUILD_NUM_FD_1=23 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=19
NGDBUILD_NUM_INV=11 NGDBUILD_NUM_IOBUF=8 NGDBUILD_NUM_LUT1=28 NGDBUILD_NUM_LUT2=38
NGDBUILD_NUM_LUT3=3 NGDBUILD_NUM_LUT4=55 NGDBUILD_NUM_MUXCY=60 NGDBUILD_NUM_MUXF5=10
NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_RAMB16_S9=2 NGDBUILD_NUM_RAMB16_S9_S9=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=32
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=38 NGDBUILD_NUM_FDE=7 NGDBUILD_NUM_FDR=42
NGDBUILD_NUM_FDRE_1=33 NGDBUILD_NUM_FD_1=23 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=27
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=11 NGDBUILD_NUM_LUT1=28 NGDBUILD_NUM_LUT2=38
NGDBUILD_NUM_LUT3=3 NGDBUILD_NUM_LUT4=55 NGDBUILD_NUM_MUXCY=60 NGDBUILD_NUM_MUXF5=10
NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_OBUFT=8 NGDBUILD_NUM_RAMB16_S9=2 NGDBUILD_NUM_RAMB16_S9_S9=1
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=32