Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.2 (WebPack) - M.63c Target Family: Spartan3E
OS Platform: LIN64 Target Device: xc3s500e
Project ID (random number) c2aacd1c16a742efb7b16ebde1b15f3a.3e658027d9514d018043b63a2e613df7.8 Target Package: vq100
Registration ID 0_0_674 Target Speed: -4
Date Generated 2010-10-30T21:34:13 Tool Flow CommandLine
 
User Environment
OS Name unknown OS Release unknown
CPU Name Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz CPU Speed 2201.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=34
  • AGG_IO=34
  • AGG_SLICE=118
  • NUM_4_INPUT_LUT=140
  • NUM_BONDED_IBUF=22
  • NUM_BONDED_IOB=12
  • NUM_BUFGMUX=1
  • NUM_CYMUX=74
  • NUM_IOB_FF=27
  • NUM_LUT_RT=28
  • NUM_RAMB16=4
  • NUM_SLICEL=118
  • NUM_SLICE_FF=131
  • NUM_XOR=48
 		NetStatistics
  • NumNets_Active=311
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=44
  • NumNodesOfType_Active_BRAMDUMMY=70
  • NumNodesOfType_Active_CLKPIN=99
  • NumNodesOfType_Active_CNTRLPIN=71
  • NumNodesOfType_Active_DOUBLE=679
  • NumNodesOfType_Active_DUMMY=359
  • NumNodesOfType_Active_DUMMYBANK=51
  • NumNodesOfType_Active_DUMMYESC=4
  • NumNodesOfType_Active_GLOBAL=54
  • NumNodesOfType_Active_HFULLHEX=18
  • NumNodesOfType_Active_HLONG=5
  • NumNodesOfType_Active_HUNIHEX=85
  • NumNodesOfType_Active_INPUT=590
  • NumNodesOfType_Active_IOBOUTPUT=31
  • NumNodesOfType_Active_OMUX=281
  • NumNodesOfType_Active_OUTPUT=218
  • NumNodesOfType_Active_PREBXBY=210
  • NumNodesOfType_Active_VFULLHEX=43
  • NumNodesOfType_Active_VLONG=6
  • NumNodesOfType_Active_VUNIHEX=85
  • NumNodesOfType_Gnd_BRAMADDR=22
  • NumNodesOfType_Gnd_BRAMDUMMY=12
  • NumNodesOfType_Gnd_DOUBLE=15
  • NumNodesOfType_Gnd_DUMMYBANK=7
  • NumNodesOfType_Gnd_INPUT=38
  • NumNodesOfType_Gnd_OMUX=16
  • NumNodesOfType_Gnd_OUTPUT=9
  • NumNodesOfType_Gnd_PREBXBY=5
  • NumNodesOfType_Gnd_VFULLHEX=1
  • NumNodesOfType_Vcc_BRAMDUMMY=4
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=9
  • NumNodesOfType_Vcc_PREBXBY=5
  • NumNodesOfType_Vcc_VCCOUT=8
 SiteStatistics
  • IBUF-DIFFM=8
  • IBUF-DIFFMI=2
  • IBUF-DIFFS=8
  • IBUF-DIFFSI=1
  • IBUF-IOB=2
  • IOB-DIFFM=5
  • IOB-DIFFS=7
  • SLICEL-SLICEM=43
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=22
  • IBUF_IFD_DELAY=19
  • IBUF_IFF1=19
  • IBUF_INBUF=22
  • IBUF_PAD=22
  • IOB=12
  • IOB_IFD_DELAY=8
  • IOB_IFF1=8
  • IOB_INBUF=8
  • IOB_OUTBUF=12
  • IOB_PAD=12
  • RAMB16=4
  • RAMB16_RAMB16=4
  • RAMB16_RAMB16A=4
  • RAMB16_RAMB16B=2
  • SLICEL=118
  • SLICEL_C1VDD=4
  • SLICEL_CYMUXF=40
  • SLICEL_CYMUXG=34
  • SLICEL_F=76
  • SLICEL_F5MUX=10
  • SLICEL_FFX=65
  • SLICEL_FFY=66
  • SLICEL_G=64
  • SLICEL_GNDF=12
  • SLICEL_GNDG=12
  • SLICEL_XORF=24
  • SLICEL_XORG=24
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF
  • ICLK1=[ICLK1_INV:15] [ICLK1:4]
 IBUF_IFF1
  • CK=[CK:4] [CK_INV:15]
  • IFF1_INIT_ATTR=[INIT0:19]
  • LATCH_OR_FF=[FF:19]
 IBUF_INBUF
  • IFD_DELAY_VALUE=[DLY3:19]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:22]
 IOB
  • ICLK1=[ICLK1_INV:8] [ICLK1:0]
  • O1=[O1_INV:4] [O1:8]
  • T1=[T1_INV:0] [T1:8]
 IOB_IFF1
  • CK=[CK:0] [CK_INV:8]
  • IFF1_INIT_ATTR=[INIT0:8]
  • LATCH_OR_FF=[FF:8]
 IOB_INBUF
  • IFD_DELAY_VALUE=[DLY3:8]
 IOB_OUTBUF
  • IN=[IN_INV:4] [IN:8]
  • TRI=[TRI_INV:0] [TRI:8]
 IOB_PAD
  • DRIVEATTRBOX=[12:12]
  • IOATTRBOX=[LVCMOS25:12]
  • SLEW=[SLOW:12]
 RAMB16
  • CLKA=[CLKA_INV:4] [CLKA:0]
  • CLKB=[CLKB_INV:2] [CLKB:0]
  • ENA=[ENA_INV:0] [ENA:4]
  • ENB=[ENB_INV:0] [ENB:2]
  • SSRA=[SSRA_INV:0] [SSRA:4]
  • SSRB=[SSRB_INV:0] [SSRB:2]
  • WEA=[WEA:4] [WEA_INV:0]
  • WEB=[WEB:2] [WEB_INV:0]
 RAMB16_RAMB16A
  • CLKA=[CLKA_INV:4] [CLKA:0]
  • ENA=[ENA_INV:0] [ENA:4]
  • PORTA_ATTR=[2048X9:4]
  • SSRA=[SSRA_INV:0] [SSRA:4]
  • WEA=[WEA:4] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:4]
 RAMB16_RAMB16B
  • CLKB=[CLKB_INV:2] [CLKB:0]
  • ENB=[ENB_INV:0] [ENB:2]
  • PORTB_ATTR=[2048X9:2]
  • SSRB=[SSRB_INV:0] [SSRB:2]
  • WEB=[WEB:2] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:2]
 SLICEL
  • BX=[BX_INV:0] [BX:60]
  • BY=[BY:41] [BY_INV:0]
  • CE=[CE:25] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:30]
  • CLK=[CLK:49] [CLK_INV:17]
  • SR=[SR:17] [SR_INV:21]
 SLICEL_CYMUXF
  • 0=[0:40] [0_INV:0]
  • 1=[1_INV:0] [1:40]
 SLICEL_CYMUXG
  • 0=[0:34] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:10] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:24] [CE_INV:0]
  • CK=[CK:49] [CK_INV:16]
  • D=[D:65] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:65]
  • FFX_SR_ATTR=[SRLOW:65]
  • LATCH_OR_FF=[FF:65]
  • SR=[SR:16] [SR_INV:21]
  • SYNC_ATTR=[ASYNC:28] [SYNC:37]
 SLICEL_FFY
  • CE=[CE:25] [CE_INV:0]
  • CK=[CK:49] [CK_INV:17]
  • D=[D:66] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:66]
  • FFY_SR_ATTR=[SRLOW:66]
  • LATCH_OR_FF=[FF:66]
  • SR=[SR:17] [SR_INV:21]
  • SYNC_ATTR=[ASYNC:28] [SYNC:38]
 SLICEL_XORF
  • 1=[1_INV:0] [1:24]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=4
  • ICLK1=19
  • IQ1=19
  • PAD=22
 IBUF_IFD_DELAY
  • IN=19
  • OUT=19
 IBUF_IFF1
  • CK=19
  • D=19
  • Q=19
 IBUF_INBUF
  • IN=22
  • OUT=22
 IBUF_PAD
  • PAD=22
 IOB
  • ICLK1=8
  • IQ1=8
  • O1=12
  • PAD=12
  • T1=8
 IOB_IFD_DELAY
  • IN=8
  • OUT=8
 IOB_IFF1
  • CK=8
  • D=8
  • Q=8
 IOB_INBUF
  • IN=8
  • OUT=8
 IOB_OUTBUF
  • IN=12
  • OUT=12
  • TRI=8
 IOB_PAD
  • PAD=12
 RAMB16
  • ADDRA10=4
  • ADDRA11=4
  • ADDRA12=4
  • ADDRA13=4
  • ADDRA3=4
  • ADDRA4=4
  • ADDRA5=4
  • ADDRA6=4
  • ADDRA7=4
  • ADDRA8=4
  • ADDRA9=4
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=4
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA2=2
  • DIA3=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIB0=2
  • DIB1=2
  • DIB2=2
  • DIB3=2
  • DIB4=2
  • DIB5=2
  • DIB6=2
  • DIB7=2
  • DIPA0=2
  • DIPB0=2
  • DOA0=4
  • DOA1=4
  • DOA2=4
  • DOA3=4
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • ENA=4
  • ENB=2
  • SSRA=4
  • SSRB=2
  • WEA=4
  • WEB=2
 RAMB16_RAMB16
  • ADDRA=4
  • ADDRB=2
  • DIA=4
  • DIB=2
  • DOA=4
  • DOB=2
 RAMB16_RAMB16A
  • ADDRA=4
  • ADDRA10=4
  • ADDRA11=4
  • ADDRA12=4
  • ADDRA13=4
  • ADDRA3=4
  • ADDRA4=4
  • ADDRA5=4
  • ADDRA6=4
  • ADDRA7=4
  • ADDRA8=4
  • ADDRA9=4
  • CLKA=4
  • DIA=4
  • DIA0=2
  • DIA1=2
  • DIA2=2
  • DIA3=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIPA0=2
  • DOA=4
  • DOA0=4
  • DOA1=4
  • DOA2=4
  • DOA3=4
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • ENA=4
  • SSRA=4
  • WEA=4
 RAMB16_RAMB16B
  • ADDRB=2
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKB=2
  • DIB=2
  • DIB0=2
  • DIB1=2
  • DIB2=2
  • DIB3=2
  • DIB4=2
  • DIB5=2
  • DIB6=2
  • DIB7=2
  • DIPB0=2
  • DOB=2
  • ENB=2
  • SSRB=2
  • WEB=2
 SLICEL
  • BX=60
  • BY=41
  • CE=25
  • CIN=30
  • CLK=66
  • COUT=34
  • F1=74
  • F2=58
  • F3=37
  • F4=20
  • G1=64
  • G2=48
  • G3=29
  • G4=11
  • SR=38
  • X=35
  • XQ=65
  • Y=13
  • YQ=66
 SLICEL_C1VDD
  • 1=4
 SLICEL_CYMUXF
  • 0=40
  • 1=40
  • OUT=40
  • S0=40
 SLICEL_CYMUXG
  • 0=34
  • 1=34
  • OUT=34
  • S0=34
 SLICEL_F
  • A1=74
  • A2=58
  • A3=37
  • A4=20
  • D=76
 SLICEL_F5MUX
  • F=10
  • G=10
  • OUT=10
  • S0=10
 SLICEL_FFX
  • CE=24
  • CK=65
  • D=65
  • Q=65
  • SR=37
 SLICEL_FFY
  • CE=25
  • CK=66
  • D=66
  • Q=66
  • SR=38
 SLICEL_G
  • A1=64
  • A2=48
  • A3=29
  • A4=11
  • D=64
 SLICEL_GNDF
  • 0=12
 SLICEL_GNDG
  • 0=12
 SLICEL_XORF
  • 0=24
  • 1=24
  • O=24
 SLICEL_XORG
  • 0=24
  • 1=24
  • O=24
 
Software Quality
Run Statistics
bitgen 90 90 0 0 0 0 0
map 110 108 0 0 0 0 0
ngdbuild 114 114 0 0 0 0 0
par 107 107 0 0 0 0 0
trce 107 107 0 0 0 0 0
xst 211 208 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=44 NGDBUILD_NUM_FDE=16 NGDBUILD_NUM_FDR=42
NGDBUILD_NUM_FDRE_1=33 NGDBUILD_NUM_FD_1=23 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=21
NGDBUILD_NUM_INV=10 NGDBUILD_NUM_IOBUF=8 NGDBUILD_NUM_LUT1=28 NGDBUILD_NUM_LUT2=40
NGDBUILD_NUM_LUT3=35 NGDBUILD_NUM_LUT4=31 NGDBUILD_NUM_MUXCY=74 NGDBUILD_NUM_MUXF5=10
NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_RAMB16_S9=2 NGDBUILD_NUM_RAMB16_S9_S9=2 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=48
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=44 NGDBUILD_NUM_FDE=16 NGDBUILD_NUM_FDR=42
NGDBUILD_NUM_FDRE_1=33 NGDBUILD_NUM_FD_1=23 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=29
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=10 NGDBUILD_NUM_LUT1=28 NGDBUILD_NUM_LUT2=40
NGDBUILD_NUM_LUT3=35 NGDBUILD_NUM_LUT4=31 NGDBUILD_NUM_MUXCY=74 NGDBUILD_NUM_MUXF5=10
NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_OBUFT=8 NGDBUILD_NUM_RAMB16_S9=2 NGDBUILD_NUM_RAMB16_S9_S9=2
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=48