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142 lines
6.6 KiB
Plaintext
142 lines
6.6 KiB
Plaintext
--------------------------------------------------------------------------------
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Release 12.2 Trace (lin64)
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Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
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/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 25
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project_r.ncd project.pcf
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Design file: project_r.ncd
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Physical constraint file: project.pcf
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Device,package,speed: xc3s500e,vq100,-4 (PRODUCTION 1.27 2010-06-22)
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Report level: verbose report, limited to 25 items per constraint
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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INFO:Timing:3390 - This architecture does not support a default System Jitter
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value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
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Uncertainty calculation.
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INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
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'Phase Error' calculations, these terms will be zero in the Clock
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Uncertainty calculation. Please make appropriate modification to
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SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
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Error.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Setup/Hold to clock clk
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------------+------------+------------+------------------+--------+
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|Max Setup to|Max Hold to | | Clock |
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Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
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------------+------------+------------+------------------+--------+
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addr<0> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
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addr<1> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
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addr<2> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
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addr<3> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
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addr<4> | 4.648(F)| -0.771(F)|clk_BUFGP | 0.000|
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addr<5> | 4.648(F)| -0.771(F)|clk_BUFGP | 0.000|
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addr<6> | 4.650(F)| -0.772(F)|clk_BUFGP | 0.000|
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addr<7> | 4.693(F)| -0.823(F)|clk_BUFGP | 0.000|
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addr<8> | 4.693(F)| -0.823(F)|clk_BUFGP | 0.000|
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addr<9> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
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addr<10> | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
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addr<11> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
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addr<12> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
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ncs | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
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nwe | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
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quadA | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
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quadB | 4.665(R)| -0.790(R)|clk_BUFGP | 0.000|
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quadC | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
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quadD | 4.663(R)| -0.788(R)|clk_BUFGP | 0.000|
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reset | 3.336(R)| -0.369(R)|clk_BUFGP | 0.000|
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| 4.315(F)| -0.589(F)|clk_BUFGP | 0.000|
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sram_data<0>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
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sram_data<1>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
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sram_data<2>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
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sram_data<3>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
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sram_data<4>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
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sram_data<5>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
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sram_data<6>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
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sram_data<7>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
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------------+------------+------------+------------------+--------+
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Clock clk to Pad
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------------+------------+------------------+--------+
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| clk (edge) | | Clock |
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Destination | to PAD |Internal Clock(s) | Phase |
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------------+------------+------------------+--------+
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hbridge<0> | 12.564(R)|clk_BUFGP | 0.000|
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| 12.481(F)|clk_BUFGP | 0.000|
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hbridge<1> | 12.901(R)|clk_BUFGP | 0.000|
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| 12.921(F)|clk_BUFGP | 0.000|
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hbridge<2> | 12.713(R)|clk_BUFGP | 0.000|
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| 12.377(F)|clk_BUFGP | 0.000|
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hbridge<3> | 13.541(R)|clk_BUFGP | 0.000|
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| 13.383(F)|clk_BUFGP | 0.000|
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sram_data<0>| 13.296(F)|clk_BUFGP | 0.000|
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sram_data<1>| 13.038(F)|clk_BUFGP | 0.000|
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sram_data<2>| 12.986(F)|clk_BUFGP | 0.000|
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sram_data<3>| 13.246(F)|clk_BUFGP | 0.000|
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sram_data<4>| 13.147(F)|clk_BUFGP | 0.000|
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sram_data<5>| 12.926(F)|clk_BUFGP | 0.000|
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sram_data<6>| 13.450(F)|clk_BUFGP | 0.000|
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sram_data<7>| 13.381(F)|clk_BUFGP | 0.000|
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------------+------------+------------------+--------+
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Clock to Setup on destination clock clk
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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clk | 6.132| 4.553| 3.790| 9.078|
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---------------+---------+---------+---------+---------+
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Pad to Pad
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---------------+---------------+---------+
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Source Pad |Destination Pad| Delay |
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---------------+---------------+---------+
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ncs |sram_data<0> | 10.289|
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ncs |sram_data<1> | 10.543|
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ncs |sram_data<2> | 10.539|
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ncs |sram_data<3> | 10.091|
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ncs |sram_data<4> | 9.970|
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ncs |sram_data<5> | 10.339|
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ncs |sram_data<6> | 9.761|
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ncs |sram_data<7> | 10.018|
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noe |sram_data<0> | 8.488|
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noe |sram_data<1> | 8.742|
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noe |sram_data<2> | 8.738|
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noe |sram_data<3> | 8.290|
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noe |sram_data<4> | 8.169|
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noe |sram_data<5> | 8.538|
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noe |sram_data<6> | 7.960|
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noe |sram_data<7> | 8.217|
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---------------+---------------+---------+
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Analysis completed Sun Oct 31 20:57:02 2010
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 239 MB
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