mirror of
git://projects.qi-hardware.com/sie-ceimtun.git
synced 2025-01-10 04:10:15 +02:00
27 lines
586 B
Verilog
27 lines
586 B
Verilog
`timescale 1ns / 1ps
|
|
|
|
module PWM(clk, enable, PWM_in, PWM_out);
|
|
input clk, enable;
|
|
input [7:0] PWM_in;
|
|
output PWM_out;
|
|
|
|
reg [7:0] PWM_in_reg=0; //Registro temporal para reiniciar el acumulador
|
|
reg [7:0] PWM_accum=0; //Acumulador
|
|
reg [8:0] ClkCount=0; //Para dividir la frecuencia en 2^VAL
|
|
|
|
//Divisor de frecuencia
|
|
always @(posedge clk) if(enable) ClkCount <= ClkCount + 1;
|
|
|
|
//Contador para el PWM
|
|
always @(posedge clk)
|
|
begin
|
|
PWM_in_reg<=PWM_in;
|
|
if(PWM_in_reg==PWM_in) PWM_accum<=PWM_accum+1; else PWM_accum<=0;
|
|
end
|
|
|
|
//Salida para el PWM
|
|
|
|
assign PWM_out=(PWM_accum<PWM_in);
|
|
|
|
endmodule
|