--- Thu 2011-09-01 ------------------------------------------------------------

PCB milling #1:
- setup:
  - board is pertinax
  - locally sourced "W.T." (Taiwan) mounting tape
- measurements:
  - board: 101.6 mm x 44.6 mm (nom. 102.0 mm x 50.0 mm)
- defects found:
  - drill broke on first hole, due to insufficient clearance found in
    run #2. Second drill just cleared the board by sheer luck.
  - drill/mill depth too shallow
  - column cavities too wide
- changes for next run:
  - narrow column cavities from 8.4 mm to 8.0 mm (bad idea, see below)

PCB milling #2;
- changes made:
  - board is FR4
  - corrected depth
- defects found:
  - clearance insufficient (top copper damaged; endmill broke)
- changes for next run:
  - increase clearance by 1 mm
  - future: include board thickness in gp2rml clearance calculation
    (gp2rml calculates "clearance" from the highest point in the plot,
   which for PCBs also happens to be the lowest point, and thus
   includes the board itself and the vertical overshoot. 2 mm are
   sufficient for 0.8 mm boards, but 1.6 mm boards need at least
   0.8 mm more.)
   
PCB milling #3:
- changes made:
  - corrected clearance
  - Tesa 5767 mounting tape (no longer available)
- measurements:
  - column cavity: ~7.6 mm x 10.3 mm (nom. 8.0 x 10.4 mm)
  - board: 102.2 mm x 50.2 mm (nom. 102.0 mm x 50.0 mm)
  - "narrow tongue": 9.1 mm (nom. 9.0 mm)
  - "wide tongue": 14.1 mm (nom. 14.0 mm)
- defects found:
  - column cavities too narrow (also in design; need 8.4 mm)
  - 100 mil header holes a little bit too small
  - 200 mil header holes much too small
  - rear edge touches wall
  - front edge very close to buttons (not sure how close)
- changes for next run:
  - widen column cavities by 0.2 mm on each side
  - compensate tool for 0.1 mm of board deflection on each side

--- Fri 2011-09-02 ------------------------------------------------------------

Layout printed on #3:
- infrastructure:
  - tried new approach of transferring both sides: instead of stapling
    the two sheets, put adhesive tape around the edges. The result is
    acceptable, but not as good as the work-intensive one side at a time
    approach used for ben-wpan.
  - battery pack for laminator control broke down mechanically. Replaced
    with adapter for obscure 500 mil pack I had laying around.
- problems found:
  - "make it look like an accident" isn't such a good idea for the trace
    connecting the relays to 5V. I was tempted to scratch off the toner,
    thinking the pin had bled into the trace.
  - annulus around DIP pins seems too small for 35 mil holes. The holes
    are nominally only 0.5 mm, but that in turn may make them too small.
- changes for next run:
  - make 5V relay traces go clearly for the centers of the respective pins
  - determine correct hole size for DIP

--- Sat 2011-09-03 ------------------------------------------------------------

Soldered #3:
- problems found:
  - DIP copper rings were too small for easy soldering, as expected
  - cosmetic: screw-down headers (K1, K2) are very loose and end up
    visibly angled
  - cosmetic: vias between OUT opto-couplers are a bit close to the
    sockets, making them almost disappear under them. Would be nicer if
    they had more clearance.
  - MCU and DIP sockets should have orientation markings on the copper
    layer. In other news, Chip Quick is quite suitable for removing a
    misplaced 32-LQFP.
  - the footprints of the 1 W resistors (R7-R10) are way too short.
    Placed 0805 instead.

--- Sun 2011-09-04 ------------------------------------------------------------

Milled face plate #0:
- setup:
  - board is pertinax
  - locally sourced "W.T." (Taiwan) mounting tape
- measurements:
  - board: 104.0-104.1 mm x 35.1-35.6 mm (nom. 104.0 mm x 35.0 mm)
  - button hole: 12.6-12.8 mm x 11.3-11.6 mm (nom. 12.6 x 11.3 mm)
- defects found:
  - engraving depth (0.2 mm) is a bit shallow, probably due to board
    curvature
  - got the banana jack diameter wrong: should be 8 mm, not 6 mm
  - button holes show significant deviation from tool path on lower
    edge
- changes for next run:
  - increase engraving depth to 0.5 mm (board is 1.6 mm)
  - correct banana jack hole diameter

Milled face plate #1:
- changes made:
  - increased engraving depth to 0.5 mm
  - increased banana jack hole diameter to 8.0 mm
- defects found:
  - job didn't complete because board became unstuck while milling
  - the 8.0 mm hole is still a bit too tight if jack sleeve is at
    upper end of tolerance range
  - noticed that the button holes are milled last, after cutting the
    board outline. This explains the poor accuracy.

--- Mon 2011-09-05 ------------------------------------------------------------

Milled face plate #2:
- changes made:
  - board is unclad FR4
  - added a bit more adhesive tape
  - increased banana jack hole diameter from 8.0 mm to 8.1 mm, to
    accommodate also jacks that are at the upper end of the tolerance
    range
  - corrected order of tool paths issues by cameo
- measurements:
  - board: 104.1-104.2 mm x 35.1 mm (nom. 104.0 mm x 35.0 mm)
  - button hole: 12.5-12.6 mm x 11.3-11.4 mm (nom. 12.6 x 11.3 mm)
- defects found:
  - tight horizontal fit in the case
  - LED holder have considerable play and retainer rings are loose to
    the point of being useless
  - adhesive tape now sticks almost too well :-) (it was hard to pry
    the board loose after milling)

Milled face plate #3:
- changes made:
  - reduced board width from 104.0 mm to 103.6 mm
  - reduced LED hole from 6.9 mm to 6.2 mm
- problems encountered:
  - raw board wasn't quite large enough for the entire face plate, but
    it seems I missed it by only < 0.1 mm.
  - depth was too shallow, at the cost of the logo
- measurements:
  - board: 103.8 mm x 35.1 mm (nom. 103.6 mm x 35.0 mm)
- defects found:
  - LED holder works better but is still a bit wobbly
  - (EE issue) there's a bit of current from 5 V through the opt-coupler
    LEDs to the pull-ups. Work-around: add 10 kOhm in parallel to each
    LED.

--- Wed 2011-09-07 ------------------------------------------------------------

Rework:
- problem: labsw occasionally (around 1% of all cycles in an automated
  test loop) gets some configuration bits wrong. The pattern observed
  so far is that, in an attempt to turn on CH1, then CH2, CH1 comes on
  normally while CH2 either doesn't come on at all or the relay switches
  but the LED doesn't.
- analysis:
  This may be a problem with the power supply or with USB. Consider
  some or all of the following improvements:

  - follow SiLab's recommendations for regulator bypassing more closely
  - enable the VDD monitor to catch brown-outs
  - add ground areas to shield CPU and USB
  - add redundancy to EP0 protocol
  - add bead to relay power, to prevent upsetting the 5 V rail
- rework:
  Implemented power supply bypassing according to SiLabs' recommendations:
  - added 4.7 uF in parallel to C1
  - added 100 nF in parallel to C2
- results:
  A test run initially showed about 10% abnormal cycles. Detailed
  observation, starting with first anomaly:

  - turn-on cycle: CH2 LED green, M1 not powered (CH2 fully off ?)
  - 21 normal cycles
  - turn-on cycle: all LEDs green, no power (LEDs didn't go dark as they
    would in DFU wait, so the MCU didn't reset)
  - 8 normal cycles
  - turn-on cycle: MAIN and CH2 LED green, M1 not powered
  - 31 normal cycles
  - turn-on cycle: all LEDs green, no power (not a reset)
  - 12 normal cycles
  - turn-on cycle: all LEDs green, no power (not a reset)
  - 3 normal cycles
  - turn-on cycle: all LEDs green, no power (not a reset)
  - 3 normal cycles
  - turn-on cycle: all LEDs green, no power (not a reset)
  - 3 normal cycles
  - turn-on cycle: all LEDs green, no power (not a reset)
  - 68 normal cycles
  - turn-on cycle: all LEDs green, no power (not a reset)
  - 5+ normal cycles

Further analysis: the absence of more abnormal states, such as LEDs
contradicting relays or LEDs just going dark suggests that the problem
is may not be USB data corruption. At least some of the symptoms would
be compatible with EMI from switching the relay creating false signals
on the buttons.

The "all LEDs green" condition would be a false press of MAIN. The
CH2 green condition would be harder to explain. Maybe the MAIN LED
was also green and I didn't notice. In this case, it would have been
a combination of the MAIN and CH1 buttons (MAIN to exit remote mode,
turn off all the channels, and enable the channel buttons. Then CH1 to
turn on CH1 again.)

To do: debounce buttons (in software) before accepting a state change.

---------------------

(next PCB run)
- changes made:
  - made 5V relay traces go clearly for the centers of the respective pins
  - changed DIP hole size from 0.5 mm to 0.8 mm, hole-to-copper ratio from
    2.5 to 2
  - bypass VBUS and VDD with 4.7 uF and 100 nF each
  - added external pull-ups to IN_* and to buttons (so that we can turn
    off the internal pull-ups and thus avoid sneak current through the
    opto-coupler LEDs from VBUS via the pull-ups into VDD)
  - added low-pass filters to button inputs, to suppress interferences,
    e.g., from load being switched (with help from Joerg Reisenweber)
  - added hardware revision ID pins
  - use SPACER-*-BARE for mounting holes without copper
  - updated 2512 footprints (forgot to refresh after editing stdpass.fpd)
  - widened column cavities by 0.2 mm on each side

Pending:
- change mill nominal diameter from 35 mil to 26-27 mil
- move vias between OUT opto-couplers 0.2 mm to the center
- add orientation markings on copper layer for MCU and DIP sockets
- add ground zones
- firmware: disable internal pull-ups (for hw revision 1)
- update version (date)
