mirror of
git://projects.qi-hardware.com/wernermisc.git
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66 lines
804 B
Prolog
66 lines
804 B
Prolog
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update=Wed Dec 22 22:49:53 2010
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last_client=pcbnew
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[eeschema]
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version=1
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LibDir=
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NetFmt=1
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HPGLSpd=20
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HPGLDm=15
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HPGLNum=1
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offX_A4=0
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offY_A4=0
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offX_A3=0
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offY_A3=0
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offX_A2=0
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offY_A2=0
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offX_A1=0
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offY_A1=0
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offX_A0=0
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offY_A0=0
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offX_A=0
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offY_A=0
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offX_B=0
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offY_B=0
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offX_C=0
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offY_C=0
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offX_D=0
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offY_D=0
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offX_E=0
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offY_E=0
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RptD_X=0
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RptD_Y=100
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RptLab=1
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LabSize=60
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PrintMonochrome=1
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ShowSheetReferenceAndTitleBlock=1
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[eeschema/libraries]
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LibName1=conn
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LibName2=./sw4
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[cvpcb]
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version=1
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NetIExt=net
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[cvpcb/libraries]
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EquName1=devcms
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[pcbnew]
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version=1
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PadDrlX=320
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PadDimH=600
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PadDimV=600
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BoardThickness=630
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SgPcb45=1
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TxtPcbV=800
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TxtPcbH=600
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TxtModV=600
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TxtModH=600
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TxtModW=120
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VEgarde=100
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DrawLar=150
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EdgeLar=150
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TxtLar=120
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MSegLar=150
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LastNetListRead=f10.net
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[pcbnew/libraries]
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LibDir=
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LibName1=./fsm100
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LibName2=./he10
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