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labsw/: first draft layout complete

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This commit is contained in:
Werner Almesberger 2011-08-27 13:18:08 -03:00
parent c0bfec4d8e
commit 80084df8a5
4 changed files with 1800 additions and 934 deletions
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120
labsw/back.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri Aug 26 01:18:37 2011
EESchema Schematic File Version 2 date Sat Aug 27 13:17:47 2011
LIBS:power
LIBS:device
LIBS:conn
@ -12,7 +12,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 2 3
Title "Lab Switch (Back panel)"
Date "26 aug 2011"
Date "27 aug 2011"
Rev "0"
Comp "Werner Almesberger"
Comment1 ""
@ -20,6 +20,38 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Label 6950 5450 2 60 ~ 0
EXT_OUT_4_N
Text Label 6950 5350 2 60 ~ 0
EXT_OUT_3_N
Text Label 6950 5250 2 60 ~ 0
EXT_OUT_2_N
Text Label 6950 5150 2 60 ~ 0
EXT_OUT_1_N
Text Label 6950 2300 2 60 ~ 0
EXT_IN_4_N
Text Label 6950 2200 2 60 ~ 0
EXT_IN_3_N
Text Label 6950 2100 2 60 ~ 0
EXT_IN_2_N
Text Label 6950 2000 2 60 ~ 0
EXT_IN_1_N
Text Label 8150 5450 0 60 ~ 0
EXT_OUT_4_P
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EXT_OUT_3_P
Text Label 8150 5250 0 60 ~ 0
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EXT_IN_4_P
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EXT_IN_1_P
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@ -36,9 +68,9 @@ Text GLabel 3300 1850 0 60 Output ~ 0
IN_2
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IN_1
Text Notes 7500 5300 0 60 ~ 0
Text Notes 9550 5300 0 60 ~ 0
Vmax = 80 V\nImax = 5...50 mA
Text Notes 7500 2050 0 60 ~ 0
Text Notes 9550 2050 0 60 ~ 0
Vmin = 1.5 V\nImin = 100 uA\nVmax = 30 V\nImax = 30 mA
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@ -279,53 +311,53 @@ Wire Wire Line
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@ -337,19 +369,19 @@ Wire Wire Line
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446
labsw/front.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri Aug 26 01:32:28 2011
EESchema Schematic File Version 2 date Sat Aug 27 13:17:47 2011
LIBS:power
LIBS:device
LIBS:conn
@ -12,7 +12,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 3 3
Title "Lab Switch (Front panel)"
Date "26 aug 2011"
Date "27 aug 2011"
Rev "0"
Comp "Werner Almesberger"
Comment1 ""
@ -20,436 +20,452 @@ Comment2 ""
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U 1 1 4E55BFD3
P 3850 2450
F 0 "D1" H 3850 2550 40 0000 C CNN
F 1 "DIODE" H 3850 2350 40 0000 C CNN
1 3850 2450
P 4450 2450
F 0 "D1" H 4450 2550 40 0000 C CNN
F 1 "DIODE" H 4450 2350 40 0000 C CNN
1 4450 2450
0 -1 -1 0
$EndComp
$Comp
L DIODE D2
U 1 1 4E55BFD2
P 3850 4950
F 0 "D2" H 3850 5050 40 0000 C CNN
F 1 "DIODE" H 3850 4850 40 0000 C CNN
1 3850 4950
P 4450 4950
F 0 "D2" H 4450 5050 40 0000 C CNN
F 1 "DIODE" H 4450 4850 40 0000 C CNN
1 4450 4950
0 -1 -1 0
$EndComp
$Comp
L +5V #PWR018
U 1 1 4E55BFD1
P 4050 4300
F 0 "#PWR018" H 4050 4390 20 0001 C CNN
F 1 "+5V" H 4050 4390 50 0000 C CNN
1 4050 4300
P 4650 4300
F 0 "#PWR018" H 4650 4390 20 0001 C CNN
F 1 "+5V" H 4650 4390 50 0000 C CNN
1 4650 4300
1 0 0 -1
$EndComp
$Comp
L +5V #PWR019
U 1 1 4E55BFD0
P 4050 1800
F 0 "#PWR019" H 4050 1890 20 0001 C CNN
F 1 "+5V" H 4050 1890 50 0000 C CNN
1 4050 1800
P 4650 1800
F 0 "#PWR019" H 4650 1890 20 0001 C CNN
F 1 "+5V" H 4650 1890 50 0000 C CNN
1 4650 1800
1 0 0 -1
$EndComp
$EndSCHEMATC

2116
labsw/labsw.brd
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File diff suppressed because it is too large Load Diff

52
labsw/labsw.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri Aug 26 01:18:37 2011
EESchema Schematic File Version 2 date Sat Aug 27 13:17:47 2011
LIBS:power
LIBS:device
LIBS:conn
@ -12,7 +12,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 1 3
Title "Lab Switch (Overview and CPU)"
Date "26 aug 2011"
Date "27 aug 2011"
Rev "0"
Comp "Werner Almesberger"
Comment1 ""
@ -20,6 +20,10 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Label 3250 3900 0 60 ~ 0
DM
Text Label 3250 3750 0 60 ~ 0
DP
Connection ~ 4250 3750
Wire Wire Line
4250 4550 4250 3750
@ -167,50 +171,50 @@ F 1 "+5V" H 3650 3640 50 0000 C CNN
1 3650 3550
1 0 0 -1
$EndComp
Text GLabel 6950 5400 3 60 Output ~ 0
OUT_4
Text GLabel 7100 5400 3 60 Output ~ 0
OUT_3
Text GLabel 7250 5400 3 60 Output ~ 0
OUT_2
Text GLabel 7400 5400 3 60 Output ~ 0
OUT_4
Text GLabel 7250 5400 3 60 Output ~ 0
OUT_3
Text GLabel 7100 5400 3 60 Output ~ 0
OUT_2
Text GLabel 6950 5400 3 60 Output ~ 0
OUT_1
Text GLabel 7550 5400 3 60 Output ~ 0
CH2_OPT
Text GLabel 7700 5400 3 60 Output ~ 0
CH2_RELAY
CH2_OPT
Text GLabel 8750 4350 2 60 Output ~ 0
CH2_RELAY
Text GLabel 7550 5400 3 60 Output ~ 0
CH1_OPT
Text GLabel 8750 4200 2 60 Output ~ 0
CH1_RELAY
NoConn ~ 8550 4050
NoConn ~ 8550 3900
Text GLabel 8750 3750 2 60 Output ~ 0
LED_CH2_G
Text GLabel 8750 3600 2 60 Output ~ 0
LED_CH2_R
Text GLabel 8750 3450 2 60 Output ~ 0
LED_CH1_G
LED_CH2_G
Text GLabel 8750 3300 2 60 Output ~ 0
LED_CH1_R
LED_CH2_R
Text GLabel 7700 2200 1 60 Output ~ 0
LED_MAIN_G
LED_CH1_G
Text GLabel 7550 2200 1 60 Output ~ 0
LED_CH1_R
Text GLabel 8750 3750 2 60 Output ~ 0
LED_MAIN_G
Text GLabel 8750 3600 2 60 Output ~ 0
LED_MAIN_R
Text GLabel 6800 2200 1 60 Input ~ 0
Text GLabel 6650 2200 1 60 Input ~ 0
IN_4
Text GLabel 7400 2200 1 60 Input ~ 0
BUT_CH2
Text GLabel 7250 2200 1 60 Input ~ 0
BUT_CH2
Text GLabel 7400 2200 1 60 Input ~ 0
BUT_CH1
Text GLabel 7100 2200 1 60 Input ~ 0
BUT_MAIN
NoConn ~ 6950 2400
Text GLabel 6650 2200 1 60 Input ~ 0
Text GLabel 6800 2200 1 60 Input ~ 0
IN_3
Text GLabel 5550 3300 0 60 Input ~ 0
IN_2
Text GLabel 5550 3450 0 60 Input ~ 0
IN_2
Text GLabel 5550 3300 0 60 Input ~ 0
IN_1
Text Label 6750 5950 1 60 ~ 0
C2D