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238 lines
9.5 KiB
Plaintext
238 lines
9.5 KiB
Plaintext
--- Thu 2011-09-01 ------------------------------------------------------------
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PCB milling #1:
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- setup:
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- board is pertinax
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- locally sourced "W.T." (Taiwan) mounting tape
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- measurements:
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- board: 101.6 mm x 44.6 mm (nom. 102.0 mm x 50.0 mm)
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- defects found:
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- drill broke on first hole, due to insufficient clearance found in
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run #2. Second drill just cleared the board by sheer luck.
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- drill/mill depth too shallow
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- column cavities too wide
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- changes for next run:
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- narrow column cavities from 8.4 mm to 8.0 mm (bad idea, see below)
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PCB milling #2;
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- changes made:
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- board is FR4
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- corrected depth
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- defects found:
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- clearance insufficient (top copper damaged; endmill broke)
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- changes for next run:
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- increase clearance by 1 mm
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- future: include board thickness in gp2rml clearance calculation
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(gp2rml calculates "clearance" from the highest point in the plot,
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which for PCBs also happens to be the lowest point, and thus
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includes the board itself and the vertical overshoot. 2 mm are
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sufficient for 0.8 mm boards, but 1.6 mm boards need at least
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0.8 mm more.)
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PCB milling #3:
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- changes made:
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- corrected clearance
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- Tesa 5767 mounting tape (no longer available)
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- measurements:
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- column cavity: ~7.6 mm x 10.3 mm (nom. 8.0 x 10.4 mm)
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- board: 102.2 mm x 50.2 mm (nom. 102.0 mm x 50.0 mm)
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- "narrow tongue": 9.1 mm (nom. 9.0 mm)
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- "wide tongue": 14.1 mm (nom. 14.0 mm)
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- defects found:
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- column cavities too narrow (also in design; need 8.4 mm)
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- 100 mil header holes a little bit too small
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- 200 mil header holes much too small
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- rear edge touches wall
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- front edge very close to buttons (not sure how close)
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- changes for next run:
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- widen column cavities by 0.2 mm on each side
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- compensate tool for 0.1 mm of board deflection on each side
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--- Fri 2011-09-02 ------------------------------------------------------------
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Layout printed on #3:
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- infrastructure:
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- tried new approach of transferring both sides: instead of stapling
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the two sheets, put adhesive tape around the edges. The result is
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acceptable, but not as good as the work-intensive one side at a time
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approach used for ben-wpan.
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- battery pack for laminator control broke down mechanically. Replaced
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with adapter for obscure 500 mil pack I had laying around.
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- problems found:
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- "make it look like an accident" isn't such a good idea for the trace
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connecting the relays to 5V. I was tempted to scratch off the toner,
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thinking the pin had bled into the trace.
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- annulus around DIP pins seems too small for 35 mil holes. The holes
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are nominally only 0.5 mm, but that in turn may make them too small.
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- changes for next run:
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- make 5V relay traces go clearly for the centers of the respective pins
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- determine correct hole size for DIP
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--- Sat 2011-09-03 ------------------------------------------------------------
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Soldered #3:
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- problems found:
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- DIP copper rings were too small for easy soldering, as expected
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- cosmetic: screw-down headers (K1, K2) are very loose and end up
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visibly angled
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- cosmetic: vias between OUT opto-couplers are a bit close to the
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sockets, making them almost disappear under them. Would be nicer if
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they had more clearance.
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- MCU and DIP sockets should have orientation markings on the copper
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layer. In other news, Chip Quick is quite suitable for removing a
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misplaced 32-LQFP.
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- the footprints of the 1 W resistors (R7-R10) are way too short.
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Placed 0805 instead.
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--- Sun 2011-09-04 ------------------------------------------------------------
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Milled face plate #0:
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- setup:
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- board is pertinax
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- locally sourced "W.T." (Taiwan) mounting tape
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- measurements:
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- board: 104.0-104.1 mm x 35.1-35.6 mm (nom. 104.0 mm x 35.0 mm)
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- button hole: 12.6-12.8 mm x 11.3-11.6 mm (nom. 12.6 x 11.3 mm)
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- defects found:
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- engraving depth (0.2 mm) is a bit shallow, probably due to board
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curvature
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- got the banana jack diameter wrong: should be 8 mm, not 6 mm
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- button holes show significant deviation from tool path on lower
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edge
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- changes for next run:
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- increase engraving depth to 0.5 mm (board is 1.6 mm)
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- correct banana jack hole diameter
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Milled face plate #1:
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- changes made:
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- increased engraving depth to 0.5 mm
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- increased banana jack hole diameter to 8.0 mm
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- defects found:
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- job didn't complete because board became unstuck while milling
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- the 8.0 mm hole is still a bit too tight if jack sleeve is at
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upper end of tolerance range
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- noticed that the button holes are milled last, after cutting the
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board outline. This explains the poor accuracy.
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--- Mon 2011-09-05 ------------------------------------------------------------
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Milled face plate #2:
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- changes made:
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- board is unclad FR4
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- added a bit more adhesive tape
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- increased banana jack hole diameter from 8.0 mm to 8.1 mm, to
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accommodate also jacks that are at the upper end of the tolerance
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range
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- corrected order of tool paths issues by cameo
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- measurements:
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- board: 104.1-104.2 mm x 35.1 mm (nom. 104.0 mm x 35.0 mm)
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- button hole: 12.5-12.6 mm x 11.3-11.4 mm (nom. 12.6 x 11.3 mm)
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- defects found:
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- tight horizontal fit in the case
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- LED holder have considerable play and retainer rings are loose to
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the point of being useless
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- adhesive tape now sticks almost too well :-) (it was hard to pry
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the board loose after milling)
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Milled face plate #3:
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- changes made:
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- reduced board width from 104.0 mm to 103.6 mm
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- reduced LED hole from 6.9 mm to 6.2 mm
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- problems encountered:
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- raw board wasn't quite large enough for the entire face plate, but
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it seems I missed it by only < 0.1 mm.
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- depth was too shallow, at the cost of the logo
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- measurements:
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- board: 103.8 mm x 35.1 mm (nom. 103.6 mm x 35.0 mm)
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- defects found:
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- LED holder works better but is still a bit wobbly
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- (EE issue) there's a bit of current from 5 V through the opt-coupler
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LEDs to the pull-ups. Work-around: add 10 kOhm in parallel to each
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LED.
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--- Wed 2011-09-07 ------------------------------------------------------------
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Rework:
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- problem: labsw occasionally (around 1% of all cycles in an automated
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test loop) gets some configuration bits wrong. The pattern observed
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so far is that, in an attempt to turn on CH1, then CH2, CH1 comes on
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normally while CH2 either doesn't come on at all or the relay switches
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but the LED doesn't.
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- analysis:
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This may be a problem with the power supply or with USB. Consider
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some or all of the following improvements:
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- follow SiLab's recommendations for regulator bypassing more closely
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- enable the VDD monitor to catch brown-outs
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- add ground areas to shield CPU and USB
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- add redundancy to EP0 protocol
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- add bead to relay power, to prevent upsetting the 5 V rail
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- rework:
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Implemented power supply bypassing according to SiLabs' recommendations:
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- added 4.7 uF in parallel to C1
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- added 100 nF in parallel to C2
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- results:
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A test run initially showed about 10% abnormal cycles. Detailed
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observation, starting with first anomaly:
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- turn-on cycle: CH2 LED green, M1 not powered (CH2 fully off ?)
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- 21 normal cycles
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- turn-on cycle: all LEDs green, no power (LEDs didn't go dark as they
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would in DFU wait, so the MCU didn't reset)
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- 8 normal cycles
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- turn-on cycle: MAIN and CH2 LED green, M1 not powered
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- 31 normal cycles
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- turn-on cycle: all LEDs green, no power (not a reset)
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- 12 normal cycles
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- turn-on cycle: all LEDs green, no power (not a reset)
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- 3 normal cycles
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- turn-on cycle: all LEDs green, no power (not a reset)
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- 3 normal cycles
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- turn-on cycle: all LEDs green, no power (not a reset)
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- 3 normal cycles
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- turn-on cycle: all LEDs green, no power (not a reset)
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- 68 normal cycles
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- turn-on cycle: all LEDs green, no power (not a reset)
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- 5+ normal cycles
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Further analysis: the absence of more abnormal states, such as LEDs
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contradicting relays or LEDs just going dark suggests that the problem
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is may not be USB data corruption. At least some of the symptoms would
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be compatible with EMI from switching the relay creating false signals
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on the buttons.
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The "all LEDs green" condition would be a false press of MAIN. The
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CH2 green condition would be harder to explain. Maybe the MAIN LED
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was also green and I didn't notice. In this case, it would have been
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a combination of the MAIN and CH1 buttons (MAIN to exit remote mode,
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turn off all the channels, and enable the channel buttons. Then CH1 to
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turn on CH1 again.)
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To do: debounce buttons (in software) before accepting a state change.
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---------------------
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(next PCB run)
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- changes made:
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- made 5V relay traces go clearly for the centers of the respective pins
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- changed DIP hole size from 0.5 mm to 0.8 mm, hole-to-copper ratio from
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2.5 to 2
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- bypass VBUS and VDD with 4.7 uF and 100 nF each
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- added external pull-ups to IN_* and to buttons (so that we can turn
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off the internal pull-ups and thus avoid sneak current through the
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opto-coupler LEDs from VBUS via the pull-ups into VDD)
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- added low-pass filters to button inputs, to suppress interferences,
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e.g., from load being switched (with help from Joerg Reisenweber)
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- added hardware revision ID pins
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Pending:
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- widen column cavities by 0.2 mm on each side
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- consider pulling in front edge a little in buttons area
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- uncopper mounting holes (using "loop" as "if" in fped)
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- change mill nominal diameter from 35 mil to 26-27 mil
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- move vias between OUT opto-couplers 0.2 mm to the center
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- add orientation markings on copper layer for MCU and DIP sockets
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- verify 2512 footprint of 1 W resistors
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- add ground zones
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- firmware: disable internal pull-ups
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