mirror of
git://projects.qi-hardware.com/wernermisc.git
synced 2024-11-28 19:01:53 +02:00
745 lines
14 KiB
C
745 lines
14 KiB
C
/*
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* picpen.c - PIC (18F{2,4}xJxx) Programmer/Emulator for Nanonote
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*
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* Written 2012 by Werner Almesberger
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* Copyright 2012 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <string.h>
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#include <assert.h>
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#include "gpio-xburst.h"
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#define POWER_OFF 3, 2 /* PD02 */
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#define nMCLR 3, 13 /* PD13 DAT3 */
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#define PGD 3, 8 /* PD09 CMD */
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#define PGC 3, 9 /* PD08 CLK */
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#define ICSP_KEY 0x4d434850
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#define P5_US 1 /* Delay Between 4-Bit Command and Command Operand */
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#define P5A_US 1 /* Delay Between 4-Bit Command Operand and Next 4-Bit
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Command */
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#define P6_US 1 /* Delay Between Last PGC down of Command Byte
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to First PGC up of Read of Data Word */
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#define P9_US 1200 /* Delay to allow Block Programming to Occur */
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#define P10_US 54000 /* Delay to allow Row Erase to Occur */
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#define P11_US 524000 /* Delay to allow Bulk Erase to Occur */
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#define P12_US 400 /* Input Data Hold Time from nMCLR up */
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#define P13_US 1 /* VDD up Setup Time to nMCLR up */
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#define P16_US 1 /* Delay Between Last PGC down and nMCLR down */
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#define P17_US 3 /* nMCLR down to VDD down */
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#define P19_US 4000 /* Delay from First nMCLR down to First PGC up for
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Key Sequence on PGD */
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#define P20_US 1 /* Delay from Last PGC down for Key Sequence on
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PGD to Second nMCLR up */
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#define CMD_INSN 0
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#define CMD_TABLAT 0x2
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#define CMD_READ_INC 0x9 /* post-increment by 1 */
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#define CMD_WRITE 0xc
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#define CMD_WRITE_INC 0xd /* post-increment by 2 */
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#define CMD_WRITE_START 0xf
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#define INSN_MOVLW 0x0e
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#define INSN_MOVWF 0x6e
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#define INSN_MOVF_W_0 0x50
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#define INSN_MOVFF1 0xcf
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#define INSN_MOVFF2 0xff
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#define REG_TABLAT 0xf5
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#define REG_TBLPTRL 0xf6
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#define REG_TBLPTRH 0xf7
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#define REG_TBLPTRU 0xf8
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#define REG_ANCON0 0x48 /* banked ! */
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#define REG_ANCON1 0x49 /* banked ! */
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#define REG_PORTA 0x80
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#define REG_PORTC 0x82
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#define REG_LATA 0x89
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#define REG_TRISA 0x92 /* 1 = in */
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#define REG_EECON1 0xa6
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#define REG_CTMUICON 0xb1
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#define REG_CTMUCONL 0xb2
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#define REG_CTMUCONH 0xb3
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#define REG_ADCON1 0xc1
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#define REG_ADCON0 0xc2
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#define REG_ADRESL 0xc3
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#define REG_ADRESH 0xc4
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#define BLOCK 64
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struct rec {
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uint32_t addr;
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uint8_t *data;
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int len;
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struct rec *next;
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};
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static int kb;
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/* The multiplier (100) is a wild guess. Tested down to 0. */
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static inline void delay(int us)
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{
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uint32_t i;
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if (us < 10)
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for (i = 0; i != us*100; i++)
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asm("");
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else
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usleep(us);
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}
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static void icsp_begin(int power)
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{
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int i;
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gpio_init();
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gpio_high(nMCLR);
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gpio_high(PGD);
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gpio_high(PGC);
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if (power) {
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gpio_output(POWER_OFF);
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gpio_output(PGD);
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gpio_output(PGC);
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gpio_output(nMCLR);
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delay(100*1000); /* precharge */
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}
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gpio_low(PGD);
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gpio_low(PGC);
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gpio_low(nMCLR);
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if (power)
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gpio_low(POWER_OFF);
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delay(P13_US);
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gpio_high(nMCLR);
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delay(1);
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gpio_low(nMCLR);
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delay(P19_US);
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for (i = 31; i >= 0; i--) {
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if ((ICSP_KEY >> i) & 1)
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gpio_high(PGD);
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else
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gpio_low(PGD);
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gpio_high(PGC);
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gpio_low(PGC);
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}
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delay(P20_US);
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gpio_high(nMCLR);
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delay(P12_US);
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}
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static void icsp_end(void)
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{
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gpio_low(PGD);
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gpio_low(PGC);
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delay(P16_US);
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gpio_low(nMCLR);
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delay(P17_US);
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gpio_high(nMCLR);
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// gpio_high(POWER_OFF);
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gpio_input(PGD);
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gpio_input(PGC);
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}
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static void icsp_send(uint8_t v, int n)
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{
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int i;
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for (i = 0; i != n; i++) {
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if ((v >> i) & 1)
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gpio_high(PGD);
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else
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gpio_low(PGD);
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gpio_high(PGC);
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gpio_low(PGC);
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}
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}
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static uint8_t icsp_recv(int n)
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{
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uint8_t v = 0;
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int i;
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for (i = 0; i != n; i++) {
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gpio_high(PGC);
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gpio_low(PGC);
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if (gpio_get(PGD))
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v |= 1 << i;
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}
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return v;
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}
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static void icsp_write(uint8_t cmd, uint8_t a, uint8_t b)
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{
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icsp_send(cmd, 4);
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delay(P5_US);
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icsp_send(b, 8);
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icsp_send(a, 8);
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delay(P5A_US);
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}
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static void write_reg(uint8_t addr, uint8_t v)
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{
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icsp_write(CMD_INSN, INSN_MOVLW, v);
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icsp_write(CMD_INSN, INSN_MOVWF, addr);
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}
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static uint8_t read_reg(uint8_t addr)
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{
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uint8_t v;
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icsp_write(CMD_INSN, 0x50, addr);
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/* for some strange reason we need two writes */
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icsp_write(CMD_INSN, INSN_MOVWF, REG_TABLAT);
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icsp_write(CMD_INSN, INSN_MOVWF, REG_TABLAT);
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icsp_send(CMD_TABLAT, 4);
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delay(P5_US);
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icsp_send(0, 8);
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delay(P6_US);
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gpio_input(PGD);
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v = icsp_recv(8);
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delay(P5A_US);
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gpio_output(PGD);
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return v;
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}
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static void set_tblptr(uint32_t addr)
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{
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write_reg(REG_TBLPTRU, addr >> 16);
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write_reg(REG_TBLPTRH, addr >> 8);
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write_reg(REG_TBLPTRL, addr);
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}
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static void read_mem(uint32_t addr, uint8_t *buf, int len)
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{
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set_tblptr(addr);
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while (len--) {
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icsp_send(CMD_READ_INC, 4);
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delay(P5_US);
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icsp_send(0, 8);
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delay(P6_US);
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gpio_input(PGD);
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*buf++ = icsp_recv(8);
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delay(P5A_US);
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gpio_output(PGD);
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}
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}
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static void bulk_erase(void)
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{
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set_tblptr(0x3c0005);
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icsp_write(CMD_WRITE, 0x01, 0x01);
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set_tblptr(0x3c0004);
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icsp_write(CMD_WRITE, 0x80, 0x80);
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icsp_write(CMD_INSN, 0, 0);
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icsp_send(0, 4);
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delay(P11_US+P10_US);
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icsp_send(0, 16);
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delay(P5A_US); /* guess*/
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}
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static void write_mem(uint32_t addr, const uint8_t *buf, int len)
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{
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int i;
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uint8_t first;
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assert(!(addr & (BLOCK-1)));
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assert(!(len & (BLOCK-1)));
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/* BSF EECON1, WREN */
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icsp_write(CMD_INSN, 0x84, REG_EECON1);
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while (len) {
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set_tblptr(addr);
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for (i = 0; i != BLOCK/2-1; i++) {
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first = *buf++;
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icsp_write(CMD_WRITE_INC, *buf++, first);
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}
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first = *buf++;
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icsp_write(CMD_WRITE_START, *buf++, first);
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icsp_send(0, 3);
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gpio_low(PGD);
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gpio_high(PGC);
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delay(P9_US);
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gpio_low(PGC);
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delay(P5_US);
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icsp_send(0, 16);
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delay(P5A_US); /* guess*/
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addr += BLOCK;
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len -= BLOCK;
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}
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}
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/* ----- Flash-level operations -------------------------------------------- */
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static void flash_record(const struct rec *rec)
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{
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uint8_t *tmp;
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int off, padded;
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off = rec->addr & (BLOCK-1);
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padded = (rec->len+off+BLOCK-1) & ~(BLOCK-1);
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if (!off && padded == rec->len) {
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write_mem(rec->addr, rec->data, rec->len);
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return;
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}
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tmp = malloc(padded);
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if (!tmp) {
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perror("malloc");
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exit(1);
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}
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memset(tmp, 0xff, off);
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memcpy(tmp+off, rec->data, rec->len);
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memset(tmp+off+rec->len, 0xff, padded-rec->len-off);
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write_mem(rec->addr-off, tmp, padded);
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}
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static void verify_record(const struct rec *rec)
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{
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uint8_t *tmp;
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int i;
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tmp = malloc(rec->len);
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if (!tmp) {
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perror("malloc");
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exit(1);
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}
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read_mem(rec->addr, tmp, rec->len);
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for (i = 0; i != rec->len; i++)
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if (rec->data[i] != tmp[i]) {
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fprintf(stderr,
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"%04x: wrote %02x != read %02x\n",
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rec->addr+i, rec->data[i], tmp[i]);
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}
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}
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static void flash_file(const struct rec *recs)
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{
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const struct rec *rec;
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for (rec = recs; rec; rec = rec->next)
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if (rec->addr+rec->len > kb*1024) {
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fprintf(stderr,
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"record 0x%x+0x%x ends outside Flash of %d bytes\n",
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rec->addr, rec->len, kb*1024-8);
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exit(1);
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}
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bulk_erase();
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for (rec = recs; rec; rec = rec->next)
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flash_record(rec);
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for (rec = recs; rec; rec = rec->next)
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verify_record(rec);
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}
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static void dump_flash(void)
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{
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uint8_t *tmp, c;
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int i, j;
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tmp = malloc(kb*1024);
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if (!tmp) {
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perror("malloc");
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exit(1);
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}
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read_mem(0, tmp, kb*1024);
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for (i = 0; i != kb*1024; i += 16) {
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printf("%04X: ", i);
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for (j = 0; j != 16; j++)
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printf("%02X ", tmp[i+j]);
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for (j = 0; j != 16; j++) {
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c = tmp[i+j];
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printf("%c", c >= ' ' && c <= '~' ? c : '.');
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}
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printf("\n");
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}
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}
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/* ----- Experiments ------------------------------------------------------- */
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#if 0
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static void blink(void)
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{
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write_reg(REG_TRISA, 0xfc);
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while (1) {
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write_reg(REG_LATA, 1);
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gpio_high(PGD);
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delay(200*1000);
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write_reg(REG_LATA, 2);
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gpio_high(PGD);
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delay(200*1000);
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}
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}
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static void adc(void)
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{
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int i;
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#if 0
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for (i = 0; i != 256; i++) {
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// write_reg(REG_ANCON0, 0xff);
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// write_reg(REG_TABLAT, i);
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// write_reg(REG_TABLAT, i);
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printf("%02x ", read_reg(REG_PORTC));
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fflush(stdout);
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}
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#endif
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write_reg(REG_TRISA, 0xfc);
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// write_reg(REG_ANCON0, 0x10); /* AN4 is analog */
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write_reg(REG_ADCON0, 0x20); /* AN4, Vss to AVdd */
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write_reg(REG_ADCON1, 0x80); /* Tad = 0, Fosc/2, right just. */
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write_reg(REG_ADCON0, 0x21); /* Enable ADC module */
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while (1) {
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uint8_t hi, lo;
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write_reg(REG_ADCON0, 0x23); /* GO */
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while (read_reg(REG_ADCON0) & 2)
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write(2, ".", 1);
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hi = read_reg(REG_ADRESH);
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lo = read_reg(REG_ADRESL);
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printf("\r%02x %02x (%u)\n", hi, lo, hi << 8 | lo);
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}
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#if 0
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while (1) {
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write_reg(
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}
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#endif
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}
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static void cap(void)
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{
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write_reg(REG_CTMUCONH, 0x00); /* page 405 */
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write_reg(REG_CTMUCONL, 0x90);
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write_reg(REG_CTMUICON, 0x01);
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write_reg(REG_TRISA, 0xfc);
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write_reg(REG_ADCON0, 0x20); /* AN4, Vss to AVdd */
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// write_reg(REG_ADCON1, 0x8e); /* Tad = 2, Fosc/32, right just. */
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write_reg(REG_ADCON1, 0x88); /* Tad = 2, Fosc/2, right just. */
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write_reg(REG_ADCON0, 0x21); /* Enable ADC module */
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/* bandgap ?!? */
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while (1) {
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uint8_t hi, lo;
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write_reg(REG_CTMUCONH, 0x80); /* enable CTMU */
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write_reg(REG_CTMUCONL, 0x90); /* clear EDGxSTAT */
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write_reg(REG_CTMUCONH, 0x82); /* ground output */
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delay(1);
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write_reg(REG_CTMUCONH, 0x80); /* end drain */
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write_reg(REG_CTMUCONL, 0x91); /* current on */
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write_reg(REG_CTMUCONL, 0x90); /* current off */
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write_reg(REG_ADCON0, 0x23); /* GO */
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while (read_reg(REG_ADCON0) & 2)
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write(2, ".", 1);
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hi = read_reg(REG_ADRESH);
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lo = read_reg(REG_ADRESL);
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printf("\r%02x %02x (%u)\n", hi, lo, hi << 8 | lo);
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}
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}
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static void dump(uint32_t addr)
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{
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uint8_t buf[BLOCK];
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int i;
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read_mem(addr, buf, BLOCK);
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for (i = 0; i != BLOCK; i++) {
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if (!(i & 15))
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printf("%04X:", i);
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printf(" %02X", buf[i]);
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if ((i & 15) == 15)
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printf("\n");
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}
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}
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static void rerwr(void)
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{
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uint8_t buf[BLOCK];
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int i;
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dump(0x3fffc0);
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dump(0);
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bulk_erase();
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dump(0);
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for (i = 0; i != BLOCK; i++)
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buf[i] = i;
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write_mem(0, buf, BLOCK);
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dump(0x3fffc0);
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dump(0);
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}
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#endif
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/* ----- Chip identification ----------------------------------------------0 */
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struct chip {
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const char *name;
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uint8_t id2, id1;
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int kb;
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} chips[] = {
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{ "PIC18F24J50", 0x4c, 0x00, 16 },
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{ NULL }
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};
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#define DEVID1 0x3ffffe
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static void identify(void)
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{
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uint8_t id[2];
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const struct chip *chip;
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read_mem(DEVID1, id, 2);
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|
for (chip = chips; chip->name; chip++) {
|
|
if ((chip->id1 ^ id[0]) & 0xe0)
|
|
continue;
|
|
if (chip->id2 == id[1])
|
|
break;
|
|
}
|
|
fprintf(stderr, "ID = 0x%02x%02x (%s)\n", id[1], id[0],
|
|
chip->name ? chip->name : "?");
|
|
if (!chip->name)
|
|
exit(1);
|
|
fprintf(stderr, "%d kB Flash\n", chip->kb);
|
|
kb = chip->kb;
|
|
}
|
|
|
|
|
|
/* ----- Intel HEX file reader --------------------------------------------- */
|
|
|
|
|
|
static int hex(char c, int lineno)
|
|
{
|
|
if (c >= '0' && c <= '9')
|
|
return c-'0';
|
|
if (c >= 'A' && c <= 'F')
|
|
return c-'A'+10;
|
|
fprintf(stderr, "non-hex character \"%c\" in line %d\n", c, lineno);
|
|
exit(1);
|
|
}
|
|
|
|
|
|
/* http://en.wikipedia.org/wiki/Intel_HEX */
|
|
|
|
|
|
static struct rec *load_file(const char *name)
|
|
{
|
|
struct rec *recs = NULL, *last = NULL, *rec;
|
|
const struct rec *other;
|
|
FILE *file;
|
|
int lineno = 1;
|
|
char line[1000];
|
|
const char *s;
|
|
uint8_t buf[sizeof(line)/2];
|
|
uint8_t *p, *t, sum;
|
|
uint32_t xaddr = 0, addr;
|
|
|
|
file = fopen(name, "r");
|
|
if (!file) {
|
|
perror(name);
|
|
exit(1);
|
|
}
|
|
while (fgets(line, sizeof(line), file)) {
|
|
if (*line != ':') {
|
|
fprintf(stderr, "line %d doesn't start with colon\n",
|
|
lineno);
|
|
exit(1);
|
|
}
|
|
p = buf;
|
|
for (s = line+1; *s > ' '; s += 2)
|
|
*p++ = hex(s[0], lineno) << 4 | hex(s[1], lineno);
|
|
if (p-buf < 5) {
|
|
fprintf(stderr, "short record in line %d\n", lineno);
|
|
exit(1);
|
|
}
|
|
lineno++;
|
|
sum = 0;
|
|
for (t = buf; t != p-1; t++)
|
|
sum += *t;
|
|
if (0x100-sum != p[-1]) {
|
|
fprintf(stderr,
|
|
"checksum error (0x%02x vs. 0x%02x) in line %d\n",
|
|
p[-1], 0x100-sum, lineno);
|
|
exit(1);
|
|
}
|
|
switch (buf[3]) {
|
|
case 0: /* Data record */
|
|
if (p-buf != buf[0]+5) {
|
|
fprintf(stderr,
|
|
"data record of %d bytes has length %d\n",
|
|
p-buf, buf[0]);
|
|
exit(1);
|
|
}
|
|
addr = xaddr << 16 | buf[1] << 8 | buf[2];
|
|
if (last && last->addr+last->len == addr) {
|
|
last->data = realloc(last->data,
|
|
last->len+buf[0]);
|
|
if (!last->data) {
|
|
perror("realloc");
|
|
exit(1);
|
|
}
|
|
memcpy(last->data+last->len, buf+4, buf[0]);
|
|
last->len += buf[0];
|
|
break;
|
|
}
|
|
rec = malloc(sizeof(struct rec));
|
|
rec->addr = xaddr << 16 | buf[1] << 8 | buf[2];
|
|
rec->len = buf[0];
|
|
rec->data = malloc(rec->len);
|
|
if (!rec->data) {
|
|
perror("realloc");
|
|
exit(1);
|
|
}
|
|
rec->next = NULL;
|
|
memcpy(rec->data, buf+4, rec->len);
|
|
if (last)
|
|
last->next = rec;
|
|
else
|
|
recs = rec;
|
|
last = rec;
|
|
break;
|
|
case 1: /* End Of File record */
|
|
goto end;
|
|
case 4: /* Extended Linear Address record */
|
|
xaddr = buf[4] << 8 | buf[5];
|
|
break;
|
|
default:
|
|
fprintf(stderr,
|
|
"unrecognized record type 0x%02x in line %d\n",
|
|
buf[3], lineno);
|
|
exit(1);
|
|
}
|
|
}
|
|
end:
|
|
for (rec = recs; rec; rec = rec->next)
|
|
for (other = rec->next; other; other = other->next)
|
|
if (rec->addr < other->addr+other->len &&
|
|
rec->addr+rec->len > other->addr) {
|
|
fprintf(stderr,
|
|
"overlapping address ranges 0x%x+0x%x "
|
|
"and 0x%x+0x%x\n",
|
|
rec->addr, rec->len, other->addr,
|
|
other->len);
|
|
}
|
|
fclose(file);
|
|
return recs;
|
|
}
|
|
|
|
|
|
/* ----- Command-line parsing ---------------------------------------------- */
|
|
|
|
|
|
static void usage(const char *name)
|
|
{
|
|
fprintf(stderr,
|
|
"usage: %s [-n] [file.bin]\n", name);
|
|
exit(1);
|
|
}
|
|
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
const struct rec *recs = NULL;
|
|
int power = 1;
|
|
int c;
|
|
|
|
while ((c = getopt(argc, argv, "n")) != EOF)
|
|
switch (c) {
|
|
case 'n':
|
|
power = 0;
|
|
break;
|
|
default:
|
|
usage(*argv);
|
|
}
|
|
|
|
switch (argc-optind) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
recs = load_file(argv[optind]);
|
|
break;
|
|
default:
|
|
usage(*argv);
|
|
}
|
|
|
|
icsp_begin(power);
|
|
identify();
|
|
|
|
if (recs)
|
|
flash_file(recs);
|
|
else
|
|
dump_flash();
|
|
icsp_end();
|
|
|
|
return 0;
|
|
}
|