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134 lines
5.1 KiB
Plaintext
134 lines
5.1 KiB
Plaintext
--- Thu 2011-09-01 ------------------------------------------------------------
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PCB milling #1:
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- setup:
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- board is pertinax
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- locally sourced "W.T." (Taiwan) mounting tape
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- measurements:
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- board: 101.6 mm x 44.6 mm (nom. 102.0 mm x 50.0 mm)
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- defects found:
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- drill broke on first hole, due to insufficient clearance found in
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run #2. Second drill just cleared the board by sheer luck.
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- drill/mill depth too shallow
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- column cavities too wide
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- changes for next run:
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- narrow column cavities from 8.4 mm to 8.0 mm (bad idea, see below)
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PCB milling #2;
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- changes made:
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- board is FR4
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- corrected depth
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- defects found:
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- clearance insufficient (top copper damaged; endmill broke)
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- changes for next run:
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- increase clearance by 1 mm
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- future: include board thickness in gp2rml clearance calculation
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(gp2rml calculates "clearance" from the highest point in the plot,
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which for PCBs also happens to be the lowest point, and thus
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includes the board itself and the vertical overshoot. 2 mm are
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sufficient for 0.8 mm boards, but 1.6 mm boards need at least
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0.8 mm more.)
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PCB milling #3:
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- changes made:
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- corrected clearance
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- Tesa 5767 mounting tape (no longer available)
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- measurements:
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- column cavity: ~7.6 mm x 10.3 mm (nom. 8.0 x 10.4 mm)
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- board: 102.2 mm x 50.2 mm (nom. 102.0 mm x 50.0 mm)
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- "narrow tongue": 9.1 mm (nom. 9.0 mm)
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- "wide tongue": 14.1 mm (nom. 14.0 mm)
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- defects found:
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- column cavities too narrow (also in design; need 8.4 mm)
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- 100 mil header holes a little bit too small
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- 200 mil header holes much too small
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- rear edge touches wall
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- front edge very close to buttons (not sure how close)
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- changes for next run:
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- widen column cavities by 0.2 mm on each side
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- compensate tool for 0.1 mm of board deflection on each side
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--- Fri 2011-09-02 ------------------------------------------------------------
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Layout printed on #3:
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- infrastructure:
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- tried new approach of transferring both sides: instead of stapling
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the two sheets, put adhesive tape around the edges. The result is
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acceptable, but not as good as the work-intensive one side at a time
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approach used for ben-wpan.
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- battery pack for laminator control broke down mechanically. Replaced
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with adapter for obscure 500 mil pack I had laying around.
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- problems found:
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- "make it look like an accident" isn't such a good idea for the trace
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connecting the relays to 5V. I was tempted to scratch off the toner,
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thinking the pin had bled into the trace.
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- annulus around DIP pins seems too small for 35 mil holes. The holes
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are nominally only 0.5 mm, but that in turn may make them too small.
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- changes for next run:
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- make 5V relay traces go clearly for the centers of the respective pins
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- determine correct hole size for DIP
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--- Sat 2011-09-03 ------------------------------------------------------------
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Soldered #3:
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- problems found:
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- DIP copper rings were too small for easy soldering, as expected
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- cosmetic: screw-down headers (K1, K2) are very loose and end up
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visibly angled
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- cosmetic: vias between OUT opto-couplers are a bit close to the
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sockets, making them almost disappear under them. Would be nicer if
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they had more clearance.
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- MCU and DIP sockets should have orientation markings on the copper
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layer. In other news, Chip Quick is quite suitable for removing a
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misplaced 32-LQFP.
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- the footprints of the 1 W resistors (R7-R10) are way too short.
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Placed 0805 instead.
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--- Sun 2011-09-04 ------------------------------------------------------------
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Milled face plate #0:
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- setup:
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- board is pertinax
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- locally sourced "W.T." (Taiwan) mounting tape
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- measurements:
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- board: 104.0-104.1 mm x 35.1-35.6 mm (nom. 104.0 mm x 35.0 mm)
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- button hole: 12.6-12.8 mm x 11.3-11.6 mm (nom. 12.6 x 11.3 mm)
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- defects found:
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- engraving depth (0.2 mm) is a bit shallow, probably due to board
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curvature
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- got the banana jack diameter wrong: should be 8 mm, not 6 mm
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- button holes show significant deviation from tool path on lower
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edge
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- changes for next run:
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- increase engraving depth to 0.5 mm (board is 1.6 mm)
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- correct banana jack hole diameter
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Milled face plate #1:
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- changes made
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- increased engraving depth to 0.5 mm
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- increased banana jack hole diameter to 8.0 mm
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- defects found:
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- job didn't complete because board became unstuck while milling
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- the 8.0 mm hole is still a bit too tight if jack sleeve is at
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upper end of tolerance range
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- noticed that the button holes are milled last, after cutting the
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board outline. This explains the poor accuracy.
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---------------------
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(next run)
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- changes made
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- made 5V relay traces go clearly for the centers of the respective pins
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- changed DIP hole size from 0.5 mm to 0.8 mm, hole-to-copper ratio from
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2.5 to 2
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Pending:
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- widen column cavities by 0.2 mm on each side
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- consider pulling in front edge a little in buttons area
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- uncopper mounting holes (using "loop" as "if" in fped)
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- change mill nominal diameter from 35 mil to 26-27 mil
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- move vias between OUT opto-couplers 0.2 mm to the center
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- add orientation markings on copper layer for MCU and DIP sockets
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- verify 2512 footprint of 1 W resistors
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- add ground zones
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