-add nandboot to xburst-tool

-nandboot load the zImage kernel

Signed-off-by: Xiangfu Liu <xiangfu.z@gmail.com>

nandboot/include/jz4730_board.h

@@ -0,0 +1,52 @@
+/*
+ * jz4730_board.h
+ *
+ * JZ4730 board definitions.
+ *
+ * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
+ *
+ */
+#ifndef __JZ4730_BOARD_H__
+#define __JZ4730_BOARD_H__
+
+/*-------------------------------------------------------------------
+ * Frequency of the external OSC in Hz.
+ */
+#define CFG_EXTAL		12000000
+
+/*-------------------------------------------------------------------
+ * CPU speed.
+ */
+#define CFG_CPU_SPEED		336000000
+
+/*-------------------------------------------------------------------
+ * Serial console.
+ */
+#define CFG_UART_BASE		UART3_BASE
+
+#define CONFIG_BAUDRATE		9600
+
+/*-------------------------------------------------------------------
+ * SDRAM info.
+ */
+
+// SDRAM paramters
+#define CFG_SDRAM_BW16		0	/* Data bus width: 0-32bit, 1-16bit */
+#define CFG_SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
+#define CFG_SDRAM_ROW		13	/* Row address: 11 to 13 */
+#define CFG_SDRAM_COL		9	/* Column address: 8 to 12 */
+#define CFG_SDRAM_CASL		2	/* CAS latency: 2 or 3 */
+
+// SDRAM Timings, unit: ns
+#define CFG_SDRAM_TRAS		45	/* RAS# Active Time */
+#define CFG_SDRAM_RCD		20	/* RAS# to CAS# Delay */
+#define CFG_SDRAM_TPC		20	/* RAS# Precharge Time */
+#define CFG_SDRAM_TRWL		7	/* Write Latency Time */
+#define CFG_SDRAM_TREF		7812	/* Refresh period: 8192 refresh cycles/64ms */
+
+/*-------------------------------------------------------------------
+ * Linux kernel command line.
+ */
+#define CFG_CMDLINE "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw init=/etc/inittab"
+
+#endif /* __JZ4730_BOARD_H__ */

nandboot/include/jz4740_board.h

@@ -0,0 +1,57 @@
+/*
+ * jz4740_board.h
+ *
+ * JZ4740 board definitions.
+ *
+ * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
+ *
+ */
+#ifndef __JZ4740_BOARD_H__
+#define __JZ4740_BOARD_H__
+
+/*-------------------------------------------------------------------
+ * NAND Boot config code
+ */
+#define JZ4740_NANDBOOT_CFG	JZ4740_NANDBOOT_B8R3	/* NAND Boot config code */
+
+/*-------------------------------------------------------------------
+ * Frequency of the external OSC in Hz.
+ */
+#define CFG_EXTAL		12000000
+
+/*-------------------------------------------------------------------
+ * CPU speed.
+ */
+#define CFG_CPU_SPEED		336000000
+
+/*-------------------------------------------------------------------
+ * Serial console.
+ */
+#define CFG_UART_BASE		UART0_BASE
+
+#define CONFIG_BAUDRATE		57600
+
+/*-------------------------------------------------------------------
+ * SDRAM info.
+ */
+
+// SDRAM paramters
+#define CFG_SDRAM_BW16		0	/* Data bus width: 0-32bit, 1-16bit */
+#define CFG_SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
+#define CFG_SDRAM_ROW		13	/* Row address: 11 to 13 */
+#define CFG_SDRAM_COL		9	/* Column address: 8 to 12 */
+#define CFG_SDRAM_CASL		2	/* CAS latency: 2 or 3 */
+
+// SDRAM Timings, unit: ns
+#define CFG_SDRAM_TRAS		45	/* RAS# Active Time */
+#define CFG_SDRAM_RCD		20	/* RAS# to CAS# Delay */
+#define CFG_SDRAM_TPC		20	/* RAS# Precharge Time */
+#define CFG_SDRAM_TRWL		7	/* Write Latency Time */
+#define CFG_SDRAM_TREF		7812	/* Refresh period: 8192 refresh cycles/64ms */
+
+/*-------------------------------------------------------------------
+ * Linux kernel command line.
+ */
+#define CFG_CMDLINE	"mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw init=/etc/inittab"
+
+#endif /* __JZ4740_BOARD_H__ */

nandboot/include/nand.h

@@ -0,0 +1,70 @@
+/*
+ * nand.h
+ *
+ * Standard NAND Flash definitions.
+ */
+#ifndef __NAND_H__
+#define __NAND_H__
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_RNDOUT		5
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_READOOB	0x50
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_STATUS_MULTI	0x71
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_RNDIN		0x85
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_RESET		0xff
+
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART	0x30
+#define NAND_CMD_RNDOUTSTART	0xE0
+#define NAND_CMD_CACHEDPROG	0x15
+
+/* Status bits */
+#define NAND_STATUS_FAIL	0x01
+#define NAND_STATUS_FAIL_N1	0x02
+#define NAND_STATUS_TRUE_READY	0x20
+#define NAND_STATUS_READY	0x40
+#define NAND_STATUS_WP		0x80
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA	0x98
+#define NAND_MFR_SAMSUNG	0xec
+#define NAND_MFR_FUJITSU	0x04
+#define NAND_MFR_NATIONAL	0x8f
+#define NAND_MFR_RENESAS	0x07
+#define NAND_MFR_STMICRO	0x20
+#define NAND_MFR_HYNIX		0xad
+#define NAND_MFR_MICRON		0x2c
+
+/*
+ * NAND parameter struct
+ */
+struct nand_param {
+	unsigned int bus_width;		/* data bus width: 8-bit/16-bit */
+	unsigned int row_cycle;		/* row address cycles: 2/3 */
+	unsigned int page_size;		/* page size in bytes: 512/2048 */
+	unsigned int oob_size;		/* oob size in bytes: 16/64 */
+	unsigned int page_per_block;	/* pages per block: 32/64/128 */
+	unsigned int bad_block_pos;	/* bad block pos in oob: 0/5 */
+};
+
+/*
+ * NAND routines
+ */
+extern void nand_enable(void);
+extern void nand_disable(void);
+extern int block_is_bad(struct nand_param *nandp, int block);
+extern int nand_read_page(struct nand_param *nandp, int block, int page, unsigned char *dst);
+
+#endif /* __NAND_H__ */

nandboot/include/types.h

@@ -0,0 +1,8 @@
+#ifndef __TYPES_H__
+#define __TYPES_H__
+
+#define u32 unsigned int
+#define u16 unsigned short
+#define u8 unsigned char
+
+#endif /* __TYPES_H__ */