From 19ce238122ea626e074762dbb31379ff84e38d33 Mon Sep 17 00:00:00 2001 From: Xiangfu Liu Date: Thu, 10 Jun 2010 14:53:20 +0800 Subject: [PATCH] [xbboot] just some cleanup, make the stage1 size less then 8KB --- xbboot/target-stage1/board-jz4760.c | 341 ++++++++++++++-------------- xbboot/target-stage1/board-jz4760.h | 2 - 2 files changed, 165 insertions(+), 178 deletions(-) diff --git a/xbboot/target-stage1/board-jz4760.c b/xbboot/target-stage1/board-jz4760.c index 68b3bea..bffeebb 100644 --- a/xbboot/target-stage1/board-jz4760.c +++ b/xbboot/target-stage1/board-jz4760.c @@ -154,20 +154,17 @@ void pll_init_4760() | CPM_CPPCR_PLLEN; /* enable PLL */ /* init PLL */ - serial_puts("cfcr = "); - serial_put_hex(cfcr); - serial_puts("plcr1 = "); - serial_put_hex(plcr1); - REG_CPM_CPCCR = cfcr; REG_CPM_CPPCR = plcr1; while(!(REG_CPM_CPPSR & (1 << 29))); +#ifdef DEBUG serial_puts("REG_CPM_CPCCR = "); serial_put_hex(REG_CPM_CPCCR); serial_puts("REG_CPM_CPPCR = "); serial_put_hex(REG_CPM_CPPCR); +#endif } #if (defined(CONFIG_SDRAM_MDDR)||defined(CONFIG_SDRAM_DDR1)||defined(CONFIG_SDRAM_DDR2)) @@ -228,10 +225,8 @@ static int dma_check_result(void *src, void *dst, int size,int print_flag) data_expect = gen_verify_data(i); dsrc = REG32(addr1); ddst = REG32(addr2); - if ((dsrc != data_expect) - || (ddst != data_expect)) { -#if 1 - //serial_puts("wrong data at34:"); + if ((dsrc != data_expect) || (ddst != data_expect)) { +#if DEBUG serial_put_hex(addr2); serial_puts("data:"); serial_put_hex(data_expect); @@ -239,7 +234,6 @@ static int dma_check_result(void *src, void *dst, int size,int print_flag) serial_put_hex(dsrc); serial_puts("dst"); serial_put_hex(ddst); - #endif err = 1; if(!print_flag) @@ -249,11 +243,10 @@ static int dma_check_result(void *src, void *dst, int size,int print_flag) addr1 += 4; addr2 += 4; } -// serial_puts("check passed!"); return err; } -#if 0 +#if DEBUG void dump_jz_dma_channel(unsigned int dmanr) { @@ -284,7 +277,6 @@ void dump_jz_dma_channel(unsigned int dmanr) serial_puts(" DMADBR = "); serial_put_hex(REG_DMAC_DMADBR(dmanr/HALF_DMA_NUM)); } -#endif void dma_nodesc_test_single(int dma_chan, int dma_src_addr, int dma_dst_addr, int size) { @@ -304,6 +296,140 @@ void dma_nodesc_test_single(int dma_chan, int dma_src_addr, int dma_dst_addr, in REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; } +static void ddrc_regs_print(void) +{ + serial_puts("\nDDRC REGS:\n"); + serial_puts("REG_DDRC_ST \t\t="); + serial_put_hex(REG_DDRC_ST); + serial_puts("REG_DDRC_CFG \t\t="); + serial_put_hex( REG_DDRC_CFG); + serial_puts("REG_DDRC_CTRL \t\t="); + serial_put_hex(REG_DDRC_CTRL); + serial_puts("REG_DDRC_LMR \t\t="); + serial_put_hex(REG_DDRC_LMR); + serial_puts("REG_DDRC_TIMING1 \t="); + serial_put_hex(REG_DDRC_TIMING1); + serial_puts("REG_DDRC_TIMING2 \t="); + serial_put_hex(REG_DDRC_TIMING2); + serial_puts("REG_DDRC_REFCNT \t\t="); + serial_put_hex(REG_DDRC_REFCNT); + serial_puts("REG_DDRC_DQS \t\t="); + serial_put_hex(REG_DDRC_DQS); + serial_puts("REG_DDRC_DQS_ADJ \t="); + serial_put_hex(REG_DDRC_DQS_ADJ); + serial_puts("REG_DDRC_MMAP0 \t\t="); + serial_put_hex(REG_DDRC_MMAP0); + serial_puts("REG_DDRC_MMAP1 \t\t="); + serial_put_hex(REG_DDRC_MMAP1); + serial_puts("REG_DDRC_MDELAY \t\t="); + serial_put_hex(REG_DDRC_MDELAY); + serial_puts("REG_EMC_PMEMPS2 \t\t="); + serial_put_hex(REG_EMC_PMEMPS2); +} + +static int dma_memcpy_test(int channle_0, int channle_1) { + int i, err = 0, banks; + unsigned int addr, DDR_DMA0_SRC, DDR_DMA0_DST, DDR_DMA1_SRC, DDR_DMA1_DST; + volatile unsigned int tmp; + register unsigned int cpu_clk; + long int memsize, banksize, testsize; + int channel; + +#ifndef CONFIG_DDRC + banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS); +#else + banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN); +#endif + memsize = initdram(0); + + banksize = memsize/banks; + testsize = 4096; + + DDR_DMA0_SRC = DDR_DMA_BASE + banksize*0; + DDR_DMA0_DST = DDR_DMA_BASE + banksize*0 + testsize; + DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2; + DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3; + + cpu_clk = ARG_CPU_SPEED; + +// for(channel = 0; channel < MAX_DMA_NUM; channel++) { + + // MDMA + REG_MDMAC_DMACR = DMAC_DMACR_DMAE; + // COMMON DMA + //REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */ + //REG_DMAC_DMACR(1) = DMAC_DMACR_DMAE; /* global DMA enable bit */ + + // Write A0 + addr = DDR_DMA0_SRC; + + for (i = 0; i < testsize; i += 4) { + *(volatile unsigned int *)addr = (i/4*0x11111111); + //*(volatile unsigned int *)addr = addr; + addr += 4; + } + + // Write A2 + addr = DDR_DMA1_SRC; + for (i = 0; i < testsize; i += 4) { + *(volatile unsigned int *)addr = (i/4*0x11111111); + //*(volatile unsigned int *)addr = addr; + addr += 4; + } + + + // MDMA + REG_MDMAC_DMACR = 0; + // COMMON DMA + //REG_DMAC_DMACR(0) = 0; + //REG_DMAC_DMACR(1) = 0; + + /* Init target buffer */ + jzmemset((void *)DDR_DMA0_DST, 0, testsize); + jzmemset((void *)DDR_DMA1_DST, 0, testsize); + + // Set DMA1 for moving data from A0 -> A1 + dma_data_move(channle_0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize, DMAC_DCMD_DS_32BYTE); + // Set DMA2 for moving data from A2 -> A3 + dma_data_move(channle_1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize, DMAC_DCMD_DS_64BYTE); + + // Start DMA0 + REG_DMAC_DCCSR(0) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; + // Wait for DMA0 finishing + while(REG_DMAC_DTCR(0)); + + // Start DMA1 + REG_DMAC_DCCSR(1) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; + + // Read from A1 & check + err = check_result((void *)DDR_DMA0_SRC, (void *)DDR_DMA0_DST, testsize); + REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */ + if (err != 0) { + serial_puts("DMA0: err!\n"); + //return err; + } + + // Wait for DMA1 finishing + while(REG_DMAC_DTCR(1)); + + // Read from A3 & check + err = check_result((void *)DDR_DMA1_SRC, (void *)DDR_DMA1_DST, testsize); + REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */ + if (err != 0) { + serial_puts("DMA1: err!\n"); + //return err; + } + + serial_puts("TEST PASSED\n\n"); + + tmp = (cpu_clk / 1000000) * 1; + while (tmp--); +// } + return err; +} + +#endif + void dma_nodesc_test(int dma_chan, int dma_src_addr, int dma_dst_addr, int size) { @@ -386,8 +512,8 @@ for(times = 0; times < banks; times++) { dma_nodesc_test(0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize); #endif #ifdef DMA_CHANNEL1_EN - //jzmemset((void *)DDR_DMA1_DST, 0, testsize); - //dma_nodesc_test(1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize); + jzmemset((void *)DDR_DMA1_DST, 0, testsize); + dma_nodesc_test(1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize); #endif REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */ @@ -427,38 +553,6 @@ for(times = 0; times < banks; times++) { } return err; } -#if 0 -static void ddrc_regs_print(void) -{ - serial_puts("\nDDRC REGS:\n"); - serial_puts("REG_DDRC_ST \t\t="); - serial_put_hex(REG_DDRC_ST); - serial_puts("REG_DDRC_CFG \t\t="); - serial_put_hex( REG_DDRC_CFG); - serial_puts("REG_DDRC_CTRL \t\t="); - serial_put_hex(REG_DDRC_CTRL); - serial_puts("REG_DDRC_LMR \t\t="); - serial_put_hex(REG_DDRC_LMR); - serial_puts("REG_DDRC_TIMING1 \t="); - serial_put_hex(REG_DDRC_TIMING1); - serial_puts("REG_DDRC_TIMING2 \t="); - serial_put_hex(REG_DDRC_TIMING2); - serial_puts("REG_DDRC_REFCNT \t\t="); - serial_put_hex(REG_DDRC_REFCNT); - serial_puts("REG_DDRC_DQS \t\t="); - serial_put_hex(REG_DDRC_DQS); - serial_puts("REG_DDRC_DQS_ADJ \t="); - serial_put_hex(REG_DDRC_DQS_ADJ); - serial_puts("REG_DDRC_MMAP0 \t\t="); - serial_put_hex(REG_DDRC_MMAP0); - serial_puts("REG_DDRC_MMAP1 \t\t="); - serial_put_hex(REG_DDRC_MMAP1); - serial_puts("REG_DDRC_MDELAY \t\t="); - serial_put_hex(REG_DDRC_MDELAY); - serial_puts("REG_EMC_PMEMPS2 \t\t="); - serial_put_hex(REG_EMC_PMEMPS2); -} -#endif void ddr_mem_init(int msel, int hl, int tsel, int arg) { @@ -743,107 +837,7 @@ static int check_result(void *src, void *dst, int size) return err; } -static int dma_memcpy_test(int channle_0, int channle_1) { - int i, err = 0, banks; - unsigned int addr, DDR_DMA0_SRC, DDR_DMA0_DST, DDR_DMA1_SRC, DDR_DMA1_DST; - volatile unsigned int tmp; - register unsigned int cpu_clk; - long int memsize, banksize, testsize; - int channel; - -#ifndef CONFIG_DDRC - banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS); -#else - banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN); #endif - memsize = initdram(0); - - banksize = memsize/banks; - testsize = 4096; - - DDR_DMA0_SRC = DDR_DMA_BASE + banksize*0; - DDR_DMA0_DST = DDR_DMA_BASE + banksize*0 + testsize; - DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2; - DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3; - - cpu_clk = ARG_CPU_SPEED; - -// for(channel = 0; channel < MAX_DMA_NUM; channel++) { - - // MDMA - REG_MDMAC_DMACR = DMAC_DMACR_DMAE; - // COMMON DMA - //REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */ - //REG_DMAC_DMACR(1) = DMAC_DMACR_DMAE; /* global DMA enable bit */ - - // Write A0 - addr = DDR_DMA0_SRC; - - for (i = 0; i < testsize; i += 4) { - *(volatile unsigned int *)addr = (i/4*0x11111111); - //*(volatile unsigned int *)addr = addr; - addr += 4; - } - - // Write A2 - addr = DDR_DMA1_SRC; - for (i = 0; i < testsize; i += 4) { - *(volatile unsigned int *)addr = (i/4*0x11111111); - //*(volatile unsigned int *)addr = addr; - addr += 4; - } - - - // MDMA - REG_MDMAC_DMACR = 0; - // COMMON DMA - //REG_DMAC_DMACR(0) = 0; - //REG_DMAC_DMACR(1) = 0; - - /* Init target buffer */ - jzmemset((void *)DDR_DMA0_DST, 0, testsize); - jzmemset((void *)DDR_DMA1_DST, 0, testsize); - - // Set DMA1 for moving data from A0 -> A1 - dma_data_move(channle_0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize, DMAC_DCMD_DS_32BYTE); - // Set DMA2 for moving data from A2 -> A3 - dma_data_move(channle_1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize, DMAC_DCMD_DS_64BYTE); - - // Start DMA0 - REG_DMAC_DCCSR(0) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; - // Wait for DMA0 finishing - while(REG_DMAC_DTCR(0)); - - // Start DMA1 - REG_DMAC_DCCSR(1) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; - - // Read from A1 & check - err = check_result((void *)DDR_DMA0_SRC, (void *)DDR_DMA0_DST, testsize); - REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */ - if (err != 0) { - serial_puts("DMA0: err!\n"); - //return err; - } - - // Wait for DMA1 finishing - while(REG_DMAC_DTCR(1)); - - // Read from A3 & check - err = check_result((void *)DDR_DMA1_SRC, (void *)DDR_DMA1_DST, testsize); - REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */ - if (err != 0) { - serial_puts("DMA1: err!\n"); - //return err; - } - - serial_puts("TEST PASSED\n\n"); - - tmp = (cpu_clk / 1000000) * 1; - while (tmp--); -// } - return err; -} -#endif/* CONFIG_SDRAM_MDDR */ #if (defined(CONFIG_SDRAM_MDDR) || defined(CONFIG_SDRAM_DDR1) || defined(CONFIG_SDRAM_DDR2)) #define DEF_DDR_CVT 0 @@ -852,51 +846,50 @@ unsigned int testall = 0; /* DDR sdram init */ void sdram_init_4760(void) { - serial_puts("REG_CPM_CPCCR = "); - serial_put_hex(REG_CPM_CPCCR); - serial_puts("REG_CPM_CPPCR = "); - serial_put_hex(REG_CPM_CPPCR); //add driver power REG_EMC_PMEMPS2 |= (3 << 18); REG_DMAC_DMADCKE(0) = 0x3f; REG_DMAC_DMADCKE(1) = 0x3f; int i, num = 0, tsel = 0, msel, hl; -#if defined(CONFIG_FPGA) - int cvt = DEF_DDR_CVT, cvt_cnt0 = 0, cvt_cnt1 = 1, max = 0, max0 = 0, max1 = 0, min0 = 0, min1 = 0, tsel0 = 0, tsel1 = 0; -#endif volatile unsigned int tmp_cnt; register unsigned int tmp, cpu_clk, mem_clk, ddr_twr, ns, ns_int; - register unsigned int ddrc_timing1_reg=0, ddrc_timing2_reg=0, init_ddrc_refcnt=0, init_ddrc_dqs=0, init_ddrc_ctrl=0; + register unsigned int ddrc_timing1_reg=0, ddrc_timing2_reg=0; + register unsigned int init_ddrc_refcnt=0, init_ddrc_dqs=0, init_ddrc_ctrl=0; + + register unsigned int memsize, ddrc_mmap0_reg, ddrc_mmap1_reg; + register unsigned int mem_base0, mem_base1, mem_mask0, mem_mask1; + #if defined(CONFIG_FPGA) + int cvt = DEF_DDR_CVT, cvt_cnt0 = 0, cvt_cnt1 = 1; + int max = 0, max0 = 0, max1 = 0, min0 = 0, min1 = 0; + int tsel0 = 0, tsel1 = 0; struct ddr_delay_sel_t ddr_delay_sel[] = { {0, 1}, {0, 0}, {1, 1}, {1, 0}, {2, 1}, {2, 0}, {3, 1}, {3, 0} }; #endif - register unsigned int memsize, ddrc_mmap0_reg, ddrc_mmap1_reg, mem_base0, mem_base1, mem_mask0, mem_mask1; testall = 0; + cpu_clk = ARG_CPU_SPEED; + #ifdef DEBUG ddrc_regs_print(); #endif - cpu_clk = ARG_CPU_SPEED; - #if defined(CONFIG_FPGA) mem_clk = ARG_EXTAL / CFG_DIV; -#else - mem_clk = __cpm_get_mclk(); -#endif - - serial_puts("mem_clk = "); - serial_put_hex(mem_clk); -#if defined(CONFIG_FPGA) ns = 7; #else + mem_clk = __cpm_get_mclk(); ns = 1000000000 / mem_clk; /* ns per tck ns <= real value */ #endif +#ifdef DEBUG + serial_puts("mem_clk = "); + serial_put_hex(mem_clk); +#endif + /* ACTIVE to PRECHARGE command period */ tmp = (DDR_tRAS%ns == 0) ? (DDR_tRAS/ns) : (DDR_tRAS/ns+1); if (tmp < 1) tmp = 1; @@ -1047,20 +1040,12 @@ void sdram_init_4760(void) while (tmp_cnt--); { - //ddrc_regs_print(); int result = 0; serial_puts("ddr test:"); result = ddr_dma_test(0); if(result != 0) - { - serial_puts("ddr test fail\n"); - } - else - { - serial_puts("ddr test ok\n"); - } - -#if 0 + serial_puts("FAIL!\n"); +#if DEBUG serial_puts("result:"); serial_put_hex(result); serial_put_hex(num); @@ -1083,15 +1068,17 @@ void sdram_init_4760(void) break; } if (tsel == 3 && num == 0) - serial_puts("\n\nDDR INIT ERROR: can't find a suitable mask delay.\n"); + serial_puts("DDR INIT ERROR\n"); /* can't find a suitable mask delay. */ index = 0; for (i = 0; i < num; i++) { index += mem_index[i]; serial_put_hex(mem_index[i]); } +#ifdef DEBUG serial_puts("index-1:"); serial_put_hex(index); +#endif if (num) index /= num; @@ -1101,12 +1088,14 @@ void sdram_init_4760(void) hl = ((index/2)&1)^1; quar = index&1; +#ifdef DEBUG serial_puts("tsel"); serial_put_hex(tsel); serial_puts("num"); serial_put_hex(num); serial_puts("index-2:"); serial_put_hex(index); +#endif /* reset ddrc_controller */ REG_DDRC_CTRL = DDRC_CTRL_RESET; diff --git a/xbboot/target-stage1/board-jz4760.h b/xbboot/target-stage1/board-jz4760.h index 67752d9..cf96abd 100644 --- a/xbboot/target-stage1/board-jz4760.h +++ b/xbboot/target-stage1/board-jz4760.h @@ -22,8 +22,6 @@ */ #define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/ -#define CONFIG_MOBILE_SDRAM 1 /* use mobile sdram */ - #ifndef CONFIG_MOBILE_SDRAM // SDRAM paramters #define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */