diff --git a/xbboot/target-stage1/board-jz4760.c b/xbboot/target-stage1/board-jz4760.c
index df2dbad..cc0645b 100644
--- a/xbboot/target-stage1/board-jz4760.c
+++ b/xbboot/target-stage1/board-jz4760.c
@@ -122,14 +122,13 @@ void pll_init_4760()
 		0, 0, 1, 2, 3, 0, 4, 0, 5
 	};
 
-     /** divisors, 
+	/** divisors, 
 	 *  for jz4760 ,I:H:H2:P:M:S.
-	 *  DIV should be one of [1, 2, 3, 4, 6, 8]
-     */
-//	int div[6] = {1, 2, 4, 4, 4, 4};
-//	int div[6] = {1, 3, 6, 6, 6, 6};
-	int div[6] = {1, 2, 2, 2, 2, 2};
-	int pllout2;
+	 *  DIV should be one of [1, 2, 3, 4, 6, 8] like:
+	 *  div[6] = {1, 2, 2, 2, 2, 2};
+	 *  div[6] = {1, 3, 6, 6, 6, 6};
+	 */
+	int div[6] = {1, 2, 4, 4, 4, 4};
 
 	cfcr = 	CPM_CPCCR_PCS |
 		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | 
@@ -152,11 +151,9 @@ void pll_init_4760()
 #endif
 	cfcr |= CPM_CPCCR_CE;
 
-	pllout2 = (cfcr & CPM_CPCCR_PCS) ? ARG_CPU_SPEED : (ARG_CPU_SPEED / 2);
-
 	plcr1 = pll_calc_m_n_od(ARG_CPU_SPEED, ARG_EXTAL);
 	plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT)	/* PLL stable time */
-		 | CPM_CPPCR_PLLEN;             /* enable PLL */
+		| CPM_CPPCR_PLLEN;             /* enable PLL */
 
 	/* init PLL */
 	REG_CPM_CPCCR = cfcr;
diff --git a/xbboot/target-stage1/stage1.c b/xbboot/target-stage1/stage1.c
index e9c9cda..ddac451 100644
--- a/xbboot/target-stage1/stage1.c
+++ b/xbboot/target-stage1/stage1.c
@@ -43,8 +43,8 @@ void load_args_4760()
 	ARG_UART_BAUD = 57600;
 	ARG_BUS_WIDTH_16 = * (int *)0x80002014;
 	ARG_BANK_ADDR_2BIT = 4;
-	ARG_ROW_ADDR = 12;
-	ARG_COL_ADDR = 9;
+	ARG_ROW_ADDR = 13;
+	ARG_COL_ADDR = 10;
 }