From 33ee0f3ae43b10d7e24577ee9d94ce81b7f1adb3 Mon Sep 17 00:00:00 2001 From: Andy Green Date: Fri, 28 Nov 2008 10:16:36 +0000 Subject: [PATCH] add-gta03-pmu-533MHz-init.patch Get GTA03 into 533MHz / 133MHz memory bus goodness Signed-off-by: Andy Green --- qiboot/src/gta03/gta03.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/qiboot/src/gta03/gta03.c b/qiboot/src/gta03/gta03.c index 1738856..cd00731 100644 --- a/qiboot/src/gta03/gta03.c +++ b/qiboot/src/gta03/gta03.c @@ -18,6 +18,10 @@ static const struct board_variant board_variants[] = { void port_init_gta03(void) { + unsigned int * MPLLCON = (unsigned int *)0x4c000004; + unsigned int * UPLLCON = (unsigned int *)0x4c000008; + unsigned int * CLKDIVN = (unsigned int *)0x4c000014; + //CAUTION:Follow the configuration order for setting the ports. // 1) setting value(GPnDAT) // 2) setting control register (GPnCON) @@ -116,7 +120,34 @@ void port_init_gta03(void) rGPJCON = 0x02AAAAAA; rGPJUP = 0x1FFFF; - serial_init_115200_s3c24xx(GTA03_DEBUG_UART, 33 /*MHz PCLK */); + /* + * We have to talk to the PMU a little bit + */ + + /* push DOWN1 (CPU Core rail) to 1.7V, allowing 533MHz */ + i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, 0x1e, 0x2b); + + /* change CPU clocking to 533MHz 1:4:8 */ + + /* clock divide 1:4:8 - do it first */ + *CLKDIVN = 5; + /* configure UPLL */ + *UPLLCON = ((88 << 12) + (4 << 4) + 2); + /* Magic delay: Page 7-19, seven nops between UPLL and MPLL */ + asm __volatile__ ( + "nop\n"\ + "nop\n"\ + "nop\n"\ + "nop\n"\ + "nop\n"\ + "nop\n"\ + "nop\n"\ + ); + /* configure MPLL */ + *MPLLCON = ((169 << 12) + (2 << 4) + 1); + + + serial_init_115200_s3c24xx(GTA03_DEBUG_UART, 50 /*MHz PCLK */); } /**