mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2024-11-01 16:25:20 +02:00
add read nand configure
This commit is contained in:
xiangfu
parent
6082b4557d
commit
392d2bb3fc
104
flash-tool/cmd.c
104
flash-tool/cmd.c
@ -39,7 +39,7 @@ extern char com_argv[MAX_ARGC][MAX_COMMAND_LENGTH];
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static struct nand_in_t nand_in;
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static struct nand_out_t nand_out;
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static struct fw_args_t fw_args;
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static struct hand_t hand;
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unsigned int total_size;
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unsigned char code_buf[4 * 512 * 1024];
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unsigned char cs[16];
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@ -47,23 +47,37 @@ unsigned char cs[16];
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static int parse_configure(char * file_path)
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{
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cfg_opt_t opts[] = {
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CFG_SIMPLE_INT("EXTCLK", &fw_args.ext_clk),
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CFG_SIMPLE_INT("CPUSPEED", &fw_args.cpu_speed),
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CFG_SIMPLE_INT("PHMDIV", &fw_args.phm_div),
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CFG_SIMPLE_INT("BOUDRATE", &fw_args.boudrate),
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CFG_SIMPLE_INT("USEUART", &fw_args.use_uart),
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CFG_SIMPLE_INT("EXTCLK", &hand.fw_args.ext_clk),
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CFG_SIMPLE_INT("CPUSPEED", &hand.fw_args.cpu_speed),
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CFG_SIMPLE_INT("PHMDIV", &hand.fw_args.phm_div),
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CFG_SIMPLE_INT("BOUDRATE", &hand.fw_args.boudrate),
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CFG_SIMPLE_INT("USEUART", &hand.fw_args.use_uart),
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CFG_SIMPLE_INT("BUSWIDTH", &fw_args.bus_width),
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CFG_SIMPLE_INT("BANKS", &fw_args.bank_num),
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CFG_SIMPLE_INT("ROWADDR", &fw_args.row_addr),
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CFG_SIMPLE_INT("COLADDR", &fw_args.col_addr),
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CFG_SIMPLE_INT("BUSWIDTH", &hand.fw_args.bus_width),
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CFG_SIMPLE_INT("BANKS", &hand.fw_args.bank_num),
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CFG_SIMPLE_INT("ROWADDR", &hand.fw_args.row_addr),
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CFG_SIMPLE_INT("COLADDR", &hand.fw_args.col_addr),
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CFG_SIMPLE_INT("ISMOBILE", &fw_args.is_mobile),
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CFG_SIMPLE_INT("ISBUSSHARE", &fw_args.is_busshare),
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CFG_SIMPLE_INT("DEBUGOPS", &fw_args.debug_ops),
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CFG_SIMPLE_INT("PINNUM", &fw_args.pin_num),
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CFG_SIMPLE_INT("START", &fw_args.start),
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CFG_SIMPLE_INT("SIZE", &fw_args.size),
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CFG_SIMPLE_INT("ISMOBILE", &hand.fw_args.is_mobile),
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CFG_SIMPLE_INT("ISBUSSHARE", &hand.fw_args.is_busshare),
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CFG_SIMPLE_INT("DEBUGOPS", &hand.fw_args.debug_ops),
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CFG_SIMPLE_INT("PINNUM", &hand.fw_args.pin_num),
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CFG_SIMPLE_INT("START", &hand.fw_args.start),
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CFG_SIMPLE_INT("SIZE", &hand.fw_args.size),
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CFG_SIMPLE_INT("NAND_BUSWIDTH", &hand.nand_bw),
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CFG_SIMPLE_INT("NAND_ROWCYCLES", &hand.nand_rc),
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CFG_SIMPLE_INT("NAND_PAGESIZE", &hand.nand_ps),
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CFG_SIMPLE_INT("NAND_PAGEPERBLOCK", &hand.nand_ppb),
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CFG_SIMPLE_INT("NAND_FORCEERASE", &hand.nand_force_erase),
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CFG_SIMPLE_INT("NAND_OOBSIZE", &hand.nand_os),
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CFG_SIMPLE_INT("NAND_ECCPOS", &hand.nand_eccpos),
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CFG_SIMPLE_INT("NAND_BADBLACKPOS", &hand.nand_bbpos),
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CFG_SIMPLE_INT("NAND_BADBLACKPAGE", &hand.nand_bbpage),
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CFG_SIMPLE_INT("NAND_PLANENUM", &hand.nand_plane),
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CFG_SIMPLE_INT("NAND_BCHBIT", &hand.nand_bchbit),
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CFG_SIMPLE_INT("NAND_WPPIN", &hand.nand_wppin),
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CFG_SIMPLE_INT("NAND_BLOCKPERCHIP", &hand.nand_bbpage),
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CFG_END()
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};
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@ -74,18 +88,18 @@ static int parse_configure(char * file_path)
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return -1;
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cfg_free(cfg);
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fw_args.cpu_id = 0x4740;
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if (fw_args.bus_width == 32)
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fw_args.bus_width = 0 ;
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hand.fw_args.cpu_id = 0x4740;
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if (hand.fw_args.bus_width == 32)
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hand.fw_args.bus_width = 0 ;
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else
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fw_args.bus_width = 1 ;
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fw_args.bank_num = fw_args.bank_num / 4;
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fw_args.cpu_speed = fw_args.cpu_speed / fw_args.ext_clk;
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hand.fw_args.bus_width = 1 ;
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hand.fw_args.bank_num = hand.fw_args.bank_num / 4;
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hand.fw_args.cpu_speed = hand.fw_args.cpu_speed / hand.fw_args.ext_clk;
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total_size = (unsigned int)
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(2 << (fw_args.row_addr + fw_args.col_addr - 1)) * 2
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* (fw_args.bank_num + 1) * 2
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* (2 - fw_args.bus_width);
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(2 << (hand.fw_args.row_addr + hand.fw_args.col_addr - 1)) * 2
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* (hand.fw_args.bank_num + 1) * 2
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* (2 - hand.fw_args.bus_width);
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return 1;
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}
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@ -94,33 +108,33 @@ int check_dump_cfg()
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{
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printf("\n Now checking whether all configure args valid: ");
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/* check PLL */
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if (fw_args.ext_clk > 27 || fw_args.ext_clk < 12 ) {
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if (hand.fw_args.ext_clk > 27 || hand.fw_args.ext_clk < 12 ) {
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printf("\n EXTCLK setting invalid!");
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return 0;
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}
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if (fw_args.phm_div > 32 || fw_args.ext_clk < 2 ) {
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if (hand.fw_args.phm_div > 32 || hand.fw_args.ext_clk < 2 ) {
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printf("\n PHMDIV setting invalid!");
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return 0;
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}
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if ( (fw_args.cpu_speed * fw_args.ext_clk ) % 12 != 0 ) {
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if ( (hand.fw_args.cpu_speed * hand.fw_args.ext_clk ) % 12 != 0 ) {
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printf("\n CPUSPEED setting invalid!");
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return 0;
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}
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/* check SDRAM */
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if (fw_args.bus_width > 1 ) {
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if (hand.fw_args.bus_width > 1 ) {
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printf("\n SDRAMWIDTH setting invalid!");
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return 0;
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}
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if (fw_args.bank_num > 1 ) {
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if (hand.fw_args.bank_num > 1 ) {
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printf("\n BANKNUM setting invalid!");
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return 0;
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}
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if (fw_args.row_addr > 13 && fw_args.row_addr < 11 ) {
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if (hand.fw_args.row_addr > 13 && hand.fw_args.row_addr < 11 ) {
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printf("\n ROWADDR setting invalid!");
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return 0;
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}
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if (fw_args.col_addr > 13 && fw_args.col_addr < 11 ) {
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if (hand.fw_args.col_addr > 13 && hand.fw_args.col_addr < 11 ) {
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printf("\n COLADDR setting invalid!");
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return 0;
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}
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@ -149,14 +163,14 @@ int check_dump_cfg()
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} */
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printf("\n Current device information:");
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printf(" CPU is Jz%x",fw_args.cpu_id);
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printf(" CPU is Jz%x",hand.fw_args.cpu_id);
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printf("\n Crystal work at %dMHz, the CCLK up to %dMHz and PMH_CLK up to %dMHz",
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fw_args.ext_clk,
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(unsigned int)fw_args.cpu_speed * fw_args.ext_clk,
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((unsigned int)fw_args.cpu_speed * fw_args.ext_clk) / fw_args.phm_div);
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hand.fw_args.ext_clk,
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(unsigned int)hand.fw_args.cpu_speed * hand.fw_args.ext_clk,
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((unsigned int)hand.fw_args.cpu_speed * hand.fw_args.ext_clk) / hand.fw_args.phm_div);
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printf("\n Total SDRAM size is %d MB, work in %d bank and %d bit mode",
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total_size / 0x100000, 2 * (fw_args.bank_num + 1), 16 * (2 - fw_args.bus_width));
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total_size / 0x100000, 2 * (hand.fw_args.bank_num + 1), 16 * (2 - hand.fw_args.bus_width));
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/* printf("\n Nand page size %d, ECC offset %d, ",
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Hand.nand_ps,Hand.nand_eccpos);
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@ -208,7 +222,7 @@ static int load_file(struct ingenic_dev *ingenic_dev, const char *file_path)
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goto close;
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}
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memcpy(ingenic_dev->file_buff + 8, &fw_args, sizeof(struct fw_args_t));
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memcpy(ingenic_dev->file_buff + 8, &hand.fw_args, sizeof(struct fw_args_t));
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res = 1;
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@ -225,7 +239,7 @@ int boot(char *stage1_path, char *stage2_path, char *config_path ){
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int status;
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memset(&ingenic_dev, 0, sizeof(struct ingenic_dev));
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memset(&fw_args, 0, sizeof(struct fw_args_t));
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memset(&hand.fw_args, 0, sizeof(struct fw_args_t));
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if (parse_configure(config_path) < 1)
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goto out;
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@ -237,19 +251,19 @@ int boot(char *stage1_path, char *stage2_path, char *config_path ){
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switch (status) {
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case 1: /* Jz4740v1 */
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status = 0;
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fw_args.cpu_id = 0x4740;
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hand.fw_args.cpu_id = 0x4740;
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break;
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case 2: /* Jz4750v1 */
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status = 0;
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fw_args.cpu_id = 0x4750;
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hand.fw_args.cpu_id = 0x4750;
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break;
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case 3: /* Boot4740 */
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status = 1;
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fw_args.cpu_id = 0x4740;
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hand.fw_args.cpu_id = 0x4740;
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break;
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case 4: /* Boot4750 */
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status = 1;
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fw_args.cpu_id = 0x4750;
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hand.fw_args.cpu_id = 0x4750;
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break;
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default:
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goto out;
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@ -331,9 +345,9 @@ int nprog(void)
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printf("%s", help);
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#if 0
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if (Hand.nand_plane > 1)
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/* API_Nand_Program_File_Planes(&nand_in,&nand_out,com_argv[2]); */
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/* API_Nand_Program_File_Planes(&nand_in,&nand_out, image_file); */
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else
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/* API_Nand_Program_File(&nand_in,&nand_out,com_argv[2]); */
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/* API_Nand_Program_File(&nand_in,&nand_out, image_file); */
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printf("\n Flash check result:");
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for (i = 0; i < 16; i++)
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@ -36,21 +36,19 @@ ISBUSSHARE = 1 #Define whether SDRAM bus share with NAND 1:shared 0:unshared
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DEBUGOPS = 0
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# [NAND]
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# BUSWIDTH = 8 #The width of the NAND flash chip in bits (8|16|32)
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# ROWCYCLES = 3 #The row address cycles (2|3)
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# PAGESIZE = 2048 #The page size of the NAND chip in bytes(512|2048|4096)
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# PAGEPERBLOCK = 128 #The page number per block
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# FORCEERASE = 1 #The force to erase flag (0|1)
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# OOBSIZE = 64 #oob size in byte
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# ECCPOS = 6 #Specify the ECC offset inside the oob data (0-[oobsize-1])
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# BADBLACKPOS = 0 #Specify the badblock flag offset inside the oob (0-[oobsize-1])
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# BADBLACKPAGE = 127 #Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
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# PLANENUM = 1 #The planes number of target nand flash
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# BCHBIT = 4 #Specify the hardware BCH algorithm for 4750 (4|8)
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# WPPIN = 0 #Specify the write protect pin number
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# BLOCKPERCHIP = 0 #Specify the block number per chip,0 means ignore
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# [END]
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NAND_BUSWIDTH = 8 #The width of the NAND flash chip in bits (8|16|32)
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NAND_ROWCYCLES = 3 #The row address cycles (2|3)
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NAND_PAGESIZE = 2048 #The page size of the NAND chip in bytes(512|2048|4096)
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NAND_PAGEPERBLOCK = 128 #The page number per block
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NAND_FORCEERASE = 1 #The force to erase flag (0|1)
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NAND_OOBSIZE = 64 #oob size in byte
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NAND_ECCPOS = 6 #Specify the ECC offset inside the oob data (0-[oobsize-1])
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NAND_BADBLACKPOS = 0 #Specify the badblock flag offset inside the oob (0-[oobsize-1])
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NAND_BADBLACKPAGE = 127 #Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
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NAND_PLANENUM = 1 #The planes number of target nand flash
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NAND_BCHBIT = 4 #Specify the hardware BCH algorithm for 4750 (4|8)
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NAND_WPPIN = 0 #Specify the write protect pin number
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NAND_BLOCKPERCHIP = 0 #Specify the block number per chip,0 means ignore
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#The program will calculate the total SDRAM size by : size = 2^(ROWADDR + COLADDR) * BANKNUM * (SDRAMWIDTH / 4)
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#The CPUSPEED has restriction as: ( CPUSPEED % EXTCLK == 0 ) && ( CPUSPEED % 12 == 0 )
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