From 433a3eebdb97cecb6d4e15ccc501a885fd36d83c Mon Sep 17 00:00:00 2001 From: Xiangfu Liu Date: Thu, 22 Jul 2010 13:26:14 +0800 Subject: [PATCH] remove useless projects: qiboot, nandboot, nandprog we can create the project for them in future Signed-off-by: Xiangfu Liu --- nandboot/README | 22 - nandboot/config.h | 14 - nandboot/include/jz4730.h | 5045 ---------------- nandboot/include/jz4730_board.h | 52 - nandboot/include/jz4740.h | 4762 --------------- nandboot/include/jz4740_board.h | 57 - nandboot/include/nand.h | 70 - nandboot/include/types.h | 8 - nandboot/src/Makefile | 36 - nandboot/src/cpu.c | 106 - nandboot/src/head.S | 50 - nandboot/src/jz4730.c | 161 - nandboot/src/jz4730_board.c | 29 - nandboot/src/jz4730_nand.c | 254 - nandboot/src/jz4740.c | 165 - nandboot/src/jz4740_board.c | 28 - nandboot/src/jz4740_nand.c | 329 -- nandboot/src/jz_serial.c | 119 - nandboot/src/ld.script | 29 - nandboot/src/nand_boot.c | 207 - nandprog/Makefile | 37 - nandprog/README | 30 - nandprog/common/cmdline.c | 605 -- nandprog/common/loadcfg.c | 214 - nandprog/common/main.c | 23 - nandprog/include/configs.h | 406 -- nandprog/include/include.h | 140 - nandprog/include/jz4730.h | 5113 ----------------- nandprog/include/jz4740.h | 4525 --------------- nandprog/include/nand_ecc.h | 89 - nandprog/jz4730/nandflash_4730.c | 606 -- nandprog/jz4740/nandflash_4740.c | 734 --- qiboot/6410-partition-sd.sh | 283 - qiboot/Makefile | 92 - qiboot/README | 149 - qiboot/build | 12 - qiboot/config.mk | 22 - qiboot/dfu-qi | 7 - qiboot/gta02-qi.ocd | 34 - qiboot/include/ext2.h | 80 - qiboot/include/fat.h | 220 - qiboot/include/glamo-init.h | 1 - qiboot/include/glamo-mmc.h | 149 - qiboot/include/glamo-regs.h | 628 -- qiboot/include/i2c-bitbang-s3c24xx.h | 3 - qiboot/include/i2c-bitbang-s3c6410.h | 3 - qiboot/include/i2c-bitbang.h | 102 - qiboot/include/image.h | 570 -- qiboot/include/linux-mmc-protocol.h | 382 -- qiboot/include/linux-mmc.h | 120 - qiboot/include/mmc.h | 110 - qiboot/include/neo_gta01.h | 30 - qiboot/include/neo_gta02.h | 32 - qiboot/include/neo_om_3d7k.h | 28 - qiboot/include/neo_smdk6410.h | 6 - qiboot/include/pcf50606.h | 260 - qiboot/include/pcf50633.h | 392 -- qiboot/include/ports-s3c24xx.h | 41 - qiboot/include/qi-ctype.h | 45 - qiboot/include/qi.h | 144 - qiboot/include/s3c24xx-mci.h | 33 - qiboot/include/s3c24xx-regs-sdi.h | 110 - qiboot/include/s3c6410.h | 1394 ----- qiboot/include/serial-s3c24xx.h | 72 - qiboot/include/serial-s3c64xx.h | 72 - qiboot/include/setup.h | 269 - qiboot/include/smdk6410.h | 6 - qiboot/openocd-openmoko-debug-6410.cfg | 16 - qiboot/src/blink_led.c | 90 - qiboot/src/blink_led.h | 39 - qiboot/src/common.h | 681 --- qiboot/src/cpu/s3c2410/gta01.c | 312 - qiboot/src/cpu/s3c2410/i2c-bitbang-s3c24xx.c | 68 - qiboot/src/cpu/s3c2410/lowlevel_init.S | 162 - qiboot/src/cpu/s3c2410/nand_read.c | 136 - qiboot/src/cpu/s3c2410/nand_read.h | 22 - qiboot/src/cpu/s3c2410/qi.lds | 63 - qiboot/src/cpu/s3c2410/s3c24xx-mci.c | 579 -- qiboot/src/cpu/s3c2410/serial-s3c24xx.c | 77 - qiboot/src/cpu/s3c2410/start.S | 304 - qiboot/src/cpu/s3c2410/start_qi.c | 131 - qiboot/src/cpu/s3c2442/gta02.c | 740 --- qiboot/src/cpu/s3c2442/i2c-bitbang-s3c24xx.c | 68 - qiboot/src/cpu/s3c2442/lowlevel_init.S | 162 - qiboot/src/cpu/s3c2442/nand_read.c | 156 - qiboot/src/cpu/s3c2442/nand_read.h | 22 - qiboot/src/cpu/s3c2442/qi.lds | 65 - qiboot/src/cpu/s3c2442/s3c24xx-mci.c | 569 -- qiboot/src/cpu/s3c2442/serial-s3c24xx.c | 77 - qiboot/src/cpu/s3c2442/start.S | 315 - qiboot/src/cpu/s3c2442/start_qi.c | 126 - qiboot/src/cpu/s3c6410/hs_mmc.c | 650 --- qiboot/src/cpu/s3c6410/hs_mmc.h | 40 - qiboot/src/cpu/s3c6410/i2c-bitbang-s3c6410.c | 69 - .../src/cpu/s3c6410/om_3d7k-steppingstone.c | 114 - qiboot/src/cpu/s3c6410/om_3d7k.c | 935 --- qiboot/src/cpu/s3c6410/qi.lds | 75 - qiboot/src/cpu/s3c6410/serial-s3c64xx.c | 38 - .../src/cpu/s3c6410/smdk6410-steppingstone.c | 73 - qiboot/src/cpu/s3c6410/smdk6410.c | 27 - qiboot/src/cpu/s3c6410/start.S | 487 -- qiboot/src/cpu/s3c6410/start_qi.c | 136 - qiboot/src/crc32.c | 90 - qiboot/src/ctype.c | 27 - qiboot/src/drivers/glamo-init.c | 103 - qiboot/src/drivers/glamo-mmc.c | 851 --- qiboot/src/drivers/i2c-bitbang.c | 252 - qiboot/src/fs/dev.c | 133 - qiboot/src/fs/ext2.c | 940 --- qiboot/src/io.h | 337 -- qiboot/src/memory-test.c | 145 - qiboot/src/part.h | 138 - qiboot/src/phase2.c | 495 -- qiboot/src/serial.h | 112 - qiboot/src/start.S | 332 -- qiboot/src/utils-phase2.c | 134 - qiboot/src/utils.c | 150 - qiboot/tools/Makefile | 39 - qiboot/tools/mkudfu.c | 314 - qiboot/tools/usb_dfu_trailer.h | 31 - 120 files changed, 42213 deletions(-) delete mode 100644 nandboot/README delete mode 100644 nandboot/config.h delete mode 100644 nandboot/include/jz4730.h delete mode 100644 nandboot/include/jz4730_board.h delete mode 100644 nandboot/include/jz4740.h delete mode 100644 nandboot/include/jz4740_board.h delete mode 100644 nandboot/include/nand.h delete mode 100644 nandboot/include/types.h delete mode 100644 nandboot/src/Makefile delete mode 100644 nandboot/src/cpu.c delete mode 100644 nandboot/src/head.S delete mode 100644 nandboot/src/jz4730.c delete mode 100644 nandboot/src/jz4730_board.c delete mode 100644 nandboot/src/jz4730_nand.c delete mode 100644 nandboot/src/jz4740.c delete mode 100644 nandboot/src/jz4740_board.c delete mode 100644 nandboot/src/jz4740_nand.c delete mode 100644 nandboot/src/jz_serial.c delete mode 100644 nandboot/src/ld.script delete mode 100644 nandboot/src/nand_boot.c delete mode 100644 nandprog/Makefile delete mode 100644 nandprog/README delete mode 100644 nandprog/common/cmdline.c delete mode 100644 nandprog/common/loadcfg.c delete mode 100644 nandprog/common/main.c delete mode 100644 nandprog/include/configs.h delete mode 100644 nandprog/include/include.h delete mode 100644 nandprog/include/jz4730.h delete mode 100644 nandprog/include/jz4740.h delete mode 100644 nandprog/include/nand_ecc.h delete mode 100755 nandprog/jz4730/nandflash_4730.c delete mode 100755 nandprog/jz4740/nandflash_4740.c delete mode 100755 qiboot/6410-partition-sd.sh delete mode 100644 qiboot/Makefile delete mode 100644 qiboot/README delete mode 100755 qiboot/build delete mode 100644 qiboot/config.mk delete mode 100755 qiboot/dfu-qi delete mode 100755 qiboot/gta02-qi.ocd delete mode 100644 qiboot/include/ext2.h delete mode 100644 qiboot/include/fat.h delete mode 100644 qiboot/include/glamo-init.h delete mode 100644 qiboot/include/glamo-mmc.h delete mode 100644 qiboot/include/glamo-regs.h delete mode 100644 qiboot/include/i2c-bitbang-s3c24xx.h delete mode 100644 qiboot/include/i2c-bitbang-s3c6410.h delete mode 100644 qiboot/include/i2c-bitbang.h delete mode 100644 qiboot/include/image.h delete mode 100644 qiboot/include/linux-mmc-protocol.h delete mode 100644 qiboot/include/linux-mmc.h delete mode 100644 qiboot/include/mmc.h delete mode 100644 qiboot/include/neo_gta01.h delete mode 100644 qiboot/include/neo_gta02.h delete mode 100644 qiboot/include/neo_om_3d7k.h delete mode 100644 qiboot/include/neo_smdk6410.h delete mode 100644 qiboot/include/pcf50606.h delete mode 100644 qiboot/include/pcf50633.h delete mode 100644 qiboot/include/ports-s3c24xx.h delete mode 100644 qiboot/include/qi-ctype.h delete mode 100644 qiboot/include/qi.h delete mode 100644 qiboot/include/s3c24xx-mci.h delete mode 100644 qiboot/include/s3c24xx-regs-sdi.h delete mode 100644 qiboot/include/s3c6410.h delete mode 100644 qiboot/include/serial-s3c24xx.h delete mode 100644 qiboot/include/serial-s3c64xx.h delete mode 100644 qiboot/include/setup.h delete mode 100644 qiboot/include/smdk6410.h delete mode 100644 qiboot/openocd-openmoko-debug-6410.cfg delete mode 100644 qiboot/src/blink_led.c delete mode 100644 qiboot/src/blink_led.h delete mode 100644 qiboot/src/common.h delete mode 100644 qiboot/src/cpu/s3c2410/gta01.c delete mode 100644 qiboot/src/cpu/s3c2410/i2c-bitbang-s3c24xx.c delete mode 100644 qiboot/src/cpu/s3c2410/lowlevel_init.S delete mode 100644 qiboot/src/cpu/s3c2410/nand_read.c delete mode 100644 qiboot/src/cpu/s3c2410/nand_read.h delete mode 100644 qiboot/src/cpu/s3c2410/qi.lds delete mode 100644 qiboot/src/cpu/s3c2410/s3c24xx-mci.c delete mode 100644 qiboot/src/cpu/s3c2410/serial-s3c24xx.c delete mode 100644 qiboot/src/cpu/s3c2410/start.S delete mode 100644 qiboot/src/cpu/s3c2410/start_qi.c delete mode 100644 qiboot/src/cpu/s3c2442/gta02.c delete mode 100644 qiboot/src/cpu/s3c2442/i2c-bitbang-s3c24xx.c delete mode 100644 qiboot/src/cpu/s3c2442/lowlevel_init.S delete mode 100644 qiboot/src/cpu/s3c2442/nand_read.c delete mode 100644 qiboot/src/cpu/s3c2442/nand_read.h delete mode 100644 qiboot/src/cpu/s3c2442/qi.lds delete mode 100644 qiboot/src/cpu/s3c2442/s3c24xx-mci.c delete mode 100644 qiboot/src/cpu/s3c2442/serial-s3c24xx.c delete mode 100644 qiboot/src/cpu/s3c2442/start.S delete mode 100644 qiboot/src/cpu/s3c2442/start_qi.c delete mode 100644 qiboot/src/cpu/s3c6410/hs_mmc.c delete mode 100644 qiboot/src/cpu/s3c6410/hs_mmc.h delete mode 100644 qiboot/src/cpu/s3c6410/i2c-bitbang-s3c6410.c delete mode 100644 qiboot/src/cpu/s3c6410/om_3d7k-steppingstone.c delete mode 100644 qiboot/src/cpu/s3c6410/om_3d7k.c delete mode 100644 qiboot/src/cpu/s3c6410/qi.lds delete mode 100644 qiboot/src/cpu/s3c6410/serial-s3c64xx.c delete mode 100644 qiboot/src/cpu/s3c6410/smdk6410-steppingstone.c delete mode 100644 qiboot/src/cpu/s3c6410/smdk6410.c delete mode 100644 qiboot/src/cpu/s3c6410/start.S delete mode 100644 qiboot/src/cpu/s3c6410/start_qi.c delete mode 100644 qiboot/src/crc32.c delete mode 100644 qiboot/src/ctype.c delete mode 100644 qiboot/src/drivers/glamo-init.c delete mode 100644 qiboot/src/drivers/glamo-mmc.c delete mode 100644 qiboot/src/drivers/i2c-bitbang.c delete mode 100644 qiboot/src/fs/dev.c delete mode 100644 qiboot/src/fs/ext2.c delete mode 100644 qiboot/src/io.h delete mode 100644 qiboot/src/memory-test.c delete mode 100644 qiboot/src/part.h delete mode 100644 qiboot/src/phase2.c delete mode 100644 qiboot/src/serial.h delete mode 100644 qiboot/src/start.S delete mode 100644 qiboot/src/utils-phase2.c delete mode 100644 qiboot/src/utils.c delete mode 100644 qiboot/tools/Makefile delete mode 100644 qiboot/tools/mkudfu.c delete mode 100644 qiboot/tools/usb_dfu_trailer.h diff --git a/nandboot/README b/nandboot/README deleted file mode 100644 index 6ce5eab..0000000 --- a/nandboot/README +++ /dev/null @@ -1,22 +0,0 @@ - -This is the source code of the NAND Secondary Program Loader (SPL). -The NAND SPL itself will be first loaded by the IPL (Initial Program Loader) -inside the CPU, then it loads the kernel image from NAND into RAM and -starts the kernel from RAM. - -To build the NAND SPL, follow next steps: - - $ cd src/ - $ make - -And you will get a binary file called n-boot.bin. - -Before building the SPL, you should open config.h and check the -configuration is correct for your system. - -For JZ4730, the n-boot.bin must be less than 4KB. - -For JZ4740, the n-boot.bin must be less than 8KB. - -The platform definitions were declared in include/jz47xx_board.h. -Please check and modify it according to your system. diff --git a/nandboot/config.h b/nandboot/config.h deleted file mode 100644 index 541a40c..0000000 --- a/nandboot/config.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * config.h - * - */ -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* - * Select one of the following definitions - */ -//#define CONFIG_JZ4730 1 -#define CONFIG_JZ4740 1 - -#endif /* __CONFIG_H__ */ diff --git a/nandboot/include/jz4730.h b/nandboot/include/jz4730.h deleted file mode 100644 index 38c04f1..0000000 --- a/nandboot/include/jz4730.h +++ /dev/null @@ -1,5045 +0,0 @@ -/* - * jz4730.h - * - * JZ4730 definitions. - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * - */ -#ifndef __JZ4730_H__ -#define __JZ4730_H__ - -#ifndef __ASSEMBLY__ - -#include - -#define REG8(addr) *((volatile u8 *)(addr)) -#define REG16(addr) *((volatile u16 *)(addr)) -#define REG32(addr) *((volatile u32 *)(addr)) - -#else - -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) - -#endif /* !ASSEMBLY */ - -#define HARB_BASE 0xB3000000 -#define EMC_BASE 0xB3010000 -#define DMAC_BASE 0xB3020000 -#define UHC_BASE 0xB3030000 -#define UDC_BASE 0xB3040000 -#define LCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define ETH_BASE 0xB3100000 -#define NBM_BASE 0xB3F00000 - -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define OST_BASE 0xB0002000 -#define RTC_BASE 0xB0003000 -#define WDT_BASE 0xB0004000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define MSC_BASE 0xB0021000 -#define UART0_BASE 0xB0030000 -#define UART1_BASE 0xB0031000 -#define UART2_BASE 0xB0032000 -#define UART3_BASE 0xB0033000 -#define FIR_BASE 0xB0040000 -#define SCC_BASE 0xB0041000 -#define SCC0_BASE 0xB0041000 -#define I2C_BASE 0xB0042000 -#define SSI_BASE 0xB0043000 -#define SCC1_BASE 0xB0044000 -#define PWM0_BASE 0xB0050000 -#define PWM1_BASE 0xB0051000 -#define DES_BASE 0xB0060000 -#define UPRT_BASE 0xB0061000 -#define KBC_BASE 0xB0062000 - - - - -/************************************************************************* - * MSC - *************************************************************************/ -#define MSC_STRPCL (MSC_BASE + 0x000) -#define MSC_STAT (MSC_BASE + 0x004) -#define MSC_CLKRT (MSC_BASE + 0x008) -#define MSC_CMDAT (MSC_BASE + 0x00C) -#define MSC_RESTO (MSC_BASE + 0x010) -#define MSC_RDTO (MSC_BASE + 0x014) -#define MSC_BLKLEN (MSC_BASE + 0x018) -#define MSC_NOB (MSC_BASE + 0x01C) -#define MSC_SNOB (MSC_BASE + 0x020) -#define MSC_IMASK (MSC_BASE + 0x024) -#define MSC_IREG (MSC_BASE + 0x028) -#define MSC_CMD (MSC_BASE + 0x02C) -#define MSC_ARG (MSC_BASE + 0x030) -#define MSC_RES (MSC_BASE + 0x034) -#define MSC_RXFIFO (MSC_BASE + 0x038) -#define MSC_TXFIFO (MSC_BASE + 0x03C) - -#define REG_MSC_STRPCL REG16(MSC_STRPCL) -#define REG_MSC_STAT REG32(MSC_STAT) -#define REG_MSC_CLKRT REG16(MSC_CLKRT) -#define REG_MSC_CMDAT REG32(MSC_CMDAT) -#define REG_MSC_RESTO REG16(MSC_RESTO) -#define REG_MSC_RDTO REG16(MSC_RDTO) -#define REG_MSC_BLKLEN REG16(MSC_BLKLEN) -#define REG_MSC_NOB REG16(MSC_NOB) -#define REG_MSC_SNOB REG16(MSC_SNOB) -#define REG_MSC_IMASK REG16(MSC_IMASK) -#define REG_MSC_IREG REG16(MSC_IREG) -#define REG_MSC_CMD REG8(MSC_CMD) -#define REG_MSC_ARG REG32(MSC_ARG) -#define REG_MSC_RES REG16(MSC_RES) -#define REG_MSC_RXFIFO REG32(MSC_RXFIFO) -#define REG_MSC_TXFIFO REG32(MSC_TXFIFO) - -/* MSC Clock and Control Register (MSC_STRPCL) */ - -#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) -#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) -#define MSC_STRPCL_START_READWAIT (1 << 5) -#define MSC_STRPCL_STOP_READWAIT (1 << 4) -#define MSC_STRPCL_RESET (1 << 3) -#define MSC_STRPCL_START_OP (1 << 2) -#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 -#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) - #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ - #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ - -/* MSC Status Register (MSC_STAT) */ - -#define MSC_STAT_IS_RESETTING (1 << 15) -#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) -#define MSC_STAT_PRG_DONE (1 << 13) -#define MSC_STAT_DATA_TRAN_DONE (1 << 12) -#define MSC_STAT_END_CMD_RES (1 << 11) -#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) -#define MSC_STAT_IS_READWAIT (1 << 9) -#define MSC_STAT_CLK_EN (1 << 8) -#define MSC_STAT_DATA_FIFO_FULL (1 << 7) -#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) -#define MSC_STAT_CRC_RES_ERR (1 << 5) -#define MSC_STAT_CRC_READ_ERROR (1 << 4) -#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 -#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) - #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR_YES (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ -#define MSC_STAT_TIME_OUT_RES (1 << 1) -#define MSC_STAT_TIME_OUT_READ (1 << 0) - -/* MSC Bus Clock Control Register (MSC_CLKRT) */ - -#define MSC_CLKRT_CLK_RATE_BIT 0 -#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ - -/* MSC Command Sequence Control Register (MSC_CMDAT) */ - -#define MSC_CMDAT_IO_ABORT (1 << 11) -#define MSC_CMDAT_BUS_WIDTH_BIT 9 -#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) - #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ - #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ - #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) - #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_DMA_EN (1 << 8) -#define MSC_CMDAT_INIT (1 << 7) -#define MSC_CMDAT_BUSY (1 << 6) -#define MSC_CMDAT_STREAM_BLOCK (1 << 5) -#define MSC_CMDAT_WRITE_READ (1 << 4) -#define MSC_CMDAT_DATA_EN (1 << 3) -#define MSC_CMDAT_RESPONSE_FORMAT_BIT 0 -#define MSC_CMDAT_RESPONSE_FORMAT_MASK (0x7 << MSC_CMDAT_RESPONSE_FORMAT_BIT) - #define MSC_CMDAT_RESPONSE_FORMAT_NONE (0x0 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* No response */ - #define MSC_CMDAT_RESPONSE_FORMAT_R1 (0x1 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R1 and R1b */ - #define MSC_CMDAT_RESPONSE_FORMAT_R2 (0x2 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R2 */ - #define MSC_CMDAT_RESPONSE_FORMAT_R3 (0x3 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R3 */ - #define MSC_CMDAT_RESPONSE_FORMAT_R4 (0x4 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R4 */ - #define MSC_CMDAT_RESPONSE_FORMAT_R5 (0x5 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R5 */ - #define MSC_CMDAT_RESPONSE_FORMAT_R6 (0x6 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R6 */ - -#define CMDAT_DMA_EN (1 << 8) -#define CMDAT_INIT (1 << 7) -#define CMDAT_BUSY (1 << 6) -#define CMDAT_STREAM (1 << 5) -#define CMDAT_WRITE (1 << 4) -#define CMDAT_DATA_EN (1 << 3) - -/* MSC Interrupts Mask Register (MSC_IMASK) */ - -#define MSC_IMASK_SDIO (1 << 7) -#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) -#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) -#define MSC_IMASK_END_CMD_RES (1 << 2) -#define MSC_IMASK_PRG_DONE (1 << 1) -#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) - -/* MSC Interrupts Status Register (MSC_IREG) */ - -#define MSC_IREG_SDIO (1 << 7) -#define MSC_IREG_TXFIFO_WR_REQ (1 << 6) -#define MSC_IREG_RXFIFO_RD_REQ (1 << 5) -#define MSC_IREG_END_CMD_RES (1 << 2) -#define MSC_IREG_PRG_DONE (1 << 1) -#define MSC_IREG_DATA_TRAN_DONE (1 << 0) - - - - -/************************************************************************* - * RTC - *************************************************************************/ -#define RTC_RCR (RTC_BASE + 0x00) -#define RTC_RSR (RTC_BASE + 0x04) -#define RTC_RSAR (RTC_BASE + 0x08) -#define RTC_RGR (RTC_BASE + 0x0c) - -#define REG_RTC_RCR REG32(RTC_RCR) -#define REG_RTC_RSR REG32(RTC_RSR) -#define REG_RTC_RSAR REG32(RTC_RSAR) -#define REG_RTC_RGR REG32(RTC_RGR) - -#define RTC_RCR_HZ (1 << 6) -#define RTC_RCR_HZIE (1 << 5) -#define RTC_RCR_AF (1 << 4) -#define RTC_RCR_AIE (1 << 3) -#define RTC_RCR_AE (1 << 2) -#define RTC_RCR_START (1 << 0) - -#define RTC_RGR_LOCK (1 << 31) -#define RTC_RGR_ADJ_BIT 16 -#define RTC_RGR_ADJ_MASK (0x3ff << RTC_RGR_ADJ_BIT) -#define RTC_RGR_DIV_BIT 0 -#define RTC_REG_DIV_MASK (0xff << RTC_RGR_DIV_BIT) - - - - -/************************************************************************* - * FIR - *************************************************************************/ -#define FIR_TDR (FIR_BASE + 0x000) -#define FIR_RDR (FIR_BASE + 0x004) -#define FIR_TFLR (FIR_BASE + 0x008) -#define FIR_AR (FIR_BASE + 0x00C) -#define FIR_CR1 (FIR_BASE + 0x010) -#define FIR_CR2 (FIR_BASE + 0x014) -#define FIR_SR (FIR_BASE + 0x018) - -#define REG_FIR_TDR REG8(FIR_TDR) -#define REG_FIR_RDR REG8(FIR_RDR) -#define REG_FIR_TFLR REG16(FIR_TFLR) -#define REG_FIR_AR REG8(FIR_AR) -#define REG_FIR_CR1 REG8(FIR_CR1) -#define REG_FIR_CR2 REG16(FIR_CR2) -#define REG_FIR_SR REG16(FIR_SR) - -/* FIR Control Register 1 (FIR_CR1) */ - -#define FIR_CR1_FIRUE (1 << 7) -#define FIR_CR1_ACE (1 << 6) -#define FIR_CR1_EOUS (1 << 5) -#define FIR_CR1_TIIE (1 << 4) -#define FIR_CR1_TFIE (1 << 3) -#define FIR_CR1_RFIE (1 << 2) -#define FIR_CR1_TXE (1 << 1) -#define FIR_CR1_RXE (1 << 0) - -/* FIR Control Register 2 (FIR_CR2) */ - -#define FIR_CR2_SIPE (1 << 10) -#define FIR_CR2_BCRC (1 << 9) -#define FIR_CR2_TFLRS (1 << 8) -#define FIR_CR2_ISS (1 << 7) -#define FIR_CR2_LMS (1 << 6) -#define FIR_CR2_TPPS (1 << 5) -#define FIR_CR2_RPPS (1 << 4) -#define FIR_CR2_TTRG_BIT 2 -#define FIR_CR2_TTRG_MASK (0x3 << FIR_CR2_TTRG_BIT) - #define FIR_CR2_TTRG_16 (0 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 16 */ - #define FIR_CR2_TTRG_32 (1 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 32 */ - #define FIR_CR2_TTRG_64 (2 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 64 */ - #define FIR_CR2_TTRG_128 (3 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 128 */ -#define FIR_CR2_RTRG_BIT 0 -#define FIR_CR2_RTRG_MASK (0x3 << FIR_CR2_RTRG_BIT) - #define FIR_CR2_RTRG_16 (0 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 16 */ - #define FIR_CR2_RTRG_32 (1 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 32 */ - #define FIR_CR2_RTRG_64 (2 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 64 */ - #define FIR_CR2_RTRG_128 (3 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 128 */ - -/* FIR Status Register (FIR_SR) */ - -#define FIR_SR_RFW (1 << 12) -#define FIR_SR_RFA (1 << 11) -#define FIR_SR_TFRTL (1 << 10) -#define FIR_SR_RFRTL (1 << 9) -#define FIR_SR_URUN (1 << 8) -#define FIR_SR_RFTE (1 << 7) -#define FIR_SR_ORUN (1 << 6) -#define FIR_SR_CRCE (1 << 5) -#define FIR_SR_FEND (1 << 4) -#define FIR_SR_TFF (1 << 3) -#define FIR_SR_RFE (1 << 2) -#define FIR_SR_TIDLE (1 << 1) -#define FIR_SR_RB (1 << 0) - - - - -/************************************************************************* - * SCC - *************************************************************************/ -#define SCC_DR(base) ((base) + 0x000) -#define SCC_FDR(base) ((base) + 0x004) -#define SCC_CR(base) ((base) + 0x008) -#define SCC_SR(base) ((base) + 0x00C) -#define SCC_TFR(base) ((base) + 0x010) -#define SCC_EGTR(base) ((base) + 0x014) -#define SCC_ECR(base) ((base) + 0x018) -#define SCC_RTOR(base) ((base) + 0x01C) - -#define REG_SCC_DR(base) REG8(SCC_DR(base)) -#define REG_SCC_FDR(base) REG8(SCC_FDR(base)) -#define REG_SCC_CR(base) REG32(SCC_CR(base)) -#define REG_SCC_SR(base) REG16(SCC_SR(base)) -#define REG_SCC_TFR(base) REG16(SCC_TFR(base)) -#define REG_SCC_EGTR(base) REG8(SCC_EGTR(base)) -#define REG_SCC_ECR(base) REG32(SCC_ECR(base)) -#define REG_SCC_RTOR(base) REG8(SCC_RTOR(base)) - -/* SCC FIFO Data Count Register (SCC_FDR) */ - -#define SCC_FDR_EMPTY 0x00 -#define SCC_FDR_FULL 0x10 - -/* SCC Control Register (SCC_CR) */ - -#define SCC_CR_SCCE (1 << 31) -#define SCC_CR_TRS (1 << 30) -#define SCC_CR_T2R (1 << 29) -#define SCC_CR_FDIV_BIT 24 -#define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT) - #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */ - #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */ -#define SCC_CR_FLUSH (1 << 23) -#define SCC_CR_TRIG_BIT 16 -#define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT) - #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */ - #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */ - #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */ - #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */ -#define SCC_CR_TP (1 << 15) -#define SCC_CR_CONV (1 << 14) -#define SCC_CR_TXIE (1 << 13) -#define SCC_CR_RXIE (1 << 12) -#define SCC_CR_TENDIE (1 << 11) -#define SCC_CR_RTOIE (1 << 10) -#define SCC_CR_ECIE (1 << 9) -#define SCC_CR_EPIE (1 << 8) -#define SCC_CR_RETIE (1 << 7) -#define SCC_CR_EOIE (1 << 6) -#define SCC_CR_TSEND (1 << 3) -#define SCC_CR_PX_BIT 1 -#define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) - #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ - #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ - #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */ -#define SCC_CR_CLKSTP (1 << 0) - -/* SCC Status Register (SCC_SR) */ - -#define SCC_SR_TRANS (1 << 15) -#define SCC_SR_ORER (1 << 12) -#define SCC_SR_RTO (1 << 11) -#define SCC_SR_PER (1 << 10) -#define SCC_SR_TFTG (1 << 9) -#define SCC_SR_RFTG (1 << 8) -#define SCC_SR_TEND (1 << 7) -#define SCC_SR_RETR_3 (1 << 4) -#define SCC_SR_ECNTO (1 << 0) - - - - -/************************************************************************* - * ETH - *************************************************************************/ -#define ETH_BMR (ETH_BASE + 0x1000) -#define ETH_TPDR (ETH_BASE + 0x1004) -#define ETH_RPDR (ETH_BASE + 0x1008) -#define ETH_RAR (ETH_BASE + 0x100C) -#define ETH_TAR (ETH_BASE + 0x1010) -#define ETH_SR (ETH_BASE + 0x1014) -#define ETH_CR (ETH_BASE + 0x1018) -#define ETH_IER (ETH_BASE + 0x101C) -#define ETH_MFCR (ETH_BASE + 0x1020) -#define ETH_CTAR (ETH_BASE + 0x1050) -#define ETH_CRAR (ETH_BASE + 0x1054) -#define ETH_MCR (ETH_BASE + 0x0000) -#define ETH_MAHR (ETH_BASE + 0x0004) -#define ETH_MALR (ETH_BASE + 0x0008) -#define ETH_HTHR (ETH_BASE + 0x000C) -#define ETH_HTLR (ETH_BASE + 0x0010) -#define ETH_MIAR (ETH_BASE + 0x0014) -#define ETH_MIDR (ETH_BASE + 0x0018) -#define ETH_FCR (ETH_BASE + 0x001C) -#define ETH_VTR1 (ETH_BASE + 0x0020) -#define ETH_VTR2 (ETH_BASE + 0x0024) -#define ETH_WKFR (ETH_BASE + 0x0028) -#define ETH_PMTR (ETH_BASE + 0x002C) - -#define REG_ETH_BMR REG32(ETH_BMR) -#define REG_ETH_TPDR REG32(ETH_TPDR) -#define REG_ETH_RPDR REG32(ETH_RPDR) -#define REG_ETH_RAR REG32(ETH_RAR) -#define REG_ETH_TAR REG32(ETH_TAR) -#define REG_ETH_SR REG32(ETH_SR) -#define REG_ETH_CR REG32(ETH_CR) -#define REG_ETH_IER REG32(ETH_IER) -#define REG_ETH_MFCR REG32(ETH_MFCR) -#define REG_ETH_CTAR REG32(ETH_CTAR) -#define REG_ETH_CRAR REG32(ETH_CRAR) -#define REG_ETH_MCR REG32(ETH_MCR) -#define REG_ETH_MAHR REG32(ETH_MAHR) -#define REG_ETH_MALR REG32(ETH_MALR) -#define REG_ETH_HTHR REG32(ETH_HTHR) -#define REG_ETH_HTLR REG32(ETH_HTLR) -#define REG_ETH_MIAR REG32(ETH_MIAR) -#define REG_ETH_MIDR REG32(ETH_MIDR) -#define REG_ETH_FCR REG32(ETH_FCR) -#define REG_ETH_VTR1 REG32(ETH_VTR1) -#define REG_ETH_VTR2 REG32(ETH_VTR2) -#define REG_ETH_WKFR REG32(ETH_WKFR) -#define REG_ETH_PMTR REG32(ETH_PMTR) - -/* Bus Mode Register (ETH_BMR) */ - -#define ETH_BMR_DBO (1 << 20) -#define ETH_BMR_PBL_BIT 8 -#define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT) - #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT) - #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT) -#define ETH_BMR_BLE (1 << 7) -#define ETH_BMR_DSL_BIT 2 -#define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT) -#define ETH_BMR_SWR (1 << 0) - -/* DMA Status Register (ETH_SR) */ - -#define ETH_SR_EB_BIT 23 -#define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT) - #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT) - #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT) -#define ETH_SR_TS_BIT 20 -#define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT) - #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT) - #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT) - #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT) - #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT) - #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT) - #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT) -#define ETH_SR_RS_BIT 17 -#define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT) - #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT) - #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT) - #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT) - #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT) - #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT) - #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT) - #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT) - #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT) -#define ETH_SR_NIS (1 << 16) -#define ETH_SR_AIS (1 << 15) -#define ETH_SR_ERI (1 << 14) -#define ETH_SR_FBE (1 << 13) -#define ETH_SR_ETI (1 << 10) -#define ETH_SR_RWT (1 << 9) -#define ETH_SR_RPS (1 << 8) -#define ETH_SR_RU (1 << 7) -#define ETH_SR_RI (1 << 6) -#define ETH_SR_UNF (1 << 5) -#define ETH_SR_TJT (1 << 3) -#define ETH_SR_TU (1 << 2) -#define ETH_SR_TPS (1 << 1) -#define ETH_SR_TI (1 << 0) - -/* Control (Operation Mode) Register (ETH_CR) */ - -#define ETH_CR_TTM (1 << 22) -#define ETH_CR_SF (1 << 21) -#define ETH_CR_TR_BIT 14 -#define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT) -#define ETH_CR_ST (1 << 13) -#define ETH_CR_OSF (1 << 2) -#define ETH_CR_SR (1 << 1) - -/* Interrupt Enable Register (ETH_IER) */ - -#define ETH_IER_NI (1 << 16) -#define ETH_IER_AI (1 << 15) -#define ETH_IER_ERE (1 << 14) -#define ETH_IER_FBE (1 << 13) -#define ETH_IER_ET (1 << 10) -#define ETH_IER_RWE (1 << 9) -#define ETH_IER_RS (1 << 8) -#define ETH_IER_RU (1 << 7) -#define ETH_IER_RI (1 << 6) -#define ETH_IER_UN (1 << 5) -#define ETH_IER_TJ (1 << 3) -#define ETH_IER_TU (1 << 2) -#define ETH_IER_TS (1 << 1) -#define ETH_IER_TI (1 << 0) - -/* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */ - -#define ETH_MFCR_OVERFLOW_BIT 17 -#define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT) -#define ETH_MFCR_MFC_BIT 0 -#define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT) - -/* MAC Control Register (ETH_MCR) */ - -#define ETH_MCR_RA (1 << 31) -#define ETH_MCR_HBD (1 << 28) -#define ETH_MCR_PS (1 << 27) -#define ETH_MCR_DRO (1 << 23) -#define ETH_MCR_OM_BIT 21 -#define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT) - #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT) - #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT) - #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT) -#define ETH_MCR_F (1 << 20) -#define ETH_MCR_PM (1 << 19) -#define ETH_MCR_PR (1 << 18) -#define ETH_MCR_IF (1 << 17) -#define ETH_MCR_PB (1 << 16) -#define ETH_MCR_HO (1 << 15) -#define ETH_MCR_HP (1 << 13) -#define ETH_MCR_LCC (1 << 12) -#define ETH_MCR_DBF (1 << 11) -#define ETH_MCR_DTRY (1 << 10) -#define ETH_MCR_ASTP (1 << 8) -#define ETH_MCR_BOLMT_BIT 6 -#define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT) - #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT) - #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT) - #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT) - #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT) -#define ETH_MCR_DC (1 << 5) -#define ETH_MCR_TE (1 << 3) -#define ETH_MCR_RE (1 << 2) - -/* MII Address Register (ETH_MIAR) */ - -#define ETH_MIAR_PHY_ADDR_BIT 11 -#define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT) -#define ETH_MIAR_MII_REG_BIT 6 -#define ETH_MIAR_MII_REG_MASK (0x1f << ETH_MIAR_MII_REG_BIT) -#define ETH_MIAR_MII_WRITE (1 << 1) -#define ETH_MIAR_MII_BUSY (1 << 0) - -/* Flow Control Register (ETH_FCR) */ - -#define ETH_FCR_PAUSE_TIME_BIT 16 -#define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT) -#define ETH_FCR_PCF (1 << 2) -#define ETH_FCR_FCE (1 << 1) -#define ETH_FCR_BUSY (1 << 0) - -/* PMT Control and Status Register (ETH_PMTR) */ - -#define ETH_PMTR_GU (1 << 9) -#define ETH_PMTR_RF (1 << 6) -#define ETH_PMTR_MF (1 << 5) -#define ETH_PMTR_RWK (1 << 2) -#define ETH_PMTR_MPK (1 << 1) - -/* Receive Descriptor 0 (ETH_RD0) Bits */ - -#define ETH_RD0_OWN (1 << 31) -#define ETH_RD0_FF (1 << 30) -#define ETH_RD0_FL_BIT 16 -#define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT) -#define ETH_RD0_ES (1 << 15) -#define ETH_RD0_DE (1 << 14) -#define ETH_RD0_LE (1 << 12) -#define ETH_RD0_RF (1 << 11) -#define ETH_RD0_MF (1 << 10) -#define ETH_RD0_FD (1 << 9) -#define ETH_RD0_LD (1 << 8) -#define ETH_RD0_TL (1 << 7) -#define ETH_RD0_CS (1 << 6) -#define ETH_RD0_FT (1 << 5) -#define ETH_RD0_WT (1 << 4) -#define ETH_RD0_ME (1 << 3) -#define ETH_RD0_DB (1 << 2) -#define ETH_RD0_CE (1 << 1) - -/* Receive Descriptor 1 (ETH_RD1) Bits */ - -#define ETH_RD1_RER (1 << 25) -#define ETH_RD1_RCH (1 << 24) -#define ETH_RD1_RBS2_BIT 11 -#define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT) -#define ETH_RD1_RBS1_BIT 0 -#define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT) - -/* Transmit Descriptor 0 (ETH_TD0) Bits */ - -#define ETH_TD0_OWN (1 << 31) -#define ETH_TD0_FA (1 << 15) -#define ETH_TD0_LOC (1 << 11) -#define ETH_TD0_NC (1 << 10) -#define ETH_TD0_LC (1 << 9) -#define ETH_TD0_EC (1 << 8) -#define ETH_TD0_HBF (1 << 7) -#define ETH_TD0_CC_BIT 3 -#define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT) -#define ETH_TD0_ED (1 << 2) -#define ETH_TD0_UF (1 << 1) -#define ETH_TD0_DF (1 << 0) - -/* Transmit Descriptor 1 (ETH_TD1) Bits */ - -#define ETH_TD1_IC (1 << 31) -#define ETH_TD1_LS (1 << 30) -#define ETH_TD1_FS (1 << 29) -#define ETH_TD1_AC (1 << 26) -#define ETH_TD1_TER (1 << 25) -#define ETH_TD1_TCH (1 << 24) -#define ETH_TD1_DPD (1 << 23) -#define ETH_TD1_TBS2_BIT 11 -#define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT) -#define ETH_TD1_TBS1_BIT 0 -#define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT) - - - - -/************************************************************************* - * WDT - *************************************************************************/ -#define WDT_WTCSR (WDT_BASE + 0x00) -#define WDT_WTCNT (WDT_BASE + 0x04) - -#define REG_WDT_WTCSR REG8(WDT_WTCSR) -#define REG_WDT_WTCNT REG32(WDT_WTCNT) - -#define WDT_WTCSR_START (1 << 4) - - - - -/************************************************************************* - * OST - *************************************************************************/ -#define OST_TER (OST_BASE + 0x00) -#define OST_TRDR(n) (OST_BASE + 0x10 + ((n) * 0x20)) -#define OST_TCNT(n) (OST_BASE + 0x14 + ((n) * 0x20)) -#define OST_TCSR(n) (OST_BASE + 0x18 + ((n) * 0x20)) -#define OST_TCRB(n) (OST_BASE + 0x1c + ((n) * 0x20)) - -#define REG_OST_TER REG8(OST_TER) -#define REG_OST_TRDR(n) REG32(OST_TRDR((n))) -#define REG_OST_TCNT(n) REG32(OST_TCNT((n))) -#define REG_OST_TCSR(n) REG16(OST_TCSR((n))) -#define REG_OST_TCRB(n) REG32(OST_TCRB((n))) - -#define OST_TCSR_BUSY (1 << 7) -#define OST_TCSR_UF (1 << 6) -#define OST_TCSR_UIE (1 << 5) -#define OST_TCSR_CKS_BIT 0 -#define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT) - -#define OST_TCSR0 OST_TCSR(0) -#define OST_TCSR1 OST_TCSR(1) -#define OST_TCSR2 OST_TCSR(2) -#define OST_TRDR0 OST_TRDR(0) -#define OST_TRDR1 OST_TRDR(1) -#define OST_TRDR2 OST_TRDR(2) -#define OST_TCNT0 OST_TCNT(0) -#define OST_TCNT1 OST_TCNT(1) -#define OST_TCNT2 OST_TCNT(2) -#define OST_TCRB0 OST_TCRB(0) -#define OST_TCRB1 OST_TCRB(1) -#define OST_TCRB2 OST_TCRB(2) - -/************************************************************************* - * UART - *************************************************************************/ - -#define IRDA_BASE UART0_BASE -#define UART_BASE UART0_BASE -#define UART_OFF 0x1000 - -/* register offset */ -#define OFF_RDR (0x00) /* R 8b H'xx */ -#define OFF_TDR (0x00) /* W 8b H'xx */ -#define OFF_DLLR (0x00) /* RW 8b H'00 */ -#define OFF_DLHR (0x04) /* RW 8b H'00 */ -#define OFF_IER (0x04) /* RW 8b H'00 */ -#define OFF_ISR (0x08) /* R 8b H'01 */ -#define OFF_FCR (0x08) /* W 8b H'00 */ -#define OFF_LCR (0x0C) /* RW 8b H'00 */ -#define OFF_MCR (0x10) /* RW 8b H'00 */ -#define OFF_LSR (0x14) /* R 8b H'00 */ -#define OFF_MSR (0x18) /* R 8b H'00 */ -#define OFF_SPR (0x1C) /* RW 8b H'00 */ -#define OFF_MCR (0x10) /* RW 8b H'00 */ -#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ - -/* register address */ -#define UART0_RDR (UART0_BASE + OFF_RDR) -#define UART0_TDR (UART0_BASE + OFF_TDR) -#define UART0_DLLR (UART0_BASE + OFF_DLLR) -#define UART0_DLHR (UART0_BASE + OFF_DLHR) -#define UART0_IER (UART0_BASE + OFF_IER) -#define UART0_ISR (UART0_BASE + OFF_ISR) -#define UART0_FCR (UART0_BASE + OFF_FCR) -#define UART0_LCR (UART0_BASE + OFF_LCR) -#define UART0_MCR (UART0_BASE + OFF_MCR) -#define UART0_LSR (UART0_BASE + OFF_LSR) -#define UART0_MSR (UART0_BASE + OFF_MSR) -#define UART0_SPR (UART0_BASE + OFF_SPR) -#define UART0_SIRCR (UART0_BASE + OFF_SIRCR) - -#define UART1_RDR (UART1_BASE + OFF_RDR) -#define UART1_TDR (UART1_BASE + OFF_TDR) -#define UART1_DLLR (UART1_BASE + OFF_DLLR) -#define UART1_DLHR (UART1_BASE + OFF_DLHR) -#define UART1_IER (UART1_BASE + OFF_IER) -#define UART1_ISR (UART1_BASE + OFF_ISR) -#define UART1_FCR (UART1_BASE + OFF_FCR) -#define UART1_LCR (UART1_BASE + OFF_LCR) -#define UART1_MCR (UART1_BASE + OFF_MCR) -#define UART1_LSR (UART1_BASE + OFF_LSR) -#define UART1_MSR (UART1_BASE + OFF_MSR) -#define UART1_SPR (UART1_BASE + OFF_SPR) -#define UART1_SIRCR (UART1_BASE + OFF_SIRCR) - -#define UART2_RDR (UART2_BASE + OFF_RDR) -#define UART2_TDR (UART2_BASE + OFF_TDR) -#define UART2_DLLR (UART2_BASE + OFF_DLLR) -#define UART2_DLHR (UART2_BASE + OFF_DLHR) -#define UART2_IER (UART2_BASE + OFF_IER) -#define UART2_ISR (UART2_BASE + OFF_ISR) -#define UART2_FCR (UART2_BASE + OFF_FCR) -#define UART2_LCR (UART2_BASE + OFF_LCR) -#define UART2_MCR (UART2_BASE + OFF_MCR) -#define UART2_LSR (UART2_BASE + OFF_LSR) -#define UART2_MSR (UART2_BASE + OFF_MSR) -#define UART2_SPR (UART2_BASE + OFF_SPR) -#define UART2_SIRCR (UART2_BASE + OFF_SIRCR) - -#define UART3_RDR (UART3_BASE + OFF_RDR) -#define UART3_TDR (UART3_BASE + OFF_TDR) -#define UART3_DLLR (UART3_BASE + OFF_DLLR) -#define UART3_DLHR (UART3_BASE + OFF_DLHR) -#define UART3_IER (UART3_BASE + OFF_IER) -#define UART3_ISR (UART3_BASE + OFF_ISR) -#define UART3_FCR (UART3_BASE + OFF_FCR) -#define UART3_LCR (UART3_BASE + OFF_LCR) -#define UART3_MCR (UART3_BASE + OFF_MCR) -#define UART3_LSR (UART3_BASE + OFF_LSR) -#define UART3_MSR (UART3_BASE + OFF_MSR) -#define UART3_SPR (UART3_BASE + OFF_SPR) -#define UART3_SIRCR (UART3_BASE + OFF_SIRCR) - -/* - * Define macros for UART_IER - * UART Interrupt Enable Register - */ -#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ -#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ -#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ -#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ -#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ - -/* - * Define macros for UART_ISR - * UART Interrupt Status Register - */ -#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ -#define UART_ISR_IID (7 << 1) /* Source of Interrupt */ -#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ -#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ -#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ -#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ -#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ -#define UART_ISR_FFMS_NO_FIFO (0 << 6) -#define UART_ISR_FFMS_FIFO_MODE (3 << 6) - -/* - * Define macros for UART_FCR - * UART FIFO Control Register - */ -#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ -#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ -#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ -#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ -#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ -#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ -#define UART_FCR_RTRG_1 (0 << 6) -#define UART_FCR_RTRG_4 (1 << 6) -#define UART_FCR_RTRG_8 (2 << 6) -#define UART_FCR_RTRG_15 (3 << 6) - -/* - * Define macros for UART_LCR - * UART Line Control Register - */ -#define UART_LCR_WLEN (3 << 0) /* word length */ -#define UART_LCR_WLEN_5 (0 << 0) -#define UART_LCR_WLEN_6 (1 << 0) -#define UART_LCR_WLEN_7 (2 << 0) -#define UART_LCR_WLEN_8 (3 << 0) -#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ - -#define UART_LCR_PE (1 << 3) /* 0: parity disable */ -#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ -#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ -#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ -#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ - -/* - * Define macros for UART_LSR - * UART Line Status Register - */ -#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ -#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ -#define UART_LSR_PER (1 << 2) /* 0: no parity error */ -#define UART_LSR_FER (1 << 3) /* 0; no framing error */ -#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ -#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ -#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ -#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ - -/* - * Define macros for UART_MCR - * UART Modem Control Register - */ -#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ -#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ -#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ -#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ -#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ -#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ - -/* - * Define macros for UART_MSR - * UART Modem Status Register - */ -#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ -#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ -#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ -#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ -#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ -#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ -#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ -#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ - -/* - * Define macros for SIRCR - * Slow IrDA Control Register - */ -#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ -#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ -#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length - 1: 0 pulse width is 1.6us for 115.2Kbps */ -#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ -#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ - - - -/************************************************************************* - * INTC - *************************************************************************/ -#define INTC_ISR (INTC_BASE + 0x00) -#define INTC_IMR (INTC_BASE + 0x04) -#define INTC_IMSR (INTC_BASE + 0x08) -#define INTC_IMCR (INTC_BASE + 0x0c) -#define INTC_IPR (INTC_BASE + 0x10) - -#define REG_INTC_ISR REG32(INTC_ISR) -#define REG_INTC_IMR REG32(INTC_IMR) -#define REG_INTC_IMSR REG32(INTC_IMSR) -#define REG_INTC_IMCR REG32(INTC_IMCR) -#define REG_INTC_IPR REG32(INTC_IPR) - -#define IRQ_I2C 1 -#define IRQ_PS2 2 -#define IRQ_UPRT 3 -#define IRQ_CORE 4 -#define IRQ_UART3 6 -#define IRQ_UART2 7 -#define IRQ_UART1 8 -#define IRQ_UART0 9 -#define IRQ_SCC1 10 -#define IRQ_SCC0 11 -#define IRQ_UDC 12 -#define IRQ_UHC 13 -#define IRQ_MSC 14 -#define IRQ_RTC 15 -#define IRQ_FIR 16 -#define IRQ_SSI 17 -#define IRQ_CIM 18 -#define IRQ_ETH 19 -#define IRQ_AIC 20 -#define IRQ_DMAC 21 -#define IRQ_OST2 22 -#define IRQ_OST1 23 -#define IRQ_OST0 24 -#define IRQ_GPIO3 25 -#define IRQ_GPIO2 26 -#define IRQ_GPIO1 27 -#define IRQ_GPIO0 28 -#define IRQ_LCD 30 - - - - -/************************************************************************* - * CIM - *************************************************************************/ -#define CIM_CFG (CIM_BASE + 0x0000) -#define CIM_CTRL (CIM_BASE + 0x0004) -#define CIM_STATE (CIM_BASE + 0x0008) -#define CIM_IID (CIM_BASE + 0x000C) -#define CIM_RXFIFO (CIM_BASE + 0x0010) -#define CIM_DA (CIM_BASE + 0x0020) -#define CIM_FA (CIM_BASE + 0x0024) -#define CIM_FID (CIM_BASE + 0x0028) -#define CIM_CMD (CIM_BASE + 0x002C) - -#define REG_CIM_CFG REG32(CIM_CFG) -#define REG_CIM_CTRL REG32(CIM_CTRL) -#define REG_CIM_STATE REG32(CIM_STATE) -#define REG_CIM_IID REG32(CIM_IID) -#define REG_CIM_RXFIFO REG32(CIM_RXFIFO) -#define REG_CIM_DA REG32(CIM_DA) -#define REG_CIM_FA REG32(CIM_FA) -#define REG_CIM_FID REG32(CIM_FID) -#define REG_CIM_CMD REG32(CIM_CMD) - -/* CIM Configuration Register (CIM_CFG) */ - -#define CIM_CFG_INV_DAT (1 << 15) -#define CIM_CFG_VSP (1 << 14) -#define CIM_CFG_HSP (1 << 13) -#define CIM_CFG_PCP (1 << 12) -#define CIM_CFG_DUMMY_ZERO (1 << 9) -#define CIM_CFG_EXT_VSYNC (1 << 8) -#define CIM_CFG_PACK_BIT 4 -#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) -#define CIM_CFG_DSM_BIT 0 -#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) - #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ - #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ - #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ - #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ - -/* CIM Control Register (CIM_CTRL) */ - -#define CIM_CTRL_MCLKDIV_BIT 24 -#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) -#define CIM_CTRL_FRC_BIT 16 -#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) - #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ - #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ - #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ - #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ - #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ - #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ - #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ - #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ - #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ - #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ - #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ - #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ - #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ - #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ - #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ - #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ -#define CIM_CTRL_VDDM (1 << 13) -#define CIM_CTRL_DMA_SOFM (1 << 12) -#define CIM_CTRL_DMA_EOFM (1 << 11) -#define CIM_CTRL_DMA_STOPM (1 << 10) -#define CIM_CTRL_RXF_TRIGM (1 << 9) -#define CIM_CTRL_RXF_OFM (1 << 8) -#define CIM_CTRL_RXF_TRIG_BIT 4 -#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) - #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ - #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ - #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ - #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ - #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ - #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ - #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ - #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ -#define CIM_CTRL_DMA_EN (1 << 2) -#define CIM_CTRL_RXF_RST (1 << 1) -#define CIM_CTRL_ENA (1 << 0) - -/* CIM State Register (CIM_STATE) */ - -#define CIM_STATE_DMA_SOF (1 << 6) -#define CIM_STATE_DMA_EOF (1 << 5) -#define CIM_STATE_DMA_STOP (1 << 4) -#define CIM_STATE_RXF_OF (1 << 3) -#define CIM_STATE_RXF_TRIG (1 << 2) -#define CIM_STATE_RXF_EMPTY (1 << 1) -#define CIM_STATE_VDD (1 << 0) - -/* CIM DMA Command Register (CIM_CMD) */ - -#define CIM_CMD_SOFINT (1 << 31) -#define CIM_CMD_EOFINT (1 << 30) -#define CIM_CMD_STOP (1 << 28) -#define CIM_CMD_LEN_BIT 0 -#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) - - - - -/************************************************************************* - * PWM - *************************************************************************/ -#define PWM_CTR(n) (PWM##n##_BASE + 0x000) -#define PWM_PER(n) (PWM##n##_BASE + 0x004) -#define PWM_DUT(n) (PWM##n##_BASE + 0x008) - -#define REG_PWM_CTR(n) REG8(PWM_CTR(n)) -#define REG_PWM_PER(n) REG16(PWM_PER(n)) -#define REG_PWM_DUT(n) REG16(PWM_DUT(n)) - -/* PWM Control Register (PWM_CTR) */ - -#define PWM_CTR_EN (1 << 7) -#define PWM_CTR_SD (1 << 6) -#define PWM_CTR_PRESCALE_BIT 0 -#define PWM_CTR_PRESCALE_MASK (0x3f << PWM_CTR_PRESCALE_BIT) - -/* PWM Period Register (PWM_PER) */ - -#define PWM_PER_PERIOD_BIT 0 -#define PWM_PER_PERIOD_MASK (0x3ff << PWM_PER_PERIOD_BIT) - -/* PWM Duty Register (PWM_DUT) */ - -#define PWM_DUT_FDUTY (1 << 10) -#define PWM_DUT_DUTY_BIT 0 -#define PWM_DUT_DUTY_MASK (0x3ff << PWM_DUT_DUTY_BIT) - - - - -/************************************************************************* - * EMC - *************************************************************************/ -#define EMC_BCR (EMC_BASE + 0x00) -#define EMC_SMCR0 (EMC_BASE + 0x10) -#define EMC_SMCR1 (EMC_BASE + 0x14) -#define EMC_SMCR2 (EMC_BASE + 0x18) -#define EMC_SMCR3 (EMC_BASE + 0x1c) -#define EMC_SMCR4 (EMC_BASE + 0x20) -#define EMC_SMCR5 (EMC_BASE + 0x24) -#define EMC_SMCR6 (EMC_BASE + 0x28) -#define EMC_SMCR7 (EMC_BASE + 0x2c) -#define EMC_SACR0 (EMC_BASE + 0x30) -#define EMC_SACR1 (EMC_BASE + 0x34) -#define EMC_SACR2 (EMC_BASE + 0x38) -#define EMC_SACR3 (EMC_BASE + 0x3c) -#define EMC_SACR4 (EMC_BASE + 0x40) -#define EMC_SACR5 (EMC_BASE + 0x44) -#define EMC_SACR6 (EMC_BASE + 0x48) -#define EMC_SACR7 (EMC_BASE + 0x4c) -#define EMC_NFCSR (EMC_BASE + 0x50) -#define EMC_NFECC (EMC_BASE + 0x54) -#define EMC_PCCR1 (EMC_BASE + 0x60) -#define EMC_PCCR2 (EMC_BASE + 0x64) -#define EMC_PCCR3 (EMC_BASE + 0x68) -#define EMC_PCCR4 (EMC_BASE + 0x6c) -#define EMC_DMCR (EMC_BASE + 0x80) -#define EMC_RTCSR (EMC_BASE + 0x84) -#define EMC_RTCNT (EMC_BASE + 0x88) -#define EMC_RTCOR (EMC_BASE + 0x8c) -#define EMC_DMAR1 (EMC_BASE + 0x90) -#define EMC_DMAR2 (EMC_BASE + 0x94) -#define EMC_DMAR3 (EMC_BASE + 0x98) -#define EMC_DMAR4 (EMC_BASE + 0x9c) - -#define EMC_SDMR0 (EMC_BASE + 0xa000) -#define EMC_SDMR1 (EMC_BASE + 0xb000) -#define EMC_SDMR2 (EMC_BASE + 0xc000) -#define EMC_SDMR3 (EMC_BASE + 0xd000) - -/* NAND command/address/data port */ -#define NAND_DATAPORT 0xB4000000 /* read-write area */ -#define NAND_CMDPORT 0xB4040000 /* write only area */ -#define NAND_ADDRPORT 0xB4080000 /* write only area */ - -#define REG_EMC_BCR REG32(EMC_BCR) -#define REG_EMC_SMCR0 REG32(EMC_SMCR0) -#define REG_EMC_SMCR1 REG32(EMC_SMCR1) -#define REG_EMC_SMCR2 REG32(EMC_SMCR2) -#define REG_EMC_SMCR3 REG32(EMC_SMCR3) -#define REG_EMC_SMCR4 REG32(EMC_SMCR4) -#define REG_EMC_SMCR5 REG32(EMC_SMCR5) -#define REG_EMC_SMCR6 REG32(EMC_SMCR6) -#define REG_EMC_SMCR7 REG32(EMC_SMCR7) -#define REG_EMC_SACR0 REG32(EMC_SACR0) -#define REG_EMC_SACR1 REG32(EMC_SACR1) -#define REG_EMC_SACR2 REG32(EMC_SACR2) -#define REG_EMC_SACR3 REG32(EMC_SACR3) -#define REG_EMC_SACR4 REG32(EMC_SACR4) -#define REG_EMC_SACR5 REG32(EMC_SACR5) -#define REG_EMC_SACR6 REG32(EMC_SACR6) -#define REG_EMC_SACR7 REG32(EMC_SACR7) -#define REG_EMC_NFCSR REG32(EMC_NFCSR) -#define REG_EMC_NFECC REG32(EMC_NFECC) -#define REG_EMC_DMCR REG32(EMC_DMCR) -#define REG_EMC_RTCSR REG16(EMC_RTCSR) -#define REG_EMC_RTCNT REG16(EMC_RTCNT) -#define REG_EMC_RTCOR REG16(EMC_RTCOR) -#define REG_EMC_DMAR1 REG32(EMC_DMAR1) -#define REG_EMC_DMAR2 REG32(EMC_DMAR2) -#define REG_EMC_DMAR3 REG32(EMC_DMAR3) -#define REG_EMC_DMAR4 REG32(EMC_DMAR4) -#define REG_EMC_PCCR1 REG32(EMC_PCCR1) -#define REG_EMC_PCCR2 REG32(EMC_PCCR2) -#define REG_EMC_PCCR3 REG32(EMC_PCCR3) -#define REG_EMC_PCCR4 REG32(EMC_PCCR4) - - -#define EMC_BCR_BRE (1 << 1) - -#define EMC_SMCR_STRV_BIT 24 -#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) -#define EMC_SMCR_TAW_BIT 20 -#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) -#define EMC_SMCR_TBP_BIT 16 -#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) -#define EMC_SMCR_TAH_BIT 12 -#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) -#define EMC_SMCR_TAS_BIT 8 -#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) -#define EMC_SMCR_BW_BIT 6 -#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) -#define EMC_SMCR_BL_BIT 1 -#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) - -#define EMC_SACR_BASE_BIT 8 -#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) -#define EMC_SACR_MASK_BIT 0 -#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) - -#define EMC_NFCSR_RB (1 << 7) -#define EMC_NFCSR_BOOT_SEL_BIT 4 -#define EMC_NFCSR_BOOT_SEL_MASK (0x07 << EMC_NFCSR_BOOT_SEL_BIT) -#define EMC_NFCSR_ERST (1 << 3) -#define EMC_NFCSR_ECCE (1 << 2) -#define EMC_NFCSR_FCE (1 << 1) -#define EMC_NFCSR_NFE (1 << 0) - -#define EMC_NFECC_ECC2_BIT 16 -#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) -#define EMC_NFECC_ECC1_BIT 8 -#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) -#define EMC_NFECC_ECC0_BIT 0 -#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) - -#define EMC_DMCR_BW_BIT 31 -#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) - #define EMC_DMCR_BW_32 (0 << EMC_DMCR_BW_BIT) - #define EMC_DMCR_BW_16 (1 << EMC_DMCR_BW_BIT) -#define EMC_DMCR_CA_BIT 26 -#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) -#define EMC_DMCR_RMODE (1 << 25) -#define EMC_DMCR_RFSH (1 << 24) -#define EMC_DMCR_MRSET (1 << 23) -#define EMC_DMCR_RA_BIT 20 -#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) -#define EMC_DMCR_BA_BIT 19 -#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) - #define EMC_DMCR_BA_2 (0 << EMC_DMCR_BA_BIT) - #define EMC_DMCR_BA_4 (1 << EMC_DMCR_BA_BIT) -#define EMC_DMCR_PDM (1 << 18) -#define EMC_DMCR_EPIN (1 << 17) -#define EMC_DMCR_TRAS_BIT 13 -#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) -#define EMC_DMCR_RCD_BIT 11 -#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) -#define EMC_DMCR_TPC_BIT 8 -#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) -#define EMC_DMCR_TRWL_BIT 5 -#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) -#define EMC_DMCR_TRC_BIT 2 -#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) -#define EMC_DMCR_TCL_BIT 0 -#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) - #define EMC_DMCR_CASL_2 (1 << EMC_DMCR_TCL_BIT) - #define EMC_DMCR_CASL_3 (2 << EMC_DMCR_TCL_BIT) - -#define EMC_RTCSR_CMF (1 << 7) -#define EMC_RTCSR_CKS_BIT 0 -#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) - -#define EMC_DMAR_BASE_BIT 8 -#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) -#define EMC_DMAR_MASK_BIT 0 -#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) - -#define EMC_SDMR_BM (1 << 9) -#define EMC_SDMR_OM_BIT 7 -#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) - #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) -#define EMC_SDMR_CAS_BIT 4 -#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) -#define EMC_SDMR_BT_BIT 3 -#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_INTR (1 << EMC_SDMR_BT_BIT) -#define EMC_SDMR_BL_BIT 0 -#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) - -#define EMC_SDMR_CAS2_16BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS2_32BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) -#define EMC_SDMR_CAS3_16BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS3_32BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) - -#define EMC_PCCR12_AMW (1 << 31) -#define EMC_PCCR12_AMAS_BIT 28 -#define EMC_PCCR12_AMAS_MASK (0x07 << EMC_PCCR12_AMAS_BIT) -#define EMC_PCCR12_AMAH_BIT 24 -#define EMC_PCCR12_AMAH_MASK (0x07 << EMC_PCCR12_AMAH_BIT) -#define EMC_PCCR12_AMPW_BIT 20 -#define EMC_PCCR12_AMPW_MASK (0x0f << EMC_PCCR12_AMPW_BIT) -#define EMC_PCCR12_AMRT_BIT 16 -#define EMC_PCCR12_AMRT_MASK (0x0f << EMC_PCCR12_AMRT_BIT) -#define EMC_PCCR12_CMW (1 << 15) -#define EMC_PCCR12_CMAS_BIT 12 -#define EMC_PCCR12_CMAS_MASK (0x07 << EMC_PCCR12_CMAS_BIT) -#define EMC_PCCR12_CMAH_BIT 8 -#define EMC_PCCR12_CMAH_MASK (0x07 << EMC_PCCR12_CMAH_BIT) -#define EMC_PCCR12_CMPW_BIT 4 -#define EMC_PCCR12_CMPW_MASK (0x0f << EMC_PCCR12_CMPW_BIT) -#define EMC_PCCR12_CMRT_BIT 0 -#define EMC_PCCR12_CMRT_MASK (0x07 << EMC_PCCR12_CMRT_BIT) - -#define EMC_PCCR34_DRS_BIT 16 -#define EMC_PCCR34_DRS_MASK (0x03 << EMC_PCCR34_DRS_BIT) - #define EMC_PCCR34_DRS_SPKR (1 << EMC_PCCR34_DRS_BIT) - #define EMC_PCCR34_DRS_IOIS16 (2 << EMC_PCCR34_DRS_BIT) - #define EMC_PCCR34_DRS_INPACK (3 << EMC_PCCR34_DRS_BIT) -#define EMC_PCCR34_IOIS16 (1 << 15) -#define EMC_PCCR34_IOW (1 << 14) -#define EMC_PCCR34_TCB_BIT 12 -#define EMC_PCCR34_TCB_MASK (0x03 << EMC_PCCR34_TCB_BIT) -#define EMC_PCCR34_IORT_BIT 8 -#define EMC_PCCR34_IORT_MASK (0x07 << EMC_PCCR34_IORT_BIT) -#define EMC_PCCR34_IOAE_BIT 6 -#define EMC_PCCR34_IOAE_MASK (0x03 << EMC_PCCR34_IOAE_BIT) - #define EMC_PCCR34_IOAE_NONE (0 << EMC_PCCR34_IOAE_BIT) - #define EMC_PCCR34_IOAE_1 (1 << EMC_PCCR34_IOAE_BIT) - #define EMC_PCCR34_IOAE_2 (2 << EMC_PCCR34_IOAE_BIT) - #define EMC_PCCR34_IOAE_5 (3 << EMC_PCCR34_IOAE_BIT) -#define EMC_PCCR34_IOAH_BIT 4 -#define EMC_PCCR34_IOAH_MASK (0x03 << EMC_PCCR34_IOAH_BIT) - #define EMC_PCCR34_IOAH_NONE (0 << EMC_PCCR34_IOAH_BIT) - #define EMC_PCCR34_IOAH_1 (1 << EMC_PCCR34_IOAH_BIT) - #define EMC_PCCR34_IOAH_2 (2 << EMC_PCCR34_IOAH_BIT) - #define EMC_PCCR34_IOAH_5 (3 << EMC_PCCR34_IOAH_BIT) -#define EMC_PCCR34_IOPW_BIT 0 -#define EMC_PCCR34_IOPW_MASK (0x0f << EMC_PCCR34_IOPW_BIT) - - - - -/************************************************************************* - * GPIO - *************************************************************************/ -#define GPIO_GPDR(n) (GPIO_BASE + (0x00 + (n)*0x30)) -#define GPIO_GPDIR(n) (GPIO_BASE + (0x04 + (n)*0x30)) -#define GPIO_GPODR(n) (GPIO_BASE + (0x08 + (n)*0x30)) -#define GPIO_GPPUR(n) (GPIO_BASE + (0x0c + (n)*0x30)) -#define GPIO_GPALR(n) (GPIO_BASE + (0x10 + (n)*0x30)) -#define GPIO_GPAUR(n) (GPIO_BASE + (0x14 + (n)*0x30)) -#define GPIO_GPIDLR(n) (GPIO_BASE + (0x18 + (n)*0x30)) -#define GPIO_GPIDUR(n) (GPIO_BASE + (0x1c + (n)*0x30)) -#define GPIO_GPIER(n) (GPIO_BASE + (0x20 + (n)*0x30)) -#define GPIO_GPIMR(n) (GPIO_BASE + (0x24 + (n)*0x30)) -#define GPIO_GPFR(n) (GPIO_BASE + (0x28 + (n)*0x30)) - -#define REG_GPIO_GPDR(n) REG32(GPIO_GPDR((n))) -#define REG_GPIO_GPDIR(n) REG32(GPIO_GPDIR((n))) -#define REG_GPIO_GPODR(n) REG32(GPIO_GPODR((n))) -#define REG_GPIO_GPPUR(n) REG32(GPIO_GPPUR((n))) -#define REG_GPIO_GPALR(n) REG32(GPIO_GPALR((n))) -#define REG_GPIO_GPAUR(n) REG32(GPIO_GPAUR((n))) -#define REG_GPIO_GPIDLR(n) REG32(GPIO_GPIDLR((n))) -#define REG_GPIO_GPIDUR(n) REG32(GPIO_GPIDUR((n))) -#define REG_GPIO_GPIER(n) REG32(GPIO_GPIER((n))) -#define REG_GPIO_GPIMR(n) REG32(GPIO_GPIMR((n))) -#define REG_GPIO_GPFR(n) REG32(GPIO_GPFR((n))) - -#define GPIO_IRQ_LOLEVEL 0 -#define GPIO_IRQ_HILEVEL 1 -#define GPIO_IRQ_FALLEDG 2 -#define GPIO_IRQ_RAISEDG 3 - -#define IRQ_GPIO_0 48 -#define NUM_GPIO 100 - -#define GPIO_GPDR0 GPIO_GPDR(0) -#define GPIO_GPDR1 GPIO_GPDR(1) -#define GPIO_GPDR2 GPIO_GPDR(2) -#define GPIO_GPDR3 GPIO_GPDR(3) -#define GPIO_GPDIR0 GPIO_GPDIR(0) -#define GPIO_GPDIR1 GPIO_GPDIR(1) -#define GPIO_GPDIR2 GPIO_GPDIR(2) -#define GPIO_GPDIR3 GPIO_GPDIR(3) -#define GPIO_GPODR0 GPIO_GPODR(0) -#define GPIO_GPODR1 GPIO_GPODR(1) -#define GPIO_GPODR2 GPIO_GPODR(2) -#define GPIO_GPODR3 GPIO_GPODR(3) -#define GPIO_GPPUR0 GPIO_GPPUR(0) -#define GPIO_GPPUR1 GPIO_GPPUR(1) -#define GPIO_GPPUR2 GPIO_GPPUR(2) -#define GPIO_GPPUR3 GPIO_GPPUR(3) -#define GPIO_GPALR0 GPIO_GPALR(0) -#define GPIO_GPALR1 GPIO_GPALR(1) -#define GPIO_GPALR2 GPIO_GPALR(2) -#define GPIO_GPALR3 GPIO_GPALR(3) -#define GPIO_GPAUR0 GPIO_GPAUR(0) -#define GPIO_GPAUR1 GPIO_GPAUR(1) -#define GPIO_GPAUR2 GPIO_GPAUR(2) -#define GPIO_GPAUR3 GPIO_GPAUR(3) -#define GPIO_GPIDLR0 GPIO_GPIDLR(0) -#define GPIO_GPIDLR1 GPIO_GPIDLR(1) -#define GPIO_GPIDLR2 GPIO_GPIDLR(2) -#define GPIO_GPIDLR3 GPIO_GPIDLR(3) -#define GPIO_GPIDUR0 GPIO_GPIDUR(0) -#define GPIO_GPIDUR1 GPIO_GPIDUR(1) -#define GPIO_GPIDUR2 GPIO_GPIDUR(2) -#define GPIO_GPIDUR3 GPIO_GPIDUR(3) -#define GPIO_GPIER0 GPIO_GPIER(0) -#define GPIO_GPIER1 GPIO_GPIER(1) -#define GPIO_GPIER2 GPIO_GPIER(2) -#define GPIO_GPIER3 GPIO_GPIER(3) -#define GPIO_GPIMR0 GPIO_GPIMR(0) -#define GPIO_GPIMR1 GPIO_GPIMR(1) -#define GPIO_GPIMR2 GPIO_GPIMR(2) -#define GPIO_GPIMR3 GPIO_GPIMR(3) -#define GPIO_GPFR0 GPIO_GPFR(0) -#define GPIO_GPFR1 GPIO_GPFR(1) -#define GPIO_GPFR2 GPIO_GPFR(2) -#define GPIO_GPFR3 GPIO_GPFR(3) - - -/************************************************************************* - * HARB - *************************************************************************/ -#define HARB_HAPOR (HARB_BASE + 0x000) -#define HARB_HMCTR (HARB_BASE + 0x010) -#define HARB_HME8H (HARB_BASE + 0x014) -#define HARB_HMCR1 (HARB_BASE + 0x018) -#define HARB_HMER2 (HARB_BASE + 0x01C) -#define HARB_HMER3 (HARB_BASE + 0x020) -#define HARB_HMLTR (HARB_BASE + 0x024) - -#define REG_HARB_HAPOR REG32(HARB_HAPOR) -#define REG_HARB_HMCTR REG32(HARB_HMCTR) -#define REG_HARB_HME8H REG32(HARB_HME8H) -#define REG_HARB_HMCR1 REG32(HARB_HMCR1) -#define REG_HARB_HMER2 REG32(HARB_HMER2) -#define REG_HARB_HMER3 REG32(HARB_HMER3) -#define REG_HARB_HMLTR REG32(HARB_HMLTR) - -/* HARB Priority Order Register (HARB_HAPOR) */ - -#define HARB_HAPOR_UCHSEL (1 << 7) -#define HARB_HAPOR_PRIO_BIT 0 -#define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT) - -/* AHB Monitor Control Register (HARB_HMCTR) */ - -#define HARB_HMCTR_HET3_BIT 20 -#define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT) -#define HARB_HMCTR_HMS3_BIT 16 -#define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT) -#define HARB_HMCTR_HET2_BIT 12 -#define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT) -#define HARB_HMCTR_HMS2_BIT 8 -#define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT) -#define HARB_HMCTR_HOVF3 (1 << 7) -#define HARB_HMCTR_HOVF2 (1 << 6) -#define HARB_HMCTR_HOVF1 (1 << 5) -#define HARB_HMCTR_HRST (1 << 4) -#define HARB_HMCTR_HEE3 (1 << 2) -#define HARB_HMCTR_HEE2 (1 << 1) -#define HARB_HMCTR_HEE1 (1 << 0) - -/* AHB Monitor Event 8bits High Register (HARB_HME8H) */ - -#define HARB_HME8H_HC8H1_BIT 16 -#define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT) -#define HARB_HME8H_HC8H2_BIT 8 -#define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT) -#define HARB_HME8H_HC8H3_BIT 0 -#define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT) - -/* AHB Monitor Latency Register (HARB_HMLTR) */ - -#define HARB_HMLTR_HLT2_BIT 16 -#define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT) -#define HARB_HMLTR_HLT3_BIT 0 -#define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT) - - - - -/************************************************************************* - * I2C - *************************************************************************/ -#define I2C_DR (I2C_BASE + 0x000) -#define I2C_CR (I2C_BASE + 0x004) -#define I2C_SR (I2C_BASE + 0x008) -#define I2C_GR (I2C_BASE + 0x00C) - -#define REG_I2C_DR REG8(I2C_DR) -#define REG_I2C_CR REG8(I2C_CR) -#define REG_I2C_SR REG8(I2C_SR) -#define REG_I2C_GR REG16(I2C_GR) - -/* I2C Control Register (I2C_CR) */ - -#define I2C_CR_IEN (1 << 4) -#define I2C_CR_STA (1 << 3) -#define I2C_CR_STO (1 << 2) -#define I2C_CR_AC (1 << 1) -#define I2C_CR_I2CE (1 << 0) - -/* I2C Status Register (I2C_SR) */ - -#define I2C_SR_STX (1 << 4) -#define I2C_SR_BUSY (1 << 3) -#define I2C_SR_TEND (1 << 2) -#define I2C_SR_DRF (1 << 1) -#define I2C_SR_ACKF (1 << 0) - - - - -/************************************************************************* - * UDC - *************************************************************************/ -#define UDC_EP0InCR (UDC_BASE + 0x00) -#define UDC_EP0InSR (UDC_BASE + 0x04) -#define UDC_EP0InBSR (UDC_BASE + 0x08) -#define UDC_EP0InMPSR (UDC_BASE + 0x0c) -#define UDC_EP0InDesR (UDC_BASE + 0x14) -#define UDC_EP1InCR (UDC_BASE + 0x20) -#define UDC_EP1InSR (UDC_BASE + 0x24) -#define UDC_EP1InBSR (UDC_BASE + 0x28) -#define UDC_EP1InMPSR (UDC_BASE + 0x2c) -#define UDC_EP1InDesR (UDC_BASE + 0x34) -#define UDC_EP2InCR (UDC_BASE + 0x40) -#define UDC_EP2InSR (UDC_BASE + 0x44) -#define UDC_EP2InBSR (UDC_BASE + 0x48) -#define UDC_EP2InMPSR (UDC_BASE + 0x4c) -#define UDC_EP2InDesR (UDC_BASE + 0x54) -#define UDC_EP3InCR (UDC_BASE + 0x60) -#define UDC_EP3InSR (UDC_BASE + 0x64) -#define UDC_EP3InBSR (UDC_BASE + 0x68) -#define UDC_EP3InMPSR (UDC_BASE + 0x6c) -#define UDC_EP3InDesR (UDC_BASE + 0x74) -#define UDC_EP4InCR (UDC_BASE + 0x80) -#define UDC_EP4InSR (UDC_BASE + 0x84) -#define UDC_EP4InBSR (UDC_BASE + 0x88) -#define UDC_EP4InMPSR (UDC_BASE + 0x8c) -#define UDC_EP4InDesR (UDC_BASE + 0x94) - -#define UDC_EP0OutCR (UDC_BASE + 0x200) -#define UDC_EP0OutSR (UDC_BASE + 0x204) -#define UDC_EP0OutPFNR (UDC_BASE + 0x208) -#define UDC_EP0OutMPSR (UDC_BASE + 0x20c) -#define UDC_EP0OutSBPR (UDC_BASE + 0x210) -#define UDC_EP0OutDesR (UDC_BASE + 0x214) -#define UDC_EP5OutCR (UDC_BASE + 0x2a0) -#define UDC_EP5OutSR (UDC_BASE + 0x2a4) -#define UDC_EP5OutPFNR (UDC_BASE + 0x2a8) -#define UDC_EP5OutMPSR (UDC_BASE + 0x2ac) -#define UDC_EP5OutDesR (UDC_BASE + 0x2b4) -#define UDC_EP6OutCR (UDC_BASE + 0x2c0) -#define UDC_EP6OutSR (UDC_BASE + 0x2c4) -#define UDC_EP6OutPFNR (UDC_BASE + 0x2c8) -#define UDC_EP6OutMPSR (UDC_BASE + 0x2cc) -#define UDC_EP6OutDesR (UDC_BASE + 0x2d4) -#define UDC_EP7OutCR (UDC_BASE + 0x2e0) -#define UDC_EP7OutSR (UDC_BASE + 0x2e4) -#define UDC_EP7OutPFNR (UDC_BASE + 0x2e8) -#define UDC_EP7OutMPSR (UDC_BASE + 0x2ec) -#define UDC_EP7OutDesR (UDC_BASE + 0x2f4) - -#define UDC_DevCFGR (UDC_BASE + 0x400) -#define UDC_DevCR (UDC_BASE + 0x404) -#define UDC_DevSR (UDC_BASE + 0x408) -#define UDC_DevIntR (UDC_BASE + 0x40c) -#define UDC_DevIntMR (UDC_BASE + 0x410) -#define UDC_EPIntR (UDC_BASE + 0x414) -#define UDC_EPIntMR (UDC_BASE + 0x418) - -#define UDC_STCMAR (UDC_BASE + 0x500) -#define UDC_EP0InfR (UDC_BASE + 0x504) -#define UDC_EP1InfR (UDC_BASE + 0x508) -#define UDC_EP2InfR (UDC_BASE + 0x50c) -#define UDC_EP3InfR (UDC_BASE + 0x510) -#define UDC_EP4InfR (UDC_BASE + 0x514) -#define UDC_EP5InfR (UDC_BASE + 0x518) -#define UDC_EP6InfR (UDC_BASE + 0x51c) -#define UDC_EP7InfR (UDC_BASE + 0x520) - -#define UDC_TXCONFIRM (UDC_BASE + 0x41C) -#define UDC_TXZLP (UDC_BASE + 0x420) -#define UDC_RXCONFIRM (UDC_BASE + 0x41C) - -#define UDC_RXFIFO (UDC_BASE + 0x800) -#define UDC_TXFIFOEP0 (UDC_BASE + 0x840) - -#define REG_UDC_EP0InCR REG32(UDC_EP0InCR) -#define REG_UDC_EP0InSR REG32(UDC_EP0InSR) -#define REG_UDC_EP0InBSR REG32(UDC_EP0InBSR) -#define REG_UDC_EP0InMPSR REG32(UDC_EP0InMPSR) -#define REG_UDC_EP0InDesR REG32(UDC_EP0InDesR) -#define REG_UDC_EP1InCR REG32(UDC_EP1InCR) -#define REG_UDC_EP1InSR REG32(UDC_EP1InSR) -#define REG_UDC_EP1InBSR REG32(UDC_EP1InBSR) -#define REG_UDC_EP1InMPSR REG32(UDC_EP1InMPSR) -#define REG_UDC_EP1InDesR REG32(UDC_EP1InDesR) -#define REG_UDC_EP2InCR REG32(UDC_EP2InCR) -#define REG_UDC_EP2InSR REG32(UDC_EP2InSR) -#define REG_UDC_EP2InBSR REG32(UDC_EP2InBSR) -#define REG_UDC_EP2InMPSR REG32(UDC_EP2InMPSR) -#define REG_UDC_EP2InDesR REG32(UDC_EP2InDesR) -#define REG_UDC_EP3InCR REG32(UDC_EP3InCR) -#define REG_UDC_EP3InSR REG32(UDC_EP3InSR) -#define REG_UDC_EP3InBSR REG32(UDC_EP3InBSR) -#define REG_UDC_EP3InMPSR REG32(UDC_EP3InMPSR) -#define REG_UDC_EP3InDesR REG32(UDC_EP3InDesR) -#define REG_UDC_EP4InCR REG32(UDC_EP4InCR) -#define REG_UDC_EP4InSR REG32(UDC_EP4InSR) -#define REG_UDC_EP4InBSR REG32(UDC_EP4InBSR) -#define REG_UDC_EP4InMPSR REG32(UDC_EP4InMPSR) -#define REG_UDC_EP4InDesR REG32(UDC_EP4InDesR) - -#define REG_UDC_EP0OutCR REG32(UDC_EP0OutCR) -#define REG_UDC_EP0OutSR REG32(UDC_EP0OutSR) -#define REG_UDC_EP0OutPFNR REG32(UDC_EP0OutPFNR) -#define REG_UDC_EP0OutMPSR REG32(UDC_EP0OutMPSR) -#define REG_UDC_EP0OutSBPR REG32(UDC_EP0OutSBPR) -#define REG_UDC_EP0OutDesR REG32(UDC_EP0OutDesR) -#define REG_UDC_EP5OutCR REG32(UDC_EP5OutCR) -#define REG_UDC_EP5OutSR REG32(UDC_EP5OutSR) -#define REG_UDC_EP5OutPFNR REG32(UDC_EP5OutPFNR) -#define REG_UDC_EP5OutMPSR REG32(UDC_EP5OutMPSR) -#define REG_UDC_EP5OutDesR REG32(UDC_EP5OutDesR) -#define REG_UDC_EP6OutCR REG32(UDC_EP6OutCR) -#define REG_UDC_EP6OutSR REG32(UDC_EP6OutSR) -#define REG_UDC_EP6OutPFNR REG32(UDC_EP6OutPFNR) -#define REG_UDC_EP6OutMPSR REG32(UDC_EP6OutMPSR) -#define REG_UDC_EP6OutDesR REG32(UDC_EP6OutDesR) -#define REG_UDC_EP7OutCR REG32(UDC_EP7OutCR) -#define REG_UDC_EP7OutSR REG32(UDC_EP7OutSR) -#define REG_UDC_EP7OutPFNR REG32(UDC_EP7OutPFNR) -#define REG_UDC_EP7OutMPSR REG32(UDC_EP7OutMPSR) -#define REG_UDC_EP7OutDesR REG32(UDC_EP7OutDesR) - -#define REG_UDC_DevCFGR REG32(UDC_DevCFGR) -#define REG_UDC_DevCR REG32(UDC_DevCR) -#define REG_UDC_DevSR REG32(UDC_DevSR) -#define REG_UDC_DevIntR REG32(UDC_DevIntR) -#define REG_UDC_DevIntMR REG32(UDC_DevIntMR) -#define REG_UDC_EPIntR REG32(UDC_EPIntR) -#define REG_UDC_EPIntMR REG32(UDC_EPIntMR) - -#define REG_UDC_STCMAR REG32(UDC_STCMAR) -#define REG_UDC_EP0InfR REG32(UDC_EP0InfR) -#define REG_UDC_EP1InfR REG32(UDC_EP1InfR) -#define REG_UDC_EP2InfR REG32(UDC_EP2InfR) -#define REG_UDC_EP3InfR REG32(UDC_EP3InfR) -#define REG_UDC_EP4InfR REG32(UDC_EP4InfR) -#define REG_UDC_EP5InfR REG32(UDC_EP5InfR) -#define REG_UDC_EP6InfR REG32(UDC_EP6InfR) -#define REG_UDC_EP7InfR REG32(UDC_EP7InfR) - -#define UDC_DevCFGR_PI (1 << 5) -#define UDC_DevCFGR_SS (1 << 4) -#define UDC_DevCFGR_SP (1 << 3) -#define UDC_DevCFGR_RW (1 << 2) -#define UDC_DevCFGR_SPD_BIT 0 -#define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT) - #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT) - #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT) - #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT) - -#define UDC_DevCR_DM (1 << 9) -#define UDC_DevCR_BE (1 << 5) -#define UDC_DevCR_RES (1 << 0) - -#define UDC_DevSR_ENUMSPD_BIT 13 -#define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT) - #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT) - #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT) - #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT) -#define UDC_DevSR_SUSP (1 << 12) -#define UDC_DevSR_ALT_BIT 8 -#define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT) -#define UDC_DevSR_INTF_BIT 4 -#define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT) -#define UDC_DevSR_CFG_BIT 0 -#define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT) - -#define UDC_DevIntR_ENUM (1 << 6) -#define UDC_DevIntR_SOF (1 << 5) -#define UDC_DevIntR_US (1 << 4) -#define UDC_DevIntR_UR (1 << 3) -#define UDC_DevIntR_SI (1 << 1) -#define UDC_DevIntR_SC (1 << 0) - -#define UDC_EPIntR_OUTEP_BIT 16 -#define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT) -#define UDC_EPIntR_OUTEP0 0x00010000 -#define UDC_EPIntR_OUTEP5 0x00200000 -#define UDC_EPIntR_OUTEP6 0x00400000 -#define UDC_EPIntR_OUTEP7 0x00800000 -#define UDC_EPIntR_INEP_BIT 0 -#define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT) -#define UDC_EPIntR_INEP0 0x00000001 -#define UDC_EPIntR_INEP1 0x00000002 -#define UDC_EPIntR_INEP2 0x00000004 -#define UDC_EPIntR_INEP3 0x00000008 -#define UDC_EPIntR_INEP4 0x00000010 - - -#define UDC_EPIntMR_OUTEP_BIT 16 -#define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT) -#define UDC_EPIntMR_INEP_BIT 0 -#define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT) - -#define UDC_EPCR_ET_BIT 4 -#define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT) - #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT) - #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT) - #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT) - #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT) -#define UDC_EPCR_SN (1 << 2) -#define UDC_EPCR_F (1 << 1) -#define UDC_EPCR_S (1 << 0) - -#define UDC_EPSR_RXPKTSIZE_BIT 11 -#define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT) -#define UDC_EPSR_IN (1 << 6) -#define UDC_EPSR_OUT_BIT 4 -#define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT) - #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT) - #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT) - #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT) -#define UDC_EPSR_PID_BIT 0 -#define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT) - -#define UDC_EPInfR_MPS_BIT 19 -#define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT) -#define UDC_EPInfR_ALTS_BIT 15 -#define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT) -#define UDC_EPInfR_IFN_BIT 11 -#define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT) -#define UDC_EPInfR_CGN_BIT 7 -#define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT) -#define UDC_EPInfR_EPT_BIT 5 -#define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT) - #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT) - #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT) - #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT) - #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT) -#define UDC_EPInfR_EPD (1 << 4) - #define UDC_EPInfR_EPD_OUT (0 << 4) - #define UDC_EPInfR_EPD_IN (1 << 4) - -#define UDC_EPInfR_EPN_BIT 0 -#define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT) - - - - -/************************************************************************* - * DMAC - *************************************************************************/ -#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) -#define DMAC_DDAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) -#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) -#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) -#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) -#define DMAC_DMAIPR (DMAC_BASE + 0xf8) -#define DMAC_DMACR (DMAC_BASE + 0xfc) - -#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) -#define REG_DMAC_DDAR(n) REG32(DMAC_DDAR((n))) -#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) -#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) -#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) -#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) -#define REG_DMAC_DMACR REG32(DMAC_DMACR) - -#define DMAC_DRSR_RS_BIT 0 -#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_EXTREXTR (0 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_PCMCIAOUT (4 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_PCMCIAIN (5 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_DESOUT (10 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_DESIN (11 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_OST2 (28 << DMAC_DRSR_RS_BIT) - -#define DMAC_DCCSR_EACKS (1 << 31) -#define DMAC_DCCSR_EACKM (1 << 30) -#define DMAC_DCCSR_ERDM_BIT 28 -#define DMAC_DCCSR_ERDM_MASK (0x03 << DMAC_DCCSR_ERDM_BIT) - #define DMAC_DCCSR_ERDM_LLEVEL (0 << DMAC_DCCSR_ERDM_BIT) - #define DMAC_DCCSR_ERDM_FEDGE (1 << DMAC_DCCSR_ERDM_BIT) - #define DMAC_DCCSR_ERDM_HLEVEL (2 << DMAC_DCCSR_ERDM_BIT) - #define DMAC_DCCSR_ERDM_REDGE (3 << DMAC_DCCSR_ERDM_BIT) -#define DMAC_DCCSR_EOPM (1 << 27) -#define DMAC_DCCSR_SAM (1 << 23) -#define DMAC_DCCSR_DAM (1 << 22) -#define DMAC_DCCSR_RDIL_BIT 16 -#define DMAC_DCCSR_RDIL_MASK (0x0f << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_IGN (0 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_2 (1 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_4 (2 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_8 (3 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_12 (4 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_16 (5 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_20 (6 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_24 (7 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_28 (8 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_32 (9 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_48 (10 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_60 (11 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_64 (12 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_124 (13 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_128 (14 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_200 (15 << DMAC_DCCSR_RDIL_BIT) -#define DMAC_DCCSR_SWDH_BIT 14 -#define DMAC_DCCSR_SWDH_MASK (0x03 << DMAC_DCCSR_SWDH_BIT) - #define DMAC_DCCSR_SWDH_32 (0 << DMAC_DCCSR_SWDH_BIT) - #define DMAC_DCCSR_SWDH_8 (1 << DMAC_DCCSR_SWDH_BIT) - #define DMAC_DCCSR_SWDH_16 (2 << DMAC_DCCSR_SWDH_BIT) -#define DMAC_DCCSR_DWDH_BIT 12 -#define DMAC_DCCSR_DWDH_MASK (0x03 << DMAC_DCCSR_DWDH_BIT) - #define DMAC_DCCSR_DWDH_32 (0 << DMAC_DCCSR_DWDH_BIT) - #define DMAC_DCCSR_DWDH_8 (1 << DMAC_DCCSR_DWDH_BIT) - #define DMAC_DCCSR_DWDH_16 (2 << DMAC_DCCSR_DWDH_BIT) -#define DMAC_DCCSR_DS_BIT 8 -#define DMAC_DCCSR_DS_MASK (0x07 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_32b (0 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_8b (1 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_16b (2 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_16B (3 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_32B (4 << DMAC_DCCSR_DS_BIT) -#define DMAC_DCCSR_TM (1 << 7) -#define DMAC_DCCSR_AR (1 << 4) -#define DMAC_DCCSR_TC (1 << 3) -#define DMAC_DCCSR_HLT (1 << 2) -#define DMAC_DCCSR_TCIE (1 << 1) -#define DMAC_DCCSR_CHDE (1 << 0) - -#define DMAC_DMAIPR_CINT_BIT 8 -#define DMAC_DMAIPR_CINT_MASK (0xff << DMAC_DMAIPR_CINT_BIT) - -#define DMAC_DMACR_PR_BIT 8 -#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_01234567 (0 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_02314675 (1 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_20136457 (2 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_ROUNDROBIN (3 << DMAC_DMACR_PR_BIT) -#define DMAC_DMACR_HTR (1 << 3) -#define DMAC_DMACR_AER (1 << 2) -#define DMAC_DMACR_DME (1 << 0) - -#define IRQ_DMA_0 32 -#define NUM_DMA 6 - - -/************************************************************************* - * AIC - *************************************************************************/ -#define AIC_FR (AIC_BASE + 0x000) -#define AIC_CR (AIC_BASE + 0x004) -#define AIC_ACCR1 (AIC_BASE + 0x008) -#define AIC_ACCR2 (AIC_BASE + 0x00C) -#define AIC_I2SCR (AIC_BASE + 0x010) -#define AIC_SR (AIC_BASE + 0x014) -#define AIC_ACSR (AIC_BASE + 0x018) -#define AIC_I2SSR (AIC_BASE + 0x01C) -#define AIC_ACCAR (AIC_BASE + 0x020) -#define AIC_ACCDR (AIC_BASE + 0x024) -#define AIC_ACSAR (AIC_BASE + 0x028) -#define AIC_ACSDR (AIC_BASE + 0x02C) -#define AIC_I2SDIV (AIC_BASE + 0x030) -#define AIC_DR (AIC_BASE + 0x034) - -#define REG_AIC_FR REG32(AIC_FR) -#define REG_AIC_CR REG32(AIC_CR) -#define REG_AIC_ACCR1 REG32(AIC_ACCR1) -#define REG_AIC_ACCR2 REG32(AIC_ACCR2) -#define REG_AIC_I2SCR REG32(AIC_I2SCR) -#define REG_AIC_SR REG32(AIC_SR) -#define REG_AIC_ACSR REG32(AIC_ACSR) -#define REG_AIC_I2SSR REG32(AIC_I2SSR) -#define REG_AIC_ACCAR REG32(AIC_ACCAR) -#define REG_AIC_ACCDR REG32(AIC_ACCDR) -#define REG_AIC_ACSAR REG32(AIC_ACSAR) -#define REG_AIC_ACSDR REG32(AIC_ACSDR) -#define REG_AIC_I2SDIV REG32(AIC_I2SDIV) -#define REG_AIC_DR REG32(AIC_DR) - -/* AIC Controller Configuration Register (AIC_FR) */ - -#define AIC_FR_RFTH_BIT 12 -#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) -#define AIC_FR_TFTH_BIT 8 -#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) -#define AIC_FR_AUSEL (1 << 4) -#define AIC_FR_RST (1 << 3) -#define AIC_FR_BCKD (1 << 2) -#define AIC_FR_SYNCD (1 << 1) -#define AIC_FR_ENB (1 << 0) - -/* AIC Controller Common Control Register (AIC_CR) */ - -#define AIC_CR_RDMS (1 << 15) -#define AIC_CR_TDMS (1 << 14) -#define AIC_CR_FLUSH (1 << 8) -#define AIC_CR_EROR (1 << 6) -#define AIC_CR_ETUR (1 << 5) -#define AIC_CR_ERFS (1 << 4) -#define AIC_CR_ETFS (1 << 3) -#define AIC_CR_ENLBF (1 << 2) -#define AIC_CR_ERPL (1 << 1) -#define AIC_CR_EREC (1 << 0) - -/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ - -#define AIC_ACCR1_RS_BIT 16 -#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) - #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ - #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ - #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ - #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit */ - #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit */ - #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit */ - #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit */ - #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ - #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit */ - #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit */ -#define AIC_ACCR1_XS_BIT 0 -#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) - #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ - #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ - #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ - #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit */ - #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit */ - #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit */ - #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit */ - #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ - #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit */ - #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit */ - -/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ - -#define AIC_ACCR2_ERSTO (1 << 18) -#define AIC_ACCR2_ESADR (1 << 17) -#define AIC_ACCR2_ECADT (1 << 16) -#define AIC_ACCR2_OASS_BIT 8 -#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) - #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ - #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ - #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ - #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ -#define AIC_ACCR2_IASS_BIT 6 -#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) - #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ - #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ - #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ - #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ -#define AIC_ACCR2_SO (1 << 3) -#define AIC_ACCR2_SR (1 << 2) -#define AIC_ACCR2_SS (1 << 1) -#define AIC_ACCR2_SA (1 << 0) - -/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ - -#define AIC_I2SCR_STPBK (1 << 12) -#define AIC_I2SCR_WL_BIT 1 -#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) - #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ - #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ - #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ - #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ - #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ -#define AIC_I2SCR_AMSL (1 << 0) - -/* AIC Controller FIFO Status Register (AIC_SR) */ - -#define AIC_SR_RFL_BIT 24 -#define AIC_SR_RFL_MASK (0x1f << AIC_SR_RFL_BIT) -#define AIC_SR_TFL_BIT 8 -#define AIC_SR_TFL_MASK (0x1f << AIC_SR_TFL_BIT) -#define AIC_SR_ROR (1 << 6) -#define AIC_SR_TUR (1 << 5) -#define AIC_SR_RFS (1 << 4) -#define AIC_SR_TFS (1 << 3) - -/* AIC Controller AC-link Status Register (AIC_ACSR) */ - -#define AIC_ACSR_CRDY (1 << 20) -#define AIC_ACSR_CLPM (1 << 19) -#define AIC_ACSR_RSTO (1 << 18) -#define AIC_ACSR_SADR (1 << 17) -#define AIC_ACSR_CADT (1 << 16) - -/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ - -#define AIC_I2SSR_BSY (1 << 2) - -/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ - -#define AIC_ACCAR_CAR_BIT 0 -#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) - -/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ - -#define AIC_ACCDR_CDR_BIT 0 -#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) - -/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ - -#define AIC_ACSAR_SAR_BIT 0 -#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) - -/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ - -#define AIC_ACSDR_SDR_BIT 0 -#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) - -/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ - -#define AIC_I2SDIV_DIV_BIT 0 -#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) - #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ - #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ - #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ - #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ - #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ - #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ - - - - -/************************************************************************* - * LCD - *************************************************************************/ -#define LCD_CFG (LCD_BASE + 0x00) -#define LCD_VSYNC (LCD_BASE + 0x04) -#define LCD_HSYNC (LCD_BASE + 0x08) -#define LCD_VAT (LCD_BASE + 0x0c) -#define LCD_DAH (LCD_BASE + 0x10) -#define LCD_DAV (LCD_BASE + 0x14) -#define LCD_PS (LCD_BASE + 0x18) -#define LCD_CLS (LCD_BASE + 0x1c) -#define LCD_SPL (LCD_BASE + 0x20) -#define LCD_REV (LCD_BASE + 0x24) -#define LCD_CTRL (LCD_BASE + 0x30) -#define LCD_STATE (LCD_BASE + 0x34) -#define LCD_IID (LCD_BASE + 0x38) -#define LCD_DA0 (LCD_BASE + 0x40) -#define LCD_SA0 (LCD_BASE + 0x44) -#define LCD_FID0 (LCD_BASE + 0x48) -#define LCD_CMD0 (LCD_BASE + 0x4c) -#define LCD_DA1 (LCD_BASE + 0x50) -#define LCD_SA1 (LCD_BASE + 0x54) -#define LCD_FID1 (LCD_BASE + 0x58) -#define LCD_CMD1 (LCD_BASE + 0x5c) - -#define REG_LCD_CFG REG32(LCD_CFG) -#define REG_LCD_VSYNC REG32(LCD_VSYNC) -#define REG_LCD_HSYNC REG32(LCD_HSYNC) -#define REG_LCD_VAT REG32(LCD_VAT) -#define REG_LCD_DAH REG32(LCD_DAH) -#define REG_LCD_DAV REG32(LCD_DAV) -#define REG_LCD_PS REG32(LCD_PS) -#define REG_LCD_CLS REG32(LCD_CLS) -#define REG_LCD_SPL REG32(LCD_SPL) -#define REG_LCD_REV REG32(LCD_REV) -#define REG_LCD_CTRL REG32(LCD_CTRL) -#define REG_LCD_STATE REG32(LCD_STATE) -#define REG_LCD_IID REG32(LCD_IID) -#define REG_LCD_DA0 REG32(LCD_DA0) -#define REG_LCD_SA0 REG32(LCD_SA0) -#define REG_LCD_FID0 REG32(LCD_FID0) -#define REG_LCD_CMD0 REG32(LCD_CMD0) -#define REG_LCD_DA1 REG32(LCD_DA1) -#define REG_LCD_SA1 REG32(LCD_SA1) -#define REG_LCD_FID1 REG32(LCD_FID1) -#define REG_LCD_CMD1 REG32(LCD_CMD1) - -#define LCD_CFG_PDW_BIT 4 -#define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) - #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT) - #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT) - #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT) - #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT) -#define LCD_CFG_MODE_BIT 0 -#define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT) - -#define LCD_VSYNC_VPS_BIT 16 -#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) -#define LCD_VSYNC_VPE_BIT 0 -#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) - -#define LCD_HSYNC_HPS_BIT 16 -#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) -#define LCD_HSYNC_HPE_BIT 0 -#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) - -#define LCD_VAT_HT_BIT 16 -#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) -#define LCD_VAT_VT_BIT 0 -#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) - -#define LCD_DAH_HDS_BIT 16 -#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) -#define LCD_DAH_HDE_BIT 0 -#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) - -#define LCD_DAV_VDS_BIT 16 -#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) -#define LCD_DAV_VDE_BIT 0 -#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) - -#define LCD_CTRL_BST_BIT 28 -#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) - #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) - #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) - #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) -#define LCD_CTRL_RGB555 (1 << 27) -#define LCD_CTRL_OFUP (1 << 26) -#define LCD_CTRL_FRC_BIT 24 -#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) - #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) - #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) - #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) -#define LCD_CTRL_PDD_BIT 16 -#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) -#define LCD_CTRL_EOFM (1 << 13) -#define LCD_CTRL_SOFM (1 << 12) -#define LCD_CTRL_OFUM (1 << 11) -#define LCD_CTRL_IFUM0 (1 << 10) -#define LCD_CTRL_IFUM1 (1 << 9) -#define LCD_CTRL_LDDM (1 << 8) -#define LCD_CTRL_QDM (1 << 7) -#define LCD_CTRL_BEDN (1 << 6) -#define LCD_CTRL_PEDN (1 << 5) -#define LCD_CTRL_DIS (1 << 4) -#define LCD_CTRL_ENA (1 << 3) -#define LCD_CTRL_BPP_BIT 0 -#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) - -#define LCD_STATE_QD (1 << 7) -#define LCD_STATE_EOF (1 << 5) -#define LCD_STATE_SOF (1 << 4) -#define LCD_STATE_OFU (1 << 3) -#define LCD_STATE_IFU0 (1 << 2) -#define LCD_STATE_IFU1 (1 << 1) -#define LCD_STATE_LDD (1 << 0) - -#define LCD_CMD_SOFINT (1 << 31) -#define LCD_CMD_EOFINT (1 << 30) -#define LCD_CMD_PAL (1 << 28) -#define LCD_CMD_LEN_BIT 0 -#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) - - - - -/************************************************************************* - * DES - *************************************************************************/ -#define DES_CR1 (DES_BASE + 0x000) -#define DES_CR2 (DES_BASE + 0x004) -#define DES_SR (DES_BASE + 0x008) -#define DES_K1L (DES_BASE + 0x010) -#define DES_K1R (DES_BASE + 0x014) -#define DES_K2L (DES_BASE + 0x018) -#define DES_K2R (DES_BASE + 0x01C) -#define DES_K3L (DES_BASE + 0x020) -#define DES_K3R (DES_BASE + 0x024) -#define DES_IVL (DES_BASE + 0x028) -#define DES_IVR (DES_BASE + 0x02C) -#define DES_DIN (DES_BASE + 0x030) -#define DES_DOUT (DES_BASE + 0x034) - -#define REG_DES_CR1 REG32(DES_CR1) -#define REG_DES_CR2 REG32(DES_CR2) -#define REG_DES_SR REG32(DES_SR) -#define REG_DES_K1L REG32(DES_K1L) -#define REG_DES_K1R REG32(DES_K1R) -#define REG_DES_K2L REG32(DES_K2L) -#define REG_DES_K2R REG32(DES_K2R) -#define REG_DES_K3L REG32(DES_K3L) -#define REG_DES_K3R REG32(DES_K3R) -#define REG_DES_IVL REG32(DES_IVL) -#define REG_DES_IVR REG32(DES_IVR) -#define REG_DES_DIN REG32(DES_DIN) -#define REG_DES_DOUT REG32(DES_DOUT) - -/* DES Control Register 1 (DES_CR1) */ - -#define DES_CR1_EN (1 << 0) - -/* DES Control Register 2 (DES_CR2) */ - -#define DES_CR2_ENDEC (1 << 3) -#define DES_CR2_MODE (1 << 2) -#define DES_CR2_ALG (1 << 1) -#define DES_CR2_DMAE (1 << 0) - -/* DES State Register (DES_SR) */ - -#define DES_SR_IN_FULL (1 << 5) -#define DES_SR_IN_LHF (1 << 4) -#define DES_SR_IN_EMPTY (1 << 3) -#define DES_SR_OUT_FULL (1 << 2) -#define DES_SR_OUT_GHF (1 << 1) -#define DES_SR_OUT_EMPTY (1 << 0) - - - - -/************************************************************************* - * CPM - *************************************************************************/ -#define CPM_CFCR (CPM_BASE+0x00) -#define CPM_PLCR1 (CPM_BASE+0x10) -#define CPM_OCR (CPM_BASE+0x1c) -#define CPM_CFCR2 (CPM_BASE+0x60) -#define CPM_LPCR (CPM_BASE+0x04) -#define CPM_RSTR (CPM_BASE+0x08) -#define CPM_MSCR (CPM_BASE+0x20) -#define CPM_SCR (CPM_BASE+0x24) -#define CPM_WRER (CPM_BASE+0x28) -#define CPM_WFER (CPM_BASE+0x2c) -#define CPM_WER (CPM_BASE+0x30) -#define CPM_WSR (CPM_BASE+0x34) -#define CPM_GSR0 (CPM_BASE+0x38) -#define CPM_GSR1 (CPM_BASE+0x3c) -#define CPM_GSR2 (CPM_BASE+0x40) -#define CPM_SPR (CPM_BASE+0x44) -#define CPM_GSR3 (CPM_BASE+0x48) - -#define REG_CPM_CFCR REG32(CPM_CFCR) -#define REG_CPM_PLCR1 REG32(CPM_PLCR1) -#define REG_CPM_OCR REG32(CPM_OCR) -#define REG_CPM_CFCR2 REG32(CPM_CFCR2) -#define REG_CPM_LPCR REG32(CPM_LPCR) -#define REG_CPM_RSTR REG32(CPM_RSTR) -#define REG_CPM_MSCR REG32(CPM_MSCR) -#define REG_CPM_SCR REG32(CPM_SCR) -#define REG_CPM_WRER REG32(CPM_WRER) -#define REG_CPM_WFER REG32(CPM_WFER) -#define REG_CPM_WER REG32(CPM_WER) -#define REG_CPM_WSR REG32(CPM_WSR) -#define REG_CPM_GSR0 REG32(CPM_GSR0) -#define REG_CPM_GSR1 REG32(CPM_GSR1) -#define REG_CPM_GSR2 REG32(CPM_GSR2) -#define REG_CPM_SPR REG32(CPM_SPR) -#define REG_CPM_GSR3 REG32(CPM_GSR3) - -#define CPM_CFCR_SSI (1 << 31) -#define CPM_CFCR_LCD (1 << 30) -#define CPM_CFCR_I2S (1 << 29) -#define CPM_CFCR_UCS (1 << 28) -#define CPM_CFCR_UFR_BIT 25 -#define CPM_CFCR_UFR_MASK (0x07 << CPM_CFCR_UFR_BIT) -#define CPM_CFCR_MSC (1 << 24) -#define CPM_CFCR_CKOEN2 (1 << 23) -#define CPM_CFCR_CKOEN1 (1 << 22) -#define CPM_CFCR_UPE (1 << 20) -#define CPM_CFCR_MFR_BIT 16 -#define CPM_CFCR_MFR_MASK (0x0f << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_1 (0 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_2 (1 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_3 (2 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_4 (3 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_6 (4 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_8 (5 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_12 (6 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_16 (7 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_24 (8 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_32 (9 << CPM_CFCR_MFR_BIT) -#define CPM_CFCR_LFR_BIT 12 -#define CPM_CFCR_LFR_MASK (0x0f << CPM_CFCR_LFR_BIT) -#define CPM_CFCR_PFR_BIT 8 -#define CPM_CFCR_PFR_MASK (0x0f << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_1 (0 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_2 (1 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_3 (2 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_4 (3 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_6 (4 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_8 (5 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_12 (6 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_16 (7 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_24 (8 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_32 (9 << CPM_CFCR_PFR_BIT) -#define CPM_CFCR_SFR_BIT 4 -#define CPM_CFCR_SFR_MASK (0x0f << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_1 (0 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_2 (1 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_3 (2 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_4 (3 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_6 (4 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_8 (5 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_12 (6 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_16 (7 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_24 (8 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_32 (9 << CPM_CFCR_SFR_BIT) -#define CPM_CFCR_IFR_BIT 0 -#define CPM_CFCR_IFR_MASK (0x0f << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_1 (0 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_2 (1 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_3 (2 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_4 (3 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_6 (4 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_8 (5 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_12 (6 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_16 (7 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_24 (8 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_32 (9 << CPM_CFCR_IFR_BIT) - -#define CPM_PLCR1_PLL1FD_BIT 23 -#define CPM_PLCR1_PLL1FD_MASK (0x1ff << CPM_PLCR1_PLL1FD_BIT) -#define CPM_PLCR1_PLL1RD_BIT 18 -#define CPM_PLCR1_PLL1RD_MASK (0x1f << CPM_PLCR1_PLL1RD_BIT) -#define CPM_PLCR1_PLL1OD_BIT 16 -#define CPM_PLCR1_PLL1OD_MASK (0x03 << CPM_PLCR1_PLL1OD_BIT) -#define CPM_PLCR1_PLL1S (1 << 10) -#define CPM_PLCR1_PLL1BP (1 << 9) -#define CPM_PLCR1_PLL1EN (1 << 8) -#define CPM_PLCR1_PLL1ST_BIT 0 -#define CPM_PLCR1_PLL1ST_MASK (0xff << CPM_PLCR1_PLL1ST_BIT) - -#define CPM_OCR_O1ST_BIT 16 -#define CPM_OCR_O1ST_MASK (0xff << CPM_OCR_O1ST_BIT) -#define CPM_OCR_O2SE_BIT 8 -#define CPM_OCR_O2SE (1 << CPM_OCR_O2SE_BIT) -#define CPM_OCR_SUSPEND1_BIT 7 -#define CPM_OCR_SUSPEND1 (1 << CPM_OCR_SUSPEND1_BIT) -#define CPM_OCR_SUSPEND0_BIT 6 -#define CPM_OCR_SUSPEND0 (1 << CPM_OCR_SUSPEND0_BIT) - -#define CPM_CFCR2_PXFR_BIT 0 -#define CPM_CFCR2_PXFR_MASK (0x1ff << CPM_CFCR2_PXFR_BIT) - -#define CPM_LPCR_DUTY_BIT 3 -#define CPM_LPCR_DUTY_MASK (0x1f << CPM_LPCR_DUTY_BIT) -#define CPM_LPCR_DOZE (1 << 2) -#define CPM_LPCR_LPM_BIT 0 -#define CPM_LPCR_LPM_MASK (0x03 << CPM_LPCR_LPM_BIT) - #define CPM_LPCR_LPM_IDLE (0 << CPM_LPCR_LPM_BIT) - #define CPM_LPCR_LPM_SLEEP (1 << CPM_LPCR_LPM_BIT) - #define CPM_LPCR_LPM_HIBERNATE (2 << CPM_LPCR_LPM_BIT) - -#define CPM_RSTR_SR (1 << 2) -#define CPM_RSTR_WR (1 << 1) -#define CPM_RSTR_HR (1 << 0) - -#define CPM_MSCR_MSTP_BIT 0 -#define CPM_MSCR_MSTP_MASK (0x1ffffff << CPM_MSCR_MSTP_BIT) - #define CPM_MSCR_MSTP_UART0 0 - #define CPM_MSCR_MSTP_UART1 1 - #define CPM_MSCR_MSTP_UART2 2 - #define CPM_MSCR_MSTP_OST 3 - #define CPM_MSCR_MSTP_RTC 4 - #define CPM_MSCR_MSTP_DMAC 5 - #define CPM_MSCR_MSTP_UHC 6 - #define CPM_MSCR_MSTP_LCD 7 - #define CPM_MSCR_MSTP_I2C 8 - #define CPM_MSCR_MSTP_AIC1 9 - #define CPM_MSCR_MSTP_PWM0 10 - #define CPM_MSCR_MSTP_PWM1 11 - #define CPM_MSCR_MSTP_SSI 12 - #define CPM_MSCR_MSTP_MSC 13 - #define CPM_MSCR_MSTP_SCC 14 - #define CPM_MSCR_MSTP_FIR 16 - #define CPM_MSCR_MSTP_AIC2 18 - #define CPM_MSCR_MSTP_DES 19 - #define CPM_MSCR_MSTP_UART3 20 - #define CPM_MSCR_MSTP_ETH 21 - #define CPM_MSCR_MSTP_PS2 22 - #define CPM_MSCR_MSTP_CIM 23 - #define CPM_MSCR_MSTP_UDC 24 - -#define CPM_SCR_O1SE (1 << 4) -#define CPM_SCR_HGP (1 << 3) -#define CPM_SCR_HZP (1 << 2) -#define CPM_SCR_HZM (1 << 1) - -#define CPM_WRER_RE_BIT 0 -#define CPM_WRER_RE_MASK (0xffff << CPM_WRER_RE_BIT) - -#define CPM_WFER_FE_BIT 0 -#define CPM_WFER_FE_MASK (0xffff << CPM_WFER_FE_BIT) - -#define CPM_WER_WERTC (1 << 31) -#define CPM_WER_WEETH (1 << 30) -#define CPM_WER_WE_BIT 0 -#define CPM_WER_WE_MASK (0xffff << CPM_WER_WE_BIT) - -#define CPM_WSR_WSRTC (1 << 31) -#define CPM_WSR_WSETH (1 << 30) -#define CPM_WSR_WS_BIT 0 -#define CPM_WSR_WS_MASK (0xffff << CPM_WSR_WS_BIT) - - - - -/************************************************************************* - * SSI - *************************************************************************/ -#define SSI_DR (SSI_BASE + 0x000) -#define SSI_CR0 (SSI_BASE + 0x004) -#define SSI_CR1 (SSI_BASE + 0x008) -#define SSI_SR (SSI_BASE + 0x00C) -#define SSI_ITR (SSI_BASE + 0x010) -#define SSI_ICR (SSI_BASE + 0x014) -#define SSI_GR (SSI_BASE + 0x018) - -#define REG_SSI_DR REG32(SSI_DR) -#define REG_SSI_CR0 REG16(SSI_CR0) -#define REG_SSI_CR1 REG32(SSI_CR1) -#define REG_SSI_SR REG32(SSI_SR) -#define REG_SSI_ITR REG16(SSI_ITR) -#define REG_SSI_ICR REG8(SSI_ICR) -#define REG_SSI_GR REG16(SSI_GR) - -/* SSI Data Register (SSI_DR) */ - -#define SSI_DR_GPC_BIT 0 -#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) - -/* SSI Control Register 0 (SSI_CR0) */ - -#define SSI_CR0_SSIE (1 << 15) -#define SSI_CR0_TIE (1 << 14) -#define SSI_CR0_RIE (1 << 13) -#define SSI_CR0_TEIE (1 << 12) -#define SSI_CR0_REIE (1 << 11) -#define SSI_CR0_LOOP (1 << 10) -#define SSI_CR0_RFINE (1 << 9) -#define SSI_CR0_RFINC (1 << 8) -#define SSI_CR0_FSEL (1 << 6) -#define SSI_CR0_TFLUSH (1 << 2) -#define SSI_CR0_RFLUSH (1 << 1) -#define SSI_CR0_DISREV (1 << 0) - -/* SSI Control Register 1 (SSI_CR1) */ - -#define SSI_CR1_FRMHL_BIT 30 -#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) - #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ - #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ - #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ - #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ -#define SSI_CR1_TFVCK_BIT 28 -#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) -#define SSI_CR1_TCKFI_BIT 26 -#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) -#define SSI_CR1_LFST (1 << 25) -#define SSI_CR1_ITFRM (1 << 24) -#define SSI_CR1_UNFIN (1 << 23) -#define SSI_CR1_MULTS (1 << 22) -#define SSI_CR1_FMAT_BIT 20 -#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) - #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ - #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ - #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ - #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ -#define SSI_CR1_MCOM_BIT 12 -#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) - #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ - #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ - #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ - #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ - #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ - #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ - #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ - #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ - #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ - #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ - #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ - #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ - #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ - #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ - #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ - #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ -#define SSI_CR1_TTRG_BIT 10 -#define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */ - #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */ - #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */ - #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */ -#define SSI_CR1_RTRG_BIT 8 -#define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */ - #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */ - #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */ - #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */ -#define SSI_CR1_FLEN_BIT 4 -#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) -#define SSI_CR1_PHA (1 << 1) -#define SSI_CR1_POL (1 << 0) - -/* SSI Status Register (SSI_SR) */ - -#define SSI_SR_TFIFONUM_BIT 13 -#define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT) -#define SSI_SR_RFIFONUM_BIT 8 -#define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT) -#define SSI_SR_END (1 << 7) -#define SSI_SR_BUSY (1 << 6) -#define SSI_SR_TFF (1 << 5) -#define SSI_SR_RFE (1 << 4) -#define SSI_SR_TFHE (1 << 3) -#define SSI_SR_RFHF (1 << 2) -#define SSI_SR_UNDR (1 << 1) -#define SSI_SR_OVER (1 << 0) - -/* SSI Interval Time Control Register (SSI_ITR) */ - -#define SSI_ITR_CNTCLK (1 << 15) -#define SSI_ITR_IVLTM_BIT 0 -#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) - -#ifndef __ASSEMBLY__ - -/*************************************************************************** - * MSC - ***************************************************************************/ - -#define __msc_start_op() \ - ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) - -#define __msc_set_resto(to) ( REG_MSC_RESTO = to ) -#define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) -#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) -#define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) -#define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) -#define __msc_get_nob() ( REG_MSC_NOB ) -#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) -#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) -#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) -#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) - -#define __msc_set_cmdat_bus_width1() \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ - REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ -} while(0) - -#define __msc_set_cmdat_bus_width4() \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ - REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ -} while(0) - -#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) -#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) -#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) -#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) -#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) -#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) -#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) -#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) - -/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ -#define __msc_set_cmdat_res_format(r) \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ - REG_MSC_CMDAT |= (r); \ -} while(0) - -#define __msc_clear_cmdat() \ - REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ - MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ - MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) - -#define __msc_get_imask() ( REG_MSC_IMASK ) -#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) -#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) -#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) -#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) -#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) -#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) -#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) -#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) -#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) -#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) -#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) -#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) - -/* n=1,2,4,8,16,32,64,128 */ -#define __msc_set_clkrt_div(n) \ -do { \ - REG_MSC_CLKRT &= ~MSC_CLKRT_CLK_RATE_MASK; \ - REG_MSC_CLKRT |= MSC_CLKRT_CLK_RATE_DIV_##n; \ -} while(0) - -#define __msc_get_ireg() ( REG_MSC_IREG ) -#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) -#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) -#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) -#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) -#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) -#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) -#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) -#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) - -#define __msc_get_stat() ( REG_MSC_STAT ) -#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) -#define __msc_stat_crc_err() \ - ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) -#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) -#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) -#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) -#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) -#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) - -#define __msc_rd_resfifo() ( REG_MSC_RES ) -#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) -#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) - -#define __msc_reset() \ -do { \ - REG_MSC_STRPCL = MSC_STRPCL_RESET; \ - while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ -} while (0) - -#define __msc_start_clk() \ -do { \ - REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ - REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_START; \ -} while (0) - -#define __msc_stop_clk() \ -do { \ - REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ - REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_STOP; \ -} while (0) - -#define MMC_CLK 19169200 -#define SD_CLK 24576000 - -/* msc_clk should little than pclk and little than clk retrieve from card */ -#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ -do { \ - unsigned int rate, pclk, i; \ - pclk = dev_clk; \ - rate = type?SD_CLK:MMC_CLK; \ - if (msc_clk && msc_clk < pclk) \ - pclk = msc_clk; \ - i = 0; \ - while (pclk < rate) \ - { \ - i ++; \ - rate >>= 1; \ - } \ - lv = i; \ -} while(0) - -/* divide rate to little than or equal to 400kHz */ -#define __msc_calc_slow_clk_divisor(type, lv) \ -do { \ - unsigned int rate, i; \ - rate = (type?SD_CLK:MMC_CLK)/1000/400; \ - i = 0; \ - while (rate > 0) \ - { \ - rate >>= 1; \ - i ++; \ - } \ - lv = i; \ -} while(0) - -/*************************************************************************** - * RTC - ***************************************************************************/ - -#define __rtc_start() ( REG_RTC_RCR |= RTC_RCR_START ) -#define __rtc_stop() ( REG_RTC_RCR &= ~RTC_RCR_START ) - -#define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE ) -#define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE ) -#define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE ) -#define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE ) - -#define __rtc_enable_1hz_irq() ( REG_RTC_RCR |= RTC_RCR_HZIE ) -#define __rtc_disable_1hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_HZIE ) - -#define __rtc_is_alarm_flag() ( REG_RTC_RCR & RTC_RCR_AF ) -#define __rtc_is_1hz_flag() ( REG_RTC_RCR & RTC_RCR_HZ ) -#define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF ) -#define __rtc_clear_1hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_HZ ) - -#define __rtc_set_second(s) ( REG_RTC_RSR = (s) ) -#define __rtc_get_second() REG_RTC_RSR -#define __rtc_set_alarm(s) ( REG_RTC_RSAR = (s) ) -#define __rtc_get_alarm() REG_RTC_RSAR - -#define __rtc_adjust_1hz(f32k) \ - ( REG_RTC_RGR = (REG_RTC_RGR & ~(RTC_REG_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 ) -#define __rtc_lock_1hz() ( REG_RTC_RGR |= RTC_RGR_LOCK ) - - -/*************************************************************************** - * FIR - ***************************************************************************/ - -/* enable/disable fir unit */ -#define __fir_enable() ( REG_FIR_CR1 |= FIR_CR1_FIRUE ) -#define __fir_disable() ( REG_FIR_CR1 &= ~FIR_CR1_FIRUE ) - -/* enable/disable address comparison */ -#define __fir_enable_ac() ( REG_FIR_CR1 |= FIR_CR1_ACE ) -#define __fir_disable_ac() ( REG_FIR_CR1 &= ~FIR_CR1_ACE ) - -/* select frame end mode as underrun or normal */ -#define __fir_set_eous() ( REG_FIR_CR1 |= FIR_CR1_EOUS ) -#define __fir_clear_eous() ( REG_FIR_CR1 &= ~FIR_CR1_EOUS ) - -/* enable/disable transmitter idle interrupt */ -#define __fir_enable_tii() ( REG_FIR_CR1 |= FIR_CR1_TIIE ) -#define __fir_disable_tii() ( REG_FIR_CR1 &= ~FIR_CR1_TIIE ) - -/* enable/disable transmit FIFO service request interrupt */ -#define __fir_enable_tfi() ( REG_FIR_CR1 |= FIR_CR1_TFIE ) -#define __fir_disable_tfi() ( REG_FIR_CR1 &= ~FIR_CR1_TFIE ) - -/* enable/disable receive FIFO service request interrupt */ -#define __fir_enable_rfi() ( REG_FIR_CR1 |= FIR_CR1_RFIE ) -#define __fir_disable_rfi() ( REG_FIR_CR1 &= ~FIR_CR1_RFIE ) - -/* enable/disable tx function */ -#define __fir_tx_enable() ( REG_FIR_CR1 |= FIR_CR1_TXE ) -#define __fir_tx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_TXE ) - -/* enable/disable rx function */ -#define __fir_rx_enable() ( REG_FIR_CR1 |= FIR_CR1_RXE ) -#define __fir_rx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_RXE ) - - -/* enable/disable serial infrared interaction pulse (SIP) */ -#define __fir_enable_sip() ( REG_FIR_CR2 |= FIR_CR2_SIPE ) -#define __fir_disable_sip() ( REG_FIR_CR2 &= ~FIR_CR2_SIPE ) - -/* un-inverted CRC value is sent out */ -#define __fir_enable_bcrc() ( REG_FIR_CR2 |= FIR_CR2_BCRC ) - -/* inverted CRC value is sent out */ -#define __fir_disable_bcrc() ( REG_FIR_CR2 &= ~FIR_CR2_BCRC ) - -/* enable/disable Transmit Frame Length Register */ -#define __fir_enable_tflr() ( REG_FIR_CR2 |= FIR_CR2_TFLRS ) -#define __fir_disable_tflr() ( REG_FIR_CR2 &= ~FIR_CR2_TFLRS ) - -/* Preamble is transmitted in idle state */ -#define __fir_set_iss() ( REG_FIR_CR2 |= FIR_CR2_ISS ) - -/* Abort symbol is transmitted in idle state */ -#define __fir_clear_iss() ( REG_FIR_CR2 &= ~FIR_CR2_ISS ) - -/* enable/disable loopback mode */ -#define __fir_enable_loopback() ( REG_FIR_CR2 |= FIR_CR2_LMS ) -#define __fir_disable_loopback() ( REG_FIR_CR2 &= ~FIR_CR2_LMS ) - -/* select transmit pin polarity */ -#define __fir_tpp_negative() ( REG_FIR_CR2 |= FIR_CR2_TPPS ) -#define __fir_tpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_TPPS ) - -/* select receive pin polarity */ -#define __fir_rpp_negative() ( REG_FIR_CR2 |= FIR_CR2_RPPS ) -#define __fir_rpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_RPPS ) - -/* n=16,32,64,128 */ -#define __fir_set_txfifo_trigger(n) \ -do { \ - REG_FIR_CR2 &= ~FIR_CR2_TTRG_MASK; \ - REG_FIR_CR2 |= FIR_CR2_TTRG_##n; \ -} while (0) - -/* n=16,32,64,128 */ -#define __fir_set_rxfifo_trigger(n) \ -do { \ - REG_FIR_CR2 &= ~FIR_CR2_RTRG_MASK; \ - REG_FIR_CR2 |= FIR_CR2_RTRG_##n; \ -} while (0) - - -/* FIR status checking */ - -#define __fir_test_rfw() ( REG_FIR_SR & FIR_SR_RFW ) -#define __fir_test_rfa() ( REG_FIR_SR & FIR_SR_RFA ) -#define __fir_test_tfrtl() ( REG_FIR_SR & FIR_SR_TFRTL ) -#define __fir_test_rfrtl() ( REG_FIR_SR & FIR_SR_RFRTL ) -#define __fir_test_urun() ( REG_FIR_SR & FIR_SR_URUN ) -#define __fir_test_rfte() ( REG_FIR_SR & FIR_SR_RFTE ) -#define __fir_test_orun() ( REG_FIR_SR & FIR_SR_ORUN ) -#define __fir_test_crce() ( REG_FIR_SR & FIR_SR_CRCE ) -#define __fir_test_fend() ( REG_FIR_SR & FIR_SR_FEND ) -#define __fir_test_tff() ( REG_FIR_SR & FIR_SR_TFF ) -#define __fir_test_rfe() ( REG_FIR_SR & FIR_SR_RFE ) -#define __fir_test_tidle() ( REG_FIR_SR & FIR_SR_TIDLE ) -#define __fir_test_rb() ( REG_FIR_SR & FIR_SR_RB ) - -#define __fir_clear_status() \ -do { \ - REG_FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; \ -} while (0) - -#define __fir_clear_rfw() ( REG_FIR_SR |= FIR_SR_RFW ) -#define __fir_clear_rfa() ( REG_FIR_SR |= FIR_SR_RFA ) -#define __fir_clear_urun() ( REG_FIR_SR |= FIR_SR_URUN ) - -#define __fir_set_tflr(len) \ -do { \ - REG_FIR_TFLR = len; \ -} while (0) - -#define __fir_set_addr(a) ( REG_FIR_AR = (a) ) - -#define __fir_write_data(data) ( REG_FIR_TDR = data ) -#define __fir_read_data(data) ( data = REG_FIR_RDR ) - -/*************************************************************************** - * SCC - ***************************************************************************/ - -#define __scc_enable(base) ( REG_SCC_CR(base) |= SCC_CR_SCCE ) -#define __scc_disable(base) ( REG_SCC_CR(base) &= ~SCC_CR_SCCE ) - -#define __scc_set_tx_mode(base) ( REG_SCC_CR(base) |= SCC_CR_TRS ) -#define __scc_set_rx_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_TRS ) - -#define __scc_enable_t2r(base) ( REG_SCC_CR(base) |= SCC_CR_T2R ) -#define __scc_disable_t2r(base) ( REG_SCC_CR(base) &= ~SCC_CR_T2R ) - -#define __scc_clk_as_devclk(base) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ - REG_SCC_CR(base) |= SCC_CR_FDIV_1; \ -} while (0) - -#define __scc_clk_as_half_devclk(base) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ - REG_SCC_CR(base) |= SCC_CR_FDIV_2; \ -} while (0) - -/* n=1,4,8,14 */ -#define __scc_set_fifo_trigger(base, n) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_TRIG_MASK; \ - REG_SCC_CR(base) |= SCC_CR_TRIG_##n; \ -} while (0) - -#define __scc_set_protocol(base, p) \ -do { \ - if (p) \ - REG_SCC_CR(base) |= SCC_CR_TP; \ - else \ - REG_SCC_CR(base) &= ~SCC_CR_TP; \ -} while (0) - -#define __scc_flush_fifo(base) ( REG_SCC_CR(base) |= SCC_CR_FLUSH ) - -#define __scc_set_invert_mode(base) ( REG_SCC_CR(base) |= SCC_CR_CONV ) -#define __scc_set_direct_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_CONV ) - -#define SCC_ERR_INTRS \ - ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) -#define SCC_ALL_INTRS \ - ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \ - SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) - -#define __scc_enable_err_intrs(base) ( REG_SCC_CR(base) |= SCC_ERR_INTRS ) -#define __scc_disable_err_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ERR_INTRS ) - -#define SCC_ALL_ERRORS \ - ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO) - -#define __scc_clear_errors(base) ( REG_SCC_SR(base) &= ~SCC_ALL_ERRORS ) - -#define __scc_enable_all_intrs(base) ( REG_SCC_CR(base) |= SCC_ALL_INTRS ) -#define __scc_disable_all_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ALL_INTRS ) - -#define __scc_enable_tx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE ) -#define __scc_disable_tx_intr(base) ( REG_SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) ) - -#define __scc_enable_rx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_RXIE) -#define __scc_disable_rx_intr(base) ( REG_SCC_CR(base) &= ~SCC_CR_RXIE) - -#define __scc_set_tsend(base) ( REG_SCC_CR(base) |= SCC_CR_TSEND ) -#define __scc_clear_tsend(base) ( REG_SCC_CR(base) &= ~SCC_CR_TSEND ) - -#define __scc_set_clockstop(base) ( REG_SCC_CR(base) |= SCC_CR_CLKSTP ) -#define __scc_clear_clockstop(base) ( REG_SCC_CR(base) &= ~SCC_CR_CLKSTP ) - -#define __scc_clockstop_low(base) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ - REG_SCC_CR(base) |= SCC_CR_PX_STOP_LOW; \ -} while (0) - -#define __scc_clockstop_high(base) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ - REG_SCC_CR(base) |= SCC_CR_PX_STOP_HIGH; \ -} while (0) - - -/* SCC status checking */ -#define __scc_check_transfer_status(base) ( REG_SCC_SR(base) & SCC_SR_TRANS ) -#define __scc_check_rx_overrun_error(base) ( REG_SCC_SR(base) & SCC_SR_ORER ) -#define __scc_check_rx_timeout(base) ( REG_SCC_SR(base) & SCC_SR_RTO ) -#define __scc_check_parity_error(base) ( REG_SCC_SR(base) & SCC_SR_PER ) -#define __scc_check_txfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_TFTG ) -#define __scc_check_rxfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_RFTG ) -#define __scc_check_tx_end(base) ( REG_SCC_SR(base) & SCC_SR_TEND ) -#define __scc_check_retx_3(base) ( REG_SCC_SR(base) & SCC_SR_RETR_3 ) -#define __scc_check_ecnt_overflow(base) ( REG_SCC_SR(base) & SCC_SR_ECNTO ) - - -/*************************************************************************** - * WDT - ***************************************************************************/ - -#define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) -#define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) -#define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) - - -/*************************************************************************** - * OST - ***************************************************************************/ - -#define __ost_enable_all() ( REG_OST_TER |= 0x07 ) -#define __ost_disable_all() ( REG_OST_TER &= ~0x07 ) -#define __ost_enable_channel(n) ( REG_OST_TER |= (1 << (n)) ) -#define __ost_disable_channel(n) ( REG_OST_TER &= ~(1 << (n)) ) -#define __ost_set_reload(n, val) ( REG_OST_TRDR(n) = (val) ) -#define __ost_set_count(n, val) ( REG_OST_TCNT(n) = (val) ) -#define __ost_get_count(n) ( REG_OST_TCNT(n) ) -#define __ost_set_clock(n, cs) ( REG_OST_TCSR(n) |= (cs) ) -#define __ost_set_mode(n, val) ( REG_OST_TCSR(n) = (val) ) -#define __ost_enable_interrupt(n) ( REG_OST_TCSR(n) |= OST_TCSR_UIE ) -#define __ost_disable_interrupt(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UIE ) -#define __ost_uf_detected(n) ( REG_OST_TCSR(n) & OST_TCSR_UF ) -#define __ost_clear_uf(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UF ) -#define __ost_is_busy(n) ( REG_OST_TCSR(n) & OST_TCSR_BUSY ) -#define __ost_clear_busy(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_BUSY ) - - -/*************************************************************************** - * UART - ***************************************************************************/ - -#define __uart_enable(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = UARTFCR_UUE | UARTFCR_FE ) -#define __uart_disable(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) - -#define __uart_enable_transmit_irq(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) -#define __uart_disable_transmit_irq(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) - -#define __uart_enable_receive_irq(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) -#define __uart_disable_receive_irq(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) - -#define __uart_enable_loopback(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) -#define __uart_disable_loopback(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) - -#define __uart_set_8n1(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) - -#define __uart_set_baud(n, devclk, baud) \ - do { \ - REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \ - REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \ - REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ - REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \ - } while (0) - -#define __uart_parity_error(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) - -#define __uart_clear_errors(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTSR_RFER) ) - -#define __uart_transmit_fifo_empty(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) - -#define __uart_transmit_end(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) - -#define __uart_transmit_char(n, ch) \ - REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) - -#define __uart_receive_fifo_full(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) - -#define __uart_receive_ready(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) - -#define __uart_receive_char(n) \ - REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) - -#define __uart_disable_irda() \ - ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) -#define __uart_enable_irda() \ - /* Tx high pulse as 0, Rx low pulse as 0 */ \ - ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) - - -/*************************************************************************** - * INTC - ***************************************************************************/ -#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) -#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) -#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) - -/*************************************************************************** - * CIM - ***************************************************************************/ - -#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) -#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) - -#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) -#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) - -#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) -#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) - -#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) -#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) - -#define __cim_sample_data_at_pclk_falling_edge() \ - ( REG_CIM_CFG |= CIM_CFG_PCP ) -#define __cim_sample_data_at_pclk_rising_edge() \ - ( REG_CIM_CFG &= ~CIM_CFG_PCP ) - -#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) -#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) - -#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) -#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) - -/* n=0-7 */ -#define __cim_set_data_packing_mode(n) \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ - REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ -} while (0) - -#define __cim_enable_ccir656_progressive_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ -} while (0) - -#define __cim_enable_ccir656_interlace_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ -} while (0) - -#define __cim_enable_gated_clock_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ -} while (0) - -#define __cim_enable_nongated_clock_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ -} while (0) - -/* sclk:system bus clock - * mclk: CIM master clock - */ -#define __cim_set_master_clk(sclk, mclk) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ - REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ -} while (0) - -#define __cim_enable_sof_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) -#define __cim_disable_sof_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) - -#define __cim_enable_eof_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) -#define __cim_disable_eof_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) - -#define __cim_enable_stop_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) -#define __cim_disable_stop_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) - -#define __cim_enable_trig_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) -#define __cim_disable_trig_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) - -#define __cim_enable_rxfifo_overflow_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) -#define __cim_disable_rxfifo_overflow_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) - -/* n=1-16 */ -#define __cim_set_frame_rate(n) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ - REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ -} while (0) - -#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) -#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) - -#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) -#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) - -/* n=4,8,12,16,20,24,28,32 */ -#define __cim_set_rxfifo_trigger(n) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ - REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ -} while (0) - -#define __cim_clear_state() ( REG_CIM_STATE = 0 ) - -#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) -#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) -#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) -#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) -#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) -#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) -#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) -#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) - -#define __cim_get_iid() ( REG_CIM_IID ) -#define __cim_get_image_data() ( REG_CIM_RXFIFO ) -#define __cim_get_dam_cmd() ( REG_CIM_CMD ) - -#define __cim_set_da(a) ( REG_CIM_DA = (a) ) - -/*************************************************************************** - * PWM - ***************************************************************************/ - -/* n is the pwm channel (0,1,..) */ -#define __pwm_enable_module(n) ( REG_PWM_CTR(n) |= PWM_CTR_EN ) -#define __pwm_disable_module(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_EN ) -#define __pwm_graceful_shutdown_mode(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_SD ) -#define __pwm_abrupt_shutdown_mode(n) ( REG_PWM_CTR(n) |= PWM_CTR_SD ) -#define __pwm_set_full_duty(n) ( REG_PWM_DUT(n) |= PWM_DUT_FDUTY ) - -#define __pwm_set_prescale(n, p) \ - ( REG_PWM_CTR(n) = ((REG_PWM_CTR(n) & ~PWM_CTR_PRESCALE_MASK) | (p) ) ) -#define __pwm_set_period(n, p) \ - ( REG_PWM_PER(n) = ( (REG_PWM_PER(n) & ~PWM_PER_PERIOD_MASK) | (p) ) ) -#define __pwm_set_duty(n, d) \ - ( REG_PWM_DUT(n) = ( (REG_PWM_DUT(n) & ~PWM_DUT_FDUTY) | (d) ) ) - -/*************************************************************************** - * EMC - ***************************************************************************/ - -#define __emc_enable_split() ( REG_EMC_BCR = EMC_BCR_BRE ) -#define __emc_disable_split() ( REG_EMC_BCR = 0 ) - -#define __emc_smem_bus_width(n) /* 8, 16 or 32*/ \ - ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BW_MASK) | \ - EMC_SMCR_BW_##n##BIT ) -#define __emc_smem_byte_control() \ - ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_BCM ) -#define __emc_normal_smem() \ - ( REG_EMC_SMCR = (REG_EMC_SMCR & ~EMC_SMCR_SMT ) -#define __emc_burst_smem() \ - ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_SMT ) -#define __emc_smem_burstlen(n) /* 4, 8, 16 or 32 */ \ - ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BL_MASK) | (EMC_SMCR_BL_##n ) - -/* - * NAND flash - */ -#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE | EMC_NFCSR_FCE) -#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFE | EMC_NFCSR_FCE)) -#define __nand_ecc_enable() (REG_EMC_NFCSR |= EMC_NFCSR_ECCE | EMC_NFCSR_ERST) -#define __nand_ecc_disable() (REG_EMC_NFCSR &= ~EMC_NFCSR_ECCE) -#define __nand_ready() (REG_EMC_NFCSR & EMC_NFCSR_RB) -#define __nand_sync() while (!__nand_ready()) -#define __nand_ecc() (REG_EMC_NFECC & 0x00ffffff) -#define __nand_cmd(n) (REG8(NAND_CMDPORT) = (n)) -#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) -#define __nand_data8() REG8(NAND_DATAPORT) -#define __nand_data16() REG16(NAND_DATAPORT) - - -/*************************************************************************** - * GPIO - ***************************************************************************/ - -/* p is the port number (0,1,2,3) - * o is the pin offset (0-31) inside the port - * n is the absolute number of a pin (0-124), regardless of the port - * m is the interrupt manner (low/high/falling/rising) - */ - -#define __gpio_port_data(p) ( REG_GPIO_GPDR(p) ) - -#define __gpio_port_as_output(p, o) \ -do { \ - unsigned int tmp; \ - REG_GPIO_GPIER(p) &= ~(1 << (o)); \ - REG_GPIO_GPDIR(p) |= (1 << (o)); \ - if (o < 16) { \ - tmp = REG_GPIO_GPALR(p); \ - tmp &= ~(3 << ((o) << 1)); \ - REG_GPIO_GPALR(p) = tmp; \ - } else { \ - tmp = REG_GPIO_GPAUR(p); \ - tmp &= ~(3 << (((o) - 16)<< 1)); \ - REG_GPIO_GPAUR(p) = tmp; \ - } \ -} while (0) - -#define __gpio_port_as_input(p, o) \ -do { \ - unsigned int tmp; \ - REG_GPIO_GPIER(p) &= ~(1 << (o)); \ - REG_GPIO_GPDIR(p) &= ~(1 << (o)); \ - if (o < 16) { \ - tmp = REG_GPIO_GPALR(p); \ - tmp &= ~(3 << ((o) << 1)); \ - REG_GPIO_GPALR(p) = tmp; \ - } else { \ - tmp = REG_GPIO_GPAUR(p); \ - tmp &= ~(3 << (((o) - 16)<< 1)); \ - REG_GPIO_GPAUR(p) = tmp; \ - } \ -} while (0) - -#define __gpio_as_output(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_output(p, o); \ -} while (0) - -#define __gpio_as_input(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_input(p, o); \ -} while (0) - -#define __gpio_set_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_data(p) |= (1 << o); \ -} while (0) - -#define __gpio_clear_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_data(p) &= ~(1 << o); \ -} while (0) - -static __inline__ unsigned int __gpio_get_pin(unsigned int n) -{ - unsigned int p, o; - p = (n) / 32; - o = (n) % 32; - if (__gpio_port_data(p) & (1 << o)) - return 1; - else - return 0; -} - - -#define __gpio_set_irq_detect_manner(p, o, m) \ -do { \ - unsigned int tmp; \ - if (o < 16) { \ - tmp = REG_GPIO_GPIDLR(p); \ - tmp &= ~(3 << ((o) << 1)); \ - tmp |= ((m) << ((o) << 1)); \ - REG_GPIO_GPIDLR(p) = tmp; \ - } else { \ - o -= 16; \ - tmp = REG_GPIO_GPIDUR(p); \ - tmp &= ~(3 << ((o) << 1)); \ - tmp |= ((m) << ((o) << 1)); \ - REG_GPIO_GPIDUR(p) = tmp; \ - } \ -} while (0) - -#define __gpio_port_as_irq(p, o, m) \ -do { \ - __gpio_set_irq_detect_manner(p, o, m); \ - __gpio_port_as_input(p, o); \ - REG_GPIO_GPIER(p) |= (1 << o); \ -} while (0) - -#define __gpio_as_irq(n, m) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_irq(p, o, m); \ -} while (0) - - -#define __gpio_as_irq_high_level(n) __gpio_as_irq(n, GPIO_IRQ_HILEVEL) -#define __gpio_as_irq_low_level(n) __gpio_as_irq(n, GPIO_IRQ_LOLEVEL) -#define __gpio_as_irq_fall_edge(n) __gpio_as_irq(n, GPIO_IRQ_FALLEDG) -#define __gpio_as_irq_rise_edge(n) __gpio_as_irq(n, GPIO_IRQ_RAISEDG) - - -#define __gpio_mask_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPIER(p) &= ~(1 << o); \ -} while (0) - -#define __gpio_unmask_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPIER(n) |= (1 << o); \ -} while (0) - -#define __gpio_ack_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPFR(p) |= (1 << o); \ -} while (0) - - -static __inline__ unsigned int __gpio_get_irq(void) -{ - unsigned int tmp, i; - - tmp = REG_GPIO_GPFR(3); - for (i=0; i<32; i++) - if (tmp & (1 << i)) - return 0x60 + i; - tmp = REG_GPIO_GPFR(2); - for (i=0; i<32; i++) - if (tmp & (1 << i)) - return 0x40 + i; - tmp = REG_GPIO_GPFR(1); - for (i=0; i<32; i++) - if (tmp & (1 << i)) - return 0x20 + i; - tmp = REG_GPIO_GPFR(0); - for (i=0; i<32; i++) - if (tmp & (1 << i)) - return i; - return 0; -} - -#define __gpio_group_irq(n) \ -({ \ - register int tmp, i; \ - tmp = REG_GPIO_GPFR((n)); \ - for (i=31;i>=0;i--) \ - if (tmp & (1 << i)) \ - break; \ - i; \ -}) - -#define __gpio_enable_pullupdown(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPPUR(p) |= (1 << o); \ -} while (0) - -#define __gpio_disable_pullupdown(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPPUR(p) &= ~(1 << o); \ -} while (0) - -/* Init the alternate function pins */ - - -#define __gpio_as_ssi() \ -do { \ - REG_GPIO_GPALR(2) &= 0xFC00FFFF; \ - REG_GPIO_GPALR(2) |= 0x01550000; \ -} while (0) - -#define __gpio_as_uart3() \ -do { \ - REG_GPIO_GPAUR(0) &= 0xFFFF0000; \ - REG_GPIO_GPAUR(0) |= 0x00005555; \ -} while (0) - -#define __gpio_as_uart2() \ -do { \ - REG_GPIO_GPALR(3) &= 0x3FFFFFFF; \ - REG_GPIO_GPALR(3) |= 0x40000000; \ - REG_GPIO_GPAUR(3) &= 0xF3FFFFFF; \ - REG_GPIO_GPAUR(3) |= 0x04000000; \ -} while (0) - -#define __gpio_as_uart1() \ -do { \ - REG_GPIO_GPAUR(0) &= 0xFFF0FFFF; \ - REG_GPIO_GPAUR(0) |= 0x00050000; \ -} while (0) - -#define __gpio_as_uart0() \ -do { \ - REG_GPIO_GPAUR(3) &= 0x0FFFFFFF; \ - REG_GPIO_GPAUR(3) |= 0x50000000; \ -} while (0) - - -#define __gpio_as_scc0() \ -do { \ - REG_GPIO_GPALR(2) &= 0xFFFFFFCC; \ - REG_GPIO_GPALR(2) |= 0x00000011; \ -} while (0) - -#define __gpio_as_scc1() \ -do { \ - REG_GPIO_GPALR(2) &= 0xFFFFFF33; \ - REG_GPIO_GPALR(2) |= 0x00000044; \ -} while (0) - -#define __gpio_as_scc() \ -do { \ - __gpio_as_scc0(); \ - __gpio_as_scc1(); \ -} while (0) - -#define __gpio_as_dma() \ -do { \ - REG_GPIO_GPALR(0) &= 0x00FFFFFF; \ - REG_GPIO_GPALR(0) |= 0x55000000; \ - REG_GPIO_GPAUR(0) &= 0xFF0FFFFF; \ - REG_GPIO_GPAUR(0) |= 0x00500000; \ -} while (0) - -#define __gpio_as_msc() \ -do { \ - REG_GPIO_GPALR(1) &= 0xFFFF000F; \ - REG_GPIO_GPALR(1) |= 0x00005550; \ -} while (0) - -#define __gpio_as_pcmcia() \ -do { \ - REG_GPIO_GPAUR(2) &= 0xF000FFFF; \ - REG_GPIO_GPAUR(2) |= 0x05550000; \ -} while (0) - -#define __gpio_as_emc() \ -do { \ - REG_GPIO_GPALR(2) &= 0x3FFFFFFF; \ - REG_GPIO_GPALR(2) |= 0x40000000; \ - REG_GPIO_GPAUR(2) &= 0xFFFF0000; \ - REG_GPIO_GPAUR(2) |= 0x00005555; \ -} while (0) - -#define __gpio_as_lcd_slave() \ -do { \ - REG_GPIO_GPALR(1) &= 0x0000FFFF; \ - REG_GPIO_GPALR(1) |= 0x55550000; \ - REG_GPIO_GPAUR(1) &= 0x00000000; \ - REG_GPIO_GPAUR(1) |= 0x55555555; \ -} while (0) - -#define __gpio_as_lcd_master() \ -do { \ - REG_GPIO_GPALR(1) &= 0x0000FFFF; \ - REG_GPIO_GPALR(1) |= 0x55550000; \ - REG_GPIO_GPAUR(1) &= 0x00000000; \ - REG_GPIO_GPAUR(1) |= 0x556A5555; \ -} while (0) - -#define __gpio_as_usb() \ -do { \ - REG_GPIO_GPAUR(0) &= 0x00FFFFFF; \ - REG_GPIO_GPAUR(0) |= 0x55000000; \ -} while (0) - -#define __gpio_as_ac97() \ -do { \ - REG_GPIO_GPALR(2) &= 0xC3FF03FF; \ - REG_GPIO_GPALR(2) |= 0x24005400; \ -} while (0) - -#define __gpio_as_i2s_slave() \ -do { \ - REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ - REG_GPIO_GPALR(2) |= 0x14005100; \ -} while (0) - -#define __gpio_as_i2s_master() \ -do { \ - REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ - REG_GPIO_GPALR(2) |= 0x28005100; \ -} while (0) - -#define __gpio_as_eth() \ -do { \ - REG_GPIO_GPAUR(3) &= 0xFC000000; \ - REG_GPIO_GPAUR(3) |= 0x01555555; \ -} while (0) - -#define __gpio_as_pwm() \ -do { \ - REG_GPIO_GPAUR(2) &= 0x0FFFFFFF; \ - REG_GPIO_GPAUR(2) |= 0x50000000; \ -} while (0) - -#define __gpio_as_ps2() \ -do { \ - REG_GPIO_GPALR(1) &= 0xFFFFFFF0; \ - REG_GPIO_GPALR(1) |= 0x00000005; \ -} while (0) - -#define __gpio_as_uprt() \ -do { \ - REG_GPIO_GPALR(1) &= 0x0000000F; \ - REG_GPIO_GPALR(1) |= 0x55555550; \ - REG_GPIO_GPALR(3) &= 0xC0000000; \ - REG_GPIO_GPALR(3) |= 0x15555555; \ -} while (0) - -#define __gpio_as_cim() \ -do { \ - REG_GPIO_GPALR(0) &= 0xFF000000; \ - REG_GPIO_GPALR(0) |= 0x00555555; \ -} while (0) - -/*************************************************************************** - * HARB - ***************************************************************************/ - -#define __harb_usb0_udc() \ -do { \ - REG_HARB_HAPOR &= ~HARB_HAPOR_UCHSEL; \ -} while (0) - -#define __harb_usb0_uhc() \ -do { \ - REG_HARB_HAPOR |= HARB_HAPOR_UCHSEL; \ -} while (0) - -#define __harb_set_priority(n) \ -do { \ - REG_HARB_HAPOR = ((REG_HARB_HAPOR & ~HARB_HAPOR_PRIO_MASK) | n); \ -} while (0) - -/*************************************************************************** - * I2C - ***************************************************************************/ - -#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) -#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) - -#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) -#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) -#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) -#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) - -#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) -#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) -#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) - -#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) -#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) -#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) - -#define __i2c_set_clk(dev_clk, i2c_clk) \ - ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) - -#define __i2c_read() ( REG_I2C_DR ) -#define __i2c_write(val) ( REG_I2C_DR = (val) ) - -/*************************************************************************** - * UDC - ***************************************************************************/ - -#define __udc_set_16bit_phy() ( REG_UDC_DevCFGR |= UDC_DevCFGR_PI ) -#define __udc_set_8bit_phy() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_PI ) - -#define __udc_enable_sync_frame() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SS ) -#define __udc_disable_sync_frame() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SS ) - -#define __udc_self_powered() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SP ) -#define __udc_bus_powered() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SP ) - -#define __udc_enable_remote_wakeup() ( REG_UDC_DevCFGR |= UDC_DevCFGR_RW ) -#define __udc_disable_remote_wakeup() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_RW ) - -#define __udc_set_speed_high() \ -do { \ - REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ - REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; \ -} while (0) - -#define __udc_set_speed_full() \ -do { \ - REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ - REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; \ -} while (0) - -#define __udc_set_speed_low() \ -do { \ - REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ - REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; \ -} while (0) - - -#define __udc_set_dma_mode() ( REG_UDC_DevCR |= UDC_DevCR_DM ) -#define __udc_set_slave_mode() ( REG_UDC_DevCR &= ~UDC_DevCR_DM ) -#define __udc_set_big_endian() ( REG_UDC_DevCR |= UDC_DevCR_BE ) -#define __udc_set_little_endian() ( REG_UDC_DevCR &= ~UDC_DevCR_BE ) -#define __udc_generate_resume() ( REG_UDC_DevCR |= UDC_DevCR_RES ) -#define __udc_clear_resume() ( REG_UDC_DevCR &= ~UDC_DevCR_RES ) - - -#define __udc_get_enumarated_speed() ( REG_UDC_DevSR & UDC_DevSR_ENUMSPD_MASK ) -#define __udc_suspend_detected() ( REG_UDC_DevSR & UDC_DevSR_SUSP ) -#define __udc_get_alternate_setting() ( (REG_UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT ) -#define __udc_get_interface_number() ( (REG_UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT ) -#define __udc_get_config_number() ( (REG_UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT ) - - -#define __udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF ) -#define __udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US ) -#define __udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR ) -#define __udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI ) -#define __udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC ) - -#define __udc_clear_sof() ( REG_UDC_DevIntR |= UDC_DevIntR_SOF ) -#define __udc_clear_usb_suspend() ( REG_UDC_DevIntR |= UDC_DevIntR_US ) -#define __udc_clear_usb_reset() ( REG_UDC_DevIntR |= UDC_DevIntR_UR ) -#define __udc_clear_set_interface() ( REG_UDC_DevIntR |= UDC_DevIntR_SI ) -#define __udc_clear_set_config() ( REG_UDC_DevIntR |= UDC_DevIntR_SC ) - -#define __udc_mask_sof() ( REG_UDC_DevIntMR |= UDC_DevIntR_SOF ) -#define __udc_mask_usb_suspend() ( REG_UDC_DevIntMR |= UDC_DevIntR_US ) -#define __udc_mask_usb_reset() ( REG_UDC_DevIntMR |= UDC_DevIntR_UR ) -#define __udc_mask_set_interface() ( REG_UDC_DevIntMR |= UDC_DevIntR_SI ) -#define __udc_mask_set_config() ( REG_UDC_DevIntMR |= UDC_DevIntR_SC ) -#define __udc_mask_all_dev_intrs() \ - ( REG_UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | \ - UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC ) - -#define __udc_unmask_sof() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SOF ) -#define __udc_unmask_usb_suspend() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_US ) -#define __udc_unmask_usb_reset() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_UR ) -#define __udc_unmask_set_interface() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SI ) -#define __udc_unmask_set_config() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SC ) -#if 0 -#define __udc_unmask_all_dev_intrs() \ - ( REG_UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | \ - UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) ) -#else -#define __udc_unmask_all_dev_intrs() \ - ( REG_UDC_DevIntMR = 0x00000000 ) -#endif - - -#define __udc_ep0out_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 ) -#define __udc_ep5out_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 ) -#define __udc_ep6out_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 ) -#define __udc_ep7out_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 ) - -#define __udc_ep0in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 ) -#define __udc_ep1in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 ) -#define __udc_ep2in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 ) -#define __udc_ep3in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 ) -#define __udc_ep4in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 ) - - -#define __udc_mask_ep0out_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) -#define __udc_mask_ep5out_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) -#define __udc_mask_ep6out_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) -#define __udc_mask_ep7out_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) - -#define __udc_unmask_ep0out_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) -#define __udc_unmask_ep5out_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) -#define __udc_unmask_ep6out_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) -#define __udc_unmask_ep7out_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) - -#define __udc_mask_ep0in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) ) -#define __udc_mask_ep1in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) ) -#define __udc_mask_ep2in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) ) -#define __udc_mask_ep3in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) ) -#define __udc_mask_ep4in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) ) - -#define __udc_unmask_ep0in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) ) -#define __udc_unmask_ep1in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) ) -#define __udc_unmask_ep2in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) ) -#define __udc_unmask_ep3in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) ) -#define __udc_unmask_ep4in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) ) - -#define __udc_mask_all_ep_intrs() \ - ( REG_UDC_EPIntMR = 0xffffffff ) -#define __udc_unmask_all_ep_intrs() \ - ( REG_UDC_EPIntMR = 0x00000000 ) - - -/* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */ -#define __udc_config_endpoint_type() \ -do { \ - REG_UDC_EP0InCR = (REG_UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ - REG_UDC_EP0OutCR = (REG_UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ - REG_UDC_EP1InCR = (REG_UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR; \ - REG_UDC_EP2InCR = (REG_UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ - REG_UDC_EP3InCR = (REG_UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ - REG_UDC_EP4InCR = (REG_UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ - REG_UDC_EP5OutCR = (REG_UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ - REG_UDC_EP6OutCR = (REG_UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ - REG_UDC_EP7OutCR = (REG_UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ -} while (0) - -#define __udc_enable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR |= UDC_EPCR_SN ) -#define __udc_enable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR |= UDC_EPCR_SN ) -#define __udc_enable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR |= UDC_EPCR_SN ) -#define __udc_enable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR |= UDC_EPCR_SN ) - -#define __udc_disable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_SN ) -#define __udc_disable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_SN ) -#define __udc_disable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_SN ) -#define __udc_disable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_SN ) - -#define __udc_flush_ep0in_fifo() ( REG_UDC_EP0InCR |= UDC_EPCR_F ) -#define __udc_flush_ep1in_fifo() ( REG_UDC_EP1InCR |= UDC_EPCR_F ) -#define __udc_flush_ep2in_fifo() ( REG_UDC_EP2InCR |= UDC_EPCR_F ) -#define __udc_flush_ep3in_fifo() ( REG_UDC_EP3InCR |= UDC_EPCR_F ) -#define __udc_flush_ep4in_fifo() ( REG_UDC_EP4InCR |= UDC_EPCR_F ) - -#define __udc_unflush_ep0in_fifo() ( REG_UDC_EP0InCR &= ~UDC_EPCR_F ) -#define __udc_unflush_ep1in_fifo() ( REG_UDC_EP1InCR &= ~UDC_EPCR_F ) -#define __udc_unflush_ep2in_fifo() ( REG_UDC_EP2InCR &= ~UDC_EPCR_F ) -#define __udc_unflush_ep3in_fifo() ( REG_UDC_EP3InCR &= ~UDC_EPCR_F ) -#define __udc_unflush_ep4in_fifo() ( REG_UDC_EP4InCR &= ~UDC_EPCR_F ) - -#define __udc_enable_ep0in_stall() ( REG_UDC_EP0InCR |= UDC_EPCR_S ) -#define __udc_enable_ep0out_stall() ( REG_UDC_EP0OutCR |= UDC_EPCR_S ) -#define __udc_enable_ep1in_stall() ( REG_UDC_EP1InCR |= UDC_EPCR_S ) -#define __udc_enable_ep2in_stall() ( REG_UDC_EP2InCR |= UDC_EPCR_S ) -#define __udc_enable_ep3in_stall() ( REG_UDC_EP3InCR |= UDC_EPCR_S ) -#define __udc_enable_ep4in_stall() ( REG_UDC_EP4InCR |= UDC_EPCR_S ) -#define __udc_enable_ep5out_stall() ( REG_UDC_EP5OutCR |= UDC_EPCR_S ) -#define __udc_enable_ep6out_stall() ( REG_UDC_EP6OutCR |= UDC_EPCR_S ) -#define __udc_enable_ep7out_stall() ( REG_UDC_EP7OutCR |= UDC_EPCR_S ) - -#define __udc_disable_ep0in_stall() ( REG_UDC_EP0InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep0out_stall() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep1in_stall() ( REG_UDC_EP1InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep2in_stall() ( REG_UDC_EP2InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep3in_stall() ( REG_UDC_EP3InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep4in_stall() ( REG_UDC_EP4InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep5out_stall() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep6out_stall() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep7out_stall() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_S ) - - -#define __udc_ep0out_packet_size() \ - ( (REG_UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) -#define __udc_ep5out_packet_size() \ - ( (REG_UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) -#define __udc_ep6out_packet_size() \ - ( (REG_UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) -#define __udc_ep7out_packet_size() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) - -#define __udc_ep0in_received_intoken() ( (REG_UDC_EP0InSR & UDC_EPSR_IN) ) -#define __udc_ep1in_received_intoken() ( (REG_UDC_EP1InSR & UDC_EPSR_IN) ) -#define __udc_ep2in_received_intoken() ( (REG_UDC_EP2InSR & UDC_EPSR_IN) ) -#define __udc_ep3in_received_intoken() ( (REG_UDC_EP3InSR & UDC_EPSR_IN) ) -#define __udc_ep4in_received_intoken() ( (REG_UDC_EP4InSR & UDC_EPSR_IN) ) - -#define __udc_ep0out_received_none() \ - ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) -#define __udc_ep0out_received_data() \ - ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) -#define __udc_ep0out_received_setup() \ - ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) - -#define __udc_ep5out_received_none() \ - ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) -#define __udc_ep5out_received_data() \ - ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) -#define __udc_ep5out_received_setup() \ - ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) - -#define __udc_ep6out_received_none() \ - ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) -#define __udc_ep6out_received_data() \ - ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) -#define __udc_ep6out_received_setup() \ - ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) - -#define __udc_ep7out_received_none() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) -#define __udc_ep7out_received_data() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) -#define __udc_ep7out_received_setup() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) - -/* ep7out ISO only */ -#define __udc_ep7out_get_pid() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT ) - - -#define __udc_ep0in_set_buffer_size(n) ( REG_UDC_EP0InBSR = (n) ) -#define __udc_ep1in_set_buffer_size(n) ( REG_UDC_EP1InBSR = (n) ) -#define __udc_ep2in_set_buffer_size(n) ( REG_UDC_EP2InBSR = (n) ) -#define __udc_ep3in_set_buffer_size(n) ( REG_UDC_EP3InBSR = (n) ) -#define __udc_ep4in_set_buffer_size(n) ( REG_UDC_EP4InBSR = (n) ) - -#define __udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR ) -#define __udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR ) -#define __udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR ) -#define __udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR ) - - -#define __udc_ep0in_set_max_packet_size(n) ( REG_UDC_EP0InMPSR = (n) ) -#define __udc_ep0out_set_max_packet_size(n) ( REG_UDC_EP0OutMPSR = (n) ) -#define __udc_ep1in_set_max_packet_size(n) ( REG_UDC_EP1InMPSR = (n) ) -#define __udc_ep2in_set_max_packet_size(n) ( REG_UDC_EP2InMPSR = (n) ) -#define __udc_ep3in_set_max_packet_size(n) ( REG_UDC_EP3InMPSR = (n) ) -#define __udc_ep4in_set_max_packet_size(n) ( REG_UDC_EP4InMPSR = (n) ) -#define __udc_ep5out_set_max_packet_size(n) ( REG_UDC_EP5OutMPSR = (n) ) -#define __udc_ep6out_set_max_packet_size(n) ( REG_UDC_EP6OutMPSR = (n) ) -#define __udc_ep7out_set_max_packet_size(n) ( REG_UDC_EP7OutMPSR = (n) ) - -/* set to 0xFFFF for UDC */ -#define __udc_set_setup_command_address(n) ( REG_UDC_STCMAR = (n) ) - -/* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7) - * c: Configuration number to which this endpoint belongs - * i: Interface number to which this endpoint belongs - * a: Alternate setting to which this endpoint belongs - * p: max Packet size of this endpoint - */ - -#define __udc_ep0info_init(c,i,a,p) \ -do { \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL; \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP0InfR |= UDC_EPInfR_EPD_OUT; \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep1info_init(c,i,a,p) \ -do { \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP1InfR |= UDC_EPInfR_EPT_INTR; \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP1InfR |= UDC_EPInfR_EPD_IN; \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep2info_init(c,i,a,p) \ -do { \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP2InfR |= UDC_EPInfR_EPT_BULK; \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP2InfR |= UDC_EPInfR_EPD_IN; \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep3info_init(c,i,a,p) \ -do { \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP3InfR |= UDC_EPInfR_EPT_BULK; \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP3InfR |= UDC_EPInfR_EPD_IN; \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep4info_init(c,i,a,p) \ -do { \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP4InfR |= UDC_EPInfR_EPT_ISO; \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP4InfR |= UDC_EPInfR_EPD_IN; \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep5info_init(c,i,a,p) \ -do { \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP5InfR |= UDC_EPInfR_EPT_BULK; \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP5InfR |= UDC_EPInfR_EPD_OUT; \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep6info_init(c,i,a,p) \ -do { \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP6InfR |= UDC_EPInfR_EPT_BULK; \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP6InfR |= UDC_EPInfR_EPD_OUT; \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep7info_init(c,i,a,p) \ -do { \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP7InfR |= UDC_EPInfR_EPT_ISO; \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP7InfR |= UDC_EPInfR_EPD_OUT; \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT); \ -} while (0) - - -/*************************************************************************** - * DMAC - ***************************************************************************/ - -/* n is the DMA channel (0 - 7) */ - -#define __dmac_enable_all_channels() \ - ( REG_DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN ) -#define __dmac_disable_all_channels() \ - ( REG_DMAC_DMACR &= ~DMAC_DMACR_DME ) - -/* p=0,1,2,3 */ -#define __dmac_set_priority(p) \ -do { \ - REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ - REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ -} while (0) - -#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HTR ) -#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AER ) - -#define __dmac_enable_channel(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE ) -#define __dmac_disable_channel(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE ) -#define __dmac_channel_enabled(n) \ - ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_CHDE ) - -#define __dmac_channel_enable_irq(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE ) -#define __dmac_channel_disable_irq(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE ) - -#define __dmac_channel_transmit_halt_detected(n) \ - ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_HLT ) -#define __dmac_channel_transmit_end_detected(n) \ - ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_TC ) -#define __dmac_channel_address_error_detected(n) \ - ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_AR ) - -#define __dmac_channel_clear_transmit_halt(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) -#define __dmac_channel_clear_transmit_end(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC ) -#define __dmac_channel_clear_address_error(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) - -#define __dmac_channel_set_single_mode(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM ) -#define __dmac_channel_set_block_mode(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TM ) - -#define __dmac_channel_set_transfer_unit_32bit(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32b; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_16bit(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16b; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_8bit(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_8b; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_16byte(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16B; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_32byte(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32B; \ -} while (0) - -/* w=8,16,32 */ -#define __dmac_channel_set_dest_port_width(n,w) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DWDH_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DWDH_##w; \ -} while (0) - -/* w=8,16,32 */ -#define __dmac_channel_set_src_port_width(n,w) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SWDH_##w; \ -} while (0) - -/* v=0-15 */ -#define __dmac_channel_set_rdil(n,v) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_RDIL_MASK; \ - REG_DMAC_DCCSR(n) |= ((v) << DMAC_DCCSR_RDIL_BIT); \ -} while (0) - -#define __dmac_channel_dest_addr_fixed(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM ) -#define __dmac_channel_dest_addr_increment(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DAM ) - -#define __dmac_channel_src_addr_fixed(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM ) -#define __dmac_channel_src_addr_increment(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SAM ) - -#define __dmac_channel_set_eop_high(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM ) -#define __dmac_channel_set_eop_low(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM ) - -#define __dmac_channel_set_erdm(n,m) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ - REG_DMAC_DCCSR(n) |= ((m) << DMAC_DCCSR_ERDM_BIT); \ -} while (0) - -#define __dmac_channel_set_eackm(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM ) -#define __dmac_channel_clear_eackm(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM ) - -#define __dmac_channel_set_eacks(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS ) -#define __dmac_channel_clear_eacks(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS ) - - -#define __dmac_channel_irq_detected(n) \ - ( REG_DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) ) - -static __inline__ int __dmac_get_irq(void) -{ - int i; - for (i=0;i> AIC_SR_TFL_BIT ) -#define __aic_get_receive_count() \ - ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) - -#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) -#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) -#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) -#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) -#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) - -#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) - -#define CODEC_READ_CMD (1 << 19) -#define CODEC_WRITE_CMD (0 << 19) -#define CODEC_REG_INDEX_BIT 12 -#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ -#define CODEC_REG_DATA_BIT 4 -#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ - -#define __ac97_out_rcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ -} while (0) - -#define __ac97_out_wcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ -} while (0) - -#define __ac97_out_data(value) \ -do { \ - REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ -} while (0) - -#define __ac97_in_data() \ - ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) - -#define __ac97_in_status_addr() \ - ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) - -#define __i2s_set_sample_rate(i2sclk, sync) \ - ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) - -#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) -#define __aic_read_rfifo() ( REG_AIC_DR ) - -// -// Define next ops for AC97 compatible -// - -#define AC97_ACSR AIC_ACSR - -#define __ac97_enable() __aic_enable(); __aic_select_ac97() -#define __ac97_disable() __aic_disable() -#define __ac97_reset() __aic_reset() - -#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __ac97_enable_record() __aic_enable_record() -#define __ac97_disable_record() __aic_disable_record() -#define __ac97_enable_replay() __aic_enable_replay() -#define __ac97_disable_replay() __aic_disable_replay() -#define __ac97_enable_loopback() __aic_enable_loopback() -#define __ac97_disable_loopback() __aic_disable_loopback() - -#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() -#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() -#define __ac97_enable_receive_dma() __aic_enable_receive_dma() -#define __ac97_disable_receive_dma() __aic_disable_receive_dma() - -#define __ac97_transmit_request() __aic_transmit_request() -#define __ac97_receive_request() __aic_receive_request() -#define __ac97_transmit_underrun() __aic_transmit_underrun() -#define __ac97_receive_overrun() __aic_receive_overrun() - -#define __ac97_clear_errors() __aic_clear_errors() - -#define __ac97_get_transmit_resident() __aic_get_transmit_resident() -#define __ac97_get_receive_count() __aic_get_receive_count() - -#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() -#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() -#define __ac97_enable_receive_intr() __aic_enable_receive_intr() -#define __ac97_disable_receive_intr() __aic_disable_receive_intr() - -#define __ac97_write_tfifo(v) __aic_write_tfifo(v) -#define __ac97_read_rfifo() __aic_read_rfifo() - -// -// Define next ops for I2S compatible -// - -#define I2S_ACSR AIC_I2SSR - -#define __i2s_enable() __aic_enable(); __aic_select_i2s() -#define __i2s_disable() __aic_disable() -#define __i2s_reset() __aic_reset() - -#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __i2s_enable_record() __aic_enable_record() -#define __i2s_disable_record() __aic_disable_record() -#define __i2s_enable_replay() __aic_enable_replay() -#define __i2s_disable_replay() __aic_disable_replay() -#define __i2s_enable_loopback() __aic_enable_loopback() -#define __i2s_disable_loopback() __aic_disable_loopback() - -#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() -#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() -#define __i2s_enable_receive_dma() __aic_enable_receive_dma() -#define __i2s_disable_receive_dma() __aic_disable_receive_dma() - -#define __i2s_transmit_request() __aic_transmit_request() -#define __i2s_receive_request() __aic_receive_request() -#define __i2s_transmit_underrun() __aic_transmit_underrun() -#define __i2s_receive_overrun() __aic_receive_overrun() - -#define __i2s_clear_errors() __aic_clear_errors() - -#define __i2s_get_transmit_resident() __aic_get_transmit_resident() -#define __i2s_get_receive_count() __aic_get_receive_count() - -#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() -#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() -#define __i2s_enable_receive_intr() __aic_enable_receive_intr() -#define __i2s_disable_receive_intr() __aic_disable_receive_intr() - -#define __i2s_write_tfifo(v) __aic_write_tfifo(v) -#define __i2s_read_rfifo() __aic_read_rfifo() - -#define __i2s_reset_codec() \ - do { \ - __gpio_as_output(111); /* SDATA_OUT */ \ - __gpio_as_input(110); /* SDATA_IN */ \ - __gpio_as_output(112); /* SYNC */ \ - __gpio_as_output(114); /* RESET# */ \ - __gpio_clear_pin(111); \ - __gpio_clear_pin(110); \ - __gpio_clear_pin(112); \ - __gpio_clear_pin(114); \ - __gpio_as_i2s_master(); \ - } while (0) - - -/*************************************************************************** - * LCD - ***************************************************************************/ - -#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) -#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) - -#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) -#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) - -/* n=1,2,4,8,16 */ -#define __lcd_set_bpp(n) \ - ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) - -/* n=4,8,16 */ -#define __lcd_set_burst_length(n) \ -do { \ - REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ - REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ -} while (0) - -#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) -#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) - -#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) -#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) - -/* n=2,4,16 */ -#define __lcd_set_stn_frc(n) \ -do { \ - REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ - REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ -} while (0) - - -#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) -#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) - -#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) -#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) - -#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) -#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) - -#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) -#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) - -#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) -#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) - -#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) -#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) - -#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) -#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) - -#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) -#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) - -#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) -#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) - - -/* LCD status register indication */ - -#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) -#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) -#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) -#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) -#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) -#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) -#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) - -#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) -#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) -#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) - -#define __lcd_panel_white() ( REG_LCD_DEV |= LCD_DEV_WHITE ) -#define __lcd_panel_black() ( REG_LCD_DEV &= ~LCD_DEV_WHITE ) - -/* n=1,2,4,8 for single mono-STN - * n=4,8 for dual mono-STN - */ -#define __lcd_set_panel_datawidth(n) \ -do { \ - REG_LCD_DEV &= ~LCD_DEV_PDW_MASK; \ - REG_LCD_DEV |= LCD_DEV_PDW_n##; \ -} while (0) - -/* m=LCD_DEV_MODE_GENERUIC_TFT_xxx */ -#define __lcd_set_panel_mode(m) \ -do { \ - REG_LCD_DEV &= ~LCD_DEV_MODE_MASK; \ - REG_LCD_DEV |= (m); \ -} while(0) - -/* n = 0-255 */ -#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) -#define __lcd_set_ac_bias(n) \ -do { \ - REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ - REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ -} while(0) - -#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) -#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) - -#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) -#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) - -#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) -#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) - -#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) -#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) - -#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) -#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) - -#define __lcd_vsync_get_vps() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) - -#define __lcd_vsync_get_vpe() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) -#define __lcd_vsync_set_vpe(n) \ -do { \ - REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ - REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ -} while (0) - -#define __lcd_hsync_get_hps() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) -#define __lcd_hsync_set_hps(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ -} while (0) - -#define __lcd_hsync_get_hpe() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) -#define __lcd_hsync_set_hpe(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ -} while (0) - -#define __lcd_vat_get_ht() \ - ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) -#define __lcd_vat_set_ht(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ -} while (0) - -#define __lcd_vat_get_vt() \ - ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) -#define __lcd_vat_set_vt(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ -} while (0) - -#define __lcd_dah_get_hds() \ - ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) -#define __lcd_dah_set_hds(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ -} while (0) - -#define __lcd_dah_get_hde() \ - ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) -#define __lcd_dah_set_hde(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ -} while (0) - -#define __lcd_dav_get_vds() \ - ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) -#define __lcd_dav_set_vds(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ -} while (0) - -#define __lcd_dav_get_vde() \ - ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) -#define __lcd_dav_set_vde(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ -} while (0) - -#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) -#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) -#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) -#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) - -#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) -#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) -#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) -#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) - -#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) -#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) - -#define __lcd_cmd0_get_len() \ - ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) -#define __lcd_cmd1_get_len() \ - ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) - - - -/*************************************************************************** - * DES - ***************************************************************************/ - - -/*************************************************************************** - * CPM - ***************************************************************************/ -#define __cpm_plcr1_fd() \ - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT) -#define __cpm_plcr1_rd() \ - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT) -#define __cpm_plcr1_od() \ - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT) -#define __cpm_cfcr_mfr() \ - ((REG_CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT) -#define __cpm_cfcr_pfr() \ - ((REG_CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT) -#define __cpm_cfcr_sfr() \ - ((REG_CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT) -#define __cpm_cfcr_ifr() \ - ((REG_CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT) - -static __inline__ unsigned int __cpm_divisor_encode(unsigned int n) -{ - unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32}; - int i; - for (i=0;i<10;i++) - if (n < encode[i]) - break; - return i; -} - -#define __cpm_set_mclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_MFR_MASK) | \ - ((n) << (CPM_CFCR_MFR_BIT)); \ -} while (0) - -#define __cpm_set_pclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_PFR_MASK) | \ - ((n) << (CPM_CFCR_PFR_BIT)); \ -} while (0) - -#define __cpm_set_sclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_SFR_MASK) | \ - ((n) << (CPM_CFCR_SFR_BIT)); \ -} while (0) - -#define __cpm_set_iclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_IFR_MASK) | \ - ((n) << (CPM_CFCR_IFR_BIT)); \ -} while (0) - -#define __cpm_set_lcdclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_LFR_MASK) | \ - ((n) << (CPM_CFCR_LFR_BIT)); \ -} while (0) - -#define __cpm_enable_cko1() (REG_CPM_CFCR |= CPM_CFCR_CKOEN1) -#define __cpm_enable_cko2() (REG_CPM_CFCR |= CPM_CFCR_CKOEN2) -#define __cpm_disable_cko1() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN1) -#define __cpm_disable_cko2() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN2) - -#define __cpm_idle_mode() \ - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ - CPM_LPCR_LPM_IDLE) -#define __cpm_sleep_mode() \ - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ - CPM_LPCR_LPM_SLEEP) -#define __cpm_hibernate_mode() \ - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ - CPM_LPCR_LPM_HIBERNATE) - -#define __cpm_stop_uart(n) \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UART##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_pwm(n) \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_PWM##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_aic(n) \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_AIC##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_ost() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_OST << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_rtc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_RTC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_dmac() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_DMAC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_uhc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UHC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_lcd() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_LCD << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_i2c() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_I2C << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_ssi() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_SSI << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_msc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_MSC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_scc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_SCC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_fir() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_FIR << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_des() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_DES << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_eth() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_eth << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_ps2() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_PS2 << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_cim() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_CIM << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_udc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UDC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_all() (REG_CPM_MSCR = 0xffffffff) - -#define __cpm_start_uart(n) \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UART##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_pwm(n) \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_PWM##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_aic(n) \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_AIC##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_ost() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_OST << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_rtc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_RTC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_dmac() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_DMAC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_uhc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UHC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_lcd() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_LCD << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_i2c() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_I2C << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_ssi() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_SSI << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_msc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_MSC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_scc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_SCC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_fir() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_FIR << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_des() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_DES << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_eth() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_ETH << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_ps2() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_PS2 << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_cim() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_CIM << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_udc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UDC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_all() (REG_CPM_MSCR = 0x00000000) - - -/*************************************************************************** - * SSI - ***************************************************************************/ - -#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) -#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) -#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) - -#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) - -#define __ssi_select_ce2() \ -do { \ - REG_SSI_CR0 |= SSI_CR0_FSEL; \ - REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ -} while (0) - -#define __ssi_select_gpc() \ -do { \ - REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ - REG_SSI_CR1 |= SSI_CR1_MULTS; \ -} while (0) - -#define __ssi_enable_tx_intr() \ - ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) - -#define __ssi_disable_tx_intr() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) - -#define __ssi_enable_rx_intr() \ - ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) - -#define __ssi_disable_rx_intr() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) - -#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) -#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) - -#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) -#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) - -#define __ssi_finish_receive() \ - ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) - -#define __ssi_disable_recvfinish() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) - -#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) -#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) - -#define __ssi_flush_fifo() \ - ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) - -#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) - -/* Motorola's SPI format, set 1 delay */ -#define __ssi_spi_format() \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ - REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ - REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ - REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ -} while (0) - -/* TI's SSP format, must clear SSI_CR1.UNFIN */ -#define __ssi_ssp_format() \ -do { \ - REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ - REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ -} while (0) - -/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ -#define __ssi_microwire_format() \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ - REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ - REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ - REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ - REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ -} while (0) - -/* CE# level (FRMHL), CE# in interval time (ITFRM), - clock phase and polarity (PHA POL), - interval time (SSIITR), interval characters/frame (SSIICR) */ - - /* frmhl,endian,mcom,flen,pha,pol MASK */ -#define SSICR1_MISC_MASK \ - ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ - | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ - -#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ -do { \ - REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ - REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ - (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ - ((pha) << 1) | (pol); \ -} while(0) - -/* Transfer with MSB or LSB first */ -#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) -#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) - -/* n = 2 - 17 */ -#define __ssi_set_frame_length(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | SSI_CR1_FLEN_##n##BIT) ) - -/* n = 1 - 16 */ -#define __ssi_set_microwire_command_length(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) - -/* Set the clock phase for SPI */ -#define __ssi_set_spi_clock_phase(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) - -/* Set the clock polarity for SPI */ -#define __ssi_set_spi_clock_polarity(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) - -/* n = 1,4,8,14 */ -#define __ssi_set_tx_trigger(n) \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ - REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ -} while (0) - -/* n = 1,4,8,14 */ -#define __ssi_set_rx_trigger(n) \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ - REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ -} while (0) - -#define __ssi_get_txfifo_count() \ - ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) - -#define __ssi_get_rxfifo_count() \ - ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) - -#define __ssi_clear_errors() \ - ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) - -#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) -#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) - -#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) -#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) -#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) - -#define __ssi_set_clk(dev_clk, ssi_clk) \ - ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) - -#define __ssi_receive_data() REG_SSI_DR -#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) - -#endif /* !__ASSEMBLY__ */ - -#endif /* __JZ4730_H__ */ diff --git a/nandboot/include/jz4730_board.h b/nandboot/include/jz4730_board.h deleted file mode 100644 index 8e2aea1..0000000 --- a/nandboot/include/jz4730_board.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * jz4730_board.h - * - * JZ4730 board definitions. - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * - */ -#ifndef __JZ4730_BOARD_H__ -#define __JZ4730_BOARD_H__ - -/*------------------------------------------------------------------- - * Frequency of the external OSC in Hz. - */ -#define CFG_EXTAL 12000000 - -/*------------------------------------------------------------------- - * CPU speed. - */ -#define CFG_CPU_SPEED 336000000 - -/*------------------------------------------------------------------- - * Serial console. - */ -#define CFG_UART_BASE UART3_BASE - -#define CONFIG_BAUDRATE 9600 - -/*------------------------------------------------------------------- - * SDRAM info. - */ - -// SDRAM paramters -#define CFG_SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ -#define CFG_SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ -#define CFG_SDRAM_ROW 13 /* Row address: 11 to 13 */ -#define CFG_SDRAM_COL 9 /* Column address: 8 to 12 */ -#define CFG_SDRAM_CASL 2 /* CAS latency: 2 or 3 */ - -// SDRAM Timings, unit: ns -#define CFG_SDRAM_TRAS 45 /* RAS# Active Time */ -#define CFG_SDRAM_RCD 20 /* RAS# to CAS# Delay */ -#define CFG_SDRAM_TPC 20 /* RAS# Precharge Time */ -#define CFG_SDRAM_TRWL 7 /* Write Latency Time */ -#define CFG_SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */ - -/*------------------------------------------------------------------- - * Linux kernel command line. - */ -#define CFG_CMDLINE "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw init=/etc/inittab" - -#endif /* __JZ4730_BOARD_H__ */ diff --git a/nandboot/include/jz4740.h b/nandboot/include/jz4740.h deleted file mode 100644 index 3e63d3f..0000000 --- a/nandboot/include/jz4740.h +++ /dev/null @@ -1,4762 +0,0 @@ -/* - * jz4740.h - * - * JZ4740 definitions. - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * - */ -#ifndef __JZ4740_H__ -#define __JZ4740_H__ - -#ifndef __ASSEMBLY__ - -#include - -#define REG8(addr) *((volatile u8 *)(addr)) -#define REG16(addr) *((volatile u16 *)(addr)) -#define REG32(addr) *((volatile u32 *)(addr)) - -#else - -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) - -#endif /* !ASSEMBLY */ - -//---------------------------------------------------------------------- -// Boot ROM Specification -// - -/* NOR Boot config */ -#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ -#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ -#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ - -/* NAND Boot config */ -#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ -#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ -#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ -#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ - - -//---------------------------------------------------------------------- -// Register Definitions -// -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define TCU_BASE 0xB0002000 -#define WDT_BASE 0xB0002000 -#define RTC_BASE 0xB0003000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define ICDC_BASE 0xB0020000 -#define MSC_BASE 0xB0021000 -#define UART0_BASE 0xB0030000 -#define I2C_BASE 0xB0042000 -#define SSI_BASE 0xB0043000 -#define SADC_BASE 0xB0070000 -#define EMC_BASE 0xB3010000 -#define DMAC_BASE 0xB3020000 -#define UHC_BASE 0xB3030000 -#define UDC_BASE 0xB3040000 -#define LCD_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define ETH_BASE 0xB3100000 - - -/************************************************************************* - * INTC (Interrupt Controller) - *************************************************************************/ -#define INTC_ISR (INTC_BASE + 0x00) -#define INTC_IMR (INTC_BASE + 0x04) -#define INTC_IMSR (INTC_BASE + 0x08) -#define INTC_IMCR (INTC_BASE + 0x0c) -#define INTC_IPR (INTC_BASE + 0x10) - -#define REG_INTC_ISR REG32(INTC_ISR) -#define REG_INTC_IMR REG32(INTC_IMR) -#define REG_INTC_IMSR REG32(INTC_IMSR) -#define REG_INTC_IMCR REG32(INTC_IMCR) -#define REG_INTC_IPR REG32(INTC_IPR) - -// 1st-level interrupts -#define IRQ_I2C 1 -#define IRQ_UHC 3 -#define IRQ_UART0 9 -#define IRQ_SADC 12 -#define IRQ_MSC 14 -#define IRQ_RTC 15 -#define IRQ_SSI 16 -#define IRQ_CIM 17 -#define IRQ_AIC 18 -#define IRQ_ETH 19 -#define IRQ_DMAC 20 -#define IRQ_TCU2 21 -#define IRQ_TCU1 22 -#define IRQ_TCU0 23 -#define IRQ_UDC 24 -#define IRQ_GPIO3 25 -#define IRQ_GPIO2 26 -#define IRQ_GPIO1 27 -#define IRQ_GPIO0 28 -#define IRQ_IPU 29 -#define IRQ_LCD 30 - -// 2nd-level interrupts -#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ -#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ - - -/************************************************************************* - * RTC - *************************************************************************/ -#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ -#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ -#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ -#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ - -#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ -#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ -#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ -#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ -#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ -#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ - -#define REG_RTC_RCR REG32(RTC_RCR) -#define REG_RTC_RSR REG32(RTC_RSR) -#define REG_RTC_RSAR REG32(RTC_RSAR) -#define REG_RTC_RGR REG32(RTC_RGR) -#define REG_RTC_HCR REG32(RTC_HCR) -#define REG_RTC_HWFCR REG32(RTC_HWFCR) -#define REG_RTC_HRCR REG32(RTC_HRCR) -#define REG_RTC_HWCR REG32(RTC_HWCR) -#define REG_RTC_HWRSR REG32(RTC_HWRSR) -#define REG_RTC_HSPR REG32(RTC_HSPR) - -/* RTC Control Register */ -#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ -#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ -#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ -#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ -#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ -#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ -#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ - -/* RTC Regulator Register */ -#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ -#define RTC_RGR_ADJC_BIT 16 -#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) -#define RTC_RGR_NC1HZ_BIT 0 -#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) - -/* Hibernate Control Register */ -#define RTC_HCR_PD (1 << 0) /* Power Down */ - -/* Hibernate Wakeup Filter Counter Register */ -#define RTC_HWFCR_BIT 5 -#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) - -/* Hibernate Reset Counter Register */ -#define RTC_HRCR_BIT 5 -#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) - -/* Hibernate Wakeup Control Register */ -#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ - -/* Hibernate Wakeup Status Register */ -#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ -#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ -#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ -#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ - - -/************************************************************************* - * CPM (Clock reset and Power control Management) - *************************************************************************/ -#define CPM_CPCCR (CPM_BASE+0x00) -#define CPM_CPPCR (CPM_BASE+0x10) -#define CPM_I2SCDR (CPM_BASE+0x60) -#define CPM_LPCDR (CPM_BASE+0x64) -#define CPM_MSCCDR (CPM_BASE+0x68) -#define CPM_UHCCDR (CPM_BASE+0x6C) - -#define CPM_LCR (CPM_BASE+0x04) -#define CPM_CLKGR (CPM_BASE+0x20) -#define CPM_SCR (CPM_BASE+0x24) - -#define CPM_HCR (CPM_BASE+0x30) -#define CPM_HWFCR (CPM_BASE+0x34) -#define CPM_HRCR (CPM_BASE+0x38) -#define CPM_HWCR (CPM_BASE+0x3c) -#define CPM_HWSR (CPM_BASE+0x40) -#define CPM_HSPR (CPM_BASE+0x44) - -#define CPM_RSR (CPM_BASE+0x08) - - -#define REG_CPM_CPCCR REG32(CPM_CPCCR) -#define REG_CPM_CPPCR REG32(CPM_CPPCR) -#define REG_CPM_I2SCDR REG32(CPM_I2SCDR) -#define REG_CPM_LPCDR REG32(CPM_LPCDR) -#define REG_CPM_MSCCDR REG32(CPM_MSCCDR) -#define REG_CPM_UHCCDR REG32(CPM_UHCCDR) - -#define REG_CPM_LCR REG32(CPM_LCR) -#define REG_CPM_CLKGR REG32(CPM_CLKGR) -#define REG_CPM_SCR REG32(CPM_SCR) -#define REG_CPM_HCR REG32(CPM_HCR) -#define REG_CPM_HWFCR REG32(CPM_HWFCR) -#define REG_CPM_HRCR REG32(CPM_HRCR) -#define REG_CPM_HWCR REG32(CPM_HWCR) -#define REG_CPM_HWSR REG32(CPM_HWSR) -#define REG_CPM_HSPR REG32(CPM_HSPR) - -#define REG_CPM_RSR REG32(CPM_RSR) - - -/* Clock Control Register */ -#define CPM_CPCCR_I2CS (1 << 31) -#define CPM_CPCCR_CLKOEN (1 << 30) -#define CPM_CPCCR_UCS (1 << 29) -#define CPM_CPCCR_UDIV_BIT 23 -#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) -#define CPM_CPCCR_CE (1 << 22) -#define CPM_CPCCR_PCS (1 << 21) -#define CPM_CPCCR_LDIV_BIT 16 -#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) -#define CPM_CPCCR_MDIV_BIT 12 -#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) -#define CPM_CPCCR_PDIV_BIT 8 -#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) -#define CPM_CPCCR_HDIV_BIT 4 -#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) -#define CPM_CPCCR_CDIV_BIT 0 -#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) - -/* I2S Clock Divider Register */ -#define CPM_I2SCDR_I2SDIV_BIT 0 -#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) - -/* LCD Pixel Clock Divider Register */ -#define CPM_LPCDR_PIXDIV_BIT 0 -#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) - -/* MSC Clock Divider Register */ -#define CPM_MSCCDR_MSCDIV_BIT 0 -#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) - -/* PLL Control Register */ -#define CPM_CPPCR_PLLM_BIT 23 -#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) -#define CPM_CPPCR_PLLN_BIT 18 -#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) -#define CPM_CPPCR_PLLOD_BIT 16 -#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) -#define CPM_CPPCR_PLLS (1 << 10) -#define CPM_CPPCR_PLLBP (1 << 9) -#define CPM_CPPCR_PLLEN (1 << 8) -#define CPM_CPPCR_PLLST_BIT 0 -#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) - -/* Low Power Control Register */ -#define CPM_LCR_DOZE_DUTY_BIT 3 -#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) -#define CPM_LCR_DOZE_ON (1 << 2) -#define CPM_LCR_LPM_BIT 0 -#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) - #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) - #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) - -/* Clock Gate Register */ -#define CPM_CLKGR_UART1 (1 << 15) -#define CPM_CLKGR_UHC (1 << 14) -#define CPM_CLKGR_IPU (1 << 13) -#define CPM_CLKGR_DMAC (1 << 12) -#define CPM_CLKGR_UDC (1 << 11) -#define CPM_CLKGR_LCD (1 << 10) -#define CPM_CLKGR_CIM (1 << 9) -#define CPM_CLKGR_SADC (1 << 8) -#define CPM_CLKGR_MSC (1 << 7) -#define CPM_CLKGR_AIC1 (1 << 6) -#define CPM_CLKGR_AIC2 (1 << 5) -#define CPM_CLKGR_SSI (1 << 4) -#define CPM_CLKGR_I2C (1 << 3) -#define CPM_CLKGR_RTC (1 << 2) -#define CPM_CLKGR_TCU (1 << 1) -#define CPM_CLKGR_UART0 (1 << 0) - -/* Sleep Control Register */ -#define CPM_SCR_O1ST_BIT 8 -#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) -#define CPM_SCR_USBPHY_ENABLE (1 << 6) -#define CPM_SCR_OSC_ENABLE (1 << 4) - -/* Hibernate Control Register */ -#define CPM_HCR_PD (1 << 0) - -/* Wakeup Filter Counter Register in Hibernate Mode */ -#define CPM_HWFCR_TIME_BIT 0 -#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) - -/* Reset Counter Register in Hibernate Mode */ -#define CPM_HRCR_TIME_BIT 0 -#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) - -/* Wakeup Control Register in Hibernate Mode */ -#define CPM_HWCR_WLE_LOW (0 << 2) -#define CPM_HWCR_WLE_HIGH (1 << 2) -#define CPM_HWCR_PIN_WAKEUP (1 << 1) -#define CPM_HWCR_RTC_WAKEUP (1 << 0) - -/* Wakeup Status Register in Hibernate Mode */ -#define CPM_HWSR_WSR_PIN (1 << 1) -#define CPM_HWSR_WSR_RTC (1 << 0) - -/* Reset Status Register */ -#define CPM_RSR_HR (1 << 2) -#define CPM_RSR_WR (1 << 1) -#define CPM_RSR_PR (1 << 0) - - -/************************************************************************* - * TCU (Timer Counter Unit) - *************************************************************************/ -#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ -#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ -#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ -#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ -#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ -#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ -#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ -#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ -#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ -#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ -#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ -#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ -#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ -#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ -#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ -#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ -#define TCU_TDFR1 (TCU_BASE + 0x50) -#define TCU_TDHR1 (TCU_BASE + 0x54) -#define TCU_TCNT1 (TCU_BASE + 0x58) -#define TCU_TCSR1 (TCU_BASE + 0x5C) -#define TCU_TDFR2 (TCU_BASE + 0x60) -#define TCU_TDHR2 (TCU_BASE + 0x64) -#define TCU_TCNT2 (TCU_BASE + 0x68) -#define TCU_TCSR2 (TCU_BASE + 0x6C) -#define TCU_TDFR3 (TCU_BASE + 0x70) -#define TCU_TDHR3 (TCU_BASE + 0x74) -#define TCU_TCNT3 (TCU_BASE + 0x78) -#define TCU_TCSR3 (TCU_BASE + 0x7C) -#define TCU_TDFR4 (TCU_BASE + 0x80) -#define TCU_TDHR4 (TCU_BASE + 0x84) -#define TCU_TCNT4 (TCU_BASE + 0x88) -#define TCU_TCSR4 (TCU_BASE + 0x8C) -#define TCU_TDFR5 (TCU_BASE + 0x90) -#define TCU_TDHR5 (TCU_BASE + 0x94) -#define TCU_TCNT5 (TCU_BASE + 0x98) -#define TCU_TCSR5 (TCU_BASE + 0x9C) - -#define REG_TCU_TSR REG32(TCU_TSR) -#define REG_TCU_TSSR REG32(TCU_TSSR) -#define REG_TCU_TSCR REG32(TCU_TSCR) -#define REG_TCU_TER REG8(TCU_TER) -#define REG_TCU_TESR REG8(TCU_TESR) -#define REG_TCU_TECR REG8(TCU_TECR) -#define REG_TCU_TFR REG32(TCU_TFR) -#define REG_TCU_TFSR REG32(TCU_TFSR) -#define REG_TCU_TFCR REG32(TCU_TFCR) -#define REG_TCU_TMR REG32(TCU_TMR) -#define REG_TCU_TMSR REG32(TCU_TMSR) -#define REG_TCU_TMCR REG32(TCU_TMCR) -#define REG_TCU_TDFR0 REG16(TCU_TDFR0) -#define REG_TCU_TDHR0 REG16(TCU_TDHR0) -#define REG_TCU_TCNT0 REG16(TCU_TCNT0) -#define REG_TCU_TCSR0 REG16(TCU_TCSR0) -#define REG_TCU_TDFR1 REG16(TCU_TDFR1) -#define REG_TCU_TDHR1 REG16(TCU_TDHR1) -#define REG_TCU_TCNT1 REG16(TCU_TCNT1) -#define REG_TCU_TCSR1 REG16(TCU_TCSR1) -#define REG_TCU_TDFR2 REG16(TCU_TDFR2) -#define REG_TCU_TDHR2 REG16(TCU_TDHR2) -#define REG_TCU_TCNT2 REG16(TCU_TCNT2) -#define REG_TCU_TCSR2 REG16(TCU_TCSR2) -#define REG_TCU_TDFR3 REG16(TCU_TDFR3) -#define REG_TCU_TDHR3 REG16(TCU_TDHR3) -#define REG_TCU_TCNT3 REG16(TCU_TCNT3) -#define REG_TCU_TCSR3 REG16(TCU_TCSR3) -#define REG_TCU_TDFR4 REG16(TCU_TDFR4) -#define REG_TCU_TDHR4 REG16(TCU_TDHR4) -#define REG_TCU_TCNT4 REG16(TCU_TCNT4) -#define REG_TCU_TCSR4 REG16(TCU_TCSR4) - -// n = 0,1,2,3,4,5 -#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ -#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ -#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ -#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ - -#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) -#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) -#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) -#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) - -// Register definitions -#define TCU_TCSR_PWM_SD (1 << 9) -#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) -#define TCU_TCSR_PWM_EN (1 << 7) -#define TCU_TCSR_PRESCALE_BIT 3 -#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_EXT_EN (1 << 2) -#define TCU_TCSR_RTC_EN (1 << 1) -#define TCU_TCSR_PCK_EN (1 << 0) - -#define TCU_TER_TCEN5 (1 << 5) -#define TCU_TER_TCEN4 (1 << 4) -#define TCU_TER_TCEN3 (1 << 3) -#define TCU_TER_TCEN2 (1 << 2) -#define TCU_TER_TCEN1 (1 << 1) -#define TCU_TER_TCEN0 (1 << 0) - -#define TCU_TESR_TCST5 (1 << 5) -#define TCU_TESR_TCST4 (1 << 4) -#define TCU_TESR_TCST3 (1 << 3) -#define TCU_TESR_TCST2 (1 << 2) -#define TCU_TESR_TCST1 (1 << 1) -#define TCU_TESR_TCST0 (1 << 0) - -#define TCU_TECR_TCCL5 (1 << 5) -#define TCU_TECR_TCCL4 (1 << 4) -#define TCU_TECR_TCCL3 (1 << 3) -#define TCU_TECR_TCCL2 (1 << 2) -#define TCU_TECR_TCCL1 (1 << 1) -#define TCU_TECR_TCCL0 (1 << 0) - -#define TCU_TFR_HFLAG5 (1 << 21) -#define TCU_TFR_HFLAG4 (1 << 20) -#define TCU_TFR_HFLAG3 (1 << 19) -#define TCU_TFR_HFLAG2 (1 << 18) -#define TCU_TFR_HFLAG1 (1 << 17) -#define TCU_TFR_HFLAG0 (1 << 16) -#define TCU_TFR_FFLAG5 (1 << 5) -#define TCU_TFR_FFLAG4 (1 << 4) -#define TCU_TFR_FFLAG3 (1 << 3) -#define TCU_TFR_FFLAG2 (1 << 2) -#define TCU_TFR_FFLAG1 (1 << 1) -#define TCU_TFR_FFLAG0 (1 << 0) - -#define TCU_TFSR_HFLAG5 (1 << 21) -#define TCU_TFSR_HFLAG4 (1 << 20) -#define TCU_TFSR_HFLAG3 (1 << 19) -#define TCU_TFSR_HFLAG2 (1 << 18) -#define TCU_TFSR_HFLAG1 (1 << 17) -#define TCU_TFSR_HFLAG0 (1 << 16) -#define TCU_TFSR_FFLAG5 (1 << 5) -#define TCU_TFSR_FFLAG4 (1 << 4) -#define TCU_TFSR_FFLAG3 (1 << 3) -#define TCU_TFSR_FFLAG2 (1 << 2) -#define TCU_TFSR_FFLAG1 (1 << 1) -#define TCU_TFSR_FFLAG0 (1 << 0) - -#define TCU_TFCR_HFLAG5 (1 << 21) -#define TCU_TFCR_HFLAG4 (1 << 20) -#define TCU_TFCR_HFLAG3 (1 << 19) -#define TCU_TFCR_HFLAG2 (1 << 18) -#define TCU_TFCR_HFLAG1 (1 << 17) -#define TCU_TFCR_HFLAG0 (1 << 16) -#define TCU_TFCR_FFLAG5 (1 << 5) -#define TCU_TFCR_FFLAG4 (1 << 4) -#define TCU_TFCR_FFLAG3 (1 << 3) -#define TCU_TFCR_FFLAG2 (1 << 2) -#define TCU_TFCR_FFLAG1 (1 << 1) -#define TCU_TFCR_FFLAG0 (1 << 0) - -#define TCU_TMR_HMASK5 (1 << 21) -#define TCU_TMR_HMASK4 (1 << 20) -#define TCU_TMR_HMASK3 (1 << 19) -#define TCU_TMR_HMASK2 (1 << 18) -#define TCU_TMR_HMASK1 (1 << 17) -#define TCU_TMR_HMASK0 (1 << 16) -#define TCU_TMR_FMASK5 (1 << 5) -#define TCU_TMR_FMASK4 (1 << 4) -#define TCU_TMR_FMASK3 (1 << 3) -#define TCU_TMR_FMASK2 (1 << 2) -#define TCU_TMR_FMASK1 (1 << 1) -#define TCU_TMR_FMASK0 (1 << 0) - -#define TCU_TMSR_HMST5 (1 << 21) -#define TCU_TMSR_HMST4 (1 << 20) -#define TCU_TMSR_HMST3 (1 << 19) -#define TCU_TMSR_HMST2 (1 << 18) -#define TCU_TMSR_HMST1 (1 << 17) -#define TCU_TMSR_HMST0 (1 << 16) -#define TCU_TMSR_FMST5 (1 << 5) -#define TCU_TMSR_FMST4 (1 << 4) -#define TCU_TMSR_FMST3 (1 << 3) -#define TCU_TMSR_FMST2 (1 << 2) -#define TCU_TMSR_FMST1 (1 << 1) -#define TCU_TMSR_FMST0 (1 << 0) - -#define TCU_TMCR_HMCL5 (1 << 21) -#define TCU_TMCR_HMCL4 (1 << 20) -#define TCU_TMCR_HMCL3 (1 << 19) -#define TCU_TMCR_HMCL2 (1 << 18) -#define TCU_TMCR_HMCL1 (1 << 17) -#define TCU_TMCR_HMCL0 (1 << 16) -#define TCU_TMCR_FMCL5 (1 << 5) -#define TCU_TMCR_FMCL4 (1 << 4) -#define TCU_TMCR_FMCL3 (1 << 3) -#define TCU_TMCR_FMCL2 (1 << 2) -#define TCU_TMCR_FMCL1 (1 << 1) -#define TCU_TMCR_FMCL0 (1 << 0) - -#define TCU_TSR_WDTS (1 << 16) -#define TCU_TSR_STOP5 (1 << 5) -#define TCU_TSR_STOP4 (1 << 4) -#define TCU_TSR_STOP3 (1 << 3) -#define TCU_TSR_STOP2 (1 << 2) -#define TCU_TSR_STOP1 (1 << 1) -#define TCU_TSR_STOP0 (1 << 0) - -#define TCU_TSSR_WDTSS (1 << 16) -#define TCU_TSSR_STPS5 (1 << 5) -#define TCU_TSSR_STPS4 (1 << 4) -#define TCU_TSSR_STPS3 (1 << 3) -#define TCU_TSSR_STPS2 (1 << 2) -#define TCU_TSSR_STPS1 (1 << 1) -#define TCU_TSSR_STPS0 (1 << 0) - -#define TCU_TSSR_WDTSC (1 << 16) -#define TCU_TSSR_STPC5 (1 << 5) -#define TCU_TSSR_STPC4 (1 << 4) -#define TCU_TSSR_STPC3 (1 << 3) -#define TCU_TSSR_STPC2 (1 << 2) -#define TCU_TSSR_STPC1 (1 << 1) -#define TCU_TSSR_STPC0 (1 << 0) - - -/************************************************************************* - * WDT (WatchDog Timer) - *************************************************************************/ -#define WDT_TDR (WDT_BASE + 0x00) -#define WDT_TCER (WDT_BASE + 0x04) -#define WDT_TCNT (WDT_BASE + 0x08) -#define WDT_TCSR (WDT_BASE + 0x0C) - -#define REG_WDT_TDR REG16(WDT_TDR) -#define REG_WDT_TCER REG8(WDT_TCER) -#define REG_WDT_TCNT REG16(WDT_TCNT) -#define REG_WDT_TCSR REG16(WDT_TCSR) - -// Register definition -#define WDT_TCSR_PRESCALE_BIT 3 -#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - - -/************************************************************************* - * DMAC (DMA Controller) - *************************************************************************/ - -#define MAX_DMA_NUM 6 /* max 6 channels */ - -#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ -#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ -#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ -#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ -#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ -#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ -#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ -#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ -#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ -#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ -#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ - -// channel 0 -#define DMAC_DSAR0 DMAC_DSAR(0) -#define DMAC_DTAR0 DMAC_DTAR(0) -#define DMAC_DTCR0 DMAC_DTCR(0) -#define DMAC_DRSR0 DMAC_DRSR(0) -#define DMAC_DCCSR0 DMAC_DCCSR(0) -#define DMAC_DCMD0 DMAC_DCMD(0) -#define DMAC_DDA0 DMAC_DDA(0) - -// channel 1 -#define DMAC_DSAR1 DMAC_DSAR(1) -#define DMAC_DTAR1 DMAC_DTAR(1) -#define DMAC_DTCR1 DMAC_DTCR(1) -#define DMAC_DRSR1 DMAC_DRSR(1) -#define DMAC_DCCSR1 DMAC_DCCSR(1) -#define DMAC_DCMD1 DMAC_DCMD(1) -#define DMAC_DDA1 DMAC_DDA(1) - -// channel 2 -#define DMAC_DSAR2 DMAC_DSAR(2) -#define DMAC_DTAR2 DMAC_DTAR(2) -#define DMAC_DTCR2 DMAC_DTCR(2) -#define DMAC_DRSR2 DMAC_DRSR(2) -#define DMAC_DCCSR2 DMAC_DCCSR(2) -#define DMAC_DCMD2 DMAC_DCMD(2) -#define DMAC_DDA2 DMAC_DDA(2) - -// channel 3 -#define DMAC_DSAR3 DMAC_DSAR(3) -#define DMAC_DTAR3 DMAC_DTAR(3) -#define DMAC_DTCR3 DMAC_DTCR(3) -#define DMAC_DRSR3 DMAC_DRSR(3) -#define DMAC_DCCSR3 DMAC_DCCSR(3) -#define DMAC_DCMD3 DMAC_DCMD(3) -#define DMAC_DDA3 DMAC_DDA(3) - -// channel 4 -#define DMAC_DSAR4 DMAC_DSAR(4) -#define DMAC_DTAR4 DMAC_DTAR(4) -#define DMAC_DTCR4 DMAC_DTCR(4) -#define DMAC_DRSR4 DMAC_DRSR(4) -#define DMAC_DCCSR4 DMAC_DCCSR(4) -#define DMAC_DCMD4 DMAC_DCMD(4) -#define DMAC_DDA4 DMAC_DDA(4) - -// channel 5 -#define DMAC_DSAR5 DMAC_DSAR(5) -#define DMAC_DTAR5 DMAC_DTAR(5) -#define DMAC_DTCR5 DMAC_DTCR(5) -#define DMAC_DRSR5 DMAC_DRSR(5) -#define DMAC_DCCSR5 DMAC_DCCSR(5) -#define DMAC_DCMD5 DMAC_DCMD(5) -#define DMAC_DDA5 DMAC_DDA(5) - -#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) -#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) -#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) -#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) -#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) -#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) -#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) -#define REG_DMAC_DMACR REG32(DMAC_DMACR) -#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) -#define REG_DMAC_DMADBR REG32(DMAC_DMADBR) -#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) - -// DMA request source register -#define DMAC_DRSR_RS_BIT 0 -#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) - -// DMA channel control/status register -#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ -#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ -#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) -#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ -#define DMAC_DCCSR_AR (1 << 4) /* address error */ -#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ -#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ -#define DMAC_DCCSR_CT (1 << 1) /* count terminated */ -#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ - -// DMA channel command register -#define DMAC_DCMD_SAI (1 << 23) /* source address increment */ -#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ -#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ -#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) -#define DMAC_DCMD_SWDH_BIT 14 /* source port width */ -#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) - #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) - #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) - #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) -#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ -#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) - #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) - #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) - #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) -#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ -#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) -#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ -#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ -#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ -#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ -#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ -#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ - -// DMA descriptor address register -#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ -#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) -#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ -#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) - -// DMA control register -#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ -#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ -#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ -#define DMAC_DMACR_AR (1 << 2) /* address error flag */ -#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ - -// DMA doorbell register -#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ -#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ -#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ -#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ -#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ -#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ - -// DMA doorbell set register -#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ -#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ -#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ -#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ -#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ -#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ - -// DMA interrupt pending register -#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ -#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ -#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ -#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ -#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ -#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ - - -/************************************************************************* - * GPIO (General-Purpose I/O Ports) - *************************************************************************/ -#define MAX_GPIO_NUM 128 - -//n = 0,1,2,3 -#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ -#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ -#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ -#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ -#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ -#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ -#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ -#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ -#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ -#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ -#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ -#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ -#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ -#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ -#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ -#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ -#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ -#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ -#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ -#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ -#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ -#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ -#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ -#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */ - -#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ -#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ -#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) -#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) -#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ -#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) -#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) -#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ -#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) -#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) -#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ -#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) -#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) -#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ -#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) -#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) -#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ -#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) -#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) -#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ -#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) -#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) -#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ -#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ - - -/************************************************************************* - * UART - *************************************************************************/ - -#define IRDA_BASE UART0_BASE -#define UART_BASE UART0_BASE -#define UART_OFF 0x1000 - -/* Register Offset */ -#define OFF_RDR (0x00) /* R 8b H'xx */ -#define OFF_TDR (0x00) /* W 8b H'xx */ -#define OFF_DLLR (0x00) /* RW 8b H'00 */ -#define OFF_DLHR (0x04) /* RW 8b H'00 */ -#define OFF_IER (0x04) /* RW 8b H'00 */ -#define OFF_ISR (0x08) /* R 8b H'01 */ -#define OFF_FCR (0x08) /* W 8b H'00 */ -#define OFF_LCR (0x0C) /* RW 8b H'00 */ -#define OFF_MCR (0x10) /* RW 8b H'00 */ -#define OFF_LSR (0x14) /* R 8b H'00 */ -#define OFF_MSR (0x18) /* R 8b H'00 */ -#define OFF_SPR (0x1C) /* RW 8b H'00 */ -#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ -#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ -#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ - -/* Register Address */ -#define UART0_RDR (UART0_BASE + OFF_RDR) -#define UART0_TDR (UART0_BASE + OFF_TDR) -#define UART0_DLLR (UART0_BASE + OFF_DLLR) -#define UART0_DLHR (UART0_BASE + OFF_DLHR) -#define UART0_IER (UART0_BASE + OFF_IER) -#define UART0_ISR (UART0_BASE + OFF_ISR) -#define UART0_FCR (UART0_BASE + OFF_FCR) -#define UART0_LCR (UART0_BASE + OFF_LCR) -#define UART0_MCR (UART0_BASE + OFF_MCR) -#define UART0_LSR (UART0_BASE + OFF_LSR) -#define UART0_MSR (UART0_BASE + OFF_MSR) -#define UART0_SPR (UART0_BASE + OFF_SPR) -#define UART0_SIRCR (UART0_BASE + OFF_SIRCR) -#define UART0_UMR (UART0_BASE + OFF_UMR) -#define UART0_UACR (UART0_BASE + OFF_UACR) - -/* - * Define macros for UART_IER - * UART Interrupt Enable Register - */ -#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ -#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ -#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ -#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ -#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ - -/* - * Define macros for UART_ISR - * UART Interrupt Status Register - */ -#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ -#define UART_ISR_IID (7 << 1) /* Source of Interrupt */ -#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ -#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ -#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ -#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ -#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ -#define UART_ISR_FFMS_NO_FIFO (0 << 6) -#define UART_ISR_FFMS_FIFO_MODE (3 << 6) - -/* - * Define macros for UART_FCR - * UART FIFO Control Register - */ -#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ -#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ -#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ -#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ -#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ -#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ -#define UART_FCR_RTRG_1 (0 << 6) -#define UART_FCR_RTRG_4 (1 << 6) -#define UART_FCR_RTRG_8 (2 << 6) -#define UART_FCR_RTRG_15 (3 << 6) - -/* - * Define macros for UART_LCR - * UART Line Control Register - */ -#define UART_LCR_WLEN (3 << 0) /* word length */ -#define UART_LCR_WLEN_5 (0 << 0) -#define UART_LCR_WLEN_6 (1 << 0) -#define UART_LCR_WLEN_7 (2 << 0) -#define UART_LCR_WLEN_8 (3 << 0) -#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ - -#define UART_LCR_PE (1 << 3) /* 0: parity disable */ -#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ -#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ -#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ -#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ - -/* - * Define macros for UART_LSR - * UART Line Status Register - */ -#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ -#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ -#define UART_LSR_PER (1 << 2) /* 0: no parity error */ -#define UART_LSR_FER (1 << 3) /* 0; no framing error */ -#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ -#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ -#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ -#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ - -/* - * Define macros for UART_MCR - * UART Modem Control Register - */ -#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ -#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ -#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ -#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ -#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ -#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ - -/* - * Define macros for UART_MSR - * UART Modem Status Register - */ -#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ -#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ -#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ -#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ -#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ -#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ -#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ -#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ - -/* - * Define macros for SIRCR - * Slow IrDA Control Register - */ -#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ -#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ -#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length - 1: 0 pulse width is 1.6us for 115.2Kbps */ -#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ -#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ - - -/************************************************************************* - * AIC (AC97/I2S Controller) - *************************************************************************/ -#define AIC_FR (AIC_BASE + 0x000) -#define AIC_CR (AIC_BASE + 0x004) -#define AIC_ACCR1 (AIC_BASE + 0x008) -#define AIC_ACCR2 (AIC_BASE + 0x00C) -#define AIC_I2SCR (AIC_BASE + 0x010) -#define AIC_SR (AIC_BASE + 0x014) -#define AIC_ACSR (AIC_BASE + 0x018) -#define AIC_I2SSR (AIC_BASE + 0x01C) -#define AIC_ACCAR (AIC_BASE + 0x020) -#define AIC_ACCDR (AIC_BASE + 0x024) -#define AIC_ACSAR (AIC_BASE + 0x028) -#define AIC_ACSDR (AIC_BASE + 0x02C) -#define AIC_I2SDIV (AIC_BASE + 0x030) -#define AIC_DR (AIC_BASE + 0x034) - -#define REG_AIC_FR REG32(AIC_FR) -#define REG_AIC_CR REG32(AIC_CR) -#define REG_AIC_ACCR1 REG32(AIC_ACCR1) -#define REG_AIC_ACCR2 REG32(AIC_ACCR2) -#define REG_AIC_I2SCR REG32(AIC_I2SCR) -#define REG_AIC_SR REG32(AIC_SR) -#define REG_AIC_ACSR REG32(AIC_ACSR) -#define REG_AIC_I2SSR REG32(AIC_I2SSR) -#define REG_AIC_ACCAR REG32(AIC_ACCAR) -#define REG_AIC_ACCDR REG32(AIC_ACCDR) -#define REG_AIC_ACSAR REG32(AIC_ACSAR) -#define REG_AIC_ACSDR REG32(AIC_ACSDR) -#define REG_AIC_I2SDIV REG32(AIC_I2SDIV) -#define REG_AIC_DR REG32(AIC_DR) - -/* AIC Controller Configuration Register (AIC_FR) */ - -#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ -#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) -#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ -#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) -#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ -#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ -#define AIC_FR_RST (1 << 3) /* AIC registers reset */ -#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ -#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ -#define AIC_FR_ENB (1 << 0) /* AIC enable bit */ - -/* AIC Controller Common Control Register (AIC_CR) */ - -#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ -#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) -#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ -#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) -#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ -#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ -#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ -#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ -#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ -#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ -#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ -#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ -#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ -#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ -#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ -#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ -#define AIC_CR_EREC (1 << 0) /* Enable Record Function */ - -/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ - -#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ -#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) - #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ - #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ - #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ - #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ - #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ - #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ - #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ - #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ - #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ - #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ -#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ -#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) - #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ - #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ - #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ - #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ - #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ - #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ - #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ - #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ - #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ - #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ - -/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ - -#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ -#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ -#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ -#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ -#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) - #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ - #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ - #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ - #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ -#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ -#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) - #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ - #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ - #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ - #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ -#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ -#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ -#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ -#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ - -/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ - -#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ -#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ -#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) - #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ - #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ - #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ - #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ - #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ -#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ - -/* AIC Controller FIFO Status Register (AIC_SR) */ - -#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ -#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) -#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ -#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) -#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ -#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ -#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ -#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ - -/* AIC Controller AC-link Status Register (AIC_ACSR) */ - -#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ -#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ -#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ -#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ -#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ -#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ - -/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ - -#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ - -/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ - -#define AIC_ACCAR_CAR_BIT 0 -#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) - -/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ - -#define AIC_ACCDR_CDR_BIT 0 -#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) - -/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ - -#define AIC_ACSAR_SAR_BIT 0 -#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) - -/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ - -#define AIC_ACSDR_SDR_BIT 0 -#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) - -/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ - -#define AIC_I2SDIV_DIV_BIT 0 -#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) - #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ - #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ - #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ - #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ - #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ - #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ - - -/************************************************************************* - * ICDC (Internal CODEC) - *************************************************************************/ -#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ -#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ -#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ -#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ -#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ -#define ICDC_CDCCR1 (ICDC_BASE + 0x0080) -#define ICDC_CDCCR2 (ICDC_BASE + 0x0084) - -#define REG_ICDC_CR REG32(ICDC_CR) -#define REG_ICDC_APWAIT REG32(ICDC_APWAIT) -#define REG_ICDC_APPRE REG32(ICDC_APPRE) -#define REG_ICDC_APHPEN REG32(ICDC_APHPEN) -#define REG_ICDC_APSR REG32(ICDC_APSR) -#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) -#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) - -/* ICDC Control Register */ -#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ -#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) -#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ -#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) -#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ -#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) - #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) - #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) - #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) - #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) -#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ -#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) - #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) - #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) - #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) - #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) -#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ -#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ -#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ -#define ICDC_CR_EADC (1 << 10) /* Enable ADC */ -#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ -#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ -#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ -#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ -#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ -#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ -#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ -#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ - -/* Anti-Pop WAIT Stage Timing Control Register */ -#define ICDC_APWAIT_WAITSN_BIT 0 -#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) - -/* Anti-Pop HPEN-PRE Stage Timing Control Register */ -#define ICDC_APPRE_PRESN_BIT 0 -#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) - -/* Anti-Pop HPEN Stage Timing Control Register */ -#define ICDC_APHPEN_HPENSN_BIT 0 -#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) - -/* Anti-Pop Status Register */ -#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ -#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) -#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ -#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ - #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ -#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ - #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ - #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ - #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ - #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ -#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ -#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) - - -/************************************************************************* - * I2C - *************************************************************************/ -#define I2C_DR (I2C_BASE + 0x000) -#define I2C_CR (I2C_BASE + 0x004) -#define I2C_SR (I2C_BASE + 0x008) -#define I2C_GR (I2C_BASE + 0x00C) - -#define REG_I2C_DR REG8(I2C_DR) -#define REG_I2C_CR REG8(I2C_CR) -#define REG_I2C_SR REG8(I2C_SR) -#define REG_I2C_GR REG16(I2C_GR) - -/* I2C Control Register (I2C_CR) */ - -#define I2C_CR_IEN (1 << 4) -#define I2C_CR_STA (1 << 3) -#define I2C_CR_STO (1 << 2) -#define I2C_CR_AC (1 << 1) -#define I2C_CR_I2CE (1 << 0) - -/* I2C Status Register (I2C_SR) */ - -#define I2C_SR_STX (1 << 4) -#define I2C_SR_BUSY (1 << 3) -#define I2C_SR_TEND (1 << 2) -#define I2C_SR_DRF (1 << 1) -#define I2C_SR_ACKF (1 << 0) - - -/************************************************************************* - * SSI - *************************************************************************/ -#define SSI_DR (SSI_BASE + 0x000) -#define SSI_CR0 (SSI_BASE + 0x004) -#define SSI_CR1 (SSI_BASE + 0x008) -#define SSI_SR (SSI_BASE + 0x00C) -#define SSI_ITR (SSI_BASE + 0x010) -#define SSI_ICR (SSI_BASE + 0x014) -#define SSI_GR (SSI_BASE + 0x018) - -#define REG_SSI_DR REG32(SSI_DR) -#define REG_SSI_CR0 REG16(SSI_CR0) -#define REG_SSI_CR1 REG32(SSI_CR1) -#define REG_SSI_SR REG32(SSI_SR) -#define REG_SSI_ITR REG16(SSI_ITR) -#define REG_SSI_ICR REG8(SSI_ICR) -#define REG_SSI_GR REG16(SSI_GR) - -/* SSI Data Register (SSI_DR) */ - -#define SSI_DR_GPC_BIT 0 -#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) - -/* SSI Control Register 0 (SSI_CR0) */ - -#define SSI_CR0_SSIE (1 << 15) -#define SSI_CR0_TIE (1 << 14) -#define SSI_CR0_RIE (1 << 13) -#define SSI_CR0_TEIE (1 << 12) -#define SSI_CR0_REIE (1 << 11) -#define SSI_CR0_LOOP (1 << 10) -#define SSI_CR0_RFINE (1 << 9) -#define SSI_CR0_RFINC (1 << 8) -#define SSI_CR0_FSEL (1 << 6) -#define SSI_CR0_TFLUSH (1 << 2) -#define SSI_CR0_RFLUSH (1 << 1) -#define SSI_CR0_DISREV (1 << 0) - -/* SSI Control Register 1 (SSI_CR1) */ - -#define SSI_CR1_FRMHL_BIT 30 -#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) - #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ - #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ - #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ - #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ -#define SSI_CR1_TFVCK_BIT 28 -#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) -#define SSI_CR1_TCKFI_BIT 26 -#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) -#define SSI_CR1_LFST (1 << 25) -#define SSI_CR1_ITFRM (1 << 24) -#define SSI_CR1_UNFIN (1 << 23) -#define SSI_CR1_MULTS (1 << 22) -#define SSI_CR1_FMAT_BIT 20 -#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) - #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ - #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ - #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ - #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ -#define SSI_CR1_TTRG_BIT 16 -#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) -#define SSI_CR1_MCOM_BIT 12 -#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) - #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ - #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ - #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ - #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ - #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ - #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ - #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ - #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ - #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ - #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ - #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ - #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ - #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ - #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ - #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ - #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ -#define SSI_CR1_RTRG_BIT 8 -#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) -#define SSI_CR1_FLEN_BIT 4 -#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) -#define SSI_CR1_PHA (1 << 1) -#define SSI_CR1_POL (1 << 0) - -/* SSI Status Register (SSI_SR) */ - -#define SSI_SR_TFIFONUM_BIT 16 -#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) -#define SSI_SR_RFIFONUM_BIT 8 -#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) -#define SSI_SR_END (1 << 7) -#define SSI_SR_BUSY (1 << 6) -#define SSI_SR_TFF (1 << 5) -#define SSI_SR_RFE (1 << 4) -#define SSI_SR_TFHE (1 << 3) -#define SSI_SR_RFHF (1 << 2) -#define SSI_SR_UNDR (1 << 1) -#define SSI_SR_OVER (1 << 0) - -/* SSI Interval Time Control Register (SSI_ITR) */ - -#define SSI_ITR_CNTCLK (1 << 15) -#define SSI_ITR_IVLTM_BIT 0 -#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) - - -/************************************************************************* - * MSC - *************************************************************************/ -#define MSC_STRPCL (MSC_BASE + 0x000) -#define MSC_STAT (MSC_BASE + 0x004) -#define MSC_CLKRT (MSC_BASE + 0x008) -#define MSC_CMDAT (MSC_BASE + 0x00C) -#define MSC_RESTO (MSC_BASE + 0x010) -#define MSC_RDTO (MSC_BASE + 0x014) -#define MSC_BLKLEN (MSC_BASE + 0x018) -#define MSC_NOB (MSC_BASE + 0x01C) -#define MSC_SNOB (MSC_BASE + 0x020) -#define MSC_IMASK (MSC_BASE + 0x024) -#define MSC_IREG (MSC_BASE + 0x028) -#define MSC_CMD (MSC_BASE + 0x02C) -#define MSC_ARG (MSC_BASE + 0x030) -#define MSC_RES (MSC_BASE + 0x034) -#define MSC_RXFIFO (MSC_BASE + 0x038) -#define MSC_TXFIFO (MSC_BASE + 0x03C) - -#define REG_MSC_STRPCL REG16(MSC_STRPCL) -#define REG_MSC_STAT REG32(MSC_STAT) -#define REG_MSC_CLKRT REG16(MSC_CLKRT) -#define REG_MSC_CMDAT REG32(MSC_CMDAT) -#define REG_MSC_RESTO REG16(MSC_RESTO) -#define REG_MSC_RDTO REG16(MSC_RDTO) -#define REG_MSC_BLKLEN REG16(MSC_BLKLEN) -#define REG_MSC_NOB REG16(MSC_NOB) -#define REG_MSC_SNOB REG16(MSC_SNOB) -#define REG_MSC_IMASK REG16(MSC_IMASK) -#define REG_MSC_IREG REG16(MSC_IREG) -#define REG_MSC_CMD REG8(MSC_CMD) -#define REG_MSC_ARG REG32(MSC_ARG) -#define REG_MSC_RES REG16(MSC_RES) -#define REG_MSC_RXFIFO REG32(MSC_RXFIFO) -#define REG_MSC_TXFIFO REG32(MSC_TXFIFO) - -/* MSC Clock and Control Register (MSC_STRPCL) */ - -#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) -#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) -#define MSC_STRPCL_START_READWAIT (1 << 5) -#define MSC_STRPCL_STOP_READWAIT (1 << 4) -#define MSC_STRPCL_RESET (1 << 3) -#define MSC_STRPCL_START_OP (1 << 2) -#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 -#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) - #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ - #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ - -/* MSC Status Register (MSC_STAT) */ - -#define MSC_STAT_IS_RESETTING (1 << 15) -#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) -#define MSC_STAT_PRG_DONE (1 << 13) -#define MSC_STAT_DATA_TRAN_DONE (1 << 12) -#define MSC_STAT_END_CMD_RES (1 << 11) -#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) -#define MSC_STAT_IS_READWAIT (1 << 9) -#define MSC_STAT_CLK_EN (1 << 8) -#define MSC_STAT_DATA_FIFO_FULL (1 << 7) -#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) -#define MSC_STAT_CRC_RES_ERR (1 << 5) -#define MSC_STAT_CRC_READ_ERROR (1 << 4) -#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 -#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) - #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ -#define MSC_STAT_TIME_OUT_RES (1 << 1) -#define MSC_STAT_TIME_OUT_READ (1 << 0) - -/* MSC Bus Clock Control Register (MSC_CLKRT) */ - -#define MSC_CLKRT_CLK_RATE_BIT 0 -#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ - -/* MSC Command Sequence Control Register (MSC_CMDAT) */ - -#define MSC_CMDAT_IO_ABORT (1 << 11) -#define MSC_CMDAT_BUS_WIDTH_BIT 9 -#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) - #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ - #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ - #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) - #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_DMA_EN (1 << 8) -#define MSC_CMDAT_INIT (1 << 7) -#define MSC_CMDAT_BUSY (1 << 6) -#define MSC_CMDAT_STREAM_BLOCK (1 << 5) -#define MSC_CMDAT_WRITE (1 << 4) -#define MSC_CMDAT_READ (0 << 4) -#define MSC_CMDAT_DATA_EN (1 << 3) -#define MSC_CMDAT_RESPONSE_BIT 0 -#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) - #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ - #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ - #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ - #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ - #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ - #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ - #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ - -#define CMDAT_DMA_EN (1 << 8) -#define CMDAT_INIT (1 << 7) -#define CMDAT_BUSY (1 << 6) -#define CMDAT_STREAM (1 << 5) -#define CMDAT_WRITE (1 << 4) -#define CMDAT_DATA_EN (1 << 3) - -/* MSC Interrupts Mask Register (MSC_IMASK) */ - -#define MSC_IMASK_SDIO (1 << 7) -#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) -#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) -#define MSC_IMASK_END_CMD_RES (1 << 2) -#define MSC_IMASK_PRG_DONE (1 << 1) -#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) - - -/* MSC Interrupts Status Register (MSC_IREG) */ - -#define MSC_IREG_SDIO (1 << 7) -#define MSC_IREG_TXFIFO_WR_REQ (1 << 6) -#define MSC_IREG_RXFIFO_RD_REQ (1 << 5) -#define MSC_IREG_END_CMD_RES (1 << 2) -#define MSC_IREG_PRG_DONE (1 << 1) -#define MSC_IREG_DATA_TRAN_DONE (1 << 0) - - -/************************************************************************* - * EMC (External Memory Controller) - *************************************************************************/ -#define EMC_BCR (EMC_BASE + 0x0) /* BCR */ - -#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ -#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ -#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ -#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ -#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ -#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ -#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ -#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ -#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ -#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ - -#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ -#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ -#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ -#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ -#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ -#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ -#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ -#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ -#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ -#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ -#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ -#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ - -#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ -#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ -#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ -#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ -#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ -#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ - -#define REG_EMC_BCR REG32(EMC_BCR) - -#define REG_EMC_SMCR0 REG32(EMC_SMCR0) -#define REG_EMC_SMCR1 REG32(EMC_SMCR1) -#define REG_EMC_SMCR2 REG32(EMC_SMCR2) -#define REG_EMC_SMCR3 REG32(EMC_SMCR3) -#define REG_EMC_SMCR4 REG32(EMC_SMCR4) -#define REG_EMC_SACR0 REG32(EMC_SACR0) -#define REG_EMC_SACR1 REG32(EMC_SACR1) -#define REG_EMC_SACR2 REG32(EMC_SACR2) -#define REG_EMC_SACR3 REG32(EMC_SACR3) -#define REG_EMC_SACR4 REG32(EMC_SACR4) - -#define REG_EMC_NFCSR REG32(EMC_NFCSR) -#define REG_EMC_NFECR REG32(EMC_NFECR) -#define REG_EMC_NFECC REG32(EMC_NFECC) -#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) -#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) -#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) -#define REG_EMC_NFINTS REG32(EMC_NFINTS) -#define REG_EMC_NFINTE REG32(EMC_NFINTE) -#define REG_EMC_NFERR0 REG32(EMC_NFERR0) -#define REG_EMC_NFERR1 REG32(EMC_NFERR1) -#define REG_EMC_NFERR2 REG32(EMC_NFERR2) -#define REG_EMC_NFERR3 REG32(EMC_NFERR3) - -#define REG_EMC_DMCR REG32(EMC_DMCR) -#define REG_EMC_RTCSR REG16(EMC_RTCSR) -#define REG_EMC_RTCNT REG16(EMC_RTCNT) -#define REG_EMC_RTCOR REG16(EMC_RTCOR) -#define REG_EMC_DMAR0 REG32(EMC_DMAR0) - -/* Static Memory Control Register */ -#define EMC_SMCR_STRV_BIT 24 -#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) -#define EMC_SMCR_TAW_BIT 20 -#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) -#define EMC_SMCR_TBP_BIT 16 -#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) -#define EMC_SMCR_TAH_BIT 12 -#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) -#define EMC_SMCR_TAS_BIT 8 -#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) -#define EMC_SMCR_BW_BIT 6 -#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) -#define EMC_SMCR_BL_BIT 1 -#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) - -/* Static Memory Bank Addr Config Reg */ -#define EMC_SACR_BASE_BIT 8 -#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) -#define EMC_SACR_MASK_BIT 0 -#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) - -/* NAND Flash Control/Status Register */ -#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ -#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ -#define EMC_NFCSR_NFCE3 (1 << 5) -#define EMC_NFCSR_NFE3 (1 << 4) -#define EMC_NFCSR_NFCE2 (1 << 3) -#define EMC_NFCSR_NFE2 (1 << 2) -#define EMC_NFCSR_NFCE1 (1 << 1) -#define EMC_NFCSR_NFE1 (1 << 0) - -/* NAND Flash ECC Control Register */ -#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ -#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ -#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ -#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ -#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ -#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ -#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ - -/* NAND Flash ECC Data Register */ -#define EMC_NFECC_ECC2_BIT 16 -#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) -#define EMC_NFECC_ECC1_BIT 8 -#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) -#define EMC_NFECC_ECC0_BIT 0 -#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) - -/* NAND Flash Interrupt Status Register */ -#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ -#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) -#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ -#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ -#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ -#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ -#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ - -/* NAND Flash Interrupt Enable Register */ -#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ -#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ -#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ -#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ -#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ - -/* NAND Flash RS Error Report Register */ -#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ -#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) -#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ -#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) - - -/* DRAM Control Register */ -#define EMC_DMCR_BW_BIT 31 -#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) -#define EMC_DMCR_CA_BIT 26 -#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) -#define EMC_DMCR_RMODE (1 << 25) -#define EMC_DMCR_RFSH (1 << 24) -#define EMC_DMCR_MRSET (1 << 23) -#define EMC_DMCR_RA_BIT 20 -#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) -#define EMC_DMCR_BA_BIT 19 -#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) -#define EMC_DMCR_PDM (1 << 18) -#define EMC_DMCR_EPIN (1 << 17) -#define EMC_DMCR_TRAS_BIT 13 -#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) -#define EMC_DMCR_RCD_BIT 11 -#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) -#define EMC_DMCR_TPC_BIT 8 -#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) -#define EMC_DMCR_TRWL_BIT 5 -#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) -#define EMC_DMCR_TRC_BIT 2 -#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) -#define EMC_DMCR_TCL_BIT 0 -#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) - -/* Refresh Time Control/Status Register */ -#define EMC_RTCSR_CMF (1 << 7) -#define EMC_RTCSR_CKS_BIT 0 -#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) - -/* SDRAM Bank Address Configuration Register */ -#define EMC_DMAR_BASE_BIT 8 -#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) -#define EMC_DMAR_MASK_BIT 0 -#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) - -/* Mode Register of SDRAM bank 0 */ -#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ -#define EMC_SDMR_OM_BIT 7 /* Operating Mode */ -#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) - #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) -#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ -#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) -#define EMC_SDMR_BT_BIT 3 /* Burst Type */ -#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ - #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ -#define EMC_SDMR_BL_BIT 0 /* Burst Length */ -#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) - -#define EMC_SDMR_CAS2_16BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS2_32BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) -#define EMC_SDMR_CAS3_16BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS3_32BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) - - -/************************************************************************* - * CIM - *************************************************************************/ -#define CIM_CFG (CIM_BASE + 0x0000) -#define CIM_CTRL (CIM_BASE + 0x0004) -#define CIM_STATE (CIM_BASE + 0x0008) -#define CIM_IID (CIM_BASE + 0x000C) -#define CIM_RXFIFO (CIM_BASE + 0x0010) -#define CIM_DA (CIM_BASE + 0x0020) -#define CIM_FA (CIM_BASE + 0x0024) -#define CIM_FID (CIM_BASE + 0x0028) -#define CIM_CMD (CIM_BASE + 0x002C) - -#define REG_CIM_CFG REG32(CIM_CFG) -#define REG_CIM_CTRL REG32(CIM_CTRL) -#define REG_CIM_STATE REG32(CIM_STATE) -#define REG_CIM_IID REG32(CIM_IID) -#define REG_CIM_RXFIFO REG32(CIM_RXFIFO) -#define REG_CIM_DA REG32(CIM_DA) -#define REG_CIM_FA REG32(CIM_FA) -#define REG_CIM_FID REG32(CIM_FID) -#define REG_CIM_CMD REG32(CIM_CMD) - -/* CIM Configuration Register (CIM_CFG) */ - -#define CIM_CFG_INV_DAT (1 << 15) -#define CIM_CFG_VSP (1 << 14) -#define CIM_CFG_HSP (1 << 13) -#define CIM_CFG_PCP (1 << 12) -#define CIM_CFG_DUMMY_ZERO (1 << 9) -#define CIM_CFG_EXT_VSYNC (1 << 8) -#define CIM_CFG_PACK_BIT 4 -#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) -#define CIM_CFG_DSM_BIT 0 -#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) - #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ - #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ - #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ - #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ - -/* CIM Control Register (CIM_CTRL) */ - -#define CIM_CTRL_MCLKDIV_BIT 24 -#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) -#define CIM_CTRL_FRC_BIT 16 -#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) - #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ - #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ - #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ - #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ - #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ - #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ - #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ - #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ - #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ - #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ - #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ - #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ - #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ - #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ - #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ - #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ -#define CIM_CTRL_VDDM (1 << 13) -#define CIM_CTRL_DMA_SOFM (1 << 12) -#define CIM_CTRL_DMA_EOFM (1 << 11) -#define CIM_CTRL_DMA_STOPM (1 << 10) -#define CIM_CTRL_RXF_TRIGM (1 << 9) -#define CIM_CTRL_RXF_OFM (1 << 8) -#define CIM_CTRL_RXF_TRIG_BIT 4 -#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) - #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ - #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ - #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ - #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ - #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ - #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ - #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ - #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ -#define CIM_CTRL_DMA_EN (1 << 2) -#define CIM_CTRL_RXF_RST (1 << 1) -#define CIM_CTRL_ENA (1 << 0) - -/* CIM State Register (CIM_STATE) */ - -#define CIM_STATE_DMA_SOF (1 << 6) -#define CIM_STATE_DMA_EOF (1 << 5) -#define CIM_STATE_DMA_STOP (1 << 4) -#define CIM_STATE_RXF_OF (1 << 3) -#define CIM_STATE_RXF_TRIG (1 << 2) -#define CIM_STATE_RXF_EMPTY (1 << 1) -#define CIM_STATE_VDD (1 << 0) - -/* CIM DMA Command Register (CIM_CMD) */ - -#define CIM_CMD_SOFINT (1 << 31) -#define CIM_CMD_EOFINT (1 << 30) -#define CIM_CMD_STOP (1 << 28) -#define CIM_CMD_LEN_BIT 0 -#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) - - -/************************************************************************* - * SADC (Smart A/D Controller) - *************************************************************************/ - -#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ -#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ -#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ -#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ -#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ -#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ -#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ -#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ -#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ - -#define REG_SADC_ENA REG8(SADC_ENA) -#define REG_SADC_CFG REG32(SADC_CFG) -#define REG_SADC_CTRL REG8(SADC_CTRL) -#define REG_SADC_STATE REG8(SADC_STATE) -#define REG_SADC_SAMETIME REG16(SADC_SAMETIME) -#define REG_SADC_WAITTIME REG16(SADC_WAITTIME) -#define REG_SADC_TSDAT REG32(SADC_TSDAT) -#define REG_SADC_BATDAT REG16(SADC_BATDAT) -#define REG_SADC_SADDAT REG16(SADC_SADDAT) - -/* ADC Enable Register */ -#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ -#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ -#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ -#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ - -/* ADC Configure Register */ -#define SADC_CFG_CLKOUT_NUM_BIT 16 -#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) -#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ -#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ -#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) - #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) - #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) - #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) -#define SADC_CFG_SNUM_BIT 10 /* Sample Number */ -#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) -#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ -#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) -#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ -#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ -#define SADC_CFG_CMD_BIT 0 /* ADC Command */ -#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) - #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ - #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ - #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ - #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ - #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ - #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ - #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ - #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ - #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ - #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ - #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ - #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ - #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ - -/* ADC Control Register */ -#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ -#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ -#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ -#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ -#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ - -/* ADC Status Register */ -#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ -#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ -#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ -#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ -#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ -#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ -#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ -#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ - -/* ADC Touch Screen Data Register */ -#define SADC_TSDAT_DATA0_BIT 0 -#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) -#define SADC_TSDAT_TYPE0 (1 << 15) -#define SADC_TSDAT_DATA1_BIT 16 -#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) -#define SADC_TSDAT_TYPE1 (1 << 31) - - -/************************************************************************* - * SLCD (Smart LCD Controller) - *************************************************************************/ - -#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ -#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ -#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ -#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ -#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ - -#define REG_SLCD_CFG REG32(SLCD_CFG) -#define REG_SLCD_CTRL REG8(SLCD_CTRL) -#define REG_SLCD_STATE REG8(SLCD_STATE) -#define REG_SLCD_DATA REG32(SLCD_DATA) -#define REG_SLCD_FIFO REG32(SLCD_FIFO) - -/* SLCD Configure Register */ -#define SLCD_CFG_BURST_BIT 14 -#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) - #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) - #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) -#define SLCD_CFG_DWIDTH_BIT 10 -#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) -#define SLCD_CFG_CWIDTH_16BIT (0 << 8) -#define SLCD_CFG_CWIDTH_8BIT (1 << 8) -#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) -#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) -#define SLCD_CFG_RS_CMD_LOW (0 << 3) -#define SLCD_CFG_RS_CMD_HIGH (1 << 3) -#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) -#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) -#define SLCD_CFG_TYPE_PARALLEL (0 << 0) -#define SLCD_CFG_TYPE_SERIAL (1 << 0) - -/* SLCD Control Register */ -#define SLCD_CTRL_DMA_EN (1 << 0) - -/* SLCD Status Register */ -#define SLCD_STATE_BUSY (1 << 0) - -/* SLCD Data Register */ -#define SLCD_DATA_RS_DATA (0 << 31) -#define SLCD_DATA_RS_COMMAND (1 << 31) - -/* SLCD FIFO Register */ -#define SLCD_FIFO_RS_DATA (0 << 31) -#define SLCD_FIFO_RS_COMMAND (1 << 31) - - -/************************************************************************* - * LCD (LCD Controller) - *************************************************************************/ -#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */ -#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */ -#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */ -#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */ -#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */ -#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */ -#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */ -#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */ -#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */ -#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */ -#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */ -#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */ -#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */ -#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */ -#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */ -#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */ -#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */ -#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */ -#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */ -#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */ -#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */ - -#define REG_LCD_CFG REG32(LCD_CFG) -#define REG_LCD_VSYNC REG32(LCD_VSYNC) -#define REG_LCD_HSYNC REG32(LCD_HSYNC) -#define REG_LCD_VAT REG32(LCD_VAT) -#define REG_LCD_DAH REG32(LCD_DAH) -#define REG_LCD_DAV REG32(LCD_DAV) -#define REG_LCD_PS REG32(LCD_PS) -#define REG_LCD_CLS REG32(LCD_CLS) -#define REG_LCD_SPL REG32(LCD_SPL) -#define REG_LCD_REV REG32(LCD_REV) -#define REG_LCD_CTRL REG32(LCD_CTRL) -#define REG_LCD_STATE REG32(LCD_STATE) -#define REG_LCD_IID REG32(LCD_IID) -#define REG_LCD_DA0 REG32(LCD_DA0) -#define REG_LCD_SA0 REG32(LCD_SA0) -#define REG_LCD_FID0 REG32(LCD_FID0) -#define REG_LCD_CMD0 REG32(LCD_CMD0) -#define REG_LCD_DA1 REG32(LCD_DA1) -#define REG_LCD_SA1 REG32(LCD_SA1) -#define REG_LCD_FID1 REG32(LCD_FID1) -#define REG_LCD_CMD1 REG32(LCD_CMD1) - -/* LCD Configure Register */ -#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ -#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) - #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) - #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) -#define LCD_CFG_PSM (1 << 23) /* PS signal mode */ -#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ -#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ -#define LCD_CFG_REVM (1 << 20) /* REV signal mode */ -#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ -#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ -#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ -#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ -#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ -#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ -#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ -#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ -#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ -#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ -#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ -#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ -#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ -#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) -#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ - #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ - #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ - #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ -#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ -#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ - #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) - /* JZ47XX defines */ - #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) - - - -/* Vertical Synchronize Register */ -#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ -#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) -#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ -#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) - -/* Horizontal Synchronize Register */ -#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ -#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) -#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ -#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) - -/* Virtual Area Setting Register */ -#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ -#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) -#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ -#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) - -/* Display Area Horizontal Start/End Point Register */ -#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ -#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) -#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ -#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) - -/* Display Area Vertical Start/End Point Register */ -#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ -#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) -#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ -#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) - -/* PS Signal Setting */ -#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ -#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) -#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ -#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) - -/* CLS Signal Setting */ -#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ -#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) -#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ -#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) - -/* SPL Signal Setting */ -#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ -#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) -#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ -#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) - -/* REV Signal Setting */ -#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ -#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) - -/* LCD Control Register */ -#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ -#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) - #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ - #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ - #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ -#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ -#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ -#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ -#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ -#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) - #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ - #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ - #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ -#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ -#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) -#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ -#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ -#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ -#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ -#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ -#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ -#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ -#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ -#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ -#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ -#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ -#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ -#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ - #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ - #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ - #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ - #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ - #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ - -/* LCD Status Register */ -#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ -#define LCD_STATE_EOF (1 << 5) /* EOF Flag */ -#define LCD_STATE_SOF (1 << 4) /* SOF Flag */ -#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ -#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ -#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ -#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ - -/* DMA Command Register */ -#define LCD_CMD_SOFINT (1 << 31) -#define LCD_CMD_EOFINT (1 << 30) -#define LCD_CMD_PAL (1 << 28) -#define LCD_CMD_LEN_BIT 0 -#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) - - -/************************************************************************* - * USB Device - *************************************************************************/ -#define USB_BASE UDC_BASE - -#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ -#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ -#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ -#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ -#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ -#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ -#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ -#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ -#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ -#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ -#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ - -#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ -#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ -#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ -#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ -#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ -#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ -#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ -#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ - -#define USB_FIFO_EP0 (USB_BASE + 0x20) -#define USB_FIFO_EP1 (USB_BASE + 0x24) -#define USB_FIFO_EP2 (USB_BASE + 0x28) - -#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ -#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ - -#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ -#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ -#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ -#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ -#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ -#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ -#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ - - -/* Power register bit masks */ -#define USB_POWER_SUSPENDM 0x01 -#define USB_POWER_RESUME 0x04 -#define USB_POWER_HSMODE 0x10 -#define USB_POWER_HSENAB 0x20 -#define USB_POWER_SOFTCONN 0x40 - -/* Interrupt register bit masks */ -#define USB_INTR_SUSPEND 0x01 -#define USB_INTR_RESUME 0x02 -#define USB_INTR_RESET 0x04 - -#define USB_INTR_EP0 0x0001 -#define USB_INTR_INEP1 0x0002 -#define USB_INTR_INEP2 0x0004 -#define USB_INTR_OUTEP1 0x0002 - -/* CSR0 bit masks */ -#define USB_CSR0_OUTPKTRDY 0x01 -#define USB_CSR0_INPKTRDY 0x02 -#define USB_CSR0_SENTSTALL 0x04 -#define USB_CSR0_DATAEND 0x08 -#define USB_CSR0_SETUPEND 0x10 -#define USB_CSR0_SENDSTALL 0x20 -#define USB_CSR0_SVDOUTPKTRDY 0x40 -#define USB_CSR0_SVDSETUPEND 0x80 - -/* Endpoint CSR register bits */ -#define USB_INCSRH_AUTOSET 0x80 -#define USB_INCSRH_ISO 0x40 -#define USB_INCSRH_MODE 0x20 -#define USB_INCSRH_DMAREQENAB 0x10 -#define USB_INCSRH_DMAREQMODE 0x04 -#define USB_INCSR_CDT 0x40 -#define USB_INCSR_SENTSTALL 0x20 -#define USB_INCSR_SENDSTALL 0x10 -#define USB_INCSR_FF 0x08 -#define USB_INCSR_UNDERRUN 0x04 -#define USB_INCSR_FFNOTEMPT 0x02 -#define USB_INCSR_INPKTRDY 0x01 -#define USB_OUTCSRH_AUTOCLR 0x80 -#define USB_OUTCSRH_ISO 0x40 -#define USB_OUTCSRH_DMAREQENAB 0x20 -#define USB_OUTCSRH_DNYT 0x10 -#define USB_OUTCSRH_DMAREQMODE 0x08 -#define USB_OUTCSR_CDT 0x80 -#define USB_OUTCSR_SENTSTALL 0x40 -#define USB_OUTCSR_SENDSTALL 0x20 -#define USB_OUTCSR_FF 0x10 -#define USB_OUTCSR_DATAERR 0x08 -#define USB_OUTCSR_OVERRUN 0x04 -#define USB_OUTCSR_FFFULL 0x02 -#define USB_OUTCSR_OUTPKTRDY 0x01 - -/* Testmode register bits */ -#define USB_TEST_SE0NAK 0x01 -#define USB_TEST_J 0x02 -#define USB_TEST_K 0x04 -#define USB_TEST_PACKET 0x08 - -/* DMA control bits */ -#define USB_CNTL_ENA 0x01 -#define USB_CNTL_DIR_IN 0x02 -#define USB_CNTL_MODE_1 0x04 -#define USB_CNTL_INTR_EN 0x08 -#define USB_CNTL_EP(n) ((n) << 4) -#define USB_CNTL_BURST_0 (0 << 9) -#define USB_CNTL_BURST_4 (1 << 9) -#define USB_CNTL_BURST_8 (2 << 9) -#define USB_CNTL_BURST_16 (3 << 9) - - -//---------------------------------------------------------------------- -// -// Module Operation Definitions -// -//---------------------------------------------------------------------- -#ifndef __ASSEMBLY__ - -/*************************************************************************** - * GPIO - ***************************************************************************/ - -//------------------------------------------------------ -// GPIO Pins Description -// -// PORT 0: -// -// PIN/BIT N FUNC0 FUNC1 -// 0 D0 - -// 1 D1 - -// 2 D2 - -// 3 D3 - -// 4 D4 - -// 5 D5 - -// 6 D6 - -// 7 D7 - -// 8 D8 - -// 9 D9 - -// 10 D10 - -// 11 D11 - -// 12 D12 - -// 13 D13 - -// 14 D14 - -// 15 D15 - -// 16 D16 - -// 17 D17 - -// 18 D18 - -// 19 D19 - -// 20 D20 - -// 21 D21 - -// 22 D22 - -// 23 D23 - -// 24 D24 - -// 25 D25 - -// 26 D26 - -// 27 D27 - -// 28 D28 - -// 29 D29 - -// 30 D30 - -// 31 D31 - -// -//------------------------------------------------------ -// PORT 1: -// -// PIN/BIT N FUNC0 FUNC1 -// 0 A0 - -// 1 A1 - -// 2 A2 - -// 3 A3 - -// 4 A4 - -// 5 A5 - -// 6 A6 - -// 7 A7 - -// 8 A8 - -// 9 A9 - -// 10 A10 - -// 11 A11 - -// 12 A12 - -// 13 A13 - -// 14 A14 - -// 15 A15/CL - -// 16 A16/AL - -// 17 LCD_CLS A21 -// 18 LCD_SPL A22 -// 19 DCS# - -// 20 RAS# - -// 21 CAS# - -// 22 RDWE#/BUFD# - -// 23 CKE - -// 24 CKO - -// 25 CS1# - -// 26 CS2# - -// 27 CS3# - -// 28 CS4# - -// 29 RD# - -// 30 WR# - -// 31 WE0# - -// -// Note: PIN15&16 are CL&AL when connecting to NAND flash. -//------------------------------------------------------ -// PORT 2: -// -// PIN/BIT N FUNC0 FUNC1 -// 0 LCD_D0 - -// 1 LCD_D1 - -// 2 LCD_D2 - -// 3 LCD_D3 - -// 4 LCD_D4 - -// 5 LCD_D5 - -// 6 LCD_D6 - -// 7 LCD_D7 - -// 8 LCD_D8 - -// 9 LCD_D9 - -// 10 LCD_D10 - -// 11 LCD_D11 - -// 12 LCD_D12 - -// 13 LCD_D13 - -// 14 LCD_D14 - -// 15 LCD_D15 - -// 16 LCD_D16 - -// 17 LCD_D17 - -// 18 LCD_PCLK - -// 19 LCD_HSYNC - -// 20 LCD_VSYNC - -// 21 LCD_DE - -// 22 LCD_PS A19 -// 23 LCD_REV A20 -// 24 WE1# - -// 25 WE2# - -// 26 WE3# - -// 27 WAIT# - -// 28 FRE# - -// 29 FWE# - -// 30(NOTE:FRB#) - - -// 31 - - -// -// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. -//------------------------------------------------------ -// PORT 3: -// -// PIN/BIT N FUNC0 FUNC1 -// 0 CIM_D0 - -// 1 CIM_D1 - -// 2 CIM_D2 - -// 3 CIM_D3 - -// 4 CIM_D4 - -// 5 CIM_D5 - -// 6 CIM_D6 - -// 7 CIM_D7 - -// 8 MSC_CMD - -// 9 MSC_CLK - -// 10 MSC_D0 - -// 11 MSC_D1 - -// 12 MSC_D2 - -// 13 MSC_D3 - -// 14 CIM_MCLK - -// 15 CIM_PCLK - -// 16 CIM_VSYNC - -// 17 CIM_HSYNC - -// 18 SSI_CLK SCLK_RSTN -// 19 SSI_CE0# BIT_CLK(AIC) -// 20 SSI_DT SDATA_OUT(AIC) -// 21 SSI_DR SDATA_IN(AIC) -// 22 SSI_CE1#&GPC SYNC(AIC) -// 23 PWM0 I2C_SDA -// 24 PWM1 I2C_SCK -// 25 PWM2 UART0_TxD -// 26 PWM3 UART0_RxD -// 27 PWM4 A17 -// 28 PWM5 A18 -// 29 - - -// 30 PWM6 UART0_CTS/UART1_RxD -// 31 PWM7 UART0_RTS/UART1_TxD -// -////////////////////////////////////////////////////////// - -/* - * p is the port number (0,1,2,3) - * o is the pin offset (0-31) inside the port - * n is the absolute number of a pin (0-127), regardless of the port - */ - -//------------------------------------------- -// Function Pins Mode - -#define __gpio_as_func0(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXFUNS(p) = (1 << o); \ - REG_GPIO_PXSELC(p) = (1 << o); \ -} while (0) - -#define __gpio_as_func1(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXFUNS(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ -} while (0) - -/* - * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, - * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# - */ -#define __gpio_as_sdram_32bit() \ -do { \ - REG_GPIO_PXFUNS(0) = 0xffffffff; \ - REG_GPIO_PXSELC(0) = 0xffffffff; \ - REG_GPIO_PXPES(0) = 0xffffffff; \ - REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ - REG_GPIO_PXSELC(1) = 0x81f9ffff; \ - REG_GPIO_PXPES(1) = 0x81f9ffff; \ - REG_GPIO_PXFUNS(2) = 0x07000000; \ - REG_GPIO_PXSELC(2) = 0x07000000; \ - REG_GPIO_PXPES(2) = 0x07000000; \ -} while (0) - -/* - * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, - * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# - */ -#define __gpio_as_sdram_16bit() \ -do { \ - REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ - REG_GPIO_PXSELC(0) = 0x5442bfaa; \ - REG_GPIO_PXPES(0) = 0x5442bfaa; \ - REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ - REG_GPIO_PXSELC(1) = 0x81f9ffff; \ - REG_GPIO_PXPES(1) = 0x81f9ffff; \ - REG_GPIO_PXFUNS(2) = 0x01000000; \ - REG_GPIO_PXSELC(2) = 0x01000000; \ - REG_GPIO_PXPES(2) = 0x01000000; \ -} while (0) - -/* - * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# - */ -#define __gpio_as_nand() \ -do { \ - REG_GPIO_PXFUNS(1) = 0x02018000; \ - REG_GPIO_PXSELC(1) = 0x02018000; \ - REG_GPIO_PXPES(1) = 0x02018000; \ - REG_GPIO_PXFUNS(2) = 0x30000000; \ - REG_GPIO_PXSELC(2) = 0x30000000; \ - REG_GPIO_PXPES(2) = 0x30000000; \ - REG_GPIO_PXFUNC(2) = 0x40000000; \ - REG_GPIO_PXSELC(2) = 0x40000000; \ - REG_GPIO_PXDIRC(2) = 0x40000000; \ - REG_GPIO_PXPES(2) = 0x40000000; \ - REG_GPIO_PXFUNS(1) = 0x00400000; \ - REG_GPIO_PXSELC(1) = 0x00400000; \ -} while (0) - -/* - * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 - */ -#define __gpio_as_nor_8bit() \ -do { \ - REG_GPIO_PXFUNS(0) = 0x000000ff; \ - REG_GPIO_PXSELC(0) = 0x000000ff; \ - REG_GPIO_PXPES(0) = 0x000000ff; \ - REG_GPIO_PXFUNS(1) = 0x7041ffff; \ - REG_GPIO_PXSELC(1) = 0x7041ffff; \ - REG_GPIO_PXPES(1) = 0x7041ffff; \ - REG_GPIO_PXFUNS(1) = 0x00060000; \ - REG_GPIO_PXSELS(1) = 0x00060000; \ - REG_GPIO_PXPES(1) = 0x00060000; \ - REG_GPIO_PXFUNS(2) = 0x08000000; \ - REG_GPIO_PXSELC(2) = 0x08000000; \ - REG_GPIO_PXPES(2) = 0x08000000; \ - REG_GPIO_PXFUNS(2) = 0x00c00000; \ - REG_GPIO_PXSELS(2) = 0x00c00000; \ - REG_GPIO_PXPES(2) = 0x00c00000; \ - REG_GPIO_PXFUNS(3) = 0x18000000; \ - REG_GPIO_PXSELS(3) = 0x18000000; \ - REG_GPIO_PXPES(3) = 0x18000000; \ -} while (0) - -/* - * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 - */ -#define __gpio_as_nor_16bit() \ -do { \ - REG_GPIO_PXFUNS(0) = 0x0000ffff; \ - REG_GPIO_PXSELC(0) = 0x0000ffff; \ - REG_GPIO_PXPES(0) = 0x0000ffff; \ - REG_GPIO_PXFUNS(1) = 0x7041ffff; \ - REG_GPIO_PXSELC(1) = 0x7041ffff; \ - REG_GPIO_PXPES(1) = 0x7041ffff; \ - REG_GPIO_PXFUNS(1) = 0x00060000; \ - REG_GPIO_PXSELS(1) = 0x00060000; \ - REG_GPIO_PXPES(1) = 0x00060000; \ - REG_GPIO_PXFUNS(2) = 0x08000000; \ - REG_GPIO_PXSELC(2) = 0x08000000; \ - REG_GPIO_PXPES(2) = 0x08000000; \ - REG_GPIO_PXFUNS(2) = 0x00c00000; \ - REG_GPIO_PXSELS(2) = 0x00c00000; \ - REG_GPIO_PXPES(2) = 0x00c00000; \ - REG_GPIO_PXFUNS(3) = 0x18000000; \ - REG_GPIO_PXSELS(3) = 0x18000000; \ - REG_GPIO_PXPES(3) = 0x18000000; \ -} while (0) - -/* - * UART0_TxD, UART_RxD0 - */ -#define __gpio_as_uart0() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x06000000; \ - REG_GPIO_PXSELS(3) = 0x06000000; \ - REG_GPIO_PXPES(3) = 0x06000000; \ -} while (0) - -/* - * UART1_TxD, UART1_RxD1 - */ -#define __gpio_as_uart1() \ -do { \ - REG_GPIO_PXFUNS(3) = 0xc0000000; \ - REG_GPIO_PXSELS(3) = 0xc0000000; \ - REG_GPIO_PXPES(3) = 0xc0000000; \ -} while (0) - -/* - * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE - */ -#define __gpio_as_lcd_16bit() \ -do { \ - REG_GPIO_PXFUNS(2) = 0x003cffff; \ - REG_GPIO_PXSELC(2) = 0x003cffff; \ - REG_GPIO_PXPES(2) = 0x003cffff; \ -} while (0) - -/* - * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE - */ -#define __gpio_as_lcd_18bit() \ -do { \ - REG_GPIO_PXFUNS(2) = 0x003fffff; \ - REG_GPIO_PXSELC(2) = 0x003fffff; \ - REG_GPIO_PXPES(2) = 0x003fffff; \ -} while (0) - -/* - * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC - */ -#define __gpio_as_cim() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ - REG_GPIO_PXSELC(3) = 0x0003c0ff; \ - REG_GPIO_PXPES(3) = 0x0003c0ff; \ -} while (0) - -/* - * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET - */ -#define __gpio_as_aic() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x007c0000; \ - REG_GPIO_PXSELS(3) = 0x007c0000; \ - REG_GPIO_PXPES(3) = 0x007c0000; \ -} while (0) - -/* - * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 - */ -#define __gpio_as_msc() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x00003f00; \ - REG_GPIO_PXSELC(3) = 0x00003f00; \ - REG_GPIO_PXPES(3) = 0x00003f00; \ -} while (0) - -/* - * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR - */ -#define __gpio_as_ssi() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x003c0000; \ - REG_GPIO_PXSELC(3) = 0x003c0000; \ - REG_GPIO_PXPES(3) = 0x003c0000; \ -} while (0) - -/* - * I2C_SCK, I2C_SDA - */ -#define __gpio_as_i2c() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x01800000; \ - REG_GPIO_PXSELS(3) = 0x01800000; \ - REG_GPIO_PXPES(3) = 0x01800000; \ -} while (0) - -/* - * PWM0 - */ -#define __gpio_as_pwm0() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x00800000; \ - REG_GPIO_PXSELC(3) = 0x00800000; \ - REG_GPIO_PXPES(3) = 0x00800000; \ -} while (0) - -/* - * PWM1 - */ -#define __gpio_as_pwm1() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x01000000; \ - REG_GPIO_PXSELC(3) = 0x01000000; \ - REG_GPIO_PXPES(3) = 0x01000000; \ -} while (0) - -/* - * PWM2 - */ -#define __gpio_as_pwm2() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x02000000; \ - REG_GPIO_PXSELC(3) = 0x02000000; \ - REG_GPIO_PXPES(3) = 0x02000000; \ -} while (0) - -/* - * PWM3 - */ -#define __gpio_as_pwm3() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x04000000; \ - REG_GPIO_PXSELC(3) = 0x04000000; \ - REG_GPIO_PXPES(3) = 0x04000000; \ -} while (0) - -/* - * PWM4 - */ -#define __gpio_as_pwm4() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x08000000; \ - REG_GPIO_PXSELC(3) = 0x08000000; \ - REG_GPIO_PXPES(3) = 0x08000000; \ -} while (0) - -/* - * PWM5 - */ -#define __gpio_as_pwm5() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x10000000; \ - REG_GPIO_PXSELC(3) = 0x10000000; \ - REG_GPIO_PXPES(3) = 0x10000000; \ -} while (0) - -/* - * PWM6 - */ -#define __gpio_as_pwm6() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x40000000; \ - REG_GPIO_PXSELC(3) = 0x40000000; \ - REG_GPIO_PXPES(3) = 0x40000000; \ -} while (0) - -/* - * PWM7 - */ -#define __gpio_as_pwm7() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x80000000; \ - REG_GPIO_PXSELC(3) = 0x80000000; \ - REG_GPIO_PXPES(3) = 0x80000000; \ -} while (0) - -/* - * n = 0 ~ 7 - */ -#define __gpio_as_pwm(n) __gpio_as_pwm##n() - -//------------------------------------------- -// GPIO or Interrupt Mode - -#define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) - -#define __gpio_port_as_output(p, o) \ -do { \ - REG_GPIO_PXFUNC(p) = (1 << (o)); \ - REG_GPIO_PXSELC(p) = (1 << (o)); \ - REG_GPIO_PXDIRS(p) = (1 << (o)); \ -} while (0) - -#define __gpio_port_as_input(p, o) \ -do { \ - REG_GPIO_PXFUNC(p) = (1 << (o)); \ - REG_GPIO_PXSELC(p) = (1 << (o)); \ - REG_GPIO_PXDIRC(p) = (1 << (o)); \ -} while (0) - -#define __gpio_as_output(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_output(p, o); \ -} while (0) - -#define __gpio_as_input(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_input(p, o); \ -} while (0) - -#define __gpio_set_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXDATS(p) = (1 << o); \ -} while (0) - -#define __gpio_clear_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXDATC(p) = (1 << o); \ -} while (0) - -#define __gpio_get_pin(n) \ -({ \ - unsigned int p, o, v; \ - p = (n) / 32; \ - o = (n) % 32; \ - if (__gpio_get_port(p) & (1 << o)) \ - v = 1; \ - else \ - v = 0; \ - v; \ -}) - -#define __gpio_as_irq_high_level(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ - REG_GPIO_PXTRGC(p) = (1 << o); \ - REG_GPIO_PXFUNC(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ - REG_GPIO_PXDIRS(p) = (1 << o); \ - REG_GPIO_PXFLGC(p) = (1 << o); \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_as_irq_low_level(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ - REG_GPIO_PXTRGC(p) = (1 << o); \ - REG_GPIO_PXFUNC(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ - REG_GPIO_PXDIRC(p) = (1 << o); \ - REG_GPIO_PXFLGC(p) = (1 << o); \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_as_irq_rise_edge(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ - REG_GPIO_PXTRGS(p) = (1 << o); \ - REG_GPIO_PXFUNC(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ - REG_GPIO_PXDIRS(p) = (1 << o); \ - REG_GPIO_PXFLGC(p) = (1 << o); \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_as_irq_fall_edge(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ - REG_GPIO_PXTRGS(p) = (1 << o); \ - REG_GPIO_PXFUNC(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ - REG_GPIO_PXDIRC(p) = (1 << o); \ - REG_GPIO_PXFLGC(p) = (1 << o); \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_mask_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ -} while (0) - -#define __gpio_unmask_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_ack_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXFLGC(p) = (1 << o); \ -} while (0) - -#define __gpio_get_irq() \ -({ \ - unsigned int p, i, tmp, v = 0; \ - for (p = 3; p >= 0; p--) { \ - tmp = REG_GPIO_PXFLG(p); \ - for (i = 0; i < 32; i++) \ - if (tmp & (1 << i)) \ - v = (32*p + i); \ - } \ - v; \ -}) - -#define __gpio_group_irq(n) \ -({ \ - register int tmp, i; \ - tmp = REG_GPIO_PXFLG((n)); \ - for (i=31;i>=0;i--) \ - if (tmp & (1 << i)) \ - break; \ - i; \ -}) - -#define __gpio_enable_pull(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXPEC(p) = (1 << o); \ -} while (0) - -#define __gpio_disable_pull(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXPES(p) = (1 << o); \ -} while (0) - - -/*************************************************************************** - * CPM - ***************************************************************************/ -#define __cpm_get_pllm() \ - ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) -#define __cpm_get_plln() \ - ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) -#define __cpm_get_pllod() \ - ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) - -#define __cpm_get_cdiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) -#define __cpm_get_hdiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) -#define __cpm_get_pdiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) -#define __cpm_get_mdiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) -#define __cpm_get_ldiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) -#define __cpm_get_udiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) -#define __cpm_get_i2sdiv() \ - ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) -#define __cpm_get_pixdiv() \ - ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) -#define __cpm_get_mscdiv() \ - ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) - -#define __cpm_set_cdiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) -#define __cpm_set_hdiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) -#define __cpm_set_pdiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) -#define __cpm_set_mdiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) -#define __cpm_set_ldiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) -#define __cpm_set_udiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) -#define __cpm_set_i2sdiv(v) \ - (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) -#define __cpm_set_pixdiv(v) \ - (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) -#define __cpm_set_mscdiv(v) \ - (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) - -#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) -#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) -#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) -#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) -#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) -#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) -#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) -#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) - -#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) -#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) -#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) - -#define __cpm_get_cclk_doze_duty() \ - ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) -#define __cpm_set_cclk_doze_duty(v) \ - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) - -#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) -#define __cpm_idle_mode() \ - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) -#define __cpm_sleep_mode() \ - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) - -#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff) -#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) -#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) -#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) -#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) -#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) -#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) -#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) -#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) -#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) -#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) -#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) -#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) -#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) -#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) -#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) -#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) - -#define __cpm_start_all() (REG_CPM_CLKGR = 0x0) -#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) -#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) -#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) -#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) -#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) -#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) -#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) -#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) -#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) -#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) -#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) -#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) -#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) -#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) -#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) -#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) - -#define __cpm_get_o1st() \ - ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) -#define __cpm_set_o1st(v) \ - (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) -#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) -#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) - - -#ifdef CFG_EXTAL -#define JZ_EXTAL CFG_EXTAL -#else -#define JZ_EXTAL 3686400 -#endif -#define JZ_EXTAL2 32768 /* RTC clock */ - -/* PLL output frequency */ -static __inline__ unsigned int __cpm_get_pllout(void) -{ - unsigned long m, n, no, pllout; - unsigned long cppcr = REG_CPM_CPPCR; - unsigned long od[4] = {1, 2, 2, 4}; - if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { - m = __cpm_get_pllm() + 2; - n = __cpm_get_plln() + 2; - no = od[__cpm_get_pllod()]; - pllout = ((JZ_EXTAL) / (n * no)) * m; - } else - pllout = JZ_EXTAL; - return pllout; -} - -/* PLL output frequency for MSC/I2S/LCD/USB */ -static __inline__ unsigned int __cpm_get_pllout2(void) -{ - if (REG_CPM_CPCCR & CPM_CPCCR_PCS) - return __cpm_get_pllout(); - else - return __cpm_get_pllout()/2; -} - -/* CPU core clock */ -static __inline__ unsigned int __cpm_get_cclk(void) -{ - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - return __cpm_get_pllout() / div[__cpm_get_cdiv()]; -} - -/* AHB system bus clock */ -static __inline__ unsigned int __cpm_get_hclk(void) -{ - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - return __cpm_get_pllout() / div[__cpm_get_hdiv()]; -} - -/* Memory bus clock */ -static __inline__ unsigned int __cpm_get_mclk(void) -{ - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - return __cpm_get_pllout() / div[__cpm_get_mdiv()]; -} - -/* APB peripheral bus clock */ -static __inline__ unsigned int __cpm_get_pclk(void) -{ - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - return __cpm_get_pllout() / div[__cpm_get_pdiv()]; -} - -/* LCDC module clock */ -static __inline__ unsigned int __cpm_get_lcdclk(void) -{ - return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); -} - -/* LCD pixel clock */ -static __inline__ unsigned int __cpm_get_pixclk(void) -{ - return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); -} - -/* I2S clock */ -static __inline__ unsigned int __cpm_get_i2sclk(void) -{ - if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { - return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); - } - else { - return JZ_EXTAL; - } -} - -/* USB clock */ -static __inline__ unsigned int __cpm_get_usbclk(void) -{ - if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { - return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); - } - else { - return JZ_EXTAL; - } -} - -/* MSC clock */ -static __inline__ unsigned int __cpm_get_mscclk(void) -{ - return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); -} - -/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ -static __inline__ unsigned int __cpm_get_extalclk(void) -{ - return JZ_EXTAL; -} - -/* RTC clock for CPM,INTC,RTC,TCU,WDT */ -static __inline__ unsigned int __cpm_get_rtcclk(void) -{ - return JZ_EXTAL2; -} - -/* - * Output 24MHz for SD and 16MHz for MMC. - */ -static inline void __cpm_select_msc_clk(int sd) -{ - unsigned int pllout2 = __cpm_get_pllout2(); - unsigned int div = 0; - - if (sd) { - div = pllout2 / 24000000; - } - else { - div = pllout2 / 16000000; - } - - REG_CPM_MSCCDR = div - 1; -} - -/*************************************************************************** - * TCU - ***************************************************************************/ -// where 'n' is the TCU channel -#define __tcu_select_extalclk(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) -#define __tcu_select_rtcclk(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) -#define __tcu_select_pclk(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) - -#define __tcu_select_clk_div1(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) -#define __tcu_select_clk_div4(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) -#define __tcu_select_clk_div16(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) -#define __tcu_select_clk_div64(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) -#define __tcu_select_clk_div256(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) -#define __tcu_select_clk_div1024(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) - -#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) -#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) - -#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) -#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) - -#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) -#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) - -#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) -#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) - -#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) -#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) -#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) -#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) -#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) -#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) -#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) -#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) -#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) -#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) - -#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) -#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) - -#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) -#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) - -#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) -#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) - -#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) -#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) -#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) -#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) - - -/*************************************************************************** - * WDT - ***************************************************************************/ -#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) -#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) -#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) -#define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) - -#define __wdt_select_extalclk() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) -#define __wdt_select_rtcclk() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) -#define __wdt_select_pclk() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) - -#define __wdt_select_clk_div1() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) -#define __wdt_select_clk_div4() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) -#define __wdt_select_clk_div16() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) -#define __wdt_select_clk_div64() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) -#define __wdt_select_clk_div256() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) -#define __wdt_select_clk_div1024() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) - - -/*************************************************************************** - * UART - ***************************************************************************/ - -#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) -#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) - -#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) -#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) - -#define __uart_enable_receive_irq() \ - ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) -#define __uart_disable_receive_irq() \ - ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) - -#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) -#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) - -#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) - -#define __uart_set_baud(devclk, baud) \ - do { \ - REG8(UART0_LCR) |= UARTLCR_DLAB; \ - REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ - REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ - REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ - } while (0) - -#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) -#define __uart_clear_errors() \ - ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) - -#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) -#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) -#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) -#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) -#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) -#define __uart_receive_char() REG8(UART0_RDR) -#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) -#define __uart_enable_irda() \ - /* Tx high pulse as 0, Rx low pulse as 0 */ \ - ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) - - -/*************************************************************************** - * DMAC - ***************************************************************************/ - -/* n is the DMA channel (0 - 5) */ - -#define __dmac_enable_module() \ - ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) -#define __dmac_disable_module() \ - ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) - -/* p=0,1,2,3 */ -#define __dmac_set_priority(p) \ -do { \ - REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ - REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ -} while (0) - -#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) -#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) - -#define __dmac_enable_descriptor(n) \ - ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) -#define __dmac_disable_descriptor(n) \ - ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) - -#define __dmac_enable_channel(n) \ - ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) -#define __dmac_disable_channel(n) \ - ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) -#define __dmac_channel_enabled(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) - -#define __dmac_channel_enable_irq(n) \ - ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) -#define __dmac_channel_disable_irq(n) \ - ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) - -#define __dmac_channel_transmit_halt_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) -#define __dmac_channel_transmit_end_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) -#define __dmac_channel_address_error_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) -#define __dmac_channel_count_terminated_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) -#define __dmac_channel_descriptor_invalid_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) - -#define __dmac_channel_clear_transmit_halt(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) -#define __dmac_channel_clear_transmit_end(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) -#define __dmac_channel_clear_address_error(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) -#define __dmac_channel_clear_count_terminated(n) \ - ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) -#define __dmac_channel_clear_descriptor_invalid(n) \ - ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) - -#define __dmac_channel_set_single_mode(n) \ - ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) -#define __dmac_channel_set_block_mode(n) \ - ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) - -#define __dmac_channel_set_transfer_unit_32bit(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_16bit(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_8bit(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_16byte(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_32byte(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ -} while (0) - -/* w=8,16,32 */ -#define __dmac_channel_set_dest_port_width(n,w) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ -} while (0) - -/* w=8,16,32 */ -#define __dmac_channel_set_src_port_width(n,w) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ -} while (0) - -/* v=0-15 */ -#define __dmac_channel_set_rdil(n,v) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ - REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ -} while (0) - -#define __dmac_channel_dest_addr_fixed(n) \ - ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) -#define __dmac_channel_dest_addr_increment(n) \ - ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) - -#define __dmac_channel_src_addr_fixed(n) \ - ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) -#define __dmac_channel_src_addr_increment(n) \ - ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) - -#define __dmac_channel_set_doorbell(n) \ - ( REG_DMAC_DMADBSR = (1 << (n)) ) - -#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) -#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) - -static __inline__ int __dmac_get_irq(void) -{ - int i; - for (i = 0; i < MAX_DMA_NUM; i++) - if (__dmac_channel_irq_detected(i)) - return i; - return -1; -} - - -/*************************************************************************** - * AIC (AC'97 & I2S Controller) - ***************************************************************************/ - -#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) -#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) - -#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) -#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) - -#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) -#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) -#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) - -#define __aic_reset() \ -do { \ - REG_AIC_FR |= AIC_FR_RST; \ -} while(0) - - -#define __aic_set_transmit_trigger(n) \ -do { \ - REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ - REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ -} while(0) - -#define __aic_set_receive_trigger(n) \ -do { \ - REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ - REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ -} while(0) - -#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) -#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) -#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) -#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) -#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) -#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) - -#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) -#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) - -#define __aic_enable_transmit_intr() \ - ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) -#define __aic_disable_transmit_intr() \ - ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) -#define __aic_enable_receive_intr() \ - ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) -#define __aic_disable_receive_intr() \ - ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) - -#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) -#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) -#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) -#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) - -#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) -#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) -#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) -#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) -#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) -#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) - -#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 -#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 -#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 -#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 -#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 -#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 - -#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 -#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 -#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 -#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 -#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 -#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 - -#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) -#define __ac97_set_xs_mono() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ -} while(0) -#define __ac97_set_xs_stereo() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ -} while(0) - -/* In fact, only stereo is support now. */ -#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) -#define __ac97_set_rs_mono() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ -} while(0) -#define __ac97_set_rs_stereo() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ -} while(0) - -#define __ac97_warm_reset_codec() \ - do { \ - REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ - REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ - udelay(2); \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ - } while (0) - -#define __ac97_cold_reset_codec() \ - do { \ - REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ - udelay(2); \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ - } while (0) - -/* n=8,16,18,20 */ -#define __ac97_set_iass(n) \ - ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) -#define __ac97_set_oass(n) \ - ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) - -#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) -#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) - -/* n=8,16,18,20,24 */ -/*#define __i2s_set_sample_size(n) \ - ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ - -#define __i2s_set_oss_sample_size(n) \ - ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) -#define __i2s_set_iss_sample_size(n) \ - ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) - -#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) -#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) - -#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) -#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) -#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) -#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) - -#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) - -#define __aic_get_transmit_resident() \ - ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) -#define __aic_get_receive_count() \ - ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) - -#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) -#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) -#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) -#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) -#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) -#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) -#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) - -#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) - -#define CODEC_READ_CMD (1 << 19) -#define CODEC_WRITE_CMD (0 << 19) -#define CODEC_REG_INDEX_BIT 12 -#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ -#define CODEC_REG_DATA_BIT 4 -#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ - -#define __ac97_out_rcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ -} while (0) - -#define __ac97_out_wcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ -} while (0) - -#define __ac97_out_data(value) \ -do { \ - REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ -} while (0) - -#define __ac97_in_data() \ - ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) - -#define __ac97_in_status_addr() \ - ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) - -#define __i2s_set_sample_rate(i2sclk, sync) \ - ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) - -#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) -#define __aic_read_rfifo() ( REG_AIC_DR ) - -#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) -#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) - -// -// Define next ops for AC97 compatible -// - -#define AC97_ACSR AIC_ACSR - -#define __ac97_enable() __aic_enable(); __aic_select_ac97() -#define __ac97_disable() __aic_disable() -#define __ac97_reset() __aic_reset() - -#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __ac97_enable_record() __aic_enable_record() -#define __ac97_disable_record() __aic_disable_record() -#define __ac97_enable_replay() __aic_enable_replay() -#define __ac97_disable_replay() __aic_disable_replay() -#define __ac97_enable_loopback() __aic_enable_loopback() -#define __ac97_disable_loopback() __aic_disable_loopback() - -#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() -#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() -#define __ac97_enable_receive_dma() __aic_enable_receive_dma() -#define __ac97_disable_receive_dma() __aic_disable_receive_dma() - -#define __ac97_transmit_request() __aic_transmit_request() -#define __ac97_receive_request() __aic_receive_request() -#define __ac97_transmit_underrun() __aic_transmit_underrun() -#define __ac97_receive_overrun() __aic_receive_overrun() - -#define __ac97_clear_errors() __aic_clear_errors() - -#define __ac97_get_transmit_resident() __aic_get_transmit_resident() -#define __ac97_get_receive_count() __aic_get_receive_count() - -#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() -#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() -#define __ac97_enable_receive_intr() __aic_enable_receive_intr() -#define __ac97_disable_receive_intr() __aic_disable_receive_intr() - -#define __ac97_write_tfifo(v) __aic_write_tfifo(v) -#define __ac97_read_rfifo() __aic_read_rfifo() - -// -// Define next ops for I2S compatible -// - -#define I2S_ACSR AIC_I2SSR - -#define __i2s_enable() __aic_enable(); __aic_select_i2s() -#define __i2s_disable() __aic_disable() -#define __i2s_reset() __aic_reset() - -#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __i2s_enable_record() __aic_enable_record() -#define __i2s_disable_record() __aic_disable_record() -#define __i2s_enable_replay() __aic_enable_replay() -#define __i2s_disable_replay() __aic_disable_replay() -#define __i2s_enable_loopback() __aic_enable_loopback() -#define __i2s_disable_loopback() __aic_disable_loopback() - -#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() -#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() -#define __i2s_enable_receive_dma() __aic_enable_receive_dma() -#define __i2s_disable_receive_dma() __aic_disable_receive_dma() - -#define __i2s_transmit_request() __aic_transmit_request() -#define __i2s_receive_request() __aic_receive_request() -#define __i2s_transmit_underrun() __aic_transmit_underrun() -#define __i2s_receive_overrun() __aic_receive_overrun() - -#define __i2s_clear_errors() __aic_clear_errors() - -#define __i2s_get_transmit_resident() __aic_get_transmit_resident() -#define __i2s_get_receive_count() __aic_get_receive_count() - -#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() -#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() -#define __i2s_enable_receive_intr() __aic_enable_receive_intr() -#define __i2s_disable_receive_intr() __aic_disable_receive_intr() - -#define __i2s_write_tfifo(v) __aic_write_tfifo(v) -#define __i2s_read_rfifo() __aic_read_rfifo() - -#define __i2s_reset_codec() \ - do { \ - } while (0) - - -/*************************************************************************** - * ICDC - ***************************************************************************/ -#define __i2s_internal_codec() __aic_internal_codec() -#define __i2s_external_codec() __aic_external_codec() - -/*************************************************************************** - * INTC - ***************************************************************************/ -#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) -#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) -#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) - - -/*************************************************************************** - * I2C - ***************************************************************************/ - -#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) -#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) - -#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) -#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) -#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) -#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) - -#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) -#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) -#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) - -#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) -#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) -#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) - -#define __i2c_set_clk(dev_clk, i2c_clk) \ - ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) - -#define __i2c_read() ( REG_I2C_DR ) -#define __i2c_write(val) ( REG_I2C_DR = (val) ) - - -/*************************************************************************** - * MSC - ***************************************************************************/ - -#define __msc_start_op() \ - ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) - -#define __msc_set_resto(to) ( REG_MSC_RESTO = to ) -#define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) -#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) -#define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) -#define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) -#define __msc_get_nob() ( REG_MSC_NOB ) -#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) -#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) -#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) -#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) - -#define __msc_set_cmdat_bus_width1() \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ - REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ -} while(0) - -#define __msc_set_cmdat_bus_width4() \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ - REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ -} while(0) - -#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) -#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) -#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) -#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) -#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) -#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) -#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) -#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) - -/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ -#define __msc_set_cmdat_res_format(r) \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ - REG_MSC_CMDAT |= (r); \ -} while(0) - -#define __msc_clear_cmdat() \ - REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ - MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ - MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) - -#define __msc_get_imask() ( REG_MSC_IMASK ) -#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) -#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) -#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) -#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) -#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) -#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) -#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) -#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) -#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) -#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) -#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) -#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) - -/* n=0,1,2,3,4,5,6,7 */ -#define __msc_set_clkrt(n) \ -do { \ - REG_MSC_CLKRT = n; \ -} while(0) - -#define __msc_get_ireg() ( REG_MSC_IREG ) -#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) -#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) -#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) -#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) -#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) -#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) -#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) -#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) - -#define __msc_get_stat() ( REG_MSC_STAT ) -#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) -#define __msc_stat_crc_err() \ - ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) -#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) -#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) -#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) -#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) -#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) - -#define __msc_rd_resfifo() ( REG_MSC_RES ) -#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) -#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) - -#define __msc_reset() \ -do { \ - REG_MSC_STRPCL = MSC_STRPCL_RESET; \ - while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ -} while (0) - -#define __msc_start_clk() \ -do { \ - REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ -} while (0) - -#define __msc_stop_clk() \ -do { \ - REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ -} while (0) - -#define MMC_CLK 19169200 -#define SD_CLK 24576000 - -/* msc_clk should little than pclk and little than clk retrieve from card */ -#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ -do { \ - unsigned int rate, pclk, i; \ - pclk = dev_clk; \ - rate = type?SD_CLK:MMC_CLK; \ - if (msc_clk && msc_clk < pclk) \ - pclk = msc_clk; \ - i = 0; \ - while (pclk < rate) \ - { \ - i ++; \ - rate >>= 1; \ - } \ - lv = i; \ -} while(0) - -/* divide rate to little than or equal to 400kHz */ -#define __msc_calc_slow_clk_divisor(type, lv) \ -do { \ - unsigned int rate, i; \ - rate = (type?SD_CLK:MMC_CLK)/1000/400; \ - i = 0; \ - while (rate > 0) \ - { \ - rate >>= 1; \ - i ++; \ - } \ - lv = i; \ -} while(0) - - -/*************************************************************************** - * SSI - ***************************************************************************/ - -#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) -#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) -#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) - -#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) - -#define __ssi_select_ce2() \ -do { \ - REG_SSI_CR0 |= SSI_CR0_FSEL; \ - REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ -} while (0) - -#define __ssi_select_gpc() \ -do { \ - REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ - REG_SSI_CR1 |= SSI_CR1_MULTS; \ -} while (0) - -#define __ssi_enable_tx_intr() \ - ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) - -#define __ssi_disable_tx_intr() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) - -#define __ssi_enable_rx_intr() \ - ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) - -#define __ssi_disable_rx_intr() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) - -#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) -#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) - -#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) -#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) - -#define __ssi_finish_receive() \ - ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) - -#define __ssi_disable_recvfinish() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) - -#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) -#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) - -#define __ssi_flush_fifo() \ - ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) - -#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) - -#define __ssi_spi_format() \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ - REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ - REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ - REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ -} while (0) - -/* TI's SSP format, must clear SSI_CR1.UNFIN */ -#define __ssi_ssp_format() \ -do { \ - REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ - REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ -} while (0) - -/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ -#define __ssi_microwire_format() \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ - REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ - REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ - REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ - REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ -} while (0) - -/* CE# level (FRMHL), CE# in interval time (ITFRM), - clock phase and polarity (PHA POL), - interval time (SSIITR), interval characters/frame (SSIICR) */ - - /* frmhl,endian,mcom,flen,pha,pol MASK */ -#define SSICR1_MISC_MASK \ - ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ - | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ - -#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ -do { \ - REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ - REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ - (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ - ((pha) << 1) | (pol); \ -} while(0) - -/* Transfer with MSB or LSB first */ -#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) -#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) - -#define __ssi_set_frame_length(n) \ - REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) - -/* n = 1 - 16 */ -#define __ssi_set_microwire_command_length(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) - -/* Set the clock phase for SPI */ -#define __ssi_set_spi_clock_phase(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) - -/* Set the clock polarity for SPI */ -#define __ssi_set_spi_clock_polarity(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) - -/* n = ix8 */ -#define __ssi_set_tx_trigger(n) \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ - REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ -} while (0) - -/* n = ix8 */ -#define __ssi_set_rx_trigger(n) \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ - REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ -} while (0) - -#define __ssi_get_txfifo_count() \ - ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) - -#define __ssi_get_rxfifo_count() \ - ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) - -#define __ssi_clear_errors() \ - ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) - -#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) -#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) - -#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) -#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) -#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) - -#define __ssi_set_clk(dev_clk, ssi_clk) \ - ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) - -#define __ssi_receive_data() REG_SSI_DR -#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) - - -/*************************************************************************** - * CIM - ***************************************************************************/ - -#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) -#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) - -#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) -#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) - -#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) -#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) - -#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) -#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) - -#define __cim_sample_data_at_pclk_falling_edge() \ - ( REG_CIM_CFG |= CIM_CFG_PCP ) -#define __cim_sample_data_at_pclk_rising_edge() \ - ( REG_CIM_CFG &= ~CIM_CFG_PCP ) - -#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) -#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) - -#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) -#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) - -/* n=0-7 */ -#define __cim_set_data_packing_mode(n) \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ - REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ -} while (0) - -#define __cim_enable_ccir656_progressive_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ -} while (0) - -#define __cim_enable_ccir656_interlace_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ -} while (0) - -#define __cim_enable_gated_clock_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ -} while (0) - -#define __cim_enable_nongated_clock_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ -} while (0) - -/* sclk:system bus clock - * mclk: CIM master clock - */ -#define __cim_set_master_clk(sclk, mclk) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ - REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ -} while (0) - -#define __cim_enable_sof_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) -#define __cim_disable_sof_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) - -#define __cim_enable_eof_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) -#define __cim_disable_eof_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) - -#define __cim_enable_stop_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) -#define __cim_disable_stop_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) - -#define __cim_enable_trig_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) -#define __cim_disable_trig_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) - -#define __cim_enable_rxfifo_overflow_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) -#define __cim_disable_rxfifo_overflow_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) - -/* n=1-16 */ -#define __cim_set_frame_rate(n) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ - REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ -} while (0) - -#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) -#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) - -#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) -#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) - -/* n=4,8,12,16,20,24,28,32 */ -#define __cim_set_rxfifo_trigger(n) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ - REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ -} while (0) - -#define __cim_clear_state() ( REG_CIM_STATE = 0 ) - -#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) -#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) -#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) -#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) -#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) -#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) -#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) -#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) - -#define __cim_get_iid() ( REG_CIM_IID ) -#define __cim_get_image_data() ( REG_CIM_RXFIFO ) -#define __cim_get_dam_cmd() ( REG_CIM_CMD ) - -#define __cim_set_da(a) ( REG_CIM_DA = (a) ) - -/*************************************************************************** - * LCD - ***************************************************************************/ -#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<> LCD_VSYNC_VPS_BIT ) - -#define __lcd_vsync_get_vpe() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) -#define __lcd_vsync_set_vpe(n) \ -do { \ - REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ - REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ -} while (0) - -#define __lcd_hsync_get_hps() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) -#define __lcd_hsync_set_hps(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ -} while (0) - -#define __lcd_hsync_get_hpe() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) -#define __lcd_hsync_set_hpe(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ -} while (0) - -#define __lcd_vat_get_ht() \ - ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) -#define __lcd_vat_set_ht(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ -} while (0) - -#define __lcd_vat_get_vt() \ - ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) -#define __lcd_vat_set_vt(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ -} while (0) - -#define __lcd_dah_get_hds() \ - ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) -#define __lcd_dah_set_hds(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ -} while (0) - -#define __lcd_dah_get_hde() \ - ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) -#define __lcd_dah_set_hde(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ -} while (0) - -#define __lcd_dav_get_vds() \ - ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) -#define __lcd_dav_set_vds(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ -} while (0) - -#define __lcd_dav_get_vde() \ - ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) -#define __lcd_dav_set_vde(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ -} while (0) - -#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) -#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) -#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) -#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) - -#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) -#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) -#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) -#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) - -#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) -#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) - -#define __lcd_cmd0_get_len() \ - ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) -#define __lcd_cmd1_get_len() \ - ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) - -/*************************************************************************** - * RTC ops - ***************************************************************************/ - -#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) -#define __rtc_enabled() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR |= RTC_RCR_RTCE ; \ -}while(0) \ - -#define __rtc_disabled() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR &= ~RTC_RCR_RTCE; \ -}while(0) -#define __rtc_enable_alarm() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR |= RTC_RCR_AE; \ -}while(0) - -#define __rtc_disable_alarm() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR &= ~RTC_RCR_AE; \ -}while(0) - -#define __rtc_enable_alarm_irq() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR |= RTC_RCR_AIE; \ -}while(0) - -#define __rtc_disable_alarm_irq() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR &= ~RTC_RCR_AIE; \ -}while(0) -#define __rtc_enable_Hz_irq() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR |= RTC_RCR_HZIE; \ -}while(0) - -#define __rtc_disable_Hz_irq() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR &= ~RTC_RCR_HZIE; \ -}while(0) -#define __rtc_get_1Hz_flag() \ -do{ \ - while(!__rtc_write_ready()); \ - ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ -}while(0) -#define __rtc_clear_1Hz_flag() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR &= ~RTC_RCR_HZ; \ -}while(0) -#define __rtc_get_alarm_flag() \ -do{ \ - while(!__rtc_write_ready()); \ - ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \ -while(0) -#define __rtc_clear_alarm_flag() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RCR &= ~RTC_RCR_AF; \ -}while(0) -#define __rtc_get_second() \ -do{ \ - while(!__rtc_write_ready());\ - REG_RTC_RSR; \ -}while(0) - -#define __rtc_set_second(v) \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RSR = v; \ -}while(0) - -#define __rtc_get_alarm_second() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RSAR; \ -}while(0) - - -#define __rtc_set_alarm_second(v) \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RSAR = v; \ -}while(0) - -#define __rtc_RGR_is_locked() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RGR >> RTC_RGR_LOCK; \ -}while(0) -#define __rtc_lock_RGR() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RGR |= RTC_RGR_LOCK; \ -}while(0) - -#define __rtc_unlock_RGR() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_RGR &= ~RTC_RGR_LOCK; \ -}while(0) - -#define __rtc_get_adjc_val() \ -do{ \ - while(!__rtc_write_ready()); \ - ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ -}while(0) -#define __rtc_set_adjc_val(v) \ -do{ \ - while(!__rtc_write_ready()); \ - ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \ -}while(0) - -#define __rtc_get_nc1Hz_val() \ - while(!__rtc_write_ready()); \ - ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) - -#define __rtc_set_nc1Hz_val(v) \ -do{ \ - while(!__rtc_write_ready()); \ - ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \ -}while(0) -#define __rtc_power_down() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_HCR |= RTC_HCR_PD; \ -}while(0) - -#define __rtc_get_hwfcr_val() \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_HWFCR & RTC_HWFCR_MASK; \ -}while(0) -#define __rtc_set_hwfcr_val(v) \ -do{ \ - while(!__rtc_write_ready()); \ - REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ -}while(0) - -#define __rtc_get_hrcr_val() \ -do{ \ - while(!__rtc_write_ready()); \ - ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ -}while(0) -#define __rtc_set_hrcr_val(v) \ -do{ \ - while(!__rtc_write_ready()); \ - ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ -}while(0) - -#define __rtc_enable_alarm_wakeup() \ -do{ \ - while(!__rtc_write_ready()); \ - ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ -}while(0) - -#define __rtc_disable_alarm_wakeup() \ -do{ \ - while(!__rtc_write_ready()); \ - ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ -}while(0) - -#define __rtc_status_hib_reset_occur() \ -do{ \ - while(!__rtc_write_ready()); \ - ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \ -}while(0) -#define __rtc_status_ppr_reset_occur() \ -do{ \ - while(!__rtc_write_ready()); \ - ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \ -}while(0) -#define __rtc_status_wakeup_pin_waken_up() \ -do{ \ - while(!__rtc_write_ready()); \ - ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ -}while(0) -#define __rtc_status_alarm_waken_up() \ -do{ \ - while(!__rtc_write_ready()); \ - ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ -}while(0) -#define __rtc_clear_hib_stat_all() \ -do{ \ - while(!__rtc_write_ready()); \ - ( REG_RTC_HWRSR = 0 ); \ -}while(0) - -#define __rtc_get_scratch_pattern() \ - while(!__rtc_write_ready()); \ - (REG_RTC_HSPR) -#define __rtc_set_scratch_pattern(n) \ -do{ \ - while(!__rtc_write_ready()); \ - (REG_RTC_HSPR = n ); \ -}while(0) - - -#endif /* !__ASSEMBLY__ */ - -#endif /* __JZ4740_H__ */ diff --git a/nandboot/include/jz4740_board.h b/nandboot/include/jz4740_board.h deleted file mode 100644 index c97f787..0000000 --- a/nandboot/include/jz4740_board.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * jz4740_board.h - * - * JZ4740 board definitions. - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * - */ -#ifndef __JZ4740_BOARD_H__ -#define __JZ4740_BOARD_H__ - -/*------------------------------------------------------------------- - * NAND Boot config code - */ -#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 /* NAND Boot config code */ - -/*------------------------------------------------------------------- - * Frequency of the external OSC in Hz. - */ -#define CFG_EXTAL 12000000 - -/*------------------------------------------------------------------- - * CPU speed. - */ -#define CFG_CPU_SPEED 336000000 - -/*------------------------------------------------------------------- - * Serial console. - */ -#define CFG_UART_BASE UART0_BASE - -#define CONFIG_BAUDRATE 57600 - -/*------------------------------------------------------------------- - * SDRAM info. - */ - -// SDRAM paramters -#define CFG_SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ -#define CFG_SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ -#define CFG_SDRAM_ROW 13 /* Row address: 11 to 13 */ -#define CFG_SDRAM_COL 9 /* Column address: 8 to 12 */ -#define CFG_SDRAM_CASL 2 /* CAS latency: 2 or 3 */ - -// SDRAM Timings, unit: ns -#define CFG_SDRAM_TRAS 45 /* RAS# Active Time */ -#define CFG_SDRAM_RCD 20 /* RAS# to CAS# Delay */ -#define CFG_SDRAM_TPC 20 /* RAS# Precharge Time */ -#define CFG_SDRAM_TRWL 7 /* Write Latency Time */ -#define CFG_SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */ - -/*------------------------------------------------------------------- - * Linux kernel command line. - */ -#define CFG_CMDLINE "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw init=/etc/inittab" - -#endif /* __JZ4740_BOARD_H__ */ diff --git a/nandboot/include/nand.h b/nandboot/include/nand.h deleted file mode 100644 index bd0e73f..0000000 --- a/nandboot/include/nand.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * nand.h - * - * Standard NAND Flash definitions. - */ -#ifndef __NAND_H__ -#define __NAND_H__ - -/* - * Standard NAND flash commands - */ -#define NAND_CMD_READ0 0 -#define NAND_CMD_READ1 1 -#define NAND_CMD_RNDOUT 5 -#define NAND_CMD_PAGEPROG 0x10 -#define NAND_CMD_READOOB 0x50 -#define NAND_CMD_ERASE1 0x60 -#define NAND_CMD_STATUS 0x70 -#define NAND_CMD_STATUS_MULTI 0x71 -#define NAND_CMD_SEQIN 0x80 -#define NAND_CMD_RNDIN 0x85 -#define NAND_CMD_READID 0x90 -#define NAND_CMD_ERASE2 0xd0 -#define NAND_CMD_RESET 0xff - -/* Extended commands for large page devices */ -#define NAND_CMD_READSTART 0x30 -#define NAND_CMD_RNDOUTSTART 0xE0 -#define NAND_CMD_CACHEDPROG 0x15 - -/* Status bits */ -#define NAND_STATUS_FAIL 0x01 -#define NAND_STATUS_FAIL_N1 0x02 -#define NAND_STATUS_TRUE_READY 0x20 -#define NAND_STATUS_READY 0x40 -#define NAND_STATUS_WP 0x80 - -/* - * NAND Flash Manufacturer ID Codes - */ -#define NAND_MFR_TOSHIBA 0x98 -#define NAND_MFR_SAMSUNG 0xec -#define NAND_MFR_FUJITSU 0x04 -#define NAND_MFR_NATIONAL 0x8f -#define NAND_MFR_RENESAS 0x07 -#define NAND_MFR_STMICRO 0x20 -#define NAND_MFR_HYNIX 0xad -#define NAND_MFR_MICRON 0x2c - -/* - * NAND parameter struct - */ -struct nand_param { - unsigned int bus_width; /* data bus width: 8-bit/16-bit */ - unsigned int row_cycle; /* row address cycles: 2/3 */ - unsigned int page_size; /* page size in bytes: 512/2048 */ - unsigned int oob_size; /* oob size in bytes: 16/64 */ - unsigned int page_per_block; /* pages per block: 32/64/128 */ - unsigned int bad_block_pos; /* bad block pos in oob: 0/5 */ -}; - -/* - * NAND routines - */ -extern void nand_enable(void); -extern void nand_disable(void); -extern int block_is_bad(struct nand_param *nandp, int block); -extern int nand_read_page(struct nand_param *nandp, int block, int page, unsigned char *dst); - -#endif /* __NAND_H__ */ diff --git a/nandboot/include/types.h b/nandboot/include/types.h deleted file mode 100644 index 1b25ba7..0000000 --- a/nandboot/include/types.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __TYPES_H__ -#define __TYPES_H__ - -#define u32 unsigned int -#define u16 unsigned short -#define u8 unsigned char - -#endif /* __TYPES_H__ */ diff --git a/nandboot/src/Makefile b/nandboot/src/Makefile deleted file mode 100644 index b609188..0000000 --- a/nandboot/src/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# -# Makefile of the n-boot -# -# Copyright (c) 2005-2008 Ingenic Semiconductor Inc. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# - -OBJS := head.o nand_boot.o cpu.o jz_serial.o \ - jz4730.o jz4730_nand.o jz4730_board.o \ - jz4740.o jz4740_nand.o jz4740_board.o - -CROSS := mipsel-openwrt-linux- - -CFLAGS := -O2 -G 0 -mno-abicalls -fno-pic -mips32 -I../include -I../ -AFLAGS = -D__ASSEMBLY__ $(CFLAGS) -LDFLAGS := -T ld.script -nostdlib -EL - -.c.o: - $(CROSS)gcc $(CFLAGS) -c $< -o $@ -.S.o: - $(CROSS)gcc $(AFLAGS) -c $< -o $@ - -n-boot.bin: n-boot - $(CROSS)objdump -D n-boot $< > n-boot.dump - $(CROSS)objcopy -O binary $< $@ - -n-boot: $(OBJS) - $(CROSS)ld $(LDFLAGS) $^ -o $@ - -clean: - rm -fr *.o n-boot n-boot.bin n-boot.dump - diff --git a/nandboot/src/cpu.c b/nandboot/src/cpu.c deleted file mode 100644 index 8df5896..0000000 --- a/nandboot/src/cpu.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * cpu.c - * - * CPU common routines - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * Author: Peter Wei - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ -#include - -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 - /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b - /* 0x1c is unused */ - /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -#define CFG_DCACHE_SIZE 16384 -#define CFG_ICACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 - -#define K0BASE 0x80000000 - -void flush_icache_all(void) -{ - unsigned int addr, t = 0; - - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = K0BASE; addr < K0BASE + CFG_ICACHE_SIZE; - addr += CFG_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Store_Tag_I), "r"(addr)); - } - - /* invalicate btb */ - asm volatile ( - ".set mips32\n\t" - "mfc0 %0, $16, 7\n\t" - "nop\n\t" - "ori %0,2\n\t" - "mtc0 %0, $16, 7\n\t" - ".set mips2\n\t" - : - : "r" (t)); -} - -void flush_dcache_all(void) -{ - unsigned int addr; - - for (addr = K0BASE; addr < K0BASE + CFG_DCACHE_SIZE; - addr += CFG_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Writeback_Inv_D), "r"(addr)); - } - - asm volatile ("sync"); -} - -void flush_cache_all(void) -{ - flush_dcache_all(); - flush_icache_all(); -} diff --git a/nandboot/src/head.S b/nandboot/src/head.S deleted file mode 100644 index b93359a..0000000 --- a/nandboot/src/head.S +++ /dev/null @@ -1,50 +0,0 @@ -/* - * head.S - * - * Entry of n-boot - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * Author: - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ -#include -#ifdef CONFIG_JZ4740 -#include -#include -#endif - - .text - .set noreorder - .global startup -startup: -#ifdef CONFIG_JZ4740 - .word JZ4740_NANDBOOT_CFG /* fetched by CPU during NAND Boot */ -#endif - /* - * Disable all interrupts - */ - la $8, 0xB0001004 /* INTC_IMR */ - li $9, 0xffffffff - sw $9, 0($8) - - /* - * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1 - */ - li $26, 0x0040FC04 - mtc0 $26, $12 /* CP0_STATUS */ - - /* IV=1, use the specical interrupt vector (0x200) */ - li $26, 0x00800000 - mtc0 $26, $13 /* CP0_CAUSE */ - - /* Setup stack pointer */ - la $29, 0x80004000 - - /* Jump to the nand boot routine */ - j nand_boot - nop - .set reorder diff --git a/nandboot/src/jz4730.c b/nandboot/src/jz4730.c deleted file mode 100644 index 671f4e4..0000000 --- a/nandboot/src/jz4730.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * jz4730.c - * - * JZ4730 common routines - * - * Copyright (c) 2005-2007 Ingenic Semiconductor Inc. - * Author: - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include - -#ifdef CONFIG_JZ4730 - -#include -#include - -void pll_init(void) -{ - unsigned int nf, plcr1; - - nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; - plcr1 = ((nf-2) << CPM_PLCR1_PLL1FD_BIT) | - (0 << CPM_PLCR1_PLL1RD_BIT) | /* RD=0, NR=2, 1.8432 = 3.6864/2 */ - (0 << CPM_PLCR1_PLL1OD_BIT) | /* OD=0, NO=1 */ - (0x20 << CPM_PLCR1_PLL1ST_BIT) | /* PLL stable time */ - CPM_PLCR1_PLL1EN; /* enable PLL */ - - /* Clock divisors. - * - * CFCR values: when CPM_CFCR_UCS(bit 28) is set, select external USB clock. - * - * 0x00411110 -> 1:2:2:2:2 - * 0x00422220 -> 1:3:3:3:3 - * 0x00433330 -> 1:4:4:4:4 - * 0x00444440 -> 1:6:6:6:6 - * 0x00455550 -> 1:8:8:8:8 - * 0x00466660 -> 1:12:12:12:12 - */ - REG_CPM_CFCR = 0x00422220 | (((CFG_CPU_SPEED/48000000) - 1) << 25); - - /* PLL out frequency */ - REG_CPM_PLCR1 = plcr1; -} - -#define MEM_CLK (CFG_CPU_SPEED / 3) - -/* - * Init SDRAM memory. - */ -void sdram_init(void) -{ - register unsigned int dmcr0, dmcr, sdmode, tmp, ns; - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - REG_EMC_BCR = 0; /* Disable bus release */ - REG_EMC_RTCSR = 0; /* Disable clock for counting */ - - /* Fault DMCR value for mode register setting*/ -#define SDRAM_ROW0 11 -#define SDRAM_COL0 8 -#define SDRAM_BANK40 0 - - dmcr0 = ((SDRAM_ROW0-11)< 11) - tmp = 11; - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); - tmp = CFG_SDRAM_RCD/ns; - if (tmp > 3) - tmp = 3; - dmcr |= (tmp << EMC_DMCR_RCD_BIT); - tmp = CFG_SDRAM_TPC/ns; - if (tmp > 7) - tmp = 7; - dmcr |= (tmp << EMC_DMCR_TPC_BIT); - tmp = CFG_SDRAM_TRWL/ns; - if (tmp > 3) - tmp = 3; - dmcr |= (tmp << EMC_DMCR_TRWL_BIT); - tmp = (CFG_SDRAM_TRAS + CFG_SDRAM_TPC)/ns; - if (tmp > 14) - tmp = 14; - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); - - /* SDRAM mode value */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((CFG_SDRAM_CASL == 3) ? 1 : 0)]; - if (CFG_SDRAM_BW16) - sdmode <<= 1; - else - sdmode <<= 2; - - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ - REG_EMC_DMCR = dmcr; - REG8(EMC_SDMR0|sdmode) = 0; - REG8(EMC_SDMR1|sdmode) = 0; - - /* Wait for precharge, > 200us */ - tmp = (CFG_CPU_SPEED / 1000000) * 1000; - while (tmp--); - - /* Stage 2. Enable auto-refresh */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; - - tmp = CFG_SDRAM_TREF/ns; - tmp = tmp/64 + 1; - if (tmp > 0xff) tmp = 0xff; - REG_EMC_RTCOR = tmp; - REG_EMC_RTCNT = 0; - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ - - /* Wait for number of auto-refresh cycles */ - tmp = (CFG_CPU_SPEED / 1000000) * 1000; - while (tmp--); - - /* Stage 3. Mode Register Set */ - REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - REG8(EMC_SDMR0|sdmode) = 0; - REG8(EMC_SDMR1|sdmode) = 0; - - /* Set back to the ture basic DMCR value */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - - /* everything is ok now */ -} - -#endif /* CONFIG_JZ4730 */ diff --git a/nandboot/src/jz4730_board.c b/nandboot/src/jz4730_board.c deleted file mode 100644 index 73762fd..0000000 --- a/nandboot/src/jz4730_board.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * board-pmp.c - * - * JZ4730-based PMP board routines. - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * Author: - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include -#include -#include - -#ifdef CONFIG_JZ4730 - -void gpio_init(void) -{ - __harb_usb0_uhc(); - __gpio_as_emc(); - __gpio_as_uart0(); - __gpio_as_uart3(); -} - -#endif /* CONFIG_JZ4730 */ diff --git a/nandboot/src/jz4730_nand.c b/nandboot/src/jz4730_nand.c deleted file mode 100644 index bf6dfba..0000000 --- a/nandboot/src/jz4730_nand.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * jz4730_nand.c - * - * NAND read routine for JZ4730 - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include - -#ifdef CONFIG_JZ4730 - -#include -#include - -/* NAND command/address/data port */ -#define NAND_DATAPORT 0xB4000000 /* read-write area */ -#define NAND_CMDPORT 0xB4040000 /* write only area */ -#define NAND_ADDRPORT 0xB4080000 /* write only area */ - -#define ECC_BLOCK 256 /* 3-bytes HW ECC per 256-bytes data */ -#define ECC_POS 4 /* ECC offset to spare area */ - -#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE | EMC_NFCSR_FCE) -#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFE | EMC_NFCSR_FCE)) -#define __nand_ecc_enable() (REG_EMC_NFCSR |= EMC_NFCSR_ECCE | EMC_NFCSR_ERST) -#define __nand_ecc_disable() (REG_EMC_NFCSR &= ~EMC_NFCSR_ECCE) -#define __nand_ready() (REG_EMC_NFCSR & EMC_NFCSR_RB) -#define __nand_sync() while (!__nand_ready()) -#define __nand_ecc() (REG_EMC_NFECC & 0x00ffffff) -#define __nand_cmd(n) (REG8(NAND_CMDPORT) = (n)) -#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) -#define __nand_data8() REG8(NAND_DATAPORT) -#define __nand_data16() REG16(NAND_DATAPORT) - -/*--------------------------------------------------------------*/ - -static inline void nand_wait_ready(void) -{ - __nand_sync(); -} - -static inline void nand_read_buf16(void *buf, int count) -{ - int i; - u16 *p = (u16 *)buf; - - for (i = 0; i < count; i += 2) - *p++ = __nand_data16(); -} - -static inline void nand_read_buf8(void *buf, int count) -{ - int i; - u8 *p = (u8 *)buf; - - for (i = 0; i < count; i++) - *p++ = __nand_data8(); -} - -static inline void nand_read_buf(void *buf, int count, int bw) -{ - if (bw == 8) - nand_read_buf8(buf, count); - else - nand_read_buf16(buf, count); -} - -/* - * Read oob - */ -static int nand_read_oob(struct nand_param *nandp, int page_addr, u8 *buf, int size) -{ - int page_size, row_cycle, bus_width; - int col_addr; - - page_size = nandp->page_size; - row_cycle = nandp->row_cycle; - bus_width = nandp->bus_width; - - if (page_size == 2048) - col_addr = 2048; - else - col_addr = 0; - - if (page_size == 2048) - /* Send READ0 command */ - __nand_cmd(NAND_CMD_READ0); - else - /* Send READOOB command */ - __nand_cmd(NAND_CMD_READOOB); - - /* Send column address */ - __nand_addr(col_addr & 0xff); - if (page_size == 2048) - __nand_addr((col_addr >> 8) & 0xff); - - /* Send page address */ - __nand_addr(page_addr & 0xff); - __nand_addr((page_addr >> 8) & 0xff); - if (row_cycle == 3) - __nand_addr((page_addr >> 16) & 0xff); - - /* Send READSTART command for 2048 ps NAND */ - if (page_size == 2048) - __nand_cmd(NAND_CMD_READSTART); - - /* Wait for device ready */ - nand_wait_ready(); - - /* Read oob data */ - nand_read_buf(buf, size, bus_width); - - return 0; -} - -/* - * nand_read_page() - * - * Input: - * - * nandp - pointer to nand info - * block - block number: 0, 1, 2, ... - * page - page number within a block: 0, 1, 2, ... - * dst - pointer to target buffer - */ -int nand_read_page(struct nand_param *nandp, int block, int page, u8 *dst) -{ - int page_size, oob_size, page_per_block; - int row_cycle, bus_width, ecc_count; - int page_addr, i, j; - u8 *databuf; - u8 oob_buf[64]; - u32 calc_ecc[8]; - - page_size = nandp->page_size; - oob_size = nandp->oob_size; - page_per_block = nandp->page_per_block; - row_cycle = nandp->row_cycle; - bus_width = nandp->bus_width; - - page_addr = page + block * page_per_block; - - /* - * Read page data - */ - - /* Send READ0 command */ - __nand_cmd(NAND_CMD_READ0); - - /* Send column address */ - __nand_addr(0); - if (page_size == 2048) - __nand_addr(0); - - /* Send page address */ - __nand_addr(page_addr & 0xff); - __nand_addr((page_addr >> 8) & 0xff); - if (row_cycle == 3) - __nand_addr((page_addr >> 16) & 0xff); - - /* Send READSTART command for 2048 ps NAND */ - if (page_size == 2048) - __nand_cmd(NAND_CMD_READSTART); - - /* Wait for device ready */ - nand_wait_ready(); - - /* Read page data */ - databuf = dst; - - ecc_count = page_size / ECC_BLOCK; - - for (i = 0; i < ecc_count; i++) { - - /* Enable HW ECC */ - __nand_ecc_enable(); - - /* Read data */ - nand_read_buf((void *)databuf, ECC_BLOCK, bus_width); - - /* Disable HW ECC */ - __nand_ecc_disable(); - - /* Record the ECC */ - calc_ecc[i] = __nand_ecc(); - - databuf += ECC_BLOCK; - } - - /* - * Read oob data - */ - nand_read_oob(nandp, page_addr, oob_buf, oob_size); - - /* - * ECC correction - * - * Note: the ECC correction algorithm should be conformed to - * the encoding algorithm. It depends on what encoding algorithm - * is used? SW ECC? HW ECC? - */ - - return 0; -} - -/* - * Check bad block - * - * Note: the bad block flag may be store in either the first or the last - * page of the block. - */ -int block_is_bad(struct nand_param *nandp, int block) -{ - int page_addr; - u8 oob_buf[64]; - - page_addr = block * nandp->page_per_block; - nand_read_oob(nandp, page_addr, oob_buf, nandp->oob_size); - if (oob_buf[nandp->bad_block_pos] != 0xff) - return 1; - - page_addr = (block + 1) * nandp->page_per_block - 1; - nand_read_oob(nandp, page_addr, oob_buf, nandp->oob_size); - if (oob_buf[nandp->bad_block_pos] != 0xff) - return 1; - - return 0; -} - -/* - * Enable NAND controller - */ -void nand_enable(void) -{ - __nand_enable(); - - REG_EMC_SMCR3 = 0x04444400; -} - -/* - * Disable NAND controller - */ -void nand_disable(void) -{ - __nand_disable(); -} - -#endif /* CONFIG_JZ4730 */ diff --git a/nandboot/src/jz4740.c b/nandboot/src/jz4740.c deleted file mode 100644 index 7328b8b..0000000 --- a/nandboot/src/jz4740.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * jz4740.c - * - * JZ4740 common routines - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * Author: Peter Wei - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include - -#ifdef CONFIG_JZ4740 - -#include -#include - -/* PLL output clock = EXTAL * NF / (NR * NO) - * - * NF = FD + 2, NR = RD + 2 - * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3) - */ -void pll_init(void) -{ - register unsigned int cfcr, plcr1; - int n2FR[33] = { - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, - 9 - }; - int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:M:L */ - int nf, pllout2; - - cfcr = CPM_CPCCR_CLKOEN | - CPM_CPCCR_PCS | - (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | - (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | - (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | - (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | - (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT); - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); - - /* Init USB Host clock, pllout2 must be n*48MHz */ - REG_CPM_UHCCDR = pllout2 / 48000000 - 1; - - nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - /* init PLL */ - REG_CPM_CPCCR = cfcr; - REG_CPM_CPPCR = plcr1; -} - -/* - * Init SDRAM memory. - */ -void sdram_init(void) -{ - register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - cpu_clk = CFG_CPU_SPEED; - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; - - REG_EMC_BCR = 0; /* Disable bus release */ - REG_EMC_RTCSR = 0; /* Disable clock for counting */ - - /* Fault DMCR value for mode register setting*/ -#define SDRAM_ROW0 11 -#define SDRAM_COL0 8 -#define SDRAM_BANK40 0 - - dmcr0 = ((SDRAM_ROW0-11)< 11) tmp = 11; - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); - tmp = CFG_SDRAM_RCD/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_RCD_BIT); - tmp = CFG_SDRAM_TPC/ns; - if (tmp > 7) tmp = 7; - dmcr |= (tmp << EMC_DMCR_TPC_BIT); - tmp = CFG_SDRAM_TRWL/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_TRWL_BIT); - tmp = (CFG_SDRAM_TRAS + CFG_SDRAM_TPC)/ns; - if (tmp > 14) tmp = 14; - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); - - /* SDRAM mode value */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((CFG_SDRAM_CASL == 3) ? 1 : 0)]; - - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ - REG_EMC_DMCR = dmcr; - REG8(EMC_SDMR0|sdmode) = 0; - - /* Wait for precharge, > 200us */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 2. Enable auto-refresh */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; - - tmp = CFG_SDRAM_TREF/ns; - tmp = tmp/64 + 1; - if (tmp > 0xff) tmp = 0xff; - REG_EMC_RTCOR = tmp; - REG_EMC_RTCNT = 0; - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ - - /* Wait for number of auto-refresh cycles */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 3. Mode Register Set */ - REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - REG8(EMC_SDMR0|sdmode) = 0; - - /* Set back to basic DMCR value */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - - /* everything is ok now */ -} - -#endif /* CONFIG_JZ4740 */ diff --git a/nandboot/src/jz4740_board.c b/nandboot/src/jz4740_board.c deleted file mode 100644 index 7897277..0000000 --- a/nandboot/src/jz4740_board.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * board-pmp.c - * - * JZ4730-based PMP board routines. - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * Author: - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include - -#ifdef CONFIG_JZ4740 - -#include -#include - -void gpio_init(void) -{ - __gpio_as_uart0(); - __gpio_as_sdram_32bit(); -} - -#endif /* CONFIG_JZ4740 */ diff --git a/nandboot/src/jz4740_nand.c b/nandboot/src/jz4740_nand.c deleted file mode 100644 index 838692d..0000000 --- a/nandboot/src/jz4740_nand.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * jz4740_nand.c - * - * NAND read routine for JZ4740 - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include - -#ifdef CONFIG_JZ4740 - -#include -#include - -#define NAND_DATAPORT 0xb8000000 -#define NAND_ADDRPORT 0xb8010000 -#define NAND_COMMPORT 0xb8008000 - -#define ECC_BLOCK 512 -#define ECC_POS 6 -#define PAR_SIZE 9 - -#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n)) -#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) -#define __nand_data8() REG8(NAND_DATAPORT) -#define __nand_data16() REG16(NAND_DATAPORT) - -#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1) -#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1)) -#define __nand_ecc_rs_encoding() \ - (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING) -#define __nand_ecc_rs_decoding() \ - (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING) -#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) -#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF)) -#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF)) - -/*--------------------------------------------------------------*/ - -static inline void nand_wait_ready(void) -{ - unsigned int timeout = 1000; - while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--); - while (!(REG_GPIO_PXPIN(2) & 0x40000000)); -} - -static inline void nand_read_buf16(void *buf, int count) -{ - int i; - u16 *p = (u16 *)buf; - - for (i = 0; i < count; i += 2) - *p++ = __nand_data16(); -} - -static inline void nand_read_buf8(void *buf, int count) -{ - int i; - u8 *p = (u8 *)buf; - - for (i = 0; i < count; i++) - *p++ = __nand_data8(); -} - -static inline void nand_read_buf(void *buf, int count, int bw) -{ - if (bw == 8) - nand_read_buf8(buf, count); - else - nand_read_buf16(buf, count); -} - -/* - * Correct 1~9-bit errors in 512-bytes data - */ -static void rs_correct(unsigned char *dat, int idx, int mask) -{ - int i, j; - unsigned short d, d1, dm; - - i = (idx * 9) >> 3; - j = (idx * 9) & 0x7; - - i = (j == 0) ? (i - 1) : i; - j = (j == 0) ? 7 : (j - 1); - - if (i > 512) return; - - if (i == 512) - d = dat[i - 1]; - else - d = (dat[i] << 8) | dat[i - 1]; - - d1 = (d >> j) & 0x1ff; - d1 ^= mask; - - dm = ~(0x1ff << j); - d = (d & dm) | (d1 << j); - - dat[i - 1] = d & 0xff; - if (i < 512) - dat[i] = (d >> 8) & 0xff; -} - -/* - * Read oob - */ -static int nand_read_oob(struct nand_param *nandp, int page_addr, u8 *buf, int size) -{ - int page_size, row_cycle, bus_width; - int col_addr; - - page_size = nandp->page_size; - row_cycle = nandp->row_cycle; - bus_width = nandp->bus_width; - - if (page_size == 2048) - col_addr = 2048; - else - col_addr = 0; - - if (page_size == 2048) - /* Send READ0 command */ - __nand_cmd(NAND_CMD_READ0); - else - /* Send READOOB command */ - __nand_cmd(NAND_CMD_READOOB); - - /* Send column address */ - __nand_addr(col_addr & 0xff); - if (page_size == 2048) - __nand_addr((col_addr >> 8) & 0xff); - - /* Send page address */ - __nand_addr(page_addr & 0xff); - __nand_addr((page_addr >> 8) & 0xff); - if (row_cycle == 3) - __nand_addr((page_addr >> 16) & 0xff); - - /* Send READSTART command for 2048 ps NAND */ - if (page_size == 2048) - __nand_cmd(NAND_CMD_READSTART); - - /* Wait for device ready */ - nand_wait_ready(); - - /* Read oob data */ - nand_read_buf(buf, size, bus_width); - - return 0; -} - - -/* - * nand_read_page() - * - * Input: - * - * nandp - pointer to nand info - * block - block number: 0, 1, 2, ... - * page - page number within a block: 0, 1, 2, ... - * dst - pointer to target buffer - */ -int nand_read_page(struct nand_param *nandp, int block, int page, u8 *dst) -{ - int page_size, oob_size, page_per_block; - int row_cycle, bus_width, ecc_count; - int page_addr, i, j; - u8 *data_buf; - u8 oob_buf[64]; - - page_size = nandp->page_size; - oob_size = nandp->oob_size; - page_per_block = nandp->page_per_block; - row_cycle = nandp->row_cycle; - bus_width = nandp->bus_width; - - page_addr = page + block * page_per_block; - - /* - * Read oob data - */ - nand_read_oob(nandp, page_addr, oob_buf, oob_size); - - /* - * Read page data - */ - - /* Send READ0 command */ - __nand_cmd(NAND_CMD_READ0); - - /* Send column address */ - __nand_addr(0); - if (page_size == 2048) - __nand_addr(0); - - /* Send page address */ - __nand_addr(page_addr & 0xff); - __nand_addr((page_addr >> 8) & 0xff); - if (row_cycle == 3) - __nand_addr((page_addr >> 16) & 0xff); - - /* Send READSTART command for 2048 ps NAND */ - if (page_size == 2048) - __nand_cmd(NAND_CMD_READSTART); - - /* Wait for device ready */ - nand_wait_ready(); - - /* Read page data */ - data_buf = dst; - - ecc_count = page_size / ECC_BLOCK; - - for (i = 0; i < ecc_count; i++) { - volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0; - unsigned int stat; - - /* Enable RS decoding */ - REG_EMC_NFINTS = 0x0; - __nand_ecc_rs_decoding(); - - /* Read data */ - nand_read_buf((void *)data_buf, ECC_BLOCK, bus_width); - - /* Set PAR values */ - for (j = 0; j < PAR_SIZE; j++) { - *paraddr++ = oob_buf[ECC_POS + i*PAR_SIZE + j]; - } - - /* Set PRDY */ - REG_EMC_NFECR |= EMC_NFECR_PRDY; - - /* Wait for completion */ - __nand_ecc_decode_sync(); - - /* Disable decoding */ - __nand_ecc_disable(); - - /* Check result of decoding */ - stat = REG_EMC_NFINTS; - if (stat & EMC_NFINTS_ERR) { - /* Error occurred */ - if (stat & EMC_NFINTS_UNCOR) { - /* Uncorrectable error occurred */ - } - else { - unsigned int errcnt, index, mask; - - errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT; - switch (errcnt) { - case 4: - index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT; - mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT; - rs_correct(data_buf, index, mask); - case 3: - index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT; - mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT; - rs_correct(data_buf, index, mask); - case 2: - index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT; - mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT; - rs_correct(data_buf, index, mask); - case 1: - index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT; - mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT; - rs_correct(data_buf, index, mask); - break; - default: - break; - } - } - } - - data_buf += ECC_BLOCK; - } - - return 0; -} - -/* - * Check bad block - * - * Note: the bad block flag may be store in either the first or the last - * page of the block. - */ -int block_is_bad(struct nand_param *nandp, int block) -{ - int page_addr; - u8 oob_buf[64]; - - page_addr = block * nandp->page_per_block; - nand_read_oob(nandp, page_addr, oob_buf, nandp->oob_size); - if (oob_buf[nandp->bad_block_pos] != 0xff) - return 1; - - page_addr = (block + 1) * nandp->page_per_block - 1; - nand_read_oob(nandp, page_addr, oob_buf, nandp->oob_size); - if (oob_buf[nandp->bad_block_pos] != 0xff) - return 1; - - return 0; -} - -/* - * Enable NAND controller - */ -void nand_enable(void) -{ - __nand_enable(); - - REG_EMC_SMCR1 = 0x04444400; -} - -/* - * Disable NAND controller - */ -void nand_disable(void) -{ - __nand_disable(); -} - -#endif /* CONFIG_JZ4740 */ diff --git a/nandboot/src/jz_serial.c b/nandboot/src/jz_serial.c deleted file mode 100644 index 9e393dc..0000000 --- a/nandboot/src/jz_serial.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Jz47xx UART support - * - * Options hardcoded to 8N1 - * - * Copyright (c) 2005 - 2008, Ingenic Semiconductor Inc. - * Ingenic Semiconductor, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CONFIG_JZ4730 -#include -#include -#endif -#ifdef CONFIG_JZ4740 -#include -#include -#endif - -#undef UART_BASE -#ifndef CFG_UART_BASE -#define UART_BASE UART0_BASE -#else -#define UART_BASE CFG_UART_BASE -#endif - -/****************************************************************************** -* -* serial_init - initialize a channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -static void serial_setbrg (void) -{ - volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR); - volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR); - volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR); - u32 baud_div, tmp; - - baud_div = CFG_EXTAL / 16 / CONFIG_BAUDRATE; - tmp = *uart_lcr; - tmp |= UART_LCR_DLAB; - *uart_lcr = tmp; - - *uart_dlhr = (baud_div >> 8) & 0xff; - *uart_dllr = baud_div & 0xff; - - tmp &= ~UART_LCR_DLAB; - *uart_lcr = tmp; -} - -int serial_init (void) -{ - volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR); - volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR); - volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER); - volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR); - - /* Disable port interrupts while changing hardware */ - *uart_ier = 0; - - /* Disable UART unit function */ - *uart_fcr = ~UART_FCR_UUE; - - /* Set both receiver and transmitter in UART mode (not SIR) */ - *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE); - - /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ - *uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1; - - /* Set baud rate */ - serial_setbrg(); - - /* Enable UART unit, enable and clear FIFO */ - *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS; - - return 0; -} - -void serial_putc (const char c) -{ - volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR); - volatile u8 *uart_tdr = (volatile u8 *)(UART_BASE + OFF_TDR); - - if (c == '\n') serial_putc ('\r'); - - /* Wait for fifo to shift out some bytes */ - while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) ); - - *uart_tdr = (u8)c; -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/nandboot/src/ld.script b/nandboot/src/ld.script deleted file mode 100644 index ae6b62f..0000000 --- a/nandboot/src/ld.script +++ /dev/null @@ -1,29 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(startup) -MEMORY -{ - ram : ORIGIN = 0x80000000 , LENGTH = 0x100000 -} - -SECTIONS -{ - . = ALIGN(4); - .text : { *(.text*) } > ram - - . = ALIGN(4); - .rodata : { *(.rodata*) } > ram - - . = ALIGN(4); - .sdata : { *(.sdata*) } > ram - - . = ALIGN(4); - .data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram - - _gp = ALIGN(16); - .got : { *(.got*) } > ram - - . = ALIGN(4); - .sbss : { *(.sbss*) } > ram - .bss : { *(.bss*) } > ram - . = ALIGN (4); -} diff --git a/nandboot/src/nand_boot.c b/nandboot/src/nand_boot.c deleted file mode 100644 index bfc82b7..0000000 --- a/nandboot/src/nand_boot.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * nand_boot.c - * - * NAND boot routine. - * - * Then nand boot loader can load the zImage type to execute. - * To get the zImage, build the kernel by 'make zImage'. - * - * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * Author: - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include -#include - -#ifdef CONFIG_JZ4730 -#include -#include -#endif - -#ifdef CONFIG_JZ4740 -#include -#include -#endif - -/* - * NAND Flash parameters (must be conformed to the NAND being used) - */ -static struct nand_param nand_p = { - .bus_width = 8, /* data bus width: 8-bit/16-bit */ - .row_cycle = 3, /* row address cycles: 2/3 */ - .page_size = 2048, /* page size in bytes: 512/2048 */ - .oob_size = 64, /* oob size in bytes: 16/64 */ - .page_per_block = 128, /* pages per block: 32/64/128 */ - .bad_block_pos = 0 /* bad block pos in oob: 0/5 */ -}; - -#define SIZE_KB (1 * 1024) -#define SIZE_MB (1 * 1024 * 1024) - -/* - * Kernel image - */ -#define CFG_KERNEL_OFFS (256 * SIZE_KB) /* NAND offset of kernel image being loaded, has to be aligned to a block address! */ -#define CFG_KERNEL_SIZE (2 * SIZE_MB) /* Size of kernel image, has to be integer multiply of a block size! */ -#define CFG_KERNEL_DST 0x80600000 /* Load kernel to this addr */ -#define CFG_KERNEL_START 0x80600000 /* Start kernel from this addr */ - -/* - * Kernel parameters - */ -#define PARAM_BASE 0x80004000 - -/* - * Local variables - */ -static u32 *param_addr = 0; -static u8 *tmpbuf = 0; - -static u8 cmdline[256] = CFG_CMDLINE; - -extern void gpio_init(void); -extern int serial_init (void); -extern void pll_init(void); -extern void sdram_init(void); - -/* - * Load kernel image from NAND into RAM - */ -static int nand_load(struct nand_param *nandp, int offs, int kernel_size, u8 *dst) -{ - int page_size, page_per_block; - int block; - int block_size; - int blockcopy_count; - int page; - - page_size = nandp->page_size; - page_per_block = nandp->page_per_block; - - /* - * Enable NANDFlash controller - */ - nand_enable(); - - /* - * offs has to be aligned to a block address! - */ - block_size = page_size * page_per_block; - block = offs / block_size; - blockcopy_count = 0; - - while (blockcopy_count < (kernel_size / block_size)) { - for (page = 0; page < page_per_block; page++) { - if (page == 0) { - /* - * New block - */ - if (block_is_bad(nandp, block)) { - block++; - - /* - * Skip bad block - */ - continue; - } - } - - nand_read_page(nandp, block, page, dst); - - dst += page_size; - } - - block++; - blockcopy_count++; - } - - /* - * Disable NANDFlash controller - */ - nand_disable(); - - return 0; -} - -/* - * NAND Boot routine - */ -void nand_boot(void) -{ - unsigned int boot_sel, i; - - void (*kernel)(int, char **, char *); - - /* - * Init gpio, serial, pll and sdram - */ - gpio_init(); - serial_init(); - - serial_puts("\n\nNAND Secondary Program Loader\n\n"); - - pll_init(); - sdram_init(); - -#ifdef CONFIG_JZ4740 - /* - * JZ4740 can detect some NAND parameters from the boot select - */ - boot_sel = REG_EMC_BCR >> 30; - if (boot_sel == 0x2) - nand_p.page_size = 512; - else - nand_p.page_size = 2048; -#endif - -#ifdef CONFIG_JZ4730 - /* - * JZ4730 can detect some NAND parameters from the boot select - */ - boot_sel = (REG_EMC_NFCSR & 0x70) >> 4; - - nand_p.bus_width = (boot_sel & 0x1) ? 16 : 8; - nand_p.page_size = (boot_sel & 0x2) ? 2048 : 512; - nand_p.row_cycle = (boot_sel & 0x4) ? 3 : 2; -#endif - - /* - * Load kernel image from NAND into RAM - */ - nand_load(&nand_p, CFG_KERNEL_OFFS, CFG_KERNEL_SIZE, (u8 *)CFG_KERNEL_DST); - - serial_puts("Starting kernel ...\n\n"); - - /* - * Prepare kernel parameters and environment - */ - param_addr = (u32 *)PARAM_BASE; - param_addr[0] = 0; /* might be address of ascii-z string: "memsize" */ - param_addr[1] = 0; /* might be address of ascii-z string: "0x01000000" */ - param_addr[2] = 0; - param_addr[3] = 0; - param_addr[4] = 0; - param_addr[5] = PARAM_BASE + 32; - param_addr[6] = CFG_KERNEL_START; - tmpbuf = (u8 *)(PARAM_BASE + 32); - - for (i = 0; i < 256; i++) - tmpbuf[i] = cmdline[i]; /* linux command line */ - - kernel = (void (*)(int, char **, char *))CFG_KERNEL_START; - - /* - * Flush caches - */ - flush_cache_all(); - - /* - * Jump to kernel image - */ - (*kernel)(2, (char **)(PARAM_BASE + 16), (char *)PARAM_BASE); -} diff --git a/nandprog/Makefile b/nandprog/Makefile deleted file mode 100644 index e18cce4..0000000 --- a/nandprog/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -# -# Makefile -# - -CROSS = mipsel-linux- -CC = $(CROSS)gcc -LD = $(CROSS)ld - -ROOTFIR = . -JZ4730DIR = $(ROOTFIR)/jz4730 -JZ4740DIR = $(ROOTFIR)/jz4740 -INCDIR = $(ROOTFIR)/include -COMDIR = $(ROOTFIR)/common - -SOURCES += $(wildcard $(JZ4730DIR)/*.c) -SOURCES += $(wildcard $(JZ4740DIR)/*.c) -SOURCES += $(wildcard $(COMDIR)/*.c) -HEADS :=$(wildcard $(INCDIR)/*.h) -OBJS := $(addsuffix .o , $(basename $(notdir $(SOURCES)))) - -CFLAGS := -I$(INCDIR) -O2 -Wall -VPATH := $(JZ4730DIR) $(COMDIR) $(JZ4740DIR) -TARGETS = nandprog - -all: $(TARGETS) - -$(TARGETS) : $(OBJS) $(HEADS) - $(CC) $(CFLAGS) -o $(TARGETS) $(OBJS) - -.c.o: - $(CC) $(CFLAGS) -o $@ -c $< - -install: - -clean: - rm -f *.o $(TARGETS) - diff --git a/nandprog/README b/nandprog/README deleted file mode 100644 index 18321ee..0000000 --- a/nandprog/README +++ /dev/null @@ -1,30 +0,0 @@ -This package contains source of the NAND flash programmer. It is an user -application program running on the Linux kernel. - -To build the software, you need to have a Linux PC and install the -mipsel-linux-gcc compiler first, and then type 'make' under the -Linux command shell: - -$ make - -The dir tree as following: - -|-- Makefile -|-- common -| |-- cmdline.c -| |-- loadcfg.c -| `-- main.c -|-- include -| |-- configs.h -| |-- include.h -| |-- jz4730.h -| |-- jz4740.h -| `-- nand_ecc.h -|-- jz4730 -| `-- nandflash_4730.c -`-- jz4740 - `-- nandflash_4740.c - - -To get more information, please read . -Any questions, contact with me . diff --git a/nandprog/common/cmdline.c b/nandprog/common/cmdline.c deleted file mode 100644 index fd4ca69..0000000 --- a/nandprog/common/cmdline.c +++ /dev/null @@ -1,605 +0,0 @@ -/* - * Command line handling. - * - * This software is free. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include "include.h" -#include "configs.h" -#include "nand_ecc.h" - -#define printf_log(fp,fmt,args...) fprintf(fp,fmt,## args) - -static u8 nand_buf[(2048+64)*128]; //Max 128 pages! -static u8 check_buf[(2048+64)*128]; -static u32 spage, epage, chip_num; -static u8 *filename,ops_t,idx,cs_index,args_num; -static np_data *npdata; -static FILE *log_fp; - -#define USE_VALID_CHECK - -int nand_check_cmp(u8 *buf1,u8 *buf2,u32 len) -{ - u32 i; - - for (i = 0; i < len; i++) - { - if (buf1[i] != buf2[i]) - { - printf("Check error! %x\n",i); - return -1; - } - } - return 0; -} - -void dump_npdata(np_data *np) -{ - int i; - - printf("Process type:%d \n",np->pt); - - printf("NAND interface ps:%d bw:%d rc:%d ppb:%d os:%d bbp:%d bba:%d\n", - np->ps,np->bw,np->rc,np->ppb,np->os,np->bbp,np->bba); - - printf("ECC configration type:%d index:%d\n",np->et,np->ep); - printf("ECC position:"); - for (i = 0;i < oob_64[np->ep].eccbytes;i++) - { - if (i % 9 == 0) printf("\n"); - printf("%d ",oob_64[np->ep].eccpos[i]); - } - -} - -//a check sample for WINCE -//Modify this function according to your system -int check_invalid_block(u8 *buf,np_data *np) -{ - int i,j; - u8 *p = buf + np->ps ,* q ; - - q = buf + (( np->ps + np->os ) * np->ppb - 1) - 10; - - if ( (*q) != 0xff ) - { -// printf("A mark erase block! \n"); - return 0; - } - - for ( i = 0; i < np->ppb; i ++ ) - { - for (j = 0; j < np->os; j ++ ) - { - if ( p[j] != 0xff ) - { - return 1; - } - } - p += np->ps; - } -// printf("A never use block! \n"); - return 0; -} - -int do_read_flash(np_data *np) -{ - FILE *fp; - u32 sp; - int i,j,k; - - if ((fp = fopen((const char *)np->fname, "w+")) == NULL ) - { - printf("Can not open source or object file!\n"); - return -1; - } - i = np->epage - np->spage; - j = i / MAX_BUF_PAGE; - k = i % MAX_BUF_PAGE; - sp = np->spage; - - for (i=0;inand_check_block(sp/np->ppb)) - { - printf_log(log_fp,"Skip a old block at %x!\n",sp/np->ppb); - sp += MAX_BUF_PAGE; - printf("Skip a old block!\n"); - continue; - } - np->nand_read(nand_buf, sp, MAX_BUF_PAGE); -#ifdef USE_VALID_CHECK - if ( check_invalid_block(nand_buf,np) ) - { -#endif - fwrite(nand_buf,1,MAX_BUF_SIZE,fp); - printf("Read block %d finish\n",sp/np->ppb); -#ifdef USE_VALID_CHECK - } - else printf("Skip a invalid block! %d \n",sp/np->ppb); -#endif - sp += MAX_BUF_PAGE; - } - if (k) - { - if (np->nand_check_block(sp/np->ppb)) - { - printf_log(log_fp,"Skip a old block at %x!\n",sp/np->ppb); - printf("Skip a old block!\n"); - } - else - { - np->nand_read(nand_buf, sp, k); -#ifdef USE_VALID_CHECK - if ( check_invalid_block(nand_buf,np) ) - { -#endif - fwrite(nand_buf, 1, k*OOBPAGE_SIZE, fp); -#ifdef USE_VALID_CHECK - } - else printf("Skip a invalid block! %d \n",sp/np->ppb); -#endif - } - } - printf("Read nand flash finish!\n"); - fclose(fp); - return 0; -} - -int do_write_flash(np_data *np) -{ - FILE *fp; - u32 sp,flen,offset; - int i,j,k,r,error_flag=0; - if ((fp = fopen((const char *)np->fname,"r")) == NULL ) - { - printf("Can not open source or object file!\n"); - return -1; - } - fseek(fp,0,SEEK_END); - flen = ftell(fp); - i = flen / OOBPAGE_SIZE; - if (flen % OOBPAGE_SIZE !=0) - { - printf("Source file length is not fit!\n"); - return -1; - } - sp = np->spage; - if (sp % np->ppb !=0) - { - printf("Start page number not blockaligned!\n"); - return -1; - } - //Erase object block first - j = sp / np->ppb; - k = flen/OOBPAGE_SIZE; - if (k % np->ppb == 0) k = k / np->ppb; - else k = k / np->ppb +1; - np->nand_erase(k,j,0); - j = i / MAX_BUF_PAGE; - k = i % MAX_BUF_PAGE; - offset = 0; -// printf("j k %d %d %d %d\n",j,k,i,flen); - - for (i=0;iepage - np->ppb;sp += np->ppb) - { //old bad block - if (!np->nand_check_block(sp/np->ppb)) - break; - printf("Skip a old bad blocks!\n"); - printf_log(log_fp,"Skip a old block at %x!\n",sp/np->ppb); - } - if (sp/np->ppb > np->epage /np->ppb) - { - printf("Program end but not finish,due to bad block!\n"); - printf_log(log_fp,"Program end but not finish,due to bad block!\n"); - return -1; - } - if (np->nand_program(nand_buf,sp,np->ppb)) - { - error_flag = 1; - printf("Program error!\n"); - printf_log(log_fp,"Program error! %x\n",sp/np->ppb); - break; - } - memset(check_buf,0,MAX_BUF_SIZE); - np->nand_read(check_buf,sp,np->ppb); - if (np->nand_check(nand_buf,check_buf, - MAX_BUF_SIZE) ) - { //check error! - error_flag = 1; - printf("Error retry!\n"); - printf_log(log_fp,"Error retry!\n"); - continue; - } - else - { - error_flag = 0; - break; - } - } - if (error_flag) - { //block has broken! - printf("Found a new bad block: %x!\n",sp/np->ppb); - printf_log(log_fp,"Found a new bad block at %x!\n",sp/np->ppb); - np->nand_erase(1,sp/np->ppb,0); //erase before mark bad block! - np->nand_block_markbad(sp /np->ppb); - sp += np->ppb; - goto BLOCK_BROKEN; - } - else - { - printf("Write block %d finish\n",sp/np->ppb); - sp += np->ppb; - offset += MAX_BUF_SIZE; - } - } - if (k) - { - fseek(fp,offset,SEEK_SET); - fread(nand_buf,1,k * OOBPAGE_SIZE ,fp); -BLOCK_BROKEN1: - for (r=0;repage - np->ppb;sp += np->ppb) - { //old bad block - if (!np->nand_check_block(sp/np->ppb)) - break; - printf("Skip a old bad blocks!\n"); - printf_log(log_fp,"Skip a old block at %x!\n",sp/np->ppb); - } - if (sp/np->ppb > np->epage/np->ppb) - { - printf("Program end but not finish,due to bad block!\n"); - printf_log(log_fp,"Program end but not finish,due to bad block!\n"); - return 0; - } - - if (np->nand_program(nand_buf,sp,k)) - { - error_flag = 1; - printf("Program error!\n"); - printf_log(log_fp,"Program error! %x\n",sp/np->ppb); - break; - } - memset(check_buf,0,MAX_BUF_SIZE); - np->nand_read(check_buf,sp,k); - if (np->nand_check(nand_buf,check_buf, - k * OOBPAGE_SIZE) ) - { //check error! - error_flag = 1; - printf("Error retry!\n"); - printf_log(log_fp,"Error retry!\n"); - continue; - } - else - { - error_flag = 0; - break; - } - } - if (error_flag) - { //block has broken! - printf("Found a new bad block : %x!\n",sp/np->ppb); - printf_log(log_fp,"Found a new bad block at %x!\n",sp/np->ppb); - np->nand_erase(1,sp/np->ppb,0); //erase before mark bad block! - np->nand_block_markbad(sp /np->ppb); - sp += np->ppb; - goto BLOCK_BROKEN1; - } - - } - printf("Nand flash write finish!\n"); - return 0; -} - -void show_usage() -{ - printf("Nand flash programmer.Version v1.0\n"); - printf("Usage: nandprog spage epage opration_type obj_file chip_index [config_index]\n\n"); - printf(" spage operation start page number\n"); - printf(" epage operation end page number\n"); - printf(" opration_type operation type read or write\n"); - printf(" obj_file source or object filename\n"); - printf(" chip_index chip select index\n"); - printf(" config_index optional,when chosen,\n"); - printf(" will use one of these default configrations instead of load from CFG\n"); - -} - -int cmdline(int argc, char *argv[], np_data *np) -{ - - if (argc<6 || argc>7) - { - show_usage(); - return -1; - } - - if (strlen(argv[1])>8) - { - printf("Start address page error!\n"); - return -1; - } - spage = atoi(argv[1]); - if (spage > MAX_PAGE) - { - printf("Start address page error!\n"); - return -1; - } - - if (strlen(argv[2])>8) - { - printf("End address page error!\n"); - return -1; - } - epage = atoi(argv[2]); - if (epage > MAX_PAGE) - { - printf("End address page error!\n"); - return -1; - } - - if (strlen(argv[3])>1) - { - printf("Operation type error!\n"); - return -1; - } - if (argv[3][0] == 'r') - ops_t = READ_FLASH; - else if (argv[3][0] == 'w') - ops_t = WRITE_FLASH; - else - { - printf("Operation type error!\n"); - return -1; - } - - if (strlen(argv[4])>20) - { - printf("Source or object file name error!\n"); - return -1; - } - filename = (unsigned char *)argv[4]; - - if (strlen(argv[5])>2) - { - printf("Chip select number error!\n"); - return -1; - } - cs_index = atoi(argv[5]); - - if (epage <= spage) - { - printf("End page number must larger than start page number!\n"); - return -1; - } - - if (argc == 7) - { - args_num = 7; - if (strlen(argv[6])>3) - { - printf("Processor type error!\n"); - return -1; - } - idx = atoi(argv[6]); - if (idx > 20) - { - printf("Processor type error!\n"); - return -1; - } - } - else args_num = 6; - - printf("Deal command line: spage%d epage%d ops%d file:%s cs%d\n", - spage,epage,ops_t,filename,cs_index); - - return 0; -} - -void init_funs(np_data *np) -{ - switch (np->pt) - { - case JZ4740: - np->ebase = 0x13010000; - np->dport = 0x18000000; - np->gport = 0x10010000; - np->bm_ms = 0x100; - np->pm_ms = 0x20000; - np->gm_ms = 0x500; - np->ap_offset = 0x10000; - np->cp_offset = 0x8000; - - np->nand_init = nand_init_4740; - np->nand_erase = nand_erase_4740; - np->nand_program = nand_program_4740; - np->nand_read = nand_read_4740_rs; - np->nand_read_raw = nand_read_raw_4740; - np->nand_read_oob = nand_read_oob_4740; - np->nand_block_markbad = nand_block_markbad_4740; - np->nand_check = nand_check_cmp; - np->nand_check_block = nand_check_block_4740; - if (np->et == HARDRS) - np->nand_read = nand_read_4740_rs; - else - np->nand_read = nand_read_4740_hm; - - break; - case JZ4730: - np->ebase = 0x13010000; - np->dport = 0x14000000; - np->gport = 0x0; - np->bm_ms = 0x100; - np->pm_ms = 0xb0000; - np->gm_ms = 0x0; - np->ap_offset = 0x80000; - np->cp_offset = 0x40000; - - np->nand_init = nand_init_4730; - np->nand_erase = nand_erase_4730; - np->nand_program = nand_program_4730; - np->nand_read = nand_read_4730; - np->nand_read_oob = nand_read_oob_4730; - np->nand_block_markbad = nand_block_markbad; - np->nand_check = nand_check_cmp; - np->nand_check_block = nand_check_block; - np->nand_select = chip_select_4730; - break; - case JZ4760: - break; - } - -// dump_npdata(np); -} - -np_data * cmdinit() -{ - int fd; - if (args_num>6) - { - npdata = &config_list[idx]; - if (npdata) - printf("Load configration index success!\n"); - else - { - printf("Load configration index fail!\n"); - return 0; - } - } - else - { - npdata = load_cfg(); - if (npdata) - printf("Load configration file success!\n"); - else - { - printf("Load configration file fail!\n"); - return 0; - } - } - if (!npdata) return 0; - - init_funs(npdata); - npdata->spage = spage; - npdata->epage = epage; - npdata->fname = filename; - npdata->ops = ops_t; - npdata->cs = cs_index; - - if((fd=open("/dev/mem",O_RDWR|O_SYNC))==-1) - { - printf("Can not open memory file!\n"); - return 0; - } - - npdata->base_map = mmap(NULL,npdata->bm_ms,PROT_READ | PROT_WRITE,MAP_SHARED,fd,npdata->ebase); - if(npdata->base_map == MAP_FAILED) - { - printf("Can not map EMC_BASE ioport!\n"); - return 0; - } - else printf("Map EMC_BASE success :%x\n",(u32)npdata->base_map); - - npdata->port_map=mmap(NULL,npdata->pm_ms ,PROT_READ | PROT_WRITE,MAP_SHARED,fd,npdata->dport); - if(npdata->port_map== MAP_FAILED) - { - printf("Can not map NAND_PORT ioport!\n"); - return 0; - } - else printf("Map NAND_PORT success :%x\n",(u32)npdata->port_map); - - if (npdata->pt == JZ4740) - { - npdata->gpio_map=mmap(NULL,npdata->gm_ms ,PROT_READ | PROT_WRITE,MAP_SHARED,fd,npdata->gport); - if(npdata->gpio_map== MAP_FAILED) - { - printf("Can not map GPIO ioport!\n"); - return 0; - } - else printf("Map GPIO_PORT success :%x\n",(u32)npdata->gpio_map); - } - - close(fd); - - printf("Memory map all success!\n"); - npdata->nand_init(npdata); - - return npdata; -} - -int cmdexcute(np_data *np) -{ - int ret; - - if ((log_fp=fopen(NUM_FILENAME,"a+"))==NULL ) - { - printf("Can not open number file!\n"); - return -1; - } - fscanf(log_fp,"%d",&chip_num); - fclose(log_fp); - chip_num++; - if ((log_fp=fopen(NUM_FILENAME,"w"))==NULL ) - { - printf("Can not open number file!\n"); - return -1; - } - printf_log(log_fp,"%d",chip_num); - fclose(log_fp); - - if ((log_fp=fopen(LOG_FILENAME,"a+"))==NULL ) - { - printf("Can not open log file!\n"); - return -1; - } - printf_log(log_fp,"\nNo.%d :\n",chip_num); - - if (np->ops == READ_FLASH) - { - printf_log(log_fp,"Read nand flash!\n"); - printf_log(log_fp,"Args:index=%d spage=%d epage=%d file=%s cs=%d\n", - idx,spage,epage,filename,cs_index); - ret= do_read_flash(np); - } - else - { - printf_log(log_fp,"Write nand flash!\n"); - printf_log(log_fp,"Args:index=%d spage=%d epage=%d file=%s cs=%d\n", - idx,spage,epage,filename,cs_index); - ret= do_write_flash(np); - } - - if (!ret) - printf_log(log_fp,"Operation success!\n"); - else - printf_log(log_fp,"Operation fail!\n"); - - fclose(log_fp); - return 0; -} - -int cmdexit(np_data *np) -{ - munmap(np->base_map,np->bm_ms); - munmap(np->port_map,np->pm_ms); - if (np->pt == JZ4740) - munmap(np->gpio_map,np->gm_ms); - return 0; -} diff --git a/nandprog/common/loadcfg.c b/nandprog/common/loadcfg.c deleted file mode 100644 index 08ac188..0000000 --- a/nandprog/common/loadcfg.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Configfile parsing. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include "include.h" - -#define CFG_FIELD_NUM 10 - -static np_data np; - -extern struct nand_oobinfo oob_64[]; - -const char CFG_FIELD[][30]= -{ - "CPUTYPE", - "BUSWIDTH", - "ROWCYCLES", - "PAGESIZE", - "PAGEPERBLOCK", - "OOBSIZE", - "BADBLOCKPOS", - "BADBLOCKPAGE", - "ECCTYPE", - "[END]", -}; - -np_data * load_cfg(void) -{ - FILE *fp; - char line[100]; - unsigned short i,j; - unsigned int d; - - if ((fp = fopen("nandprog.cfg", "r"))==NULL) - { - printf("Can not open configration file!\n"); - return 0; - } - - while(!strstr(line, "[NANDPROG]")) //find the nandprog section! - { - if (feof(fp)) - { - printf("nand programmer configration file illege!\n"); - return 0; - } - fscanf(fp,"%s",line); - } - - while(1) - { - if (feof(fp)) - { - printf("nand programmer configration file illege!\n"); - return 0; - } - fscanf(fp,"%s",line); - if (line[0]==';') - { - line[0]='\0'; - continue; - } - - for (i=0;i2048) continue; - np.bbp = d; - break; - } - break; - case 7: //BADBLOCKPAGE - while (!feof(fp)) - { - fscanf(fp,"%d",&d); - if (d>np.ppb) continue; - np.bba = d; - break; - } - - break; - case 8: //ECCTYPE - while (!feof(fp)) - { - fscanf(fp,"%s",line); - if (strstr(line,"RS")) - { - np.et = HARDRS; - d = 36; //36 bytes ecc - oob_64[4].eccbytes = 36; - np.ep = 4; - break; - } - else if (strstr(line,"HM")) - { - np.et = HARDHM; - d = 24; //24 bytes ecc - oob_64[4].eccbytes = 24; - np.ep = 4; - break; - } - else continue; - } - while (!feof(fp)) - { - fscanf(fp,"%s",line); - if (strstr(line,"{")) break; - } - for (j = 0;j < d;j++) - { - if (feof(fp)) - { - printf("nand programmer configration file illege!\n"); - return 0; - } - fscanf(fp,"%d",&d); - if (d > np.os) - { - printf("nand programmer configration file illege!\n"); - return 0; - } - oob_64[4].eccpos[j] = d; - } - - while (!feof(fp)) - { - fscanf(fp,"%s",line); - if (strstr(line,"}")) break; - } - break; - case 9: - return &np; - default: - ; - } - - } -} diff --git a/nandprog/common/main.c b/nandprog/common/main.c deleted file mode 100644 index 4b86d52..0000000 --- a/nandprog/common/main.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Main entry of the program. - */ -#include -#include -#include -#include -#include - -#include "include.h" - -static np_data *npdata; - -int main(int argc, char *argv[]) -{ - if (cmdline(argc, argv, npdata)) return 0; - npdata=cmdinit(); - if (!npdata) return 0; - if (cmdexcute(npdata)) return 0; - if (cmdexit(npdata)) return 0; - - return 0; -} diff --git a/nandprog/include/configs.h b/nandprog/include/configs.h deleted file mode 100644 index aa99385..0000000 --- a/nandprog/include/configs.h +++ /dev/null @@ -1,406 +0,0 @@ -#ifndef __CONFIGS_H__ -#define __CONFIGS_H__ - -#include "include.h" - -np_data config_list[]= -{ - { - //No 0 - //The config for jz4730 uboot - .pt = JZ4730, - .et = HARDHM, //HW HM ECC - .ep = 0, //ecc position index 0 - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 64, - .rc = 3, - .bbp = 0, - .bba = 0, - - .ebase = 0x13010000, - .dport = 0x14000000, - .gport = 0, - .bm_ms = 0x100, - .pm_ms = 0xb0000, - .gm_ms = 0, - .ap_offset = 0x80000, - .cp_offset = 0x40000, - - .nand_init = nand_init_4730, - .nand_erase = nand_erase_4730, - .nand_program = nand_program_4730, - .nand_read = nand_read_4730, - .nand_read_oob = nand_read_oob_4730, - .nand_block_markbad = nand_block_markbad, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block, - .nand_select = chip_select_4730, - }, - - { - //No 1 - //The config for jz4730 linux fs - - .pt = JZ4730, - .et = HARDHM, //HW HM ECC - .ep = 1, //ecc position index 1 - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 64, - .rc = 3, - .bbp = 0, - .bba = 0, - - .ebase = 0x13010000, - .dport = 0x14000000, - .gport = 0, - .bm_ms = 0x100, - .pm_ms = 0xb0000, - .gm_ms = 0, - .ap_offset = 0x80000, - .cp_offset = 0x40000, - - .nand_init = nand_init_4730, - .nand_erase = nand_erase_4730, - .nand_program = nand_program_4730, - .nand_read = nand_read_4730, - .nand_read_oob = nand_read_oob_4730, - .nand_block_markbad = nand_block_markbad, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block, - .nand_select = chip_select_4730, - - }, - - { - //No 2 - //The config for jz4730 ucos - .pt = JZ4730, - .et = HARDHM, //HW HM ECC - .ep = 1, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 64, - .rc = 3, - .bbp = 0, //need modify - .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x14000000, - .gport = 0, - .bm_ms = 0x100, - .pm_ms = 0xb0000, - .gm_ms = 0, - .ap_offset = 0x80000, - .cp_offset = 0x40000, - - .nand_init = nand_init_4730, - .nand_erase = nand_erase_4730, - .nand_program = nand_program_4730, - .nand_read = nand_read_4730, - .nand_read_oob = nand_read_oob_4730, - .nand_block_markbad = nand_block_markbad, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block, - .nand_select = chip_select_4730, - - }, - { - //No 3 - //The config for jz4730 wince - .pt = JZ4730, - .et = HARDHM, //HW HM ECC - .ep = 1, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 64, - .rc = 3, - .bbp = 0, //need modify - .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x14000000, - .gport = 0, - .bm_ms = 0x100, - .pm_ms = 0xb0000, - .gm_ms = 0, - .ap_offset = 0x80000, - .cp_offset = 0x40000, - - .nand_init = nand_init_4730, - .nand_erase = nand_erase_4730, - .nand_program = nand_program_4730, - .nand_read = nand_read_4730, - .nand_read_oob = nand_read_oob_4730, - .nand_block_markbad = nand_block_markbad, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block, - .nand_select = chip_select_4730, - - }, - - { - //No 4 - //The config for jz4740 uboot use HW RS - .pt = JZ4740, - .et = HARDRS, //HW HM ECC - .ep = 2, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 128, - .rc = 3, - .bbp = 0, //need modify - .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x18000000, - .gport = 0x10010000, - .bm_ms = 0x100, - .pm_ms = 0x20000, - .gm_ms = 0x500, - .ap_offset = 0x10000, - .cp_offset = 0x8000, - - .nand_init = nand_init_4740, - .nand_erase = nand_erase_4740, - .nand_program = nand_program_4740, - .nand_read = nand_read_4740_rs, - .nand_read_oob = nand_read_oob_4740, - .nand_block_markbad = nand_block_markbad_4740, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block_4740, - .nand_select = chip_select_4740, - - }, - - { - //No 5 - //The config for jz4740 linux use HW RS - .pt = JZ4740, - .et = HARDRS, //HW HM ECC - .ep = 3, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 128, - .rc = 3, - .bbp = 1, //need modify - .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x18000000, - .gport = 0x10010000, - .bm_ms = 0x100, - .pm_ms = 0x20000, - .gm_ms = 0x500, - .ap_offset = 0x10000, - .cp_offset = 0x8000, - - .nand_init = nand_init_4740, - .nand_fini = nand_fini_4740, - .nand_erase = nand_erase_4740, - .nand_program = nand_program_4740, - .nand_read = nand_read_4740_rs, - .nand_read_oob = nand_read_oob_4740, - .nand_block_markbad = nand_block_markbad_4740, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block_4740, - .nand_select = chip_select_4740, - - }, - - { - //No 6 - //The config for jz4740 linux use HW HM - .pt = JZ4740, - .et = HARDHM, //HW HM ECC - .ep = 1, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 128, - .rc = 3, - .bbp = 0, //need modify - .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x18000000, - .gport = 0x10010000, - .bm_ms = 0x100, - .pm_ms = 0x20000, - .gm_ms = 0x500, - .ap_offset = 0x10000, - .cp_offset = 0x8000, - - .nand_init = nand_init_4740, - .nand_erase = nand_erase_4740, - .nand_program = nand_program_4740, - .nand_read = nand_read_4740_hm, - .nand_read_oob = nand_read_oob_4740, - .nand_block_markbad = nand_block_markbad_4740, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block_4740, - .nand_select = chip_select_4740, - - }, - - { - //No 7 - //The config for jz4740 ucos use HW RS - .pt = JZ4740, - .et = HARDRS, //HW HM ECC -// .ep = 3, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 128, - .rc = 3, -// .bbp = 0, //need modify -// .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x18000000, - .gport = 0x10010000, - .bm_ms = 0x100, - .pm_ms = 0x20000, - .gm_ms = 0x500, - .ap_offset = 0x10000, - .cp_offset = 0x8000, - - .nand_init = nand_init_4740, - .nand_erase = nand_erase_4740, - .nand_program = nand_program_4740, - .nand_read = nand_read_4740_rs, - .nand_read_oob = nand_read_oob_4740, - .nand_block_markbad = nand_block_markbad_4740, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block_4740, - .nand_select = chip_select_4740, - - }, - - { - //No 8 - //The config for jz4740 ucos use HW HM - .pt = JZ4740, - .et = HARDHM, //HW HM ECC -// .ep = 3, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 128, - .rc = 3, -// .bbp = 0, //need modify -// .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x18000000, - .gport = 0x10010000, - .bm_ms = 0x100, - .pm_ms = 0x20000, - .gm_ms = 0x500, - .ap_offset = 0x10000, - .cp_offset = 0x8000, - - .nand_init = nand_init_4740, - .nand_erase = nand_erase_4740, - .nand_program = nand_program_4740, - .nand_read = nand_read_4740_hm, - .nand_read_oob = nand_read_oob_4740, - .nand_block_markbad = nand_block_markbad_4740, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block_4740, - .nand_select = chip_select_4740, - - }, - - { - //No 9 - //The config for jz4740 wince use HW RS - .pt = JZ4740, - .et = HARDRS, //HW HM ECC -// .ep = 3, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 128, - .rc = 3, -// .bbp = 0, //need modify -// .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x18000000, - .gport = 0x10010000, - .bm_ms = 0x100, - .pm_ms = 0x20000, - .gm_ms = 0x500, - .ap_offset = 0x10000, - .cp_offset = 0x8000, - - .nand_init = nand_init_4740, - .nand_erase = nand_erase_4740, - .nand_program = nand_program_4740, - .nand_read = nand_read_4740_rs, - .nand_read_oob = nand_read_oob_4740, - .nand_block_markbad = nand_block_markbad_4740, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block_4740, - .nand_select = chip_select_4740, - - }, - - { - //No 10 - //The config for jz4740 wince use HW RS - .pt = JZ4740, - .et = HARDHM, //HW HM ECC -// .ep = 3, //need modify - .bw = 8, - .ps = 2048, - .os = 64, - .ppb = 128, - .rc = 3, -// .bbp = 0, //need modify -// .bba = 0, //need modify - - //do not need modify - .ebase = 0x13010000, - .dport = 0x18000000, - .gport = 0x10010000, - .bm_ms = 0x100, - .pm_ms = 0x20000, - .gm_ms = 0x500, - .ap_offset = 0x10000, - .cp_offset = 0x8000, - - .nand_init = nand_init_4740, - .nand_erase = nand_erase_4740, - .nand_program = nand_program_4740, - .nand_read = nand_read_4740_hm, - .nand_read_oob = nand_read_oob_4740, - .nand_block_markbad = nand_block_markbad_4740, - .nand_check = nand_check_cmp, - .nand_check_block = nand_check_block_4740, - .nand_select = chip_select_4740, - - }, - - -}; - - -#endif diff --git a/nandprog/include/include.h b/nandprog/include/include.h deleted file mode 100644 index cbf65d2..0000000 --- a/nandprog/include/include.h +++ /dev/null @@ -1,140 +0,0 @@ -#ifndef __INCLUDE_H__ -#define __INCLUDE_H__ -//#include "nand_ecc.h" - -#define u32 unsigned int -#define u16 unsigned short -#define u8 unsigned char -#define MAX_PAGE 0xffffffff -#define PAGE_SIZE np->ps -#define OOB_SIZE np->os -#define OOBPAGE_SIZE (PAGE_SIZE + OOB_SIZE) -#define MAX_BUF_PAGE np->ppb -#define MAX_BUF_SIZE OOBPAGE_SIZE*MAX_BUF_PAGE -#define MAX_RETRY 3 -#define LAST_PAGE 65536 -#define LOG_FILENAME "nprog.log" -#define NUM_FILENAME "number.log" - -enum -{ - JZ4730CPU, - LINUXHM, - JZ4740CPU, - LINUXRS, - USERSPEC, -}; - -struct nand_oobinfo -{ - int eccname; - unsigned int eccbytes; - unsigned int eccpos[64]; -}; - -enum -{ - SOFTHM, - SOFTRS, - HARDHM, - HARDRS -}; - -enum -{ - JZ4730, - JZ4740, - JZ4760 -}; - -enum -{ - READ_FLASH, - WRITE_FLASH -}; - -typedef struct _NP_DATA -{ - u8 pt; //processor type jz4730/jz4740/jz4760.... - u8 et; //ECC type software HM/RS or hardware HM/RS - u8 ep; //ECC position index - u8 ops; //opration type read/write - u8 cs; //chip select index number - u8 *fname; //Source or object file name - u32 spage; //opration start page number of nand flash - u32 epage; //opration end page number of nand flash - - u32 bw; //nand flash bus width - u32 ps; //nand flash page size - u32 os; //nand flash oob size - u32 ppb; //nand flash page per block - u32 rc; //nand flash row syscle - u32 bbp; //nand flash bad block ID position - u32 bba; //nand flash bad block ID page position - - u32 ebase; //EMC base PHY address - void *base_map; //EMC base mapped address - u32 bm_ms; // EMC base mapped size - - u32 dport; //Nand flash port base PHY address - void *port_map; //nand port mapped address - u32 pm_ms; // EMC base mapped size - - u32 gport; //GPIO base PHY address - void *gpio_map; //GPIO mapped address - u32 gm_ms; // EMC base mapped size - - u32 ap_offset; //addrport offset - u32 cp_offset; //cmdportoffset - - int (*nand_init)(struct _NP_DATA *); - int (*nand_fini)(void); - u32 (*nand_query)(void); - int (*nand_erase)(int, int, int); - int (*nand_program)(u8 *, int, int ); - int (*nand_read)(u8 *, u32, u32); - int (*nand_read_raw)(u8 *, u32, u32); - int (*nand_read_oob)(u8 *, u32, u32); - int (*nand_check_block) (u32); - int (*nand_check) (u8 *,u8 *,u32 ); - void (*nand_block_markbad) (u32); - int (*nand_select) (u8); - -}np_data; - -//jz4730 functions -extern int nand_init_4730(np_data *); -extern int nand_fini_4730(void); -extern unsigned int nand_query_4730(void); -extern int nand_erase_4730(int blk_num, int sblk, int force); -extern int nand_program_4730(u8 *buf, int startpage, int pagenum); -extern int nand_read_4730(u8 *buf, u32 startpage, u32 pagenum); -extern int nand_read_raw_4730(u8 *buf, u32 startpage, u32 pagenum); -extern int nand_read_oob_4730(u8 *buf, u32 startpage, u32 pagenum); -extern int nand_check_block(u32); -extern void nand_block_markbad(u32); -extern int chip_select_4730(u8 cs); - -//jz4740 functions -extern int nand_init_4740(np_data *); -extern int nand_fini_4740(void); -extern unsigned int nand_query_4740(void); -extern int nand_erase_4740(int blk_num, int sblk, int force); -extern int nand_program_4740(u8 *buf, int startpage, int pagenum); -extern int nand_read_4740_hm(u8 *buf, u32 startpage, u32 pagenum); -extern int nand_read_4740_rs(u8 *buf, u32 startpage, u32 pagenum); -extern int nand_read_raw_4740(u8 *buf, u32 startpage, u32 pagenum); -extern int nand_read_oob_4740(u8 *buf, u32 startpage, u32 pagenum); -extern int nand_check_block_4740(u32); -extern void nand_block_markbad_4740(u32); -extern int chip_select_4740(u8 cs); - -//common functions -extern int cmdline(int,char **,np_data *); -extern np_data * cmdinit(); -extern int cmdexcute(np_data *); -extern int cmdexit(np_data *); -extern int nand_check_cmp(u8 *buf1,u8 *buf2,u32 len); -extern np_data * load_cfg(); - -#endif diff --git a/nandprog/include/jz4730.h b/nandprog/include/jz4730.h deleted file mode 100644 index ae7ea97..0000000 --- a/nandprog/include/jz4730.h +++ /dev/null @@ -1,5113 +0,0 @@ -/* - * jz4730.h - * - * Registers definition of the JZ4730 CPU. - * - * Copyright (c) 2005-2007 Ingenic Semiconductor Inc. - * - * This program is free software. - */ -#ifndef __JZ4730_H__ -#define __JZ4730_H__ - -#ifndef __ASSEMBLY__ - -#define u32 unsigned int -#define u16 unsigned short -#define u8 unsigned char - -#define REG8(addr) *((volatile u8 *)(addr)) -#define REG16(addr) *((volatile u16 *)(addr)) -#define REG32(addr) *((volatile u32 *)(addr)) - -#else - -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) - -#endif /* !ASSEMBLY */ - -#define HARB_BASE 0xB3000000 -//#define EMC_BASE 0xB3010000 -#define DMAC_BASE 0xB3020000 -#define UHC_BASE 0xB3030000 -#define UDC_BASE 0xB3040000 -#define LCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define ETH_BASE 0xB3100000 -#define NBM_BASE 0xB3F00000 - -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define OST_BASE 0xB0002000 -#define RTC_BASE 0xB0003000 -#define WDT_BASE 0xB0004000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define MSC_BASE 0xB0021000 -#define UART0_BASE 0xB0030000 -#define UART1_BASE 0xB0031000 -#define UART2_BASE 0xB0032000 -#define UART3_BASE 0xB0033000 -#define FIR_BASE 0xB0040000 -#define SCC_BASE 0xB0041000 -#define SCC0_BASE 0xB0041000 -#define I2C_BASE 0xB0042000 -#define SSI_BASE 0xB0043000 -#define SCC1_BASE 0xB0044000 -#define PWM0_BASE 0xB0050000 -#define PWM1_BASE 0xB0051000 -#define DES_BASE 0xB0060000 -#define UPRT_BASE 0xB0061000 -#define KBC_BASE 0xB0062000 - - - - -/************************************************************************* - * MSC - *************************************************************************/ -#define MSC_STRPCL (MSC_BASE + 0x000) -#define MSC_STAT (MSC_BASE + 0x004) -#define MSC_CLKRT (MSC_BASE + 0x008) -#define MSC_CMDAT (MSC_BASE + 0x00C) -#define MSC_RESTO (MSC_BASE + 0x010) -#define MSC_RDTO (MSC_BASE + 0x014) -#define MSC_BLKLEN (MSC_BASE + 0x018) -#define MSC_NOB (MSC_BASE + 0x01C) -#define MSC_SNOB (MSC_BASE + 0x020) -#define MSC_IMASK (MSC_BASE + 0x024) -#define MSC_IREG (MSC_BASE + 0x028) -#define MSC_CMD (MSC_BASE + 0x02C) -#define MSC_ARG (MSC_BASE + 0x030) -#define MSC_RES (MSC_BASE + 0x034) -#define MSC_RXFIFO (MSC_BASE + 0x038) -#define MSC_TXFIFO (MSC_BASE + 0x03C) - -#define REG_MSC_STRPCL REG16(MSC_STRPCL) -#define REG_MSC_STAT REG32(MSC_STAT) -#define REG_MSC_CLKRT REG16(MSC_CLKRT) -#define REG_MSC_CMDAT REG32(MSC_CMDAT) -#define REG_MSC_RESTO REG16(MSC_RESTO) -#define REG_MSC_RDTO REG16(MSC_RDTO) -#define REG_MSC_BLKLEN REG16(MSC_BLKLEN) -#define REG_MSC_NOB REG16(MSC_NOB) -#define REG_MSC_SNOB REG16(MSC_SNOB) -#define REG_MSC_IMASK REG16(MSC_IMASK) -#define REG_MSC_IREG REG16(MSC_IREG) -#define REG_MSC_CMD REG8(MSC_CMD) -#define REG_MSC_ARG REG32(MSC_ARG) -#define REG_MSC_RES REG16(MSC_RES) -#define REG_MSC_RXFIFO REG32(MSC_RXFIFO) -#define REG_MSC_TXFIFO REG32(MSC_TXFIFO) - -/* MSC Clock and Control Register (MSC_STRPCL) */ - -#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) -#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) -#define MSC_STRPCL_START_READWAIT (1 << 5) -#define MSC_STRPCL_STOP_READWAIT (1 << 4) -#define MSC_STRPCL_RESET (1 << 3) -#define MSC_STRPCL_START_OP (1 << 2) -#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 -#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) - #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ - #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ - -/* MSC Status Register (MSC_STAT) */ - -#define MSC_STAT_IS_RESETTING (1 << 15) -#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) -#define MSC_STAT_PRG_DONE (1 << 13) -#define MSC_STAT_DATA_TRAN_DONE (1 << 12) -#define MSC_STAT_END_CMD_RES (1 << 11) -#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) -#define MSC_STAT_IS_READWAIT (1 << 9) -#define MSC_STAT_CLK_EN (1 << 8) -#define MSC_STAT_DATA_FIFO_FULL (1 << 7) -#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) -#define MSC_STAT_CRC_RES_ERR (1 << 5) -#define MSC_STAT_CRC_READ_ERROR (1 << 4) -#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 -#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) - #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR_YES (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ -#define MSC_STAT_TIME_OUT_RES (1 << 1) -#define MSC_STAT_TIME_OUT_READ (1 << 0) - -/* MSC Bus Clock Control Register (MSC_CLKRT) */ - -#define MSC_CLKRT_CLK_RATE_BIT 0 -#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ - -/* MSC Command Sequence Control Register (MSC_CMDAT) */ - -#define MSC_CMDAT_IO_ABORT (1 << 11) -#define MSC_CMDAT_BUS_WIDTH_BIT 9 -#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) - #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ - #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ - #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) - #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_DMA_EN (1 << 8) -#define MSC_CMDAT_INIT (1 << 7) -#define MSC_CMDAT_BUSY (1 << 6) -#define MSC_CMDAT_STREAM_BLOCK (1 << 5) -#define MSC_CMDAT_WRITE_READ (1 << 4) -#define MSC_CMDAT_DATA_EN (1 << 3) -#define MSC_CMDAT_RESPONSE_FORMAT_BIT 0 -#define MSC_CMDAT_RESPONSE_FORMAT_MASK (0x7 << MSC_CMDAT_RESPONSE_FORMAT_BIT) - #define MSC_CMDAT_RESPONSE_FORMAT_NONE (0x0 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* No response */ - #define MSC_CMDAT_RESPONSE_FORMAT_R1 (0x1 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R1 and R1b */ - #define MSC_CMDAT_RESPONSE_FORMAT_R2 (0x2 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R2 */ - #define MSC_CMDAT_RESPONSE_FORMAT_R3 (0x3 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R3 */ - #define MSC_CMDAT_RESPONSE_FORMAT_R4 (0x4 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R4 */ - #define MSC_CMDAT_RESPONSE_FORMAT_R5 (0x5 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R5 */ - #define MSC_CMDAT_RESPONSE_FORMAT_R6 (0x6 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R6 */ - -#define CMDAT_DMA_EN (1 << 8) -#define CMDAT_INIT (1 << 7) -#define CMDAT_BUSY (1 << 6) -#define CMDAT_STREAM (1 << 5) -#define CMDAT_WRITE (1 << 4) -#define CMDAT_DATA_EN (1 << 3) - -/* MSC Interrupts Mask Register (MSC_IMASK) */ - -#define MSC_IMASK_SDIO (1 << 7) -#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) -#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) -#define MSC_IMASK_END_CMD_RES (1 << 2) -#define MSC_IMASK_PRG_DONE (1 << 1) -#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) - -/* MSC Interrupts Status Register (MSC_IREG) */ - -#define MSC_IREG_SDIO (1 << 7) -#define MSC_IREG_TXFIFO_WR_REQ (1 << 6) -#define MSC_IREG_RXFIFO_RD_REQ (1 << 5) -#define MSC_IREG_END_CMD_RES (1 << 2) -#define MSC_IREG_PRG_DONE (1 << 1) -#define MSC_IREG_DATA_TRAN_DONE (1 << 0) - - - - -/************************************************************************* - * RTC - *************************************************************************/ -#define RTC_RCR (RTC_BASE + 0x00) -#define RTC_RSR (RTC_BASE + 0x04) -#define RTC_RSAR (RTC_BASE + 0x08) -#define RTC_RGR (RTC_BASE + 0x0c) - -#define REG_RTC_RCR REG32(RTC_RCR) -#define REG_RTC_RSR REG32(RTC_RSR) -#define REG_RTC_RSAR REG32(RTC_RSAR) -#define REG_RTC_RGR REG32(RTC_RGR) - -#define RTC_RCR_HZ (1 << 6) -#define RTC_RCR_HZIE (1 << 5) -#define RTC_RCR_AF (1 << 4) -#define RTC_RCR_AIE (1 << 3) -#define RTC_RCR_AE (1 << 2) -#define RTC_RCR_START (1 << 0) - -#define RTC_RGR_LOCK (1 << 31) -#define RTC_RGR_ADJ_BIT 16 -#define RTC_RGR_ADJ_MASK (0x3ff << RTC_RGR_ADJ_BIT) -#define RTC_RGR_DIV_BIT 0 -#define RTC_REG_DIV_MASK (0xff << RTC_RGR_DIV_BIT) - - - - -/************************************************************************* - * FIR - *************************************************************************/ -#define FIR_TDR (FIR_BASE + 0x000) -#define FIR_RDR (FIR_BASE + 0x004) -#define FIR_TFLR (FIR_BASE + 0x008) -#define FIR_AR (FIR_BASE + 0x00C) -#define FIR_CR1 (FIR_BASE + 0x010) -#define FIR_CR2 (FIR_BASE + 0x014) -#define FIR_SR (FIR_BASE + 0x018) - -#define REG_FIR_TDR REG8(FIR_TDR) -#define REG_FIR_RDR REG8(FIR_RDR) -#define REG_FIR_TFLR REG16(FIR_TFLR) -#define REG_FIR_AR REG8(FIR_AR) -#define REG_FIR_CR1 REG8(FIR_CR1) -#define REG_FIR_CR2 REG16(FIR_CR2) -#define REG_FIR_SR REG16(FIR_SR) - -/* FIR Control Register 1 (FIR_CR1) */ - -#define FIR_CR1_FIRUE (1 << 7) -#define FIR_CR1_ACE (1 << 6) -#define FIR_CR1_EOUS (1 << 5) -#define FIR_CR1_TIIE (1 << 4) -#define FIR_CR1_TFIE (1 << 3) -#define FIR_CR1_RFIE (1 << 2) -#define FIR_CR1_TXE (1 << 1) -#define FIR_CR1_RXE (1 << 0) - -/* FIR Control Register 2 (FIR_CR2) */ - -#define FIR_CR2_SIPE (1 << 10) -#define FIR_CR2_BCRC (1 << 9) -#define FIR_CR2_TFLRS (1 << 8) -#define FIR_CR2_ISS (1 << 7) -#define FIR_CR2_LMS (1 << 6) -#define FIR_CR2_TPPS (1 << 5) -#define FIR_CR2_RPPS (1 << 4) -#define FIR_CR2_TTRG_BIT 2 -#define FIR_CR2_TTRG_MASK (0x3 << FIR_CR2_TTRG_BIT) - #define FIR_CR2_TTRG_16 (0 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 16 */ - #define FIR_CR2_TTRG_32 (1 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 32 */ - #define FIR_CR2_TTRG_64 (2 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 64 */ - #define FIR_CR2_TTRG_128 (3 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 128 */ -#define FIR_CR2_RTRG_BIT 0 -#define FIR_CR2_RTRG_MASK (0x3 << FIR_CR2_RTRG_BIT) - #define FIR_CR2_RTRG_16 (0 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 16 */ - #define FIR_CR2_RTRG_32 (1 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 32 */ - #define FIR_CR2_RTRG_64 (2 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 64 */ - #define FIR_CR2_RTRG_128 (3 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 128 */ - -/* FIR Status Register (FIR_SR) */ - -#define FIR_SR_RFW (1 << 12) -#define FIR_SR_RFA (1 << 11) -#define FIR_SR_TFRTL (1 << 10) -#define FIR_SR_RFRTL (1 << 9) -#define FIR_SR_URUN (1 << 8) -#define FIR_SR_RFTE (1 << 7) -#define FIR_SR_ORUN (1 << 6) -#define FIR_SR_CRCE (1 << 5) -#define FIR_SR_FEND (1 << 4) -#define FIR_SR_TFF (1 << 3) -#define FIR_SR_RFE (1 << 2) -#define FIR_SR_TIDLE (1 << 1) -#define FIR_SR_RB (1 << 0) - - - - -/************************************************************************* - * SCC - *************************************************************************/ -#define SCC_DR(base) ((base) + 0x000) -#define SCC_FDR(base) ((base) + 0x004) -#define SCC_CR(base) ((base) + 0x008) -#define SCC_SR(base) ((base) + 0x00C) -#define SCC_TFR(base) ((base) + 0x010) -#define SCC_EGTR(base) ((base) + 0x014) -#define SCC_ECR(base) ((base) + 0x018) -#define SCC_RTOR(base) ((base) + 0x01C) - -#define REG_SCC_DR(base) REG8(SCC_DR(base)) -#define REG_SCC_FDR(base) REG8(SCC_FDR(base)) -#define REG_SCC_CR(base) REG32(SCC_CR(base)) -#define REG_SCC_SR(base) REG16(SCC_SR(base)) -#define REG_SCC_TFR(base) REG16(SCC_TFR(base)) -#define REG_SCC_EGTR(base) REG8(SCC_EGTR(base)) -#define REG_SCC_ECR(base) REG32(SCC_ECR(base)) -#define REG_SCC_RTOR(base) REG8(SCC_RTOR(base)) - -/* SCC FIFO Data Count Register (SCC_FDR) */ - -#define SCC_FDR_EMPTY 0x00 -#define SCC_FDR_FULL 0x10 - -/* SCC Control Register (SCC_CR) */ - -#define SCC_CR_SCCE (1 << 31) -#define SCC_CR_TRS (1 << 30) -#define SCC_CR_T2R (1 << 29) -#define SCC_CR_FDIV_BIT 24 -#define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT) - #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */ - #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */ -#define SCC_CR_FLUSH (1 << 23) -#define SCC_CR_TRIG_BIT 16 -#define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT) - #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */ - #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */ - #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */ - #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */ -#define SCC_CR_TP (1 << 15) -#define SCC_CR_CONV (1 << 14) -#define SCC_CR_TXIE (1 << 13) -#define SCC_CR_RXIE (1 << 12) -#define SCC_CR_TENDIE (1 << 11) -#define SCC_CR_RTOIE (1 << 10) -#define SCC_CR_ECIE (1 << 9) -#define SCC_CR_EPIE (1 << 8) -#define SCC_CR_RETIE (1 << 7) -#define SCC_CR_EOIE (1 << 6) -#define SCC_CR_TSEND (1 << 3) -#define SCC_CR_PX_BIT 1 -#define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) - #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ - #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ - #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */ -#define SCC_CR_CLKSTP (1 << 0) - -/* SCC Status Register (SCC_SR) */ - -#define SCC_SR_TRANS (1 << 15) -#define SCC_SR_ORER (1 << 12) -#define SCC_SR_RTO (1 << 11) -#define SCC_SR_PER (1 << 10) -#define SCC_SR_TFTG (1 << 9) -#define SCC_SR_RFTG (1 << 8) -#define SCC_SR_TEND (1 << 7) -#define SCC_SR_RETR_3 (1 << 4) -#define SCC_SR_ECNTO (1 << 0) - - - - -/************************************************************************* - * ETH - *************************************************************************/ -#define ETH_BMR (ETH_BASE + 0x1000) -#define ETH_TPDR (ETH_BASE + 0x1004) -#define ETH_RPDR (ETH_BASE + 0x1008) -#define ETH_RAR (ETH_BASE + 0x100C) -#define ETH_TAR (ETH_BASE + 0x1010) -#define ETH_SR (ETH_BASE + 0x1014) -#define ETH_CR (ETH_BASE + 0x1018) -#define ETH_IER (ETH_BASE + 0x101C) -#define ETH_MFCR (ETH_BASE + 0x1020) -#define ETH_CTAR (ETH_BASE + 0x1050) -#define ETH_CRAR (ETH_BASE + 0x1054) -#define ETH_MCR (ETH_BASE + 0x0000) -#define ETH_MAHR (ETH_BASE + 0x0004) -#define ETH_MALR (ETH_BASE + 0x0008) -#define ETH_HTHR (ETH_BASE + 0x000C) -#define ETH_HTLR (ETH_BASE + 0x0010) -#define ETH_MIAR (ETH_BASE + 0x0014) -#define ETH_MIDR (ETH_BASE + 0x0018) -#define ETH_FCR (ETH_BASE + 0x001C) -#define ETH_VTR1 (ETH_BASE + 0x0020) -#define ETH_VTR2 (ETH_BASE + 0x0024) -#define ETH_WKFR (ETH_BASE + 0x0028) -#define ETH_PMTR (ETH_BASE + 0x002C) - -#define REG_ETH_BMR REG32(ETH_BMR) -#define REG_ETH_TPDR REG32(ETH_TPDR) -#define REG_ETH_RPDR REG32(ETH_RPDR) -#define REG_ETH_RAR REG32(ETH_RAR) -#define REG_ETH_TAR REG32(ETH_TAR) -#define REG_ETH_SR REG32(ETH_SR) -#define REG_ETH_CR REG32(ETH_CR) -#define REG_ETH_IER REG32(ETH_IER) -#define REG_ETH_MFCR REG32(ETH_MFCR) -#define REG_ETH_CTAR REG32(ETH_CTAR) -#define REG_ETH_CRAR REG32(ETH_CRAR) -#define REG_ETH_MCR REG32(ETH_MCR) -#define REG_ETH_MAHR REG32(ETH_MAHR) -#define REG_ETH_MALR REG32(ETH_MALR) -#define REG_ETH_HTHR REG32(ETH_HTHR) -#define REG_ETH_HTLR REG32(ETH_HTLR) -#define REG_ETH_MIAR REG32(ETH_MIAR) -#define REG_ETH_MIDR REG32(ETH_MIDR) -#define REG_ETH_FCR REG32(ETH_FCR) -#define REG_ETH_VTR1 REG32(ETH_VTR1) -#define REG_ETH_VTR2 REG32(ETH_VTR2) -#define REG_ETH_WKFR REG32(ETH_WKFR) -#define REG_ETH_PMTR REG32(ETH_PMTR) - -/* Bus Mode Register (ETH_BMR) */ - -#define ETH_BMR_DBO (1 << 20) -#define ETH_BMR_PBL_BIT 8 -#define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT) - #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT) - #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT) -#define ETH_BMR_BLE (1 << 7) -#define ETH_BMR_DSL_BIT 2 -#define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT) - #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT) -#define ETH_BMR_SWR (1 << 0) - -/* DMA Status Register (ETH_SR) */ - -#define ETH_SR_EB_BIT 23 -#define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT) - #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT) - #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT) -#define ETH_SR_TS_BIT 20 -#define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT) - #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT) - #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT) - #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT) - #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT) - #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT) - #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT) -#define ETH_SR_RS_BIT 17 -#define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT) - #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT) - #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT) - #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT) - #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT) - #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT) - #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT) - #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT) - #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT) -#define ETH_SR_NIS (1 << 16) -#define ETH_SR_AIS (1 << 15) -#define ETH_SR_ERI (1 << 14) -#define ETH_SR_FBE (1 << 13) -#define ETH_SR_ETI (1 << 10) -#define ETH_SR_RWT (1 << 9) -#define ETH_SR_RPS (1 << 8) -#define ETH_SR_RU (1 << 7) -#define ETH_SR_RI (1 << 6) -#define ETH_SR_UNF (1 << 5) -#define ETH_SR_TJT (1 << 3) -#define ETH_SR_TU (1 << 2) -#define ETH_SR_TPS (1 << 1) -#define ETH_SR_TI (1 << 0) - -/* Control (Operation Mode) Register (ETH_CR) */ - -#define ETH_CR_TTM (1 << 22) -#define ETH_CR_SF (1 << 21) -#define ETH_CR_TR_BIT 14 -#define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT) -#define ETH_CR_ST (1 << 13) -#define ETH_CR_OSF (1 << 2) -#define ETH_CR_SR (1 << 1) - -/* Interrupt Enable Register (ETH_IER) */ - -#define ETH_IER_NI (1 << 16) -#define ETH_IER_AI (1 << 15) -#define ETH_IER_ERE (1 << 14) -#define ETH_IER_FBE (1 << 13) -#define ETH_IER_ET (1 << 10) -#define ETH_IER_RWE (1 << 9) -#define ETH_IER_RS (1 << 8) -#define ETH_IER_RU (1 << 7) -#define ETH_IER_RI (1 << 6) -#define ETH_IER_UN (1 << 5) -#define ETH_IER_TJ (1 << 3) -#define ETH_IER_TU (1 << 2) -#define ETH_IER_TS (1 << 1) -#define ETH_IER_TI (1 << 0) - -/* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */ - -#define ETH_MFCR_OVERFLOW_BIT 17 -#define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT) -#define ETH_MFCR_MFC_BIT 0 -#define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT) - -/* MAC Control Register (ETH_MCR) */ - -#define ETH_MCR_RA (1 << 31) -#define ETH_MCR_HBD (1 << 28) -#define ETH_MCR_PS (1 << 27) -#define ETH_MCR_DRO (1 << 23) -#define ETH_MCR_OM_BIT 21 -#define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT) - #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT) - #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT) - #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT) -#define ETH_MCR_F (1 << 20) -#define ETH_MCR_PM (1 << 19) -#define ETH_MCR_PR (1 << 18) -#define ETH_MCR_IF (1 << 17) -#define ETH_MCR_PB (1 << 16) -#define ETH_MCR_HO (1 << 15) -#define ETH_MCR_HP (1 << 13) -#define ETH_MCR_LCC (1 << 12) -#define ETH_MCR_DBF (1 << 11) -#define ETH_MCR_DTRY (1 << 10) -#define ETH_MCR_ASTP (1 << 8) -#define ETH_MCR_BOLMT_BIT 6 -#define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT) - #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT) - #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT) - #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT) - #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT) -#define ETH_MCR_DC (1 << 5) -#define ETH_MCR_TE (1 << 3) -#define ETH_MCR_RE (1 << 2) - -/* MII Address Register (ETH_MIAR) */ - -#define ETH_MIAR_PHY_ADDR_BIT 11 -#define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT) -#define ETH_MIAR_MII_REG_BIT 6 -#define ETH_MIAR_MII_REG_MASK (0x1f << ETH_MIAR_MII_REG_BIT) -#define ETH_MIAR_MII_WRITE (1 << 1) -#define ETH_MIAR_MII_BUSY (1 << 0) - -/* Flow Control Register (ETH_FCR) */ - -#define ETH_FCR_PAUSE_TIME_BIT 16 -#define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT) -#define ETH_FCR_PCF (1 << 2) -#define ETH_FCR_FCE (1 << 1) -#define ETH_FCR_BUSY (1 << 0) - -/* PMT Control and Status Register (ETH_PMTR) */ - -#define ETH_PMTR_GU (1 << 9) -#define ETH_PMTR_RF (1 << 6) -#define ETH_PMTR_MF (1 << 5) -#define ETH_PMTR_RWK (1 << 2) -#define ETH_PMTR_MPK (1 << 1) - -/* Receive Descriptor 0 (ETH_RD0) Bits */ - -#define ETH_RD0_OWN (1 << 31) -#define ETH_RD0_FF (1 << 30) -#define ETH_RD0_FL_BIT 16 -#define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT) -#define ETH_RD0_ES (1 << 15) -#define ETH_RD0_DE (1 << 14) -#define ETH_RD0_LE (1 << 12) -#define ETH_RD0_RF (1 << 11) -#define ETH_RD0_MF (1 << 10) -#define ETH_RD0_FD (1 << 9) -#define ETH_RD0_LD (1 << 8) -#define ETH_RD0_TL (1 << 7) -#define ETH_RD0_CS (1 << 6) -#define ETH_RD0_FT (1 << 5) -#define ETH_RD0_WT (1 << 4) -#define ETH_RD0_ME (1 << 3) -#define ETH_RD0_DB (1 << 2) -#define ETH_RD0_CE (1 << 1) - -/* Receive Descriptor 1 (ETH_RD1) Bits */ - -#define ETH_RD1_RER (1 << 25) -#define ETH_RD1_RCH (1 << 24) -#define ETH_RD1_RBS2_BIT 11 -#define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT) -#define ETH_RD1_RBS1_BIT 0 -#define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT) - -/* Transmit Descriptor 0 (ETH_TD0) Bits */ - -#define ETH_TD0_OWN (1 << 31) -#define ETH_TD0_FA (1 << 15) -#define ETH_TD0_LOC (1 << 11) -#define ETH_TD0_NC (1 << 10) -#define ETH_TD0_LC (1 << 9) -#define ETH_TD0_EC (1 << 8) -#define ETH_TD0_HBF (1 << 7) -#define ETH_TD0_CC_BIT 3 -#define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT) -#define ETH_TD0_ED (1 << 2) -#define ETH_TD0_UF (1 << 1) -#define ETH_TD0_DF (1 << 0) - -/* Transmit Descriptor 1 (ETH_TD1) Bits */ - -#define ETH_TD1_IC (1 << 31) -#define ETH_TD1_LS (1 << 30) -#define ETH_TD1_FS (1 << 29) -#define ETH_TD1_AC (1 << 26) -#define ETH_TD1_TER (1 << 25) -#define ETH_TD1_TCH (1 << 24) -#define ETH_TD1_DPD (1 << 23) -#define ETH_TD1_TBS2_BIT 11 -#define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT) -#define ETH_TD1_TBS1_BIT 0 -#define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT) - - - - -/************************************************************************* - * WDT - *************************************************************************/ -#define WDT_WTCSR (WDT_BASE + 0x00) -#define WDT_WTCNT (WDT_BASE + 0x04) - -#define REG_WDT_WTCSR REG8(WDT_WTCSR) -#define REG_WDT_WTCNT REG32(WDT_WTCNT) - -#define WDT_WTCSR_START (1 << 4) - - - - -/************************************************************************* - * OST - *************************************************************************/ -#define OST_TER (OST_BASE + 0x00) -#define OST_TRDR(n) (OST_BASE + 0x10 + ((n) * 0x20)) -#define OST_TCNT(n) (OST_BASE + 0x14 + ((n) * 0x20)) -#define OST_TCSR(n) (OST_BASE + 0x18 + ((n) * 0x20)) -#define OST_TCRB(n) (OST_BASE + 0x1c + ((n) * 0x20)) - -#define REG_OST_TER REG8(OST_TER) -#define REG_OST_TRDR(n) REG32(OST_TRDR((n))) -#define REG_OST_TCNT(n) REG32(OST_TCNT((n))) -#define REG_OST_TCSR(n) REG16(OST_TCSR((n))) -#define REG_OST_TCRB(n) REG32(OST_TCRB((n))) - -#define OST_TCSR_BUSY (1 << 7) -#define OST_TCSR_UF (1 << 6) -#define OST_TCSR_UIE (1 << 5) -#define OST_TCSR_CKS_BIT 0 -#define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT) - #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT) - -#define OST_TCSR0 OST_TCSR(0) -#define OST_TCSR1 OST_TCSR(1) -#define OST_TCSR2 OST_TCSR(2) -#define OST_TRDR0 OST_TRDR(0) -#define OST_TRDR1 OST_TRDR(1) -#define OST_TRDR2 OST_TRDR(2) -#define OST_TCNT0 OST_TCNT(0) -#define OST_TCNT1 OST_TCNT(1) -#define OST_TCNT2 OST_TCNT(2) -#define OST_TCRB0 OST_TCRB(0) -#define OST_TCRB1 OST_TCRB(1) -#define OST_TCRB2 OST_TCRB(2) - -/************************************************************************* - * UART - *************************************************************************/ - -#define IRDA_BASE UART0_BASE -#define UART_BASE UART0_BASE -#define UART_OFF 0x1000 - -/* register offset */ -#define OFF_RDR (0x00) /* R 8b H'xx */ -#define OFF_TDR (0x00) /* W 8b H'xx */ -#define OFF_DLLR (0x00) /* RW 8b H'00 */ -#define OFF_DLHR (0x04) /* RW 8b H'00 */ -#define OFF_IER (0x04) /* RW 8b H'00 */ -#define OFF_ISR (0x08) /* R 8b H'01 */ -#define OFF_FCR (0x08) /* W 8b H'00 */ -#define OFF_LCR (0x0C) /* RW 8b H'00 */ -#define OFF_MCR (0x10) /* RW 8b H'00 */ -#define OFF_LSR (0x14) /* R 8b H'00 */ -#define OFF_MSR (0x18) /* R 8b H'00 */ -#define OFF_SPR (0x1C) /* RW 8b H'00 */ -#define OFF_MCR (0x10) /* RW 8b H'00 */ -#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ - -/* register address */ -#define UART0_RDR (UART0_BASE + OFF_RDR) -#define UART0_TDR (UART0_BASE + OFF_TDR) -#define UART0_DLLR (UART0_BASE + OFF_DLLR) -#define UART0_DLHR (UART0_BASE + OFF_DLHR) -#define UART0_IER (UART0_BASE + OFF_IER) -#define UART0_ISR (UART0_BASE + OFF_ISR) -#define UART0_FCR (UART0_BASE + OFF_FCR) -#define UART0_LCR (UART0_BASE + OFF_LCR) -#define UART0_MCR (UART0_BASE + OFF_MCR) -#define UART0_LSR (UART0_BASE + OFF_LSR) -#define UART0_MSR (UART0_BASE + OFF_MSR) -#define UART0_SPR (UART0_BASE + OFF_SPR) -#define UART0_SIRCR (UART0_BASE + OFF_SIRCR) - -#define UART1_RDR (UART1_BASE + OFF_RDR) -#define UART1_TDR (UART1_BASE + OFF_TDR) -#define UART1_DLLR (UART1_BASE + OFF_DLLR) -#define UART1_DLHR (UART1_BASE + OFF_DLHR) -#define UART1_IER (UART1_BASE + OFF_IER) -#define UART1_ISR (UART1_BASE + OFF_ISR) -#define UART1_FCR (UART1_BASE + OFF_FCR) -#define UART1_LCR (UART1_BASE + OFF_LCR) -#define UART1_MCR (UART1_BASE + OFF_MCR) -#define UART1_LSR (UART1_BASE + OFF_LSR) -#define UART1_MSR (UART1_BASE + OFF_MSR) -#define UART1_SPR (UART1_BASE + OFF_SPR) -#define UART1_SIRCR (UART1_BASE + OFF_SIRCR) - -#define UART2_RDR (UART2_BASE + OFF_RDR) -#define UART2_TDR (UART2_BASE + OFF_TDR) -#define UART2_DLLR (UART2_BASE + OFF_DLLR) -#define UART2_DLHR (UART2_BASE + OFF_DLHR) -#define UART2_IER (UART2_BASE + OFF_IER) -#define UART2_ISR (UART2_BASE + OFF_ISR) -#define UART2_FCR (UART2_BASE + OFF_FCR) -#define UART2_LCR (UART2_BASE + OFF_LCR) -#define UART2_MCR (UART2_BASE + OFF_MCR) -#define UART2_LSR (UART2_BASE + OFF_LSR) -#define UART2_MSR (UART2_BASE + OFF_MSR) -#define UART2_SPR (UART2_BASE + OFF_SPR) -#define UART2_SIRCR (UART2_BASE + OFF_SIRCR) - -#define UART3_RDR (UART3_BASE + OFF_RDR) -#define UART3_TDR (UART3_BASE + OFF_TDR) -#define UART3_DLLR (UART3_BASE + OFF_DLLR) -#define UART3_DLHR (UART3_BASE + OFF_DLHR) -#define UART3_IER (UART3_BASE + OFF_IER) -#define UART3_ISR (UART3_BASE + OFF_ISR) -#define UART3_FCR (UART3_BASE + OFF_FCR) -#define UART3_LCR (UART3_BASE + OFF_LCR) -#define UART3_MCR (UART3_BASE + OFF_MCR) -#define UART3_LSR (UART3_BASE + OFF_LSR) -#define UART3_MSR (UART3_BASE + OFF_MSR) -#define UART3_SPR (UART3_BASE + OFF_SPR) -#define UART3_SIRCR (UART3_BASE + OFF_SIRCR) - -/* - * Define macros for UART_IER - * UART Interrupt Enable Register - */ -#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ -#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ -#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ -#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ -#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ - -/* - * Define macros for UART_ISR - * UART Interrupt Status Register - */ -#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ -#define UART_ISR_IID (7 << 1) /* Source of Interrupt */ -#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ -#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ -#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ -#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ -#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ -#define UART_ISR_FFMS_NO_FIFO (0 << 6) -#define UART_ISR_FFMS_FIFO_MODE (3 << 6) - -/* - * Define macros for UART_FCR - * UART FIFO Control Register - */ -#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ -#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ -#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ -#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ -#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ -#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ -#define UART_FCR_RTRG_1 (0 << 6) -#define UART_FCR_RTRG_4 (1 << 6) -#define UART_FCR_RTRG_8 (2 << 6) -#define UART_FCR_RTRG_15 (3 << 6) - -/* - * Define macros for UART_LCR - * UART Line Control Register - */ -#define UART_LCR_WLEN (3 << 0) /* word length */ -#define UART_LCR_WLEN_5 (0 << 0) -#define UART_LCR_WLEN_6 (1 << 0) -#define UART_LCR_WLEN_7 (2 << 0) -#define UART_LCR_WLEN_8 (3 << 0) -#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ - -#define UART_LCR_PE (1 << 3) /* 0: parity disable */ -#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ -#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ -#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ -#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ - -/* - * Define macros for UART_LSR - * UART Line Status Register - */ -#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ -#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ -#define UART_LSR_PER (1 << 2) /* 0: no parity error */ -#define UART_LSR_FER (1 << 3) /* 0; no framing error */ -#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ -#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ -#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ -#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ - -/* - * Define macros for UART_MCR - * UART Modem Control Register - */ -#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ -#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ -#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ -#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ -#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ -#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ - -/* - * Define macros for UART_MSR - * UART Modem Status Register - */ -#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ -#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ -#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ -#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ -#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ -#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ -#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ -#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ - -/* - * Define macros for SIRCR - * Slow IrDA Control Register - */ -#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ -#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ -#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length - 1: 0 pulse width is 1.6us for 115.2Kbps */ -#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ -#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ - - - -/************************************************************************* - * INTC - *************************************************************************/ -#define INTC_ISR (INTC_BASE + 0x00) -#define INTC_IMR (INTC_BASE + 0x04) -#define INTC_IMSR (INTC_BASE + 0x08) -#define INTC_IMCR (INTC_BASE + 0x0c) -#define INTC_IPR (INTC_BASE + 0x10) - -#define REG_INTC_ISR REG32(INTC_ISR) -#define REG_INTC_IMR REG32(INTC_IMR) -#define REG_INTC_IMSR REG32(INTC_IMSR) -#define REG_INTC_IMCR REG32(INTC_IMCR) -#define REG_INTC_IPR REG32(INTC_IPR) - -#define IRQ_I2C 1 -#define IRQ_PS2 2 -#define IRQ_UPRT 3 -#define IRQ_CORE 4 -#define IRQ_UART3 6 -#define IRQ_UART2 7 -#define IRQ_UART1 8 -#define IRQ_UART0 9 -#define IRQ_SCC1 10 -#define IRQ_SCC0 11 -#define IRQ_UDC 12 -#define IRQ_UHC 13 -#define IRQ_MSC 14 -#define IRQ_RTC 15 -#define IRQ_FIR 16 -#define IRQ_SSI 17 -#define IRQ_CIM 18 -#define IRQ_ETH 19 -#define IRQ_AIC 20 -#define IRQ_DMAC 21 -#define IRQ_OST2 22 -#define IRQ_OST1 23 -#define IRQ_OST0 24 -#define IRQ_GPIO3 25 -#define IRQ_GPIO2 26 -#define IRQ_GPIO1 27 -#define IRQ_GPIO0 28 -#define IRQ_LCD 30 - - - - -/************************************************************************* - * CIM - *************************************************************************/ -#define CIM_CFG (CIM_BASE + 0x0000) -#define CIM_CTRL (CIM_BASE + 0x0004) -#define CIM_STATE (CIM_BASE + 0x0008) -#define CIM_IID (CIM_BASE + 0x000C) -#define CIM_RXFIFO (CIM_BASE + 0x0010) -#define CIM_DA (CIM_BASE + 0x0020) -#define CIM_FA (CIM_BASE + 0x0024) -#define CIM_FID (CIM_BASE + 0x0028) -#define CIM_CMD (CIM_BASE + 0x002C) - -#define REG_CIM_CFG REG32(CIM_CFG) -#define REG_CIM_CTRL REG32(CIM_CTRL) -#define REG_CIM_STATE REG32(CIM_STATE) -#define REG_CIM_IID REG32(CIM_IID) -#define REG_CIM_RXFIFO REG32(CIM_RXFIFO) -#define REG_CIM_DA REG32(CIM_DA) -#define REG_CIM_FA REG32(CIM_FA) -#define REG_CIM_FID REG32(CIM_FID) -#define REG_CIM_CMD REG32(CIM_CMD) - -/* CIM Configuration Register (CIM_CFG) */ - -#define CIM_CFG_INV_DAT (1 << 15) -#define CIM_CFG_VSP (1 << 14) -#define CIM_CFG_HSP (1 << 13) -#define CIM_CFG_PCP (1 << 12) -#define CIM_CFG_DUMMY_ZERO (1 << 9) -#define CIM_CFG_EXT_VSYNC (1 << 8) -#define CIM_CFG_PACK_BIT 4 -#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) -#define CIM_CFG_DSM_BIT 0 -#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) - #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ - #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ - #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ - #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ - -/* CIM Control Register (CIM_CTRL) */ - -#define CIM_CTRL_MCLKDIV_BIT 24 -#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) -#define CIM_CTRL_FRC_BIT 16 -#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) - #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ - #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ - #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ - #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ - #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ - #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ - #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ - #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ - #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ - #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ - #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ - #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ - #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ - #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ - #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ - #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ -#define CIM_CTRL_VDDM (1 << 13) -#define CIM_CTRL_DMA_SOFM (1 << 12) -#define CIM_CTRL_DMA_EOFM (1 << 11) -#define CIM_CTRL_DMA_STOPM (1 << 10) -#define CIM_CTRL_RXF_TRIGM (1 << 9) -#define CIM_CTRL_RXF_OFM (1 << 8) -#define CIM_CTRL_RXF_TRIG_BIT 4 -#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) - #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ - #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ - #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ - #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ - #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ - #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ - #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ - #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ -#define CIM_CTRL_DMA_EN (1 << 2) -#define CIM_CTRL_RXF_RST (1 << 1) -#define CIM_CTRL_ENA (1 << 0) - -/* CIM State Register (CIM_STATE) */ - -#define CIM_STATE_DMA_SOF (1 << 6) -#define CIM_STATE_DMA_EOF (1 << 5) -#define CIM_STATE_DMA_STOP (1 << 4) -#define CIM_STATE_RXF_OF (1 << 3) -#define CIM_STATE_RXF_TRIG (1 << 2) -#define CIM_STATE_RXF_EMPTY (1 << 1) -#define CIM_STATE_VDD (1 << 0) - -/* CIM DMA Command Register (CIM_CMD) */ - -#define CIM_CMD_SOFINT (1 << 31) -#define CIM_CMD_EOFINT (1 << 30) -#define CIM_CMD_STOP (1 << 28) -#define CIM_CMD_LEN_BIT 0 -#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) - - - - -/************************************************************************* - * PWM - *************************************************************************/ -#define PWM_CTR(n) (PWM##n##_BASE + 0x000) -#define PWM_PER(n) (PWM##n##_BASE + 0x004) -#define PWM_DUT(n) (PWM##n##_BASE + 0x008) - -#define REG_PWM_CTR(n) REG8(PWM_CTR(n)) -#define REG_PWM_PER(n) REG16(PWM_PER(n)) -#define REG_PWM_DUT(n) REG16(PWM_DUT(n)) - -/* PWM Control Register (PWM_CTR) */ - -#define PWM_CTR_EN (1 << 7) -#define PWM_CTR_SD (1 << 6) -#define PWM_CTR_PRESCALE_BIT 0 -#define PWM_CTR_PRESCALE_MASK (0x3f << PWM_CTR_PRESCALE_BIT) - -/* PWM Period Register (PWM_PER) */ - -#define PWM_PER_PERIOD_BIT 0 -#define PWM_PER_PERIOD_MASK (0x3ff << PWM_PER_PERIOD_BIT) - -/* PWM Duty Register (PWM_DUT) */ - -#define PWM_DUT_FDUTY (1 << 10) -#define PWM_DUT_DUTY_BIT 0 -#define PWM_DUT_DUTY_MASK (0x3ff << PWM_DUT_DUTY_BIT) - - - - -/************************************************************************* - * EMC - *************************************************************************/ -#define EMC_BCR (EMC_BASE + 0x00) -#define EMC_SMCR0 (EMC_BASE + 0x10) -#define EMC_SMCR1 (EMC_BASE + 0x14) -#define EMC_SMCR2 (EMC_BASE + 0x18) -#define EMC_SMCR3 (EMC_BASE + 0x1c) -#define EMC_SMCR4 (EMC_BASE + 0x20) -#define EMC_SMCR5 (EMC_BASE + 0x24) -#define EMC_SMCR6 (EMC_BASE + 0x28) -#define EMC_SMCR7 (EMC_BASE + 0x2c) -#define EMC_SACR0 (EMC_BASE + 0x30) -#define EMC_SACR1 (EMC_BASE + 0x34) -#define EMC_SACR2 (EMC_BASE + 0x38) -#define EMC_SACR3 (EMC_BASE + 0x3c) -#define EMC_SACR4 (EMC_BASE + 0x40) -#define EMC_SACR5 (EMC_BASE + 0x44) -#define EMC_SACR6 (EMC_BASE + 0x48) -#define EMC_SACR7 (EMC_BASE + 0x4c) -#define EMC_NFCSR (EMC_BASE + 0x50) -#define EMC_NFECC (EMC_BASE + 0x54) -#define EMC_PCCR1 (EMC_BASE + 0x60) -#define EMC_PCCR2 (EMC_BASE + 0x64) -#define EMC_PCCR3 (EMC_BASE + 0x68) -#define EMC_PCCR4 (EMC_BASE + 0x6c) -#define EMC_DMCR (EMC_BASE + 0x80) -#define EMC_RTCSR (EMC_BASE + 0x84) -#define EMC_RTCNT (EMC_BASE + 0x88) -#define EMC_RTCOR (EMC_BASE + 0x8c) -#define EMC_DMAR1 (EMC_BASE + 0x90) -#define EMC_DMAR2 (EMC_BASE + 0x94) -#define EMC_DMAR3 (EMC_BASE + 0x98) -#define EMC_DMAR4 (EMC_BASE + 0x9c) - -#define EMC_SDMR0 (EMC_BASE + 0xa000) -#define EMC_SDMR1 (EMC_BASE + 0xb000) -#define EMC_SDMR2 (EMC_BASE + 0xc000) -#define EMC_SDMR3 (EMC_BASE + 0xd000) - -/* NAND command/address/data port */ -#define NAND_DATAPORT 0xB4000000 /* read-write area */ -#define NAND_CMDPORT 0xB4040000 /* write only area */ -#define NAND_ADDRPORT 0xB4080000 /* write only area */ - -#define REG_EMC_BCR REG32(EMC_BCR) -#define REG_EMC_SMCR0 REG32(EMC_SMCR0) -#define REG_EMC_SMCR1 REG32(EMC_SMCR1) -#define REG_EMC_SMCR2 REG32(EMC_SMCR2) -#define REG_EMC_SMCR3 REG32(EMC_SMCR3) -#define REG_EMC_SMCR4 REG32(EMC_SMCR4) -#define REG_EMC_SMCR5 REG32(EMC_SMCR5) -#define REG_EMC_SMCR6 REG32(EMC_SMCR6) -#define REG_EMC_SMCR7 REG32(EMC_SMCR7) -#define REG_EMC_SACR0 REG32(EMC_SACR0) -#define REG_EMC_SACR1 REG32(EMC_SACR1) -#define REG_EMC_SACR2 REG32(EMC_SACR2) -#define REG_EMC_SACR3 REG32(EMC_SACR3) -#define REG_EMC_SACR4 REG32(EMC_SACR4) -#define REG_EMC_SACR5 REG32(EMC_SACR5) -#define REG_EMC_SACR6 REG32(EMC_SACR6) -#define REG_EMC_SACR7 REG32(EMC_SACR7) -#define REG_EMC_NFCSR REG32(EMC_NFCSR) -#define REG_EMC_NFECC REG32(EMC_NFECC) -#define REG_EMC_DMCR REG32(EMC_DMCR) -#define REG_EMC_RTCSR REG16(EMC_RTCSR) -#define REG_EMC_RTCNT REG16(EMC_RTCNT) -#define REG_EMC_RTCOR REG16(EMC_RTCOR) -#define REG_EMC_DMAR1 REG32(EMC_DMAR1) -#define REG_EMC_DMAR2 REG32(EMC_DMAR2) -#define REG_EMC_DMAR3 REG32(EMC_DMAR3) -#define REG_EMC_DMAR4 REG32(EMC_DMAR4) -#define REG_EMC_PCCR1 REG32(EMC_PCCR1) -#define REG_EMC_PCCR2 REG32(EMC_PCCR2) -#define REG_EMC_PCCR3 REG32(EMC_PCCR3) -#define REG_EMC_PCCR4 REG32(EMC_PCCR4) - - -#define EMC_BCR_BRE (1 << 1) - -#define EMC_SMCR_STRV_BIT 24 -#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) -#define EMC_SMCR_TAW_BIT 20 -#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) -#define EMC_SMCR_TBP_BIT 16 -#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) -#define EMC_SMCR_TAH_BIT 12 -#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) -#define EMC_SMCR_TAS_BIT 8 -#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) -#define EMC_SMCR_BW_BIT 6 -#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) -#define EMC_SMCR_BL_BIT 1 -#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) - -#define EMC_SACR_BASE_BIT 8 -#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) -#define EMC_SACR_MASK_BIT 0 -#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) - -#define EMC_NFCSR_RB (1 << 7) -#define EMC_NFCSR_BOOT_SEL_BIT 4 -#define EMC_NFCSR_BOOT_SEL_MASK (0x07 << EMC_NFCSR_BOOT_SEL_BIT) -#define EMC_NFCSR_ERST (1 << 3) -#define EMC_NFCSR_ECCE (1 << 2) -#define EMC_NFCSR_FCE (1 << 1) -#define EMC_NFCSR_NFE (1 << 0) - -#define EMC_NFECC_ECC2_BIT 16 -#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) -#define EMC_NFECC_ECC1_BIT 8 -#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) -#define EMC_NFECC_ECC0_BIT 0 -#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) - -#define EMC_DMCR_BW_BIT 31 -#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) - #define EMC_DMCR_BW_32 (0 << EMC_DMCR_BW_BIT) - #define EMC_DMCR_BW_16 (1 << EMC_DMCR_BW_BIT) -#define EMC_DMCR_CA_BIT 26 -#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) -#define EMC_DMCR_RMODE (1 << 25) -#define EMC_DMCR_RFSH (1 << 24) -#define EMC_DMCR_MRSET (1 << 23) -#define EMC_DMCR_RA_BIT 20 -#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) -#define EMC_DMCR_BA_BIT 19 -#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) - #define EMC_DMCR_BA_2 (0 << EMC_DMCR_BA_BIT) - #define EMC_DMCR_BA_4 (1 << EMC_DMCR_BA_BIT) -#define EMC_DMCR_PDM (1 << 18) -#define EMC_DMCR_EPIN (1 << 17) -#define EMC_DMCR_TRAS_BIT 13 -#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) -#define EMC_DMCR_RCD_BIT 11 -#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) -#define EMC_DMCR_TPC_BIT 8 -#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) -#define EMC_DMCR_TRWL_BIT 5 -#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) -#define EMC_DMCR_TRC_BIT 2 -#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) -#define EMC_DMCR_TCL_BIT 0 -#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) - #define EMC_DMCR_CASL_2 (1 << EMC_DMCR_TCL_BIT) - #define EMC_DMCR_CASL_3 (2 << EMC_DMCR_TCL_BIT) - -#define EMC_RTCSR_CMF (1 << 7) -#define EMC_RTCSR_CKS_BIT 0 -#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) - -#define EMC_DMAR_BASE_BIT 8 -#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) -#define EMC_DMAR_MASK_BIT 0 -#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) - -#define EMC_SDMR_BM (1 << 9) -#define EMC_SDMR_OM_BIT 7 -#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) - #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) -#define EMC_SDMR_CAS_BIT 4 -#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) -#define EMC_SDMR_BT_BIT 3 -#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_INTR (1 << EMC_SDMR_BT_BIT) -#define EMC_SDMR_BL_BIT 0 -#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) - -#define EMC_SDMR_CAS2_16BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS2_32BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) -#define EMC_SDMR_CAS3_16BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS3_32BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) - -#define EMC_PCCR12_AMW (1 << 31) -#define EMC_PCCR12_AMAS_BIT 28 -#define EMC_PCCR12_AMAS_MASK (0x07 << EMC_PCCR12_AMAS_BIT) -#define EMC_PCCR12_AMAH_BIT 24 -#define EMC_PCCR12_AMAH_MASK (0x07 << EMC_PCCR12_AMAH_BIT) -#define EMC_PCCR12_AMPW_BIT 20 -#define EMC_PCCR12_AMPW_MASK (0x0f << EMC_PCCR12_AMPW_BIT) -#define EMC_PCCR12_AMRT_BIT 16 -#define EMC_PCCR12_AMRT_MASK (0x0f << EMC_PCCR12_AMRT_BIT) -#define EMC_PCCR12_CMW (1 << 15) -#define EMC_PCCR12_CMAS_BIT 12 -#define EMC_PCCR12_CMAS_MASK (0x07 << EMC_PCCR12_CMAS_BIT) -#define EMC_PCCR12_CMAH_BIT 8 -#define EMC_PCCR12_CMAH_MASK (0x07 << EMC_PCCR12_CMAH_BIT) -#define EMC_PCCR12_CMPW_BIT 4 -#define EMC_PCCR12_CMPW_MASK (0x0f << EMC_PCCR12_CMPW_BIT) -#define EMC_PCCR12_CMRT_BIT 0 -#define EMC_PCCR12_CMRT_MASK (0x07 << EMC_PCCR12_CMRT_BIT) - -#define EMC_PCCR34_DRS_BIT 16 -#define EMC_PCCR34_DRS_MASK (0x03 << EMC_PCCR34_DRS_BIT) - #define EMC_PCCR34_DRS_SPKR (1 << EMC_PCCR34_DRS_BIT) - #define EMC_PCCR34_DRS_IOIS16 (2 << EMC_PCCR34_DRS_BIT) - #define EMC_PCCR34_DRS_INPACK (3 << EMC_PCCR34_DRS_BIT) -#define EMC_PCCR34_IOIS16 (1 << 15) -#define EMC_PCCR34_IOW (1 << 14) -#define EMC_PCCR34_TCB_BIT 12 -#define EMC_PCCR34_TCB_MASK (0x03 << EMC_PCCR34_TCB_BIT) -#define EMC_PCCR34_IORT_BIT 8 -#define EMC_PCCR34_IORT_MASK (0x07 << EMC_PCCR34_IORT_BIT) -#define EMC_PCCR34_IOAE_BIT 6 -#define EMC_PCCR34_IOAE_MASK (0x03 << EMC_PCCR34_IOAE_BIT) - #define EMC_PCCR34_IOAE_NONE (0 << EMC_PCCR34_IOAE_BIT) - #define EMC_PCCR34_IOAE_1 (1 << EMC_PCCR34_IOAE_BIT) - #define EMC_PCCR34_IOAE_2 (2 << EMC_PCCR34_IOAE_BIT) - #define EMC_PCCR34_IOAE_5 (3 << EMC_PCCR34_IOAE_BIT) -#define EMC_PCCR34_IOAH_BIT 4 -#define EMC_PCCR34_IOAH_MASK (0x03 << EMC_PCCR34_IOAH_BIT) - #define EMC_PCCR34_IOAH_NONE (0 << EMC_PCCR34_IOAH_BIT) - #define EMC_PCCR34_IOAH_1 (1 << EMC_PCCR34_IOAH_BIT) - #define EMC_PCCR34_IOAH_2 (2 << EMC_PCCR34_IOAH_BIT) - #define EMC_PCCR34_IOAH_5 (3 << EMC_PCCR34_IOAH_BIT) -#define EMC_PCCR34_IOPW_BIT 0 -#define EMC_PCCR34_IOPW_MASK (0x0f << EMC_PCCR34_IOPW_BIT) - - - - -/************************************************************************* - * GPIO - *************************************************************************/ -#define GPIO_GPDR(n) (GPIO_BASE + (0x00 + (n)*0x30)) -#define GPIO_GPDIR(n) (GPIO_BASE + (0x04 + (n)*0x30)) -#define GPIO_GPODR(n) (GPIO_BASE + (0x08 + (n)*0x30)) -#define GPIO_GPPUR(n) (GPIO_BASE + (0x0c + (n)*0x30)) -#define GPIO_GPALR(n) (GPIO_BASE + (0x10 + (n)*0x30)) -#define GPIO_GPAUR(n) (GPIO_BASE + (0x14 + (n)*0x30)) -#define GPIO_GPIDLR(n) (GPIO_BASE + (0x18 + (n)*0x30)) -#define GPIO_GPIDUR(n) (GPIO_BASE + (0x1c + (n)*0x30)) -#define GPIO_GPIER(n) (GPIO_BASE + (0x20 + (n)*0x30)) -#define GPIO_GPIMR(n) (GPIO_BASE + (0x24 + (n)*0x30)) -#define GPIO_GPFR(n) (GPIO_BASE + (0x28 + (n)*0x30)) - -#define REG_GPIO_GPDR(n) REG32(GPIO_GPDR((n))) -#define REG_GPIO_GPDIR(n) REG32(GPIO_GPDIR((n))) -#define REG_GPIO_GPODR(n) REG32(GPIO_GPODR((n))) -#define REG_GPIO_GPPUR(n) REG32(GPIO_GPPUR((n))) -#define REG_GPIO_GPALR(n) REG32(GPIO_GPALR((n))) -#define REG_GPIO_GPAUR(n) REG32(GPIO_GPAUR((n))) -#define REG_GPIO_GPIDLR(n) REG32(GPIO_GPIDLR((n))) -#define REG_GPIO_GPIDUR(n) REG32(GPIO_GPIDUR((n))) -#define REG_GPIO_GPIER(n) REG32(GPIO_GPIER((n))) -#define REG_GPIO_GPIMR(n) REG32(GPIO_GPIMR((n))) -#define REG_GPIO_GPFR(n) REG32(GPIO_GPFR((n))) - -#define GPIO_IRQ_LOLEVEL 0 -#define GPIO_IRQ_HILEVEL 1 -#define GPIO_IRQ_FALLEDG 2 -#define GPIO_IRQ_RAISEDG 3 - -#define IRQ_GPIO_0 48 -#define NUM_GPIO 100 - -#define GPIO_GPDR0 GPIO_GPDR(0) -#define GPIO_GPDR1 GPIO_GPDR(1) -#define GPIO_GPDR2 GPIO_GPDR(2) -#define GPIO_GPDR3 GPIO_GPDR(3) -#define GPIO_GPDIR0 GPIO_GPDIR(0) -#define GPIO_GPDIR1 GPIO_GPDIR(1) -#define GPIO_GPDIR2 GPIO_GPDIR(2) -#define GPIO_GPDIR3 GPIO_GPDIR(3) -#define GPIO_GPODR0 GPIO_GPODR(0) -#define GPIO_GPODR1 GPIO_GPODR(1) -#define GPIO_GPODR2 GPIO_GPODR(2) -#define GPIO_GPODR3 GPIO_GPODR(3) -#define GPIO_GPPUR0 GPIO_GPPUR(0) -#define GPIO_GPPUR1 GPIO_GPPUR(1) -#define GPIO_GPPUR2 GPIO_GPPUR(2) -#define GPIO_GPPUR3 GPIO_GPPUR(3) -#define GPIO_GPALR0 GPIO_GPALR(0) -#define GPIO_GPALR1 GPIO_GPALR(1) -#define GPIO_GPALR2 GPIO_GPALR(2) -#define GPIO_GPALR3 GPIO_GPALR(3) -#define GPIO_GPAUR0 GPIO_GPAUR(0) -#define GPIO_GPAUR1 GPIO_GPAUR(1) -#define GPIO_GPAUR2 GPIO_GPAUR(2) -#define GPIO_GPAUR3 GPIO_GPAUR(3) -#define GPIO_GPIDLR0 GPIO_GPIDLR(0) -#define GPIO_GPIDLR1 GPIO_GPIDLR(1) -#define GPIO_GPIDLR2 GPIO_GPIDLR(2) -#define GPIO_GPIDLR3 GPIO_GPIDLR(3) -#define GPIO_GPIDUR0 GPIO_GPIDUR(0) -#define GPIO_GPIDUR1 GPIO_GPIDUR(1) -#define GPIO_GPIDUR2 GPIO_GPIDUR(2) -#define GPIO_GPIDUR3 GPIO_GPIDUR(3) -#define GPIO_GPIER0 GPIO_GPIER(0) -#define GPIO_GPIER1 GPIO_GPIER(1) -#define GPIO_GPIER2 GPIO_GPIER(2) -#define GPIO_GPIER3 GPIO_GPIER(3) -#define GPIO_GPIMR0 GPIO_GPIMR(0) -#define GPIO_GPIMR1 GPIO_GPIMR(1) -#define GPIO_GPIMR2 GPIO_GPIMR(2) -#define GPIO_GPIMR3 GPIO_GPIMR(3) -#define GPIO_GPFR0 GPIO_GPFR(0) -#define GPIO_GPFR1 GPIO_GPFR(1) -#define GPIO_GPFR2 GPIO_GPFR(2) -#define GPIO_GPFR3 GPIO_GPFR(3) - - -/************************************************************************* - * HARB - *************************************************************************/ -#define HARB_HAPOR (HARB_BASE + 0x000) -#define HARB_HMCTR (HARB_BASE + 0x010) -#define HARB_HME8H (HARB_BASE + 0x014) -#define HARB_HMCR1 (HARB_BASE + 0x018) -#define HARB_HMER2 (HARB_BASE + 0x01C) -#define HARB_HMER3 (HARB_BASE + 0x020) -#define HARB_HMLTR (HARB_BASE + 0x024) - -#define REG_HARB_HAPOR REG32(HARB_HAPOR) -#define REG_HARB_HMCTR REG32(HARB_HMCTR) -#define REG_HARB_HME8H REG32(HARB_HME8H) -#define REG_HARB_HMCR1 REG32(HARB_HMCR1) -#define REG_HARB_HMER2 REG32(HARB_HMER2) -#define REG_HARB_HMER3 REG32(HARB_HMER3) -#define REG_HARB_HMLTR REG32(HARB_HMLTR) - -/* HARB Priority Order Register (HARB_HAPOR) */ - -#define HARB_HAPOR_UCHSEL (1 << 7) -#define HARB_HAPOR_PRIO_BIT 0 -#define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT) - -/* AHB Monitor Control Register (HARB_HMCTR) */ - -#define HARB_HMCTR_HET3_BIT 20 -#define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT) -#define HARB_HMCTR_HMS3_BIT 16 -#define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT) -#define HARB_HMCTR_HET2_BIT 12 -#define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT) -#define HARB_HMCTR_HMS2_BIT 8 -#define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT) -#define HARB_HMCTR_HOVF3 (1 << 7) -#define HARB_HMCTR_HOVF2 (1 << 6) -#define HARB_HMCTR_HOVF1 (1 << 5) -#define HARB_HMCTR_HRST (1 << 4) -#define HARB_HMCTR_HEE3 (1 << 2) -#define HARB_HMCTR_HEE2 (1 << 1) -#define HARB_HMCTR_HEE1 (1 << 0) - -/* AHB Monitor Event 8bits High Register (HARB_HME8H) */ - -#define HARB_HME8H_HC8H1_BIT 16 -#define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT) -#define HARB_HME8H_HC8H2_BIT 8 -#define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT) -#define HARB_HME8H_HC8H3_BIT 0 -#define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT) - -/* AHB Monitor Latency Register (HARB_HMLTR) */ - -#define HARB_HMLTR_HLT2_BIT 16 -#define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT) -#define HARB_HMLTR_HLT3_BIT 0 -#define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT) - - - - -/************************************************************************* - * I2C - *************************************************************************/ -#define I2C_DR (I2C_BASE + 0x000) -#define I2C_CR (I2C_BASE + 0x004) -#define I2C_SR (I2C_BASE + 0x008) -#define I2C_GR (I2C_BASE + 0x00C) - -#define REG_I2C_DR REG8(I2C_DR) -#define REG_I2C_CR REG8(I2C_CR) -#define REG_I2C_SR REG8(I2C_SR) -#define REG_I2C_GR REG16(I2C_GR) - -/* I2C Control Register (I2C_CR) */ - -#define I2C_CR_IEN (1 << 4) -#define I2C_CR_STA (1 << 3) -#define I2C_CR_STO (1 << 2) -#define I2C_CR_AC (1 << 1) -#define I2C_CR_I2CE (1 << 0) - -/* I2C Status Register (I2C_SR) */ - -#define I2C_SR_STX (1 << 4) -#define I2C_SR_BUSY (1 << 3) -#define I2C_SR_TEND (1 << 2) -#define I2C_SR_DRF (1 << 1) -#define I2C_SR_ACKF (1 << 0) - - - - -/************************************************************************* - * UDC - *************************************************************************/ -#define UDC_EP0InCR (UDC_BASE + 0x00) -#define UDC_EP0InSR (UDC_BASE + 0x04) -#define UDC_EP0InBSR (UDC_BASE + 0x08) -#define UDC_EP0InMPSR (UDC_BASE + 0x0c) -#define UDC_EP0InDesR (UDC_BASE + 0x14) -#define UDC_EP1InCR (UDC_BASE + 0x20) -#define UDC_EP1InSR (UDC_BASE + 0x24) -#define UDC_EP1InBSR (UDC_BASE + 0x28) -#define UDC_EP1InMPSR (UDC_BASE + 0x2c) -#define UDC_EP1InDesR (UDC_BASE + 0x34) -#define UDC_EP2InCR (UDC_BASE + 0x40) -#define UDC_EP2InSR (UDC_BASE + 0x44) -#define UDC_EP2InBSR (UDC_BASE + 0x48) -#define UDC_EP2InMPSR (UDC_BASE + 0x4c) -#define UDC_EP2InDesR (UDC_BASE + 0x54) -#define UDC_EP3InCR (UDC_BASE + 0x60) -#define UDC_EP3InSR (UDC_BASE + 0x64) -#define UDC_EP3InBSR (UDC_BASE + 0x68) -#define UDC_EP3InMPSR (UDC_BASE + 0x6c) -#define UDC_EP3InDesR (UDC_BASE + 0x74) -#define UDC_EP4InCR (UDC_BASE + 0x80) -#define UDC_EP4InSR (UDC_BASE + 0x84) -#define UDC_EP4InBSR (UDC_BASE + 0x88) -#define UDC_EP4InMPSR (UDC_BASE + 0x8c) -#define UDC_EP4InDesR (UDC_BASE + 0x94) - -#define UDC_EP0OutCR (UDC_BASE + 0x200) -#define UDC_EP0OutSR (UDC_BASE + 0x204) -#define UDC_EP0OutPFNR (UDC_BASE + 0x208) -#define UDC_EP0OutMPSR (UDC_BASE + 0x20c) -#define UDC_EP0OutSBPR (UDC_BASE + 0x210) -#define UDC_EP0OutDesR (UDC_BASE + 0x214) -#define UDC_EP5OutCR (UDC_BASE + 0x2a0) -#define UDC_EP5OutSR (UDC_BASE + 0x2a4) -#define UDC_EP5OutPFNR (UDC_BASE + 0x2a8) -#define UDC_EP5OutMPSR (UDC_BASE + 0x2ac) -#define UDC_EP5OutDesR (UDC_BASE + 0x2b4) -#define UDC_EP6OutCR (UDC_BASE + 0x2c0) -#define UDC_EP6OutSR (UDC_BASE + 0x2c4) -#define UDC_EP6OutPFNR (UDC_BASE + 0x2c8) -#define UDC_EP6OutMPSR (UDC_BASE + 0x2cc) -#define UDC_EP6OutDesR (UDC_BASE + 0x2d4) -#define UDC_EP7OutCR (UDC_BASE + 0x2e0) -#define UDC_EP7OutSR (UDC_BASE + 0x2e4) -#define UDC_EP7OutPFNR (UDC_BASE + 0x2e8) -#define UDC_EP7OutMPSR (UDC_BASE + 0x2ec) -#define UDC_EP7OutDesR (UDC_BASE + 0x2f4) - -#define UDC_DevCFGR (UDC_BASE + 0x400) -#define UDC_DevCR (UDC_BASE + 0x404) -#define UDC_DevSR (UDC_BASE + 0x408) -#define UDC_DevIntR (UDC_BASE + 0x40c) -#define UDC_DevIntMR (UDC_BASE + 0x410) -#define UDC_EPIntR (UDC_BASE + 0x414) -#define UDC_EPIntMR (UDC_BASE + 0x418) - -#define UDC_STCMAR (UDC_BASE + 0x500) -#define UDC_EP0InfR (UDC_BASE + 0x504) -#define UDC_EP1InfR (UDC_BASE + 0x508) -#define UDC_EP2InfR (UDC_BASE + 0x50c) -#define UDC_EP3InfR (UDC_BASE + 0x510) -#define UDC_EP4InfR (UDC_BASE + 0x514) -#define UDC_EP5InfR (UDC_BASE + 0x518) -#define UDC_EP6InfR (UDC_BASE + 0x51c) -#define UDC_EP7InfR (UDC_BASE + 0x520) - -#define UDC_TXCONFIRM (UDC_BASE + 0x41C) -#define UDC_TXZLP (UDC_BASE + 0x420) -#define UDC_RXCONFIRM (UDC_BASE + 0x41C) - -#define UDC_RXFIFO (UDC_BASE + 0x800) -#define UDC_TXFIFOEP0 (UDC_BASE + 0x840) - -#define REG_UDC_EP0InCR REG32(UDC_EP0InCR) -#define REG_UDC_EP0InSR REG32(UDC_EP0InSR) -#define REG_UDC_EP0InBSR REG32(UDC_EP0InBSR) -#define REG_UDC_EP0InMPSR REG32(UDC_EP0InMPSR) -#define REG_UDC_EP0InDesR REG32(UDC_EP0InDesR) -#define REG_UDC_EP1InCR REG32(UDC_EP1InCR) -#define REG_UDC_EP1InSR REG32(UDC_EP1InSR) -#define REG_UDC_EP1InBSR REG32(UDC_EP1InBSR) -#define REG_UDC_EP1InMPSR REG32(UDC_EP1InMPSR) -#define REG_UDC_EP1InDesR REG32(UDC_EP1InDesR) -#define REG_UDC_EP2InCR REG32(UDC_EP2InCR) -#define REG_UDC_EP2InSR REG32(UDC_EP2InSR) -#define REG_UDC_EP2InBSR REG32(UDC_EP2InBSR) -#define REG_UDC_EP2InMPSR REG32(UDC_EP2InMPSR) -#define REG_UDC_EP2InDesR REG32(UDC_EP2InDesR) -#define REG_UDC_EP3InCR REG32(UDC_EP3InCR) -#define REG_UDC_EP3InSR REG32(UDC_EP3InSR) -#define REG_UDC_EP3InBSR REG32(UDC_EP3InBSR) -#define REG_UDC_EP3InMPSR REG32(UDC_EP3InMPSR) -#define REG_UDC_EP3InDesR REG32(UDC_EP3InDesR) -#define REG_UDC_EP4InCR REG32(UDC_EP4InCR) -#define REG_UDC_EP4InSR REG32(UDC_EP4InSR) -#define REG_UDC_EP4InBSR REG32(UDC_EP4InBSR) -#define REG_UDC_EP4InMPSR REG32(UDC_EP4InMPSR) -#define REG_UDC_EP4InDesR REG32(UDC_EP4InDesR) - -#define REG_UDC_EP0OutCR REG32(UDC_EP0OutCR) -#define REG_UDC_EP0OutSR REG32(UDC_EP0OutSR) -#define REG_UDC_EP0OutPFNR REG32(UDC_EP0OutPFNR) -#define REG_UDC_EP0OutMPSR REG32(UDC_EP0OutMPSR) -#define REG_UDC_EP0OutSBPR REG32(UDC_EP0OutSBPR) -#define REG_UDC_EP0OutDesR REG32(UDC_EP0OutDesR) -#define REG_UDC_EP5OutCR REG32(UDC_EP5OutCR) -#define REG_UDC_EP5OutSR REG32(UDC_EP5OutSR) -#define REG_UDC_EP5OutPFNR REG32(UDC_EP5OutPFNR) -#define REG_UDC_EP5OutMPSR REG32(UDC_EP5OutMPSR) -#define REG_UDC_EP5OutDesR REG32(UDC_EP5OutDesR) -#define REG_UDC_EP6OutCR REG32(UDC_EP6OutCR) -#define REG_UDC_EP6OutSR REG32(UDC_EP6OutSR) -#define REG_UDC_EP6OutPFNR REG32(UDC_EP6OutPFNR) -#define REG_UDC_EP6OutMPSR REG32(UDC_EP6OutMPSR) -#define REG_UDC_EP6OutDesR REG32(UDC_EP6OutDesR) -#define REG_UDC_EP7OutCR REG32(UDC_EP7OutCR) -#define REG_UDC_EP7OutSR REG32(UDC_EP7OutSR) -#define REG_UDC_EP7OutPFNR REG32(UDC_EP7OutPFNR) -#define REG_UDC_EP7OutMPSR REG32(UDC_EP7OutMPSR) -#define REG_UDC_EP7OutDesR REG32(UDC_EP7OutDesR) - -#define REG_UDC_DevCFGR REG32(UDC_DevCFGR) -#define REG_UDC_DevCR REG32(UDC_DevCR) -#define REG_UDC_DevSR REG32(UDC_DevSR) -#define REG_UDC_DevIntR REG32(UDC_DevIntR) -#define REG_UDC_DevIntMR REG32(UDC_DevIntMR) -#define REG_UDC_EPIntR REG32(UDC_EPIntR) -#define REG_UDC_EPIntMR REG32(UDC_EPIntMR) - -#define REG_UDC_STCMAR REG32(UDC_STCMAR) -#define REG_UDC_EP0InfR REG32(UDC_EP0InfR) -#define REG_UDC_EP1InfR REG32(UDC_EP1InfR) -#define REG_UDC_EP2InfR REG32(UDC_EP2InfR) -#define REG_UDC_EP3InfR REG32(UDC_EP3InfR) -#define REG_UDC_EP4InfR REG32(UDC_EP4InfR) -#define REG_UDC_EP5InfR REG32(UDC_EP5InfR) -#define REG_UDC_EP6InfR REG32(UDC_EP6InfR) -#define REG_UDC_EP7InfR REG32(UDC_EP7InfR) - -#define UDC_DevCFGR_PI (1 << 5) -#define UDC_DevCFGR_SS (1 << 4) -#define UDC_DevCFGR_SP (1 << 3) -#define UDC_DevCFGR_RW (1 << 2) -#define UDC_DevCFGR_SPD_BIT 0 -#define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT) - #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT) - #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT) - #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT) - -#define UDC_DevCR_DM (1 << 9) -#define UDC_DevCR_BE (1 << 5) -#define UDC_DevCR_RES (1 << 0) - -#define UDC_DevSR_ENUMSPD_BIT 13 -#define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT) - #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT) - #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT) - #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT) -#define UDC_DevSR_SUSP (1 << 12) -#define UDC_DevSR_ALT_BIT 8 -#define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT) -#define UDC_DevSR_INTF_BIT 4 -#define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT) -#define UDC_DevSR_CFG_BIT 0 -#define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT) - -#define UDC_DevIntR_ENUM (1 << 6) -#define UDC_DevIntR_SOF (1 << 5) -#define UDC_DevIntR_US (1 << 4) -#define UDC_DevIntR_UR (1 << 3) -#define UDC_DevIntR_SI (1 << 1) -#define UDC_DevIntR_SC (1 << 0) - -#define UDC_EPIntR_OUTEP_BIT 16 -#define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT) -#define UDC_EPIntR_OUTEP0 0x00010000 -#define UDC_EPIntR_OUTEP5 0x00200000 -#define UDC_EPIntR_OUTEP6 0x00400000 -#define UDC_EPIntR_OUTEP7 0x00800000 -#define UDC_EPIntR_INEP_BIT 0 -#define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT) -#define UDC_EPIntR_INEP0 0x00000001 -#define UDC_EPIntR_INEP1 0x00000002 -#define UDC_EPIntR_INEP2 0x00000004 -#define UDC_EPIntR_INEP3 0x00000008 -#define UDC_EPIntR_INEP4 0x00000010 - - -#define UDC_EPIntMR_OUTEP_BIT 16 -#define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT) -#define UDC_EPIntMR_INEP_BIT 0 -#define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT) - -#define UDC_EPCR_ET_BIT 4 -#define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT) - #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT) - #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT) - #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT) - #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT) -#define UDC_EPCR_SN (1 << 2) -#define UDC_EPCR_F (1 << 1) -#define UDC_EPCR_S (1 << 0) - -#define UDC_EPSR_RXPKTSIZE_BIT 11 -#define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT) -#define UDC_EPSR_IN (1 << 6) -#define UDC_EPSR_OUT_BIT 4 -#define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT) - #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT) - #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT) - #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT) -#define UDC_EPSR_PID_BIT 0 -#define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT) - -#define UDC_EPInfR_MPS_BIT 19 -#define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT) -#define UDC_EPInfR_ALTS_BIT 15 -#define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT) -#define UDC_EPInfR_IFN_BIT 11 -#define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT) -#define UDC_EPInfR_CGN_BIT 7 -#define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT) -#define UDC_EPInfR_EPT_BIT 5 -#define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT) - #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT) - #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT) - #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT) - #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT) -#define UDC_EPInfR_EPD (1 << 4) - #define UDC_EPInfR_EPD_OUT (0 << 4) - #define UDC_EPInfR_EPD_IN (1 << 4) - -#define UDC_EPInfR_EPN_BIT 0 -#define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT) - - - - -/************************************************************************* - * DMAC - *************************************************************************/ -#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) -#define DMAC_DDAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) -#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) -#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) -#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) -#define DMAC_DMAIPR (DMAC_BASE + 0xf8) -#define DMAC_DMACR (DMAC_BASE + 0xfc) - -#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) -#define REG_DMAC_DDAR(n) REG32(DMAC_DDAR((n))) -#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) -#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) -#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) -#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) -#define REG_DMAC_DMACR REG32(DMAC_DMACR) - -#define DMAC_DRSR_RS_BIT 0 -#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_EXTREXTR (0 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_PCMCIAOUT (4 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_PCMCIAIN (5 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_DESOUT (10 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_DESIN (11 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_OST2 (28 << DMAC_DRSR_RS_BIT) - -#define DMAC_DCCSR_EACKS (1 << 31) -#define DMAC_DCCSR_EACKM (1 << 30) -#define DMAC_DCCSR_ERDM_BIT 28 -#define DMAC_DCCSR_ERDM_MASK (0x03 << DMAC_DCCSR_ERDM_BIT) - #define DMAC_DCCSR_ERDM_LLEVEL (0 << DMAC_DCCSR_ERDM_BIT) - #define DMAC_DCCSR_ERDM_FEDGE (1 << DMAC_DCCSR_ERDM_BIT) - #define DMAC_DCCSR_ERDM_HLEVEL (2 << DMAC_DCCSR_ERDM_BIT) - #define DMAC_DCCSR_ERDM_REDGE (3 << DMAC_DCCSR_ERDM_BIT) -#define DMAC_DCCSR_EOPM (1 << 27) -#define DMAC_DCCSR_SAM (1 << 23) -#define DMAC_DCCSR_DAM (1 << 22) -#define DMAC_DCCSR_RDIL_BIT 16 -#define DMAC_DCCSR_RDIL_MASK (0x0f << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_IGN (0 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_2 (1 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_4 (2 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_8 (3 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_12 (4 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_16 (5 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_20 (6 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_24 (7 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_28 (8 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_32 (9 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_48 (10 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_60 (11 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_64 (12 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_124 (13 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_128 (14 << DMAC_DCCSR_RDIL_BIT) - #define DMAC_DCCSR_RDIL_200 (15 << DMAC_DCCSR_RDIL_BIT) -#define DMAC_DCCSR_SWDH_BIT 14 -#define DMAC_DCCSR_SWDH_MASK (0x03 << DMAC_DCCSR_SWDH_BIT) - #define DMAC_DCCSR_SWDH_32 (0 << DMAC_DCCSR_SWDH_BIT) - #define DMAC_DCCSR_SWDH_8 (1 << DMAC_DCCSR_SWDH_BIT) - #define DMAC_DCCSR_SWDH_16 (2 << DMAC_DCCSR_SWDH_BIT) -#define DMAC_DCCSR_DWDH_BIT 12 -#define DMAC_DCCSR_DWDH_MASK (0x03 << DMAC_DCCSR_DWDH_BIT) - #define DMAC_DCCSR_DWDH_32 (0 << DMAC_DCCSR_DWDH_BIT) - #define DMAC_DCCSR_DWDH_8 (1 << DMAC_DCCSR_DWDH_BIT) - #define DMAC_DCCSR_DWDH_16 (2 << DMAC_DCCSR_DWDH_BIT) -#define DMAC_DCCSR_DS_BIT 8 -#define DMAC_DCCSR_DS_MASK (0x07 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_32b (0 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_8b (1 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_16b (2 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_16B (3 << DMAC_DCCSR_DS_BIT) - #define DMAC_DCCSR_DS_32B (4 << DMAC_DCCSR_DS_BIT) -#define DMAC_DCCSR_TM (1 << 7) -#define DMAC_DCCSR_AR (1 << 4) -#define DMAC_DCCSR_TC (1 << 3) -#define DMAC_DCCSR_HLT (1 << 2) -#define DMAC_DCCSR_TCIE (1 << 1) -#define DMAC_DCCSR_CHDE (1 << 0) - -#define DMAC_DMAIPR_CINT_BIT 8 -#define DMAC_DMAIPR_CINT_MASK (0xff << DMAC_DMAIPR_CINT_BIT) - -#define DMAC_DMACR_PR_BIT 8 -#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_01234567 (0 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_02314675 (1 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_20136457 (2 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_ROUNDROBIN (3 << DMAC_DMACR_PR_BIT) -#define DMAC_DMACR_HTR (1 << 3) -#define DMAC_DMACR_AER (1 << 2) -#define DMAC_DMACR_DME (1 << 0) - -#define IRQ_DMA_0 32 -#define NUM_DMA 6 - - -/************************************************************************* - * AIC - *************************************************************************/ -#define AIC_FR (AIC_BASE + 0x000) -#define AIC_CR (AIC_BASE + 0x004) -#define AIC_ACCR1 (AIC_BASE + 0x008) -#define AIC_ACCR2 (AIC_BASE + 0x00C) -#define AIC_I2SCR (AIC_BASE + 0x010) -#define AIC_SR (AIC_BASE + 0x014) -#define AIC_ACSR (AIC_BASE + 0x018) -#define AIC_I2SSR (AIC_BASE + 0x01C) -#define AIC_ACCAR (AIC_BASE + 0x020) -#define AIC_ACCDR (AIC_BASE + 0x024) -#define AIC_ACSAR (AIC_BASE + 0x028) -#define AIC_ACSDR (AIC_BASE + 0x02C) -#define AIC_I2SDIV (AIC_BASE + 0x030) -#define AIC_DR (AIC_BASE + 0x034) - -#define REG_AIC_FR REG32(AIC_FR) -#define REG_AIC_CR REG32(AIC_CR) -#define REG_AIC_ACCR1 REG32(AIC_ACCR1) -#define REG_AIC_ACCR2 REG32(AIC_ACCR2) -#define REG_AIC_I2SCR REG32(AIC_I2SCR) -#define REG_AIC_SR REG32(AIC_SR) -#define REG_AIC_ACSR REG32(AIC_ACSR) -#define REG_AIC_I2SSR REG32(AIC_I2SSR) -#define REG_AIC_ACCAR REG32(AIC_ACCAR) -#define REG_AIC_ACCDR REG32(AIC_ACCDR) -#define REG_AIC_ACSAR REG32(AIC_ACSAR) -#define REG_AIC_ACSDR REG32(AIC_ACSDR) -#define REG_AIC_I2SDIV REG32(AIC_I2SDIV) -#define REG_AIC_DR REG32(AIC_DR) - -/* AIC Controller Configuration Register (AIC_FR) */ - -#define AIC_FR_RFTH_BIT 12 -#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) -#define AIC_FR_TFTH_BIT 8 -#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) -#define AIC_FR_AUSEL (1 << 4) -#define AIC_FR_RST (1 << 3) -#define AIC_FR_BCKD (1 << 2) -#define AIC_FR_SYNCD (1 << 1) -#define AIC_FR_ENB (1 << 0) - -/* AIC Controller Common Control Register (AIC_CR) */ - -#define AIC_CR_RDMS (1 << 15) -#define AIC_CR_TDMS (1 << 14) -#define AIC_CR_FLUSH (1 << 8) -#define AIC_CR_EROR (1 << 6) -#define AIC_CR_ETUR (1 << 5) -#define AIC_CR_ERFS (1 << 4) -#define AIC_CR_ETFS (1 << 3) -#define AIC_CR_ENLBF (1 << 2) -#define AIC_CR_ERPL (1 << 1) -#define AIC_CR_EREC (1 << 0) - -/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ - -#define AIC_ACCR1_RS_BIT 16 -#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) - #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ - #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ - #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ - #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit */ - #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit */ - #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit */ - #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit */ - #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ - #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit */ - #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit */ -#define AIC_ACCR1_XS_BIT 0 -#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) - #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ - #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ - #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ - #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit */ - #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit */ - #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit */ - #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit */ - #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ - #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit */ - #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit */ - -/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ - -#define AIC_ACCR2_ERSTO (1 << 18) -#define AIC_ACCR2_ESADR (1 << 17) -#define AIC_ACCR2_ECADT (1 << 16) -#define AIC_ACCR2_OASS_BIT 8 -#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) - #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ - #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ - #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ - #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ -#define AIC_ACCR2_IASS_BIT 6 -#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) - #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ - #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ - #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ - #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ -#define AIC_ACCR2_SO (1 << 3) -#define AIC_ACCR2_SR (1 << 2) -#define AIC_ACCR2_SS (1 << 1) -#define AIC_ACCR2_SA (1 << 0) - -/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ - -#define AIC_I2SCR_STPBK (1 << 12) -#define AIC_I2SCR_WL_BIT 1 -#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) - #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ - #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ - #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ - #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ - #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ -#define AIC_I2SCR_AMSL (1 << 0) - -/* AIC Controller FIFO Status Register (AIC_SR) */ - -#define AIC_SR_RFL_BIT 24 -#define AIC_SR_RFL_MASK (0x1f << AIC_SR_RFL_BIT) -#define AIC_SR_TFL_BIT 8 -#define AIC_SR_TFL_MASK (0x1f << AIC_SR_TFL_BIT) -#define AIC_SR_ROR (1 << 6) -#define AIC_SR_TUR (1 << 5) -#define AIC_SR_RFS (1 << 4) -#define AIC_SR_TFS (1 << 3) - -/* AIC Controller AC-link Status Register (AIC_ACSR) */ - -#define AIC_ACSR_CRDY (1 << 20) -#define AIC_ACSR_CLPM (1 << 19) -#define AIC_ACSR_RSTO (1 << 18) -#define AIC_ACSR_SADR (1 << 17) -#define AIC_ACSR_CADT (1 << 16) - -/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ - -#define AIC_I2SSR_BSY (1 << 2) - -/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ - -#define AIC_ACCAR_CAR_BIT 0 -#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) - -/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ - -#define AIC_ACCDR_CDR_BIT 0 -#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) - -/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ - -#define AIC_ACSAR_SAR_BIT 0 -#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) - -/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ - -#define AIC_ACSDR_SDR_BIT 0 -#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) - -/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ - -#define AIC_I2SDIV_DIV_BIT 0 -#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) - #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ - #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ - #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ - #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ - #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ - #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ - - - - -/************************************************************************* - * LCD - *************************************************************************/ -#define LCD_CFG (LCD_BASE + 0x00) -#define LCD_VSYNC (LCD_BASE + 0x04) -#define LCD_HSYNC (LCD_BASE + 0x08) -#define LCD_VAT (LCD_BASE + 0x0c) -#define LCD_DAH (LCD_BASE + 0x10) -#define LCD_DAV (LCD_BASE + 0x14) -#define LCD_PS (LCD_BASE + 0x18) -#define LCD_CLS (LCD_BASE + 0x1c) -#define LCD_SPL (LCD_BASE + 0x20) -#define LCD_REV (LCD_BASE + 0x24) -#define LCD_CTRL (LCD_BASE + 0x30) -#define LCD_STATE (LCD_BASE + 0x34) -#define LCD_IID (LCD_BASE + 0x38) -#define LCD_DA0 (LCD_BASE + 0x40) -#define LCD_SA0 (LCD_BASE + 0x44) -#define LCD_FID0 (LCD_BASE + 0x48) -#define LCD_CMD0 (LCD_BASE + 0x4c) -#define LCD_DA1 (LCD_BASE + 0x50) -#define LCD_SA1 (LCD_BASE + 0x54) -#define LCD_FID1 (LCD_BASE + 0x58) -#define LCD_CMD1 (LCD_BASE + 0x5c) - -#define REG_LCD_CFG REG32(LCD_CFG) -#define REG_LCD_VSYNC REG32(LCD_VSYNC) -#define REG_LCD_HSYNC REG32(LCD_HSYNC) -#define REG_LCD_VAT REG32(LCD_VAT) -#define REG_LCD_DAH REG32(LCD_DAH) -#define REG_LCD_DAV REG32(LCD_DAV) -#define REG_LCD_PS REG32(LCD_PS) -#define REG_LCD_CLS REG32(LCD_CLS) -#define REG_LCD_SPL REG32(LCD_SPL) -#define REG_LCD_REV REG32(LCD_REV) -#define REG_LCD_CTRL REG32(LCD_CTRL) -#define REG_LCD_STATE REG32(LCD_STATE) -#define REG_LCD_IID REG32(LCD_IID) -#define REG_LCD_DA0 REG32(LCD_DA0) -#define REG_LCD_SA0 REG32(LCD_SA0) -#define REG_LCD_FID0 REG32(LCD_FID0) -#define REG_LCD_CMD0 REG32(LCD_CMD0) -#define REG_LCD_DA1 REG32(LCD_DA1) -#define REG_LCD_SA1 REG32(LCD_SA1) -#define REG_LCD_FID1 REG32(LCD_FID1) -#define REG_LCD_CMD1 REG32(LCD_CMD1) - -#define LCD_CFG_PDW_BIT 4 -#define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) - #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT) - #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT) - #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT) - #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT) -#define LCD_CFG_MODE_BIT 0 -#define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT) - #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT) - -#define LCD_VSYNC_VPS_BIT 16 -#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) -#define LCD_VSYNC_VPE_BIT 0 -#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) - -#define LCD_HSYNC_HPS_BIT 16 -#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) -#define LCD_HSYNC_HPE_BIT 0 -#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) - -#define LCD_VAT_HT_BIT 16 -#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) -#define LCD_VAT_VT_BIT 0 -#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) - -#define LCD_DAH_HDS_BIT 16 -#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) -#define LCD_DAH_HDE_BIT 0 -#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) - -#define LCD_DAV_VDS_BIT 16 -#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) -#define LCD_DAV_VDE_BIT 0 -#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) - -#define LCD_CTRL_BST_BIT 28 -#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) - #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) - #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) - #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) -#define LCD_CTRL_RGB555 (1 << 27) -#define LCD_CTRL_OFUP (1 << 26) -#define LCD_CTRL_FRC_BIT 24 -#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) - #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) - #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) - #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) -#define LCD_CTRL_PDD_BIT 16 -#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) -#define LCD_CTRL_EOFM (1 << 13) -#define LCD_CTRL_SOFM (1 << 12) -#define LCD_CTRL_OFUM (1 << 11) -#define LCD_CTRL_IFUM0 (1 << 10) -#define LCD_CTRL_IFUM1 (1 << 9) -#define LCD_CTRL_LDDM (1 << 8) -#define LCD_CTRL_QDM (1 << 7) -#define LCD_CTRL_BEDN (1 << 6) -#define LCD_CTRL_PEDN (1 << 5) -#define LCD_CTRL_DIS (1 << 4) -#define LCD_CTRL_ENA (1 << 3) -#define LCD_CTRL_BPP_BIT 0 -#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) - -#define LCD_STATE_QD (1 << 7) -#define LCD_STATE_EOF (1 << 5) -#define LCD_STATE_SOF (1 << 4) -#define LCD_STATE_OFU (1 << 3) -#define LCD_STATE_IFU0 (1 << 2) -#define LCD_STATE_IFU1 (1 << 1) -#define LCD_STATE_LDD (1 << 0) - -#define LCD_CMD_SOFINT (1 << 31) -#define LCD_CMD_EOFINT (1 << 30) -#define LCD_CMD_PAL (1 << 28) -#define LCD_CMD_LEN_BIT 0 -#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) - - - - -/************************************************************************* - * DES - *************************************************************************/ -#define DES_CR1 (DES_BASE + 0x000) -#define DES_CR2 (DES_BASE + 0x004) -#define DES_SR (DES_BASE + 0x008) -#define DES_K1L (DES_BASE + 0x010) -#define DES_K1R (DES_BASE + 0x014) -#define DES_K2L (DES_BASE + 0x018) -#define DES_K2R (DES_BASE + 0x01C) -#define DES_K3L (DES_BASE + 0x020) -#define DES_K3R (DES_BASE + 0x024) -#define DES_IVL (DES_BASE + 0x028) -#define DES_IVR (DES_BASE + 0x02C) -#define DES_DIN (DES_BASE + 0x030) -#define DES_DOUT (DES_BASE + 0x034) - -#define REG_DES_CR1 REG32(DES_CR1) -#define REG_DES_CR2 REG32(DES_CR2) -#define REG_DES_SR REG32(DES_SR) -#define REG_DES_K1L REG32(DES_K1L) -#define REG_DES_K1R REG32(DES_K1R) -#define REG_DES_K2L REG32(DES_K2L) -#define REG_DES_K2R REG32(DES_K2R) -#define REG_DES_K3L REG32(DES_K3L) -#define REG_DES_K3R REG32(DES_K3R) -#define REG_DES_IVL REG32(DES_IVL) -#define REG_DES_IVR REG32(DES_IVR) -#define REG_DES_DIN REG32(DES_DIN) -#define REG_DES_DOUT REG32(DES_DOUT) - -/* DES Control Register 1 (DES_CR1) */ - -#define DES_CR1_EN (1 << 0) - -/* DES Control Register 2 (DES_CR2) */ - -#define DES_CR2_ENDEC (1 << 3) -#define DES_CR2_MODE (1 << 2) -#define DES_CR2_ALG (1 << 1) -#define DES_CR2_DMAE (1 << 0) - -/* DES State Register (DES_SR) */ - -#define DES_SR_IN_FULL (1 << 5) -#define DES_SR_IN_LHF (1 << 4) -#define DES_SR_IN_EMPTY (1 << 3) -#define DES_SR_OUT_FULL (1 << 2) -#define DES_SR_OUT_GHF (1 << 1) -#define DES_SR_OUT_EMPTY (1 << 0) - - - - -/************************************************************************* - * CPM - *************************************************************************/ -#define CPM_CFCR (CPM_BASE+0x00) -#define CPM_PLCR1 (CPM_BASE+0x10) -#define CPM_OCR (CPM_BASE+0x1c) -#define CPM_CFCR2 (CPM_BASE+0x60) -#define CPM_LPCR (CPM_BASE+0x04) -#define CPM_RSTR (CPM_BASE+0x08) -#define CPM_MSCR (CPM_BASE+0x20) -#define CPM_SCR (CPM_BASE+0x24) -#define CPM_WRER (CPM_BASE+0x28) -#define CPM_WFER (CPM_BASE+0x2c) -#define CPM_WER (CPM_BASE+0x30) -#define CPM_WSR (CPM_BASE+0x34) -#define CPM_GSR0 (CPM_BASE+0x38) -#define CPM_GSR1 (CPM_BASE+0x3c) -#define CPM_GSR2 (CPM_BASE+0x40) -#define CPM_SPR (CPM_BASE+0x44) -#define CPM_GSR3 (CPM_BASE+0x48) - -#define REG_CPM_CFCR REG32(CPM_CFCR) -#define REG_CPM_PLCR1 REG32(CPM_PLCR1) -#define REG_CPM_OCR REG32(CPM_OCR) -#define REG_CPM_CFCR2 REG32(CPM_CFCR2) -#define REG_CPM_LPCR REG32(CPM_LPCR) -#define REG_CPM_RSTR REG32(CPM_RSTR) -#define REG_CPM_MSCR REG32(CPM_MSCR) -#define REG_CPM_SCR REG32(CPM_SCR) -#define REG_CPM_WRER REG32(CPM_WRER) -#define REG_CPM_WFER REG32(CPM_WFER) -#define REG_CPM_WER REG32(CPM_WER) -#define REG_CPM_WSR REG32(CPM_WSR) -#define REG_CPM_GSR0 REG32(CPM_GSR0) -#define REG_CPM_GSR1 REG32(CPM_GSR1) -#define REG_CPM_GSR2 REG32(CPM_GSR2) -#define REG_CPM_SPR REG32(CPM_SPR) -#define REG_CPM_GSR3 REG32(CPM_GSR3) - -#define CPM_CFCR_SSI (1 << 31) -#define CPM_CFCR_LCD (1 << 30) -#define CPM_CFCR_I2S (1 << 29) -#define CPM_CFCR_UCS (1 << 28) -#define CPM_CFCR_UFR_BIT 25 -#define CPM_CFCR_UFR_MASK (0x07 << CPM_CFCR_UFR_BIT) -#define CPM_CFCR_MSC (1 << 24) -#define CPM_CFCR_CKOEN2 (1 << 23) -#define CPM_CFCR_CKOEN1 (1 << 22) -#define CPM_CFCR_UPE (1 << 20) -#define CPM_CFCR_MFR_BIT 16 -#define CPM_CFCR_MFR_MASK (0x0f << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_1 (0 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_2 (1 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_3 (2 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_4 (3 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_6 (4 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_8 (5 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_12 (6 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_16 (7 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_24 (8 << CPM_CFCR_MFR_BIT) - #define CFCR_MDIV_32 (9 << CPM_CFCR_MFR_BIT) -#define CPM_CFCR_LFR_BIT 12 -#define CPM_CFCR_LFR_MASK (0x0f << CPM_CFCR_LFR_BIT) -#define CPM_CFCR_PFR_BIT 8 -#define CPM_CFCR_PFR_MASK (0x0f << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_1 (0 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_2 (1 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_3 (2 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_4 (3 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_6 (4 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_8 (5 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_12 (6 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_16 (7 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_24 (8 << CPM_CFCR_PFR_BIT) - #define CFCR_PDIV_32 (9 << CPM_CFCR_PFR_BIT) -#define CPM_CFCR_SFR_BIT 4 -#define CPM_CFCR_SFR_MASK (0x0f << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_1 (0 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_2 (1 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_3 (2 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_4 (3 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_6 (4 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_8 (5 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_12 (6 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_16 (7 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_24 (8 << CPM_CFCR_SFR_BIT) - #define CFCR_SDIV_32 (9 << CPM_CFCR_SFR_BIT) -#define CPM_CFCR_IFR_BIT 0 -#define CPM_CFCR_IFR_MASK (0x0f << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_1 (0 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_2 (1 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_3 (2 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_4 (3 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_6 (4 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_8 (5 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_12 (6 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_16 (7 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_24 (8 << CPM_CFCR_IFR_BIT) - #define CFCR_IDIV_32 (9 << CPM_CFCR_IFR_BIT) - -#define CPM_PLCR1_PLL1FD_BIT 23 -#define CPM_PLCR1_PLL1FD_MASK (0x1ff << CPM_PLCR1_PLL1FD_BIT) -#define CPM_PLCR1_PLL1RD_BIT 18 -#define CPM_PLCR1_PLL1RD_MASK (0x1f << CPM_PLCR1_PLL1RD_BIT) -#define CPM_PLCR1_PLL1OD_BIT 16 -#define CPM_PLCR1_PLL1OD_MASK (0x03 << CPM_PLCR1_PLL1OD_BIT) -#define CPM_PLCR1_PLL1S (1 << 10) -#define CPM_PLCR1_PLL1BP (1 << 9) -#define CPM_PLCR1_PLL1EN (1 << 8) -#define CPM_PLCR1_PLL1ST_BIT 0 -#define CPM_PLCR1_PLL1ST_MASK (0xff << CPM_PLCR1_PLL1ST_BIT) - -#define CPM_OCR_O1ST_BIT 16 -#define CPM_OCR_O1ST_MASK (0xff << CPM_OCR_O1ST_BIT) -#define CPM_OCR_O2SE_BIT 8 -#define CPM_OCR_O2SE (1 << CPM_OCR_O2SE_BIT) -#define CPM_OCR_SUSPEND1_BIT 7 -#define CPM_OCR_SUSPEND1 (1 << CPM_OCR_SUSPEND1_BIT) -#define CPM_OCR_SUSPEND0_BIT 6 -#define CPM_OCR_SUSPEND0 (1 << CPM_OCR_SUSPEND0_BIT) - -#define CPM_CFCR2_PXFR_BIT 0 -#define CPM_CFCR2_PXFR_MASK (0x1ff << CPM_CFCR2_PXFR_BIT) - -#define CPM_LPCR_DUTY_BIT 3 -#define CPM_LPCR_DUTY_MASK (0x1f << CPM_LPCR_DUTY_BIT) -#define CPM_LPCR_DOZE (1 << 2) -#define CPM_LPCR_LPM_BIT 0 -#define CPM_LPCR_LPM_MASK (0x03 << CPM_LPCR_LPM_BIT) - #define CPM_LPCR_LPM_IDLE (0 << CPM_LPCR_LPM_BIT) - #define CPM_LPCR_LPM_SLEEP (1 << CPM_LPCR_LPM_BIT) - #define CPM_LPCR_LPM_HIBERNATE (2 << CPM_LPCR_LPM_BIT) - -#define CPM_RSTR_SR (1 << 2) -#define CPM_RSTR_WR (1 << 1) -#define CPM_RSTR_HR (1 << 0) - -#define CPM_MSCR_MSTP_BIT 0 -#define CPM_MSCR_MSTP_MASK (0x1ffffff << CPM_MSCR_MSTP_BIT) - #define CPM_MSCR_MSTP_UART0 0 - #define CPM_MSCR_MSTP_UART1 1 - #define CPM_MSCR_MSTP_UART2 2 - #define CPM_MSCR_MSTP_OST 3 - #define CPM_MSCR_MSTP_RTC 4 - #define CPM_MSCR_MSTP_DMAC 5 - #define CPM_MSCR_MSTP_UHC 6 - #define CPM_MSCR_MSTP_LCD 7 - #define CPM_MSCR_MSTP_I2C 8 - #define CPM_MSCR_MSTP_AIC1 9 - #define CPM_MSCR_MSTP_PWM0 10 - #define CPM_MSCR_MSTP_PWM1 11 - #define CPM_MSCR_MSTP_SSI 12 - #define CPM_MSCR_MSTP_MSC 13 - #define CPM_MSCR_MSTP_SCC 14 - #define CPM_MSCR_MSTP_FIR 16 - #define CPM_MSCR_MSTP_AIC2 18 - #define CPM_MSCR_MSTP_DES 19 - #define CPM_MSCR_MSTP_UART3 20 - #define CPM_MSCR_MSTP_ETH 21 - #define CPM_MSCR_MSTP_PS2 22 - #define CPM_MSCR_MSTP_CIM 23 - #define CPM_MSCR_MSTP_UDC 24 - -#define CPM_SCR_O1SE (1 << 4) -#define CPM_SCR_HGP (1 << 3) -#define CPM_SCR_HZP (1 << 2) -#define CPM_SCR_HZM (1 << 1) - -#define CPM_WRER_RE_BIT 0 -#define CPM_WRER_RE_MASK (0xffff << CPM_WRER_RE_BIT) - -#define CPM_WFER_FE_BIT 0 -#define CPM_WFER_FE_MASK (0xffff << CPM_WFER_FE_BIT) - -#define CPM_WER_WERTC (1 << 31) -#define CPM_WER_WEETH (1 << 30) -#define CPM_WER_WE_BIT 0 -#define CPM_WER_WE_MASK (0xffff << CPM_WER_WE_BIT) - -#define CPM_WSR_WSRTC (1 << 31) -#define CPM_WSR_WSETH (1 << 30) -#define CPM_WSR_WS_BIT 0 -#define CPM_WSR_WS_MASK (0xffff << CPM_WSR_WS_BIT) - - - - -/************************************************************************* - * SSI - *************************************************************************/ -#define SSI_DR (SSI_BASE + 0x000) -#define SSI_CR0 (SSI_BASE + 0x004) -#define SSI_CR1 (SSI_BASE + 0x008) -#define SSI_SR (SSI_BASE + 0x00C) -#define SSI_ITR (SSI_BASE + 0x010) -#define SSI_ICR (SSI_BASE + 0x014) -#define SSI_GR (SSI_BASE + 0x018) - -#define REG_SSI_DR REG32(SSI_DR) -#define REG_SSI_CR0 REG16(SSI_CR0) -#define REG_SSI_CR1 REG32(SSI_CR1) -#define REG_SSI_SR REG32(SSI_SR) -#define REG_SSI_ITR REG16(SSI_ITR) -#define REG_SSI_ICR REG8(SSI_ICR) -#define REG_SSI_GR REG16(SSI_GR) - -/* SSI Data Register (SSI_DR) */ - -#define SSI_DR_GPC_BIT 0 -#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) - -/* SSI Control Register 0 (SSI_CR0) */ - -#define SSI_CR0_SSIE (1 << 15) -#define SSI_CR0_TIE (1 << 14) -#define SSI_CR0_RIE (1 << 13) -#define SSI_CR0_TEIE (1 << 12) -#define SSI_CR0_REIE (1 << 11) -#define SSI_CR0_LOOP (1 << 10) -#define SSI_CR0_RFINE (1 << 9) -#define SSI_CR0_RFINC (1 << 8) -#define SSI_CR0_FSEL (1 << 6) -#define SSI_CR0_TFLUSH (1 << 2) -#define SSI_CR0_RFLUSH (1 << 1) -#define SSI_CR0_DISREV (1 << 0) - -/* SSI Control Register 1 (SSI_CR1) */ - -#define SSI_CR1_FRMHL_BIT 30 -#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) - #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ - #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ - #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ - #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ -#define SSI_CR1_TFVCK_BIT 28 -#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) -#define SSI_CR1_TCKFI_BIT 26 -#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) -#define SSI_CR1_LFST (1 << 25) -#define SSI_CR1_ITFRM (1 << 24) -#define SSI_CR1_UNFIN (1 << 23) -#define SSI_CR1_MULTS (1 << 22) -#define SSI_CR1_FMAT_BIT 20 -#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) - #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ - #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ - #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ - #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ -#define SSI_CR1_MCOM_BIT 12 -#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) - #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ - #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ - #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ - #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ - #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ - #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ - #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ - #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ - #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ - #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ - #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ - #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ - #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ - #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ - #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ - #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ -#define SSI_CR1_TTRG_BIT 10 -#define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */ - #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */ - #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */ - #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */ -#define SSI_CR1_RTRG_BIT 8 -#define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */ - #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */ - #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */ - #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */ -#define SSI_CR1_FLEN_BIT 4 -#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) -#define SSI_CR1_PHA (1 << 1) -#define SSI_CR1_POL (1 << 0) - -/* SSI Status Register (SSI_SR) */ - -#define SSI_SR_TFIFONUM_BIT 13 -#define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT) -#define SSI_SR_RFIFONUM_BIT 8 -#define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT) -#define SSI_SR_END (1 << 7) -#define SSI_SR_BUSY (1 << 6) -#define SSI_SR_TFF (1 << 5) -#define SSI_SR_RFE (1 << 4) -#define SSI_SR_TFHE (1 << 3) -#define SSI_SR_RFHF (1 << 2) -#define SSI_SR_UNDR (1 << 1) -#define SSI_SR_OVER (1 << 0) - -/* SSI Interval Time Control Register (SSI_ITR) */ - -#define SSI_ITR_CNTCLK (1 << 15) -#define SSI_ITR_IVLTM_BIT 0 -#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) - -#ifndef __ASSEMBLY__ - -/*************************************************************************** - * MSC - ***************************************************************************/ - -#define __msc_start_op() \ - ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) - -#define __msc_set_resto(to) ( REG_MSC_RESTO = to ) -#define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) -#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) -#define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) -#define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) -#define __msc_get_nob() ( REG_MSC_NOB ) -#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) -#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) -#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) -#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) - -#define __msc_set_cmdat_bus_width1() \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ - REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ -} while(0) - -#define __msc_set_cmdat_bus_width4() \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ - REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ -} while(0) - -#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) -#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) -#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) -#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) -#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) -#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) -#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) -#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) - -/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ -#define __msc_set_cmdat_res_format(r) \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ - REG_MSC_CMDAT |= (r); \ -} while(0) - -#define __msc_clear_cmdat() \ - REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ - MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ - MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) - -#define __msc_get_imask() ( REG_MSC_IMASK ) -#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) -#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) -#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) -#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) -#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) -#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) -#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) -#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) -#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) -#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) -#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) -#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) - -/* n=1,2,4,8,16,32,64,128 */ -#define __msc_set_clkrt_div(n) \ -do { \ - REG_MSC_CLKRT &= ~MSC_CLKRT_CLK_RATE_MASK; \ - REG_MSC_CLKRT |= MSC_CLKRT_CLK_RATE_DIV_##n; \ -} while(0) - -#define __msc_get_ireg() ( REG_MSC_IREG ) -#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) -#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) -#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) -#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) -#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) -#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) -#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) -#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) - -#define __msc_get_stat() ( REG_MSC_STAT ) -#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) -#define __msc_stat_crc_err() \ - ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) -#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) -#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) -#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) -#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) -#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) - -#define __msc_rd_resfifo() ( REG_MSC_RES ) -#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) -#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) - -#define __msc_reset() \ -do { \ - REG_MSC_STRPCL = MSC_STRPCL_RESET; \ - while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ -} while (0) - -#define __msc_start_clk() \ -do { \ - REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ - REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_START; \ -} while (0) - -#define __msc_stop_clk() \ -do { \ - REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ - REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_STOP; \ -} while (0) - -#define MMC_CLK 19169200 -#define SD_CLK 24576000 - -/* msc_clk should little than pclk and little than clk retrieve from card */ -#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ -do { \ - unsigned int rate, pclk, i; \ - pclk = dev_clk; \ - rate = type?SD_CLK:MMC_CLK; \ - if (msc_clk && msc_clk < pclk) \ - pclk = msc_clk; \ - i = 0; \ - while (pclk < rate) \ - { \ - i ++; \ - rate >>= 1; \ - } \ - lv = i; \ -} while(0) - -/* divide rate to little than or equal to 400kHz */ -#define __msc_calc_slow_clk_divisor(type, lv) \ -do { \ - unsigned int rate, i; \ - rate = (type?SD_CLK:MMC_CLK)/1000/400; \ - i = 0; \ - while (rate > 0) \ - { \ - rate >>= 1; \ - i ++; \ - } \ - lv = i; \ -} while(0) - -/*************************************************************************** - * RTC - ***************************************************************************/ - -#define __rtc_start() ( REG_RTC_RCR |= RTC_RCR_START ) -#define __rtc_stop() ( REG_RTC_RCR &= ~RTC_RCR_START ) - -#define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE ) -#define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE ) -#define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE ) -#define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE ) - -#define __rtc_enable_1hz_irq() ( REG_RTC_RCR |= RTC_RCR_HZIE ) -#define __rtc_disable_1hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_HZIE ) - -#define __rtc_is_alarm_flag() ( REG_RTC_RCR & RTC_RCR_AF ) -#define __rtc_is_1hz_flag() ( REG_RTC_RCR & RTC_RCR_HZ ) -#define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF ) -#define __rtc_clear_1hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_HZ ) - -#define __rtc_set_second(s) ( REG_RTC_RSR = (s) ) -#define __rtc_get_second() REG_RTC_RSR -#define __rtc_set_alarm(s) ( REG_RTC_RSAR = (s) ) -#define __rtc_get_alarm() REG_RTC_RSAR - -#define __rtc_adjust_1hz(f32k) \ - ( REG_RTC_RGR = (REG_RTC_RGR & ~(RTC_REG_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 ) -#define __rtc_lock_1hz() ( REG_RTC_RGR |= RTC_RGR_LOCK ) - - -/*************************************************************************** - * FIR - ***************************************************************************/ - -/* enable/disable fir unit */ -#define __fir_enable() ( REG_FIR_CR1 |= FIR_CR1_FIRUE ) -#define __fir_disable() ( REG_FIR_CR1 &= ~FIR_CR1_FIRUE ) - -/* enable/disable address comparison */ -#define __fir_enable_ac() ( REG_FIR_CR1 |= FIR_CR1_ACE ) -#define __fir_disable_ac() ( REG_FIR_CR1 &= ~FIR_CR1_ACE ) - -/* select frame end mode as underrun or normal */ -#define __fir_set_eous() ( REG_FIR_CR1 |= FIR_CR1_EOUS ) -#define __fir_clear_eous() ( REG_FIR_CR1 &= ~FIR_CR1_EOUS ) - -/* enable/disable transmitter idle interrupt */ -#define __fir_enable_tii() ( REG_FIR_CR1 |= FIR_CR1_TIIE ) -#define __fir_disable_tii() ( REG_FIR_CR1 &= ~FIR_CR1_TIIE ) - -/* enable/disable transmit FIFO service request interrupt */ -#define __fir_enable_tfi() ( REG_FIR_CR1 |= FIR_CR1_TFIE ) -#define __fir_disable_tfi() ( REG_FIR_CR1 &= ~FIR_CR1_TFIE ) - -/* enable/disable receive FIFO service request interrupt */ -#define __fir_enable_rfi() ( REG_FIR_CR1 |= FIR_CR1_RFIE ) -#define __fir_disable_rfi() ( REG_FIR_CR1 &= ~FIR_CR1_RFIE ) - -/* enable/disable tx function */ -#define __fir_tx_enable() ( REG_FIR_CR1 |= FIR_CR1_TXE ) -#define __fir_tx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_TXE ) - -/* enable/disable rx function */ -#define __fir_rx_enable() ( REG_FIR_CR1 |= FIR_CR1_RXE ) -#define __fir_rx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_RXE ) - - -/* enable/disable serial infrared interaction pulse (SIP) */ -#define __fir_enable_sip() ( REG_FIR_CR2 |= FIR_CR2_SIPE ) -#define __fir_disable_sip() ( REG_FIR_CR2 &= ~FIR_CR2_SIPE ) - -/* un-inverted CRC value is sent out */ -#define __fir_enable_bcrc() ( REG_FIR_CR2 |= FIR_CR2_BCRC ) - -/* inverted CRC value is sent out */ -#define __fir_disable_bcrc() ( REG_FIR_CR2 &= ~FIR_CR2_BCRC ) - -/* enable/disable Transmit Frame Length Register */ -#define __fir_enable_tflr() ( REG_FIR_CR2 |= FIR_CR2_TFLRS ) -#define __fir_disable_tflr() ( REG_FIR_CR2 &= ~FIR_CR2_TFLRS ) - -/* Preamble is transmitted in idle state */ -#define __fir_set_iss() ( REG_FIR_CR2 |= FIR_CR2_ISS ) - -/* Abort symbol is transmitted in idle state */ -#define __fir_clear_iss() ( REG_FIR_CR2 &= ~FIR_CR2_ISS ) - -/* enable/disable loopback mode */ -#define __fir_enable_loopback() ( REG_FIR_CR2 |= FIR_CR2_LMS ) -#define __fir_disable_loopback() ( REG_FIR_CR2 &= ~FIR_CR2_LMS ) - -/* select transmit pin polarity */ -#define __fir_tpp_negative() ( REG_FIR_CR2 |= FIR_CR2_TPPS ) -#define __fir_tpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_TPPS ) - -/* select receive pin polarity */ -#define __fir_rpp_negative() ( REG_FIR_CR2 |= FIR_CR2_RPPS ) -#define __fir_rpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_RPPS ) - -/* n=16,32,64,128 */ -#define __fir_set_txfifo_trigger(n) \ -do { \ - REG_FIR_CR2 &= ~FIR_CR2_TTRG_MASK; \ - REG_FIR_CR2 |= FIR_CR2_TTRG_##n; \ -} while (0) - -/* n=16,32,64,128 */ -#define __fir_set_rxfifo_trigger(n) \ -do { \ - REG_FIR_CR2 &= ~FIR_CR2_RTRG_MASK; \ - REG_FIR_CR2 |= FIR_CR2_RTRG_##n; \ -} while (0) - - -/* FIR status checking */ - -#define __fir_test_rfw() ( REG_FIR_SR & FIR_SR_RFW ) -#define __fir_test_rfa() ( REG_FIR_SR & FIR_SR_RFA ) -#define __fir_test_tfrtl() ( REG_FIR_SR & FIR_SR_TFRTL ) -#define __fir_test_rfrtl() ( REG_FIR_SR & FIR_SR_RFRTL ) -#define __fir_test_urun() ( REG_FIR_SR & FIR_SR_URUN ) -#define __fir_test_rfte() ( REG_FIR_SR & FIR_SR_RFTE ) -#define __fir_test_orun() ( REG_FIR_SR & FIR_SR_ORUN ) -#define __fir_test_crce() ( REG_FIR_SR & FIR_SR_CRCE ) -#define __fir_test_fend() ( REG_FIR_SR & FIR_SR_FEND ) -#define __fir_test_tff() ( REG_FIR_SR & FIR_SR_TFF ) -#define __fir_test_rfe() ( REG_FIR_SR & FIR_SR_RFE ) -#define __fir_test_tidle() ( REG_FIR_SR & FIR_SR_TIDLE ) -#define __fir_test_rb() ( REG_FIR_SR & FIR_SR_RB ) - -#define __fir_clear_status() \ -do { \ - REG_FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; \ -} while (0) - -#define __fir_clear_rfw() ( REG_FIR_SR |= FIR_SR_RFW ) -#define __fir_clear_rfa() ( REG_FIR_SR |= FIR_SR_RFA ) -#define __fir_clear_urun() ( REG_FIR_SR |= FIR_SR_URUN ) - -#define __fir_set_tflr(len) \ -do { \ - REG_FIR_TFLR = len; \ -} while (0) - -#define __fir_set_addr(a) ( REG_FIR_AR = (a) ) - -#define __fir_write_data(data) ( REG_FIR_TDR = data ) -#define __fir_read_data(data) ( data = REG_FIR_RDR ) - -/*************************************************************************** - * SCC - ***************************************************************************/ - -#define __scc_enable(base) ( REG_SCC_CR(base) |= SCC_CR_SCCE ) -#define __scc_disable(base) ( REG_SCC_CR(base) &= ~SCC_CR_SCCE ) - -#define __scc_set_tx_mode(base) ( REG_SCC_CR(base) |= SCC_CR_TRS ) -#define __scc_set_rx_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_TRS ) - -#define __scc_enable_t2r(base) ( REG_SCC_CR(base) |= SCC_CR_T2R ) -#define __scc_disable_t2r(base) ( REG_SCC_CR(base) &= ~SCC_CR_T2R ) - -#define __scc_clk_as_devclk(base) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ - REG_SCC_CR(base) |= SCC_CR_FDIV_1; \ -} while (0) - -#define __scc_clk_as_half_devclk(base) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ - REG_SCC_CR(base) |= SCC_CR_FDIV_2; \ -} while (0) - -/* n=1,4,8,14 */ -#define __scc_set_fifo_trigger(base, n) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_TRIG_MASK; \ - REG_SCC_CR(base) |= SCC_CR_TRIG_##n; \ -} while (0) - -#define __scc_set_protocol(base, p) \ -do { \ - if (p) \ - REG_SCC_CR(base) |= SCC_CR_TP; \ - else \ - REG_SCC_CR(base) &= ~SCC_CR_TP; \ -} while (0) - -#define __scc_flush_fifo(base) ( REG_SCC_CR(base) |= SCC_CR_FLUSH ) - -#define __scc_set_invert_mode(base) ( REG_SCC_CR(base) |= SCC_CR_CONV ) -#define __scc_set_direct_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_CONV ) - -#define SCC_ERR_INTRS \ - ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) -#define SCC_ALL_INTRS \ - ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \ - SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) - -#define __scc_enable_err_intrs(base) ( REG_SCC_CR(base) |= SCC_ERR_INTRS ) -#define __scc_disable_err_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ERR_INTRS ) - -#define SCC_ALL_ERRORS \ - ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO) - -#define __scc_clear_errors(base) ( REG_SCC_SR(base) &= ~SCC_ALL_ERRORS ) - -#define __scc_enable_all_intrs(base) ( REG_SCC_CR(base) |= SCC_ALL_INTRS ) -#define __scc_disable_all_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ALL_INTRS ) - -#define __scc_enable_tx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE ) -#define __scc_disable_tx_intr(base) ( REG_SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) ) - -#define __scc_enable_rx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_RXIE) -#define __scc_disable_rx_intr(base) ( REG_SCC_CR(base) &= ~SCC_CR_RXIE) - -#define __scc_set_tsend(base) ( REG_SCC_CR(base) |= SCC_CR_TSEND ) -#define __scc_clear_tsend(base) ( REG_SCC_CR(base) &= ~SCC_CR_TSEND ) - -#define __scc_set_clockstop(base) ( REG_SCC_CR(base) |= SCC_CR_CLKSTP ) -#define __scc_clear_clockstop(base) ( REG_SCC_CR(base) &= ~SCC_CR_CLKSTP ) - -#define __scc_clockstop_low(base) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ - REG_SCC_CR(base) |= SCC_CR_PX_STOP_LOW; \ -} while (0) - -#define __scc_clockstop_high(base) \ -do { \ - REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ - REG_SCC_CR(base) |= SCC_CR_PX_STOP_HIGH; \ -} while (0) - - -/* SCC status checking */ -#define __scc_check_transfer_status(base) ( REG_SCC_SR(base) & SCC_SR_TRANS ) -#define __scc_check_rx_overrun_error(base) ( REG_SCC_SR(base) & SCC_SR_ORER ) -#define __scc_check_rx_timeout(base) ( REG_SCC_SR(base) & SCC_SR_RTO ) -#define __scc_check_parity_error(base) ( REG_SCC_SR(base) & SCC_SR_PER ) -#define __scc_check_txfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_TFTG ) -#define __scc_check_rxfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_RFTG ) -#define __scc_check_tx_end(base) ( REG_SCC_SR(base) & SCC_SR_TEND ) -#define __scc_check_retx_3(base) ( REG_SCC_SR(base) & SCC_SR_RETR_3 ) -#define __scc_check_ecnt_overflow(base) ( REG_SCC_SR(base) & SCC_SR_ECNTO ) - - -/*************************************************************************** - * WDT - ***************************************************************************/ - -#define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) -#define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) -#define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) - - -/*************************************************************************** - * OST - ***************************************************************************/ - -#define __ost_enable_all() ( REG_OST_TER |= 0x07 ) -#define __ost_disable_all() ( REG_OST_TER &= ~0x07 ) -#define __ost_enable_channel(n) ( REG_OST_TER |= (1 << (n)) ) -#define __ost_disable_channel(n) ( REG_OST_TER &= ~(1 << (n)) ) -#define __ost_set_reload(n, val) ( REG_OST_TRDR(n) = (val) ) -#define __ost_set_count(n, val) ( REG_OST_TCNT(n) = (val) ) -#define __ost_get_count(n) ( REG_OST_TCNT(n) ) -#define __ost_set_clock(n, cs) ( REG_OST_TCSR(n) |= (cs) ) -#define __ost_set_mode(n, val) ( REG_OST_TCSR(n) = (val) ) -#define __ost_enable_interrupt(n) ( REG_OST_TCSR(n) |= OST_TCSR_UIE ) -#define __ost_disable_interrupt(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UIE ) -#define __ost_uf_detected(n) ( REG_OST_TCSR(n) & OST_TCSR_UF ) -#define __ost_clear_uf(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UF ) -#define __ost_is_busy(n) ( REG_OST_TCSR(n) & OST_TCSR_BUSY ) -#define __ost_clear_busy(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_BUSY ) - - -/*************************************************************************** - * UART - ***************************************************************************/ - -#define __uart_enable(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = UARTFCR_UUE | UARTFCR_FE ) -#define __uart_disable(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) - -#define __uart_enable_transmit_irq(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) -#define __uart_disable_transmit_irq(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) - -#define __uart_enable_receive_irq(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) -#define __uart_disable_receive_irq(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) - -#define __uart_enable_loopback(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) -#define __uart_disable_loopback(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) - -#define __uart_set_8n1(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) - -#define __uart_set_baud(n, devclk, baud) \ - do { \ - REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \ - REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \ - REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ - REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \ - } while (0) - -#define __uart_parity_error(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) - -#define __uart_clear_errors(n) \ - ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTSR_RFER) ) - -#define __uart_transmit_fifo_empty(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) - -#define __uart_transmit_end(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) - -#define __uart_transmit_char(n, ch) \ - REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) - -#define __uart_receive_fifo_full(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) - -#define __uart_receive_ready(n) \ - ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) - -#define __uart_receive_char(n) \ - REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) - -#define __uart_disable_irda() \ - ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) -#define __uart_enable_irda() \ - /* Tx high pulse as 0, Rx low pulse as 0 */ \ - ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) - - -/*************************************************************************** - * INTC - ***************************************************************************/ -#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) -#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) -#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) - -/*************************************************************************** - * CIM - ***************************************************************************/ - -#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) -#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) - -#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) -#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) - -#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) -#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) - -#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) -#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) - -#define __cim_sample_data_at_pclk_falling_edge() \ - ( REG_CIM_CFG |= CIM_CFG_PCP ) -#define __cim_sample_data_at_pclk_rising_edge() \ - ( REG_CIM_CFG &= ~CIM_CFG_PCP ) - -#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) -#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) - -#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) -#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) - -/* n=0-7 */ -#define __cim_set_data_packing_mode(n) \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ - REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ -} while (0) - -#define __cim_enable_ccir656_progressive_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ -} while (0) - -#define __cim_enable_ccir656_interlace_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ -} while (0) - -#define __cim_enable_gated_clock_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ -} while (0) - -#define __cim_enable_nongated_clock_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ -} while (0) - -/* sclk:system bus clock - * mclk: CIM master clock - */ -#define __cim_set_master_clk(sclk, mclk) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ - REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ -} while (0) - -#define __cim_enable_sof_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) -#define __cim_disable_sof_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) - -#define __cim_enable_eof_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) -#define __cim_disable_eof_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) - -#define __cim_enable_stop_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) -#define __cim_disable_stop_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) - -#define __cim_enable_trig_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) -#define __cim_disable_trig_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) - -#define __cim_enable_rxfifo_overflow_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) -#define __cim_disable_rxfifo_overflow_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) - -/* n=1-16 */ -#define __cim_set_frame_rate(n) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ - REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ -} while (0) - -#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) -#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) - -#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) -#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) - -/* n=4,8,12,16,20,24,28,32 */ -#define __cim_set_rxfifo_trigger(n) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ - REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ -} while (0) - -#define __cim_clear_state() ( REG_CIM_STATE = 0 ) - -#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) -#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) -#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) -#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) -#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) -#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) -#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) -#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) - -#define __cim_get_iid() ( REG_CIM_IID ) -#define __cim_get_image_data() ( REG_CIM_RXFIFO ) -#define __cim_get_dam_cmd() ( REG_CIM_CMD ) - -#define __cim_set_da(a) ( REG_CIM_DA = (a) ) - -/*************************************************************************** - * PWM - ***************************************************************************/ - -/* n is the pwm channel (0,1,..) */ -#define __pwm_enable_module(n) ( REG_PWM_CTR(n) |= PWM_CTR_EN ) -#define __pwm_disable_module(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_EN ) -#define __pwm_graceful_shutdown_mode(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_SD ) -#define __pwm_abrupt_shutdown_mode(n) ( REG_PWM_CTR(n) |= PWM_CTR_SD ) -#define __pwm_set_full_duty(n) ( REG_PWM_DUT(n) |= PWM_DUT_FDUTY ) - -#define __pwm_set_prescale(n, p) \ - ( REG_PWM_CTR(n) = ((REG_PWM_CTR(n) & ~PWM_CTR_PRESCALE_MASK) | (p) ) ) -#define __pwm_set_period(n, p) \ - ( REG_PWM_PER(n) = ( (REG_PWM_PER(n) & ~PWM_PER_PERIOD_MASK) | (p) ) ) -#define __pwm_set_duty(n, d) \ - ( REG_PWM_DUT(n) = ( (REG_PWM_DUT(n) & ~PWM_DUT_FDUTY) | (d) ) ) - -/*************************************************************************** - * EMC - ***************************************************************************/ - -#define __emc_enable_split() ( REG_EMC_BCR = EMC_BCR_BRE ) -#define __emc_disable_split() ( REG_EMC_BCR = 0 ) - -#define __emc_smem_bus_width(n) /* 8, 16 or 32*/ \ - ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BW_MASK) | \ - EMC_SMCR_BW_##n##BIT ) -#define __emc_smem_byte_control() \ - ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_BCM ) -#define __emc_normal_smem() \ - ( REG_EMC_SMCR = (REG_EMC_SMCR & ~EMC_SMCR_SMT ) -#define __emc_burst_smem() \ - ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_SMT ) -#define __emc_smem_burstlen(n) /* 4, 8, 16 or 32 */ \ - ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BL_MASK) | (EMC_SMCR_BL_##n ) - -/*************************************************************************** - * GPIO - ***************************************************************************/ - -/* p is the port number (0,1,2,3) - * o is the pin offset (0-31) inside the port - * n is the absolute number of a pin (0-124), regardless of the port - * m is the interrupt manner (low/high/falling/rising) - */ - -#define __gpio_port_data(p) ( REG_GPIO_GPDR(p) ) - -#define __gpio_port_as_output(p, o) \ -do { \ - unsigned int tmp; \ - REG_GPIO_GPIER(p) &= ~(1 << (o)); \ - REG_GPIO_GPDIR(p) |= (1 << (o)); \ - if (o < 16) { \ - tmp = REG_GPIO_GPALR(p); \ - tmp &= ~(3 << ((o) << 1)); \ - REG_GPIO_GPALR(p) = tmp; \ - } else { \ - tmp = REG_GPIO_GPAUR(p); \ - tmp &= ~(3 << (((o) - 16)<< 1)); \ - REG_GPIO_GPAUR(p) = tmp; \ - } \ -} while (0) - -#define __gpio_port_as_input(p, o) \ -do { \ - unsigned int tmp; \ - REG_GPIO_GPIER(p) &= ~(1 << (o)); \ - REG_GPIO_GPDIR(p) &= ~(1 << (o)); \ - if (o < 16) { \ - tmp = REG_GPIO_GPALR(p); \ - tmp &= ~(3 << ((o) << 1)); \ - REG_GPIO_GPALR(p) = tmp; \ - } else { \ - tmp = REG_GPIO_GPAUR(p); \ - tmp &= ~(3 << (((o) - 16)<< 1)); \ - REG_GPIO_GPAUR(p) = tmp; \ - } \ -} while (0) - -#define __gpio_as_output(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_output(p, o); \ -} while (0) - -#define __gpio_as_input(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_input(p, o); \ -} while (0) - -#define __gpio_set_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_data(p) |= (1 << o); \ -} while (0) - -#define __gpio_clear_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_data(p) &= ~(1 << o); \ -} while (0) - -static __inline__ unsigned int __gpio_get_pin(unsigned int n) -{ - unsigned int p, o; - p = (n) / 32; - o = (n) % 32; - if (__gpio_port_data(p) & (1 << o)) - return 1; - else - return 0; -} - - -#define __gpio_set_irq_detect_manner(p, o, m) \ -do { \ - unsigned int tmp; \ - if (o < 16) { \ - tmp = REG_GPIO_GPIDLR(p); \ - tmp &= ~(3 << ((o) << 1)); \ - tmp |= ((m) << ((o) << 1)); \ - REG_GPIO_GPIDLR(p) = tmp; \ - } else { \ - o -= 16; \ - tmp = REG_GPIO_GPIDUR(p); \ - tmp &= ~(3 << ((o) << 1)); \ - tmp |= ((m) << ((o) << 1)); \ - REG_GPIO_GPIDUR(p) = tmp; \ - } \ -} while (0) - -#define __gpio_port_as_irq(p, o, m) \ -do { \ - __gpio_set_irq_detect_manner(p, o, m); \ - __gpio_port_as_input(p, o); \ - REG_GPIO_GPIER(p) |= (1 << o); \ -} while (0) - -#define __gpio_as_irq(n, m) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_irq(p, o, m); \ -} while (0) - - -#define __gpio_as_irq_high_level(n) __gpio_as_irq(n, GPIO_IRQ_HILEVEL) -#define __gpio_as_irq_low_level(n) __gpio_as_irq(n, GPIO_IRQ_LOLEVEL) -#define __gpio_as_irq_fall_edge(n) __gpio_as_irq(n, GPIO_IRQ_FALLEDG) -#define __gpio_as_irq_rise_edge(n) __gpio_as_irq(n, GPIO_IRQ_RAISEDG) - - -#define __gpio_mask_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPIER(p) &= ~(1 << o); \ -} while (0) - -#define __gpio_unmask_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPIER(n) |= (1 << o); \ -} while (0) - -#define __gpio_ack_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPFR(p) |= (1 << o); \ -} while (0) - - -static __inline__ unsigned int __gpio_get_irq(void) -{ - unsigned int tmp, i; - - tmp = REG_GPIO_GPFR(3); - for (i=0; i<32; i++) - if (tmp & (1 << i)) - return 0x60 + i; - tmp = REG_GPIO_GPFR(2); - for (i=0; i<32; i++) - if (tmp & (1 << i)) - return 0x40 + i; - tmp = REG_GPIO_GPFR(1); - for (i=0; i<32; i++) - if (tmp & (1 << i)) - return 0x20 + i; - tmp = REG_GPIO_GPFR(0); - for (i=0; i<32; i++) - if (tmp & (1 << i)) - return i; - return 0; -} - -#define __gpio_group_irq(n) \ -({ \ - register int tmp, i; \ - tmp = REG_GPIO_GPFR((n)); \ - for (i=31;i>=0;i--) \ - if (tmp & (1 << i)) \ - break; \ - i; \ -}) - -#define __gpio_enable_pullupdown(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPPUR(p) |= (1 << o); \ -} while (0) - -#define __gpio_disable_pullupdown(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_GPPUR(p) &= ~(1 << o); \ -} while (0) - -/* Init the alternate function pins */ - - -#define __gpio_as_ssi() \ -do { \ - REG_GPIO_GPALR(2) &= 0xFC00FFFF; \ - REG_GPIO_GPALR(2) |= 0x01550000; \ -} while (0) - -#define __gpio_as_uart3() \ -do { \ - REG_GPIO_GPAUR(0) &= 0xFFFF0000; \ - REG_GPIO_GPAUR(0) |= 0x00005555; \ -} while (0) - -#define __gpio_as_uart2() \ -do { \ - REG_GPIO_GPALR(3) &= 0x3FFFFFFF; \ - REG_GPIO_GPALR(3) |= 0x40000000; \ - REG_GPIO_GPAUR(3) &= 0xF3FFFFFF; \ - REG_GPIO_GPAUR(3) |= 0x04000000; \ -} while (0) - -#define __gpio_as_uart1() \ -do { \ - REG_GPIO_GPAUR(0) &= 0xFFF0FFFF; \ - REG_GPIO_GPAUR(0) |= 0x00050000; \ -} while (0) - -#define __gpio_as_uart0() \ -do { \ - REG_GPIO_GPAUR(3) &= 0x0FFFFFFF; \ - REG_GPIO_GPAUR(3) |= 0x50000000; \ -} while (0) - - -#define __gpio_as_scc0() \ -do { \ - REG_GPIO_GPALR(2) &= 0xFFFFFFCC; \ - REG_GPIO_GPALR(2) |= 0x00000011; \ -} while (0) - -#define __gpio_as_scc1() \ -do { \ - REG_GPIO_GPALR(2) &= 0xFFFFFF33; \ - REG_GPIO_GPALR(2) |= 0x00000044; \ -} while (0) - -#define __gpio_as_scc() \ -do { \ - __gpio_as_scc0(); \ - __gpio_as_scc1(); \ -} while (0) - -#define __gpio_as_dma() \ -do { \ - REG_GPIO_GPALR(0) &= 0x00FFFFFF; \ - REG_GPIO_GPALR(0) |= 0x55000000; \ - REG_GPIO_GPAUR(0) &= 0xFF0FFFFF; \ - REG_GPIO_GPAUR(0) |= 0x00500000; \ -} while (0) - -#define __gpio_as_msc() \ -do { \ - REG_GPIO_GPALR(1) &= 0xFFFF000F; \ - REG_GPIO_GPALR(1) |= 0x00005550; \ -} while (0) - -#define __gpio_as_pcmcia() \ -do { \ - REG_GPIO_GPAUR(2) &= 0xF000FFFF; \ - REG_GPIO_GPAUR(2) |= 0x05550000; \ -} while (0) - -#define __gpio_as_emc() \ -do { \ - REG_GPIO_GPALR(2) &= 0x3FFFFFFF; \ - REG_GPIO_GPALR(2) |= 0x40000000; \ - REG_GPIO_GPAUR(2) &= 0xFFFF0000; \ - REG_GPIO_GPAUR(2) |= 0x00005555; \ -} while (0) - -#define __gpio_as_lcd_slave() \ -do { \ - REG_GPIO_GPALR(1) &= 0x0000FFFF; \ - REG_GPIO_GPALR(1) |= 0x55550000; \ - REG_GPIO_GPAUR(1) &= 0x00000000; \ - REG_GPIO_GPAUR(1) |= 0x55555555; \ -} while (0) - -#define __gpio_as_lcd_master() \ -do { \ - REG_GPIO_GPALR(1) &= 0x0000FFFF; \ - REG_GPIO_GPALR(1) |= 0x55550000; \ - REG_GPIO_GPAUR(1) &= 0x00000000; \ - REG_GPIO_GPAUR(1) |= 0x556A5555; \ -} while (0) - -#define __gpio_as_usb() \ -do { \ - REG_GPIO_GPAUR(0) &= 0x00FFFFFF; \ - REG_GPIO_GPAUR(0) |= 0x55000000; \ -} while (0) - -#define __gpio_as_ac97() \ -do { \ - REG_GPIO_GPALR(2) &= 0xC3FF03FF; \ - REG_GPIO_GPALR(2) |= 0x24005400; \ -} while (0) - -#define __gpio_as_i2s_slave() \ -do { \ - REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ - REG_GPIO_GPALR(2) |= 0x14005100; \ -} while (0) - -#define __gpio_as_i2s_master() \ -do { \ - REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ - REG_GPIO_GPALR(2) |= 0x28005100; \ -} while (0) - -#define __gpio_as_eth() \ -do { \ - REG_GPIO_GPAUR(3) &= 0xFC000000; \ - REG_GPIO_GPAUR(3) |= 0x01555555; \ -} while (0) - -#define __gpio_as_pwm() \ -do { \ - REG_GPIO_GPAUR(2) &= 0x0FFFFFFF; \ - REG_GPIO_GPAUR(2) |= 0x50000000; \ -} while (0) - -#define __gpio_as_ps2() \ -do { \ - REG_GPIO_GPALR(1) &= 0xFFFFFFF0; \ - REG_GPIO_GPALR(1) |= 0x00000005; \ -} while (0) - -#define __gpio_as_uprt() \ -do { \ - REG_GPIO_GPALR(1) &= 0x0000000F; \ - REG_GPIO_GPALR(1) |= 0x55555550; \ - REG_GPIO_GPALR(3) &= 0xC0000000; \ - REG_GPIO_GPALR(3) |= 0x15555555; \ -} while (0) - -#define __gpio_as_cim() \ -do { \ - REG_GPIO_GPALR(0) &= 0xFF000000; \ - REG_GPIO_GPALR(0) |= 0x00555555; \ -} while (0) - -/*************************************************************************** - * HARB - ***************************************************************************/ - -#define __harb_usb0_udc() \ -do { \ - REG_HARB_HAPOR &= ~HARB_HAPOR_UCHSEL; \ -} while (0) - -#define __harb_usb0_uhc() \ -do { \ - REG_HARB_HAPOR |= HARB_HAPOR_UCHSEL; \ -} while (0) - -#define __harb_set_priority(n) \ -do { \ - REG_HARB_HAPOR = ((REG_HARB_HAPOR & ~HARB_HAPOR_PRIO_MASK) | n); \ -} while (0) - -/*************************************************************************** - * I2C - ***************************************************************************/ - -#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) -#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) - -#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) -#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) -#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) -#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) - -#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) -#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) -#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) - -#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) -#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) -#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) - -#define __i2c_set_clk(dev_clk, i2c_clk) \ - ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) - -#define __i2c_read() ( REG_I2C_DR ) -#define __i2c_write(val) ( REG_I2C_DR = (val) ) - -/*************************************************************************** - * UDC - ***************************************************************************/ - -#define __udc_set_16bit_phy() ( REG_UDC_DevCFGR |= UDC_DevCFGR_PI ) -#define __udc_set_8bit_phy() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_PI ) - -#define __udc_enable_sync_frame() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SS ) -#define __udc_disable_sync_frame() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SS ) - -#define __udc_self_powered() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SP ) -#define __udc_bus_powered() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SP ) - -#define __udc_enable_remote_wakeup() ( REG_UDC_DevCFGR |= UDC_DevCFGR_RW ) -#define __udc_disable_remote_wakeup() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_RW ) - -#define __udc_set_speed_high() \ -do { \ - REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ - REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; \ -} while (0) - -#define __udc_set_speed_full() \ -do { \ - REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ - REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; \ -} while (0) - -#define __udc_set_speed_low() \ -do { \ - REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ - REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; \ -} while (0) - - -#define __udc_set_dma_mode() ( REG_UDC_DevCR |= UDC_DevCR_DM ) -#define __udc_set_slave_mode() ( REG_UDC_DevCR &= ~UDC_DevCR_DM ) -#define __udc_set_big_endian() ( REG_UDC_DevCR |= UDC_DevCR_BE ) -#define __udc_set_little_endian() ( REG_UDC_DevCR &= ~UDC_DevCR_BE ) -#define __udc_generate_resume() ( REG_UDC_DevCR |= UDC_DevCR_RES ) -#define __udc_clear_resume() ( REG_UDC_DevCR &= ~UDC_DevCR_RES ) - - -#define __udc_get_enumarated_speed() ( REG_UDC_DevSR & UDC_DevSR_ENUMSPD_MASK ) -#define __udc_suspend_detected() ( REG_UDC_DevSR & UDC_DevSR_SUSP ) -#define __udc_get_alternate_setting() ( (REG_UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT ) -#define __udc_get_interface_number() ( (REG_UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT ) -#define __udc_get_config_number() ( (REG_UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT ) - - -#define __udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF ) -#define __udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US ) -#define __udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR ) -#define __udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI ) -#define __udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC ) - -#define __udc_clear_sof() ( REG_UDC_DevIntR |= UDC_DevIntR_SOF ) -#define __udc_clear_usb_suspend() ( REG_UDC_DevIntR |= UDC_DevIntR_US ) -#define __udc_clear_usb_reset() ( REG_UDC_DevIntR |= UDC_DevIntR_UR ) -#define __udc_clear_set_interface() ( REG_UDC_DevIntR |= UDC_DevIntR_SI ) -#define __udc_clear_set_config() ( REG_UDC_DevIntR |= UDC_DevIntR_SC ) - -#define __udc_mask_sof() ( REG_UDC_DevIntMR |= UDC_DevIntR_SOF ) -#define __udc_mask_usb_suspend() ( REG_UDC_DevIntMR |= UDC_DevIntR_US ) -#define __udc_mask_usb_reset() ( REG_UDC_DevIntMR |= UDC_DevIntR_UR ) -#define __udc_mask_set_interface() ( REG_UDC_DevIntMR |= UDC_DevIntR_SI ) -#define __udc_mask_set_config() ( REG_UDC_DevIntMR |= UDC_DevIntR_SC ) -#define __udc_mask_all_dev_intrs() \ - ( REG_UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | \ - UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC ) - -#define __udc_unmask_sof() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SOF ) -#define __udc_unmask_usb_suspend() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_US ) -#define __udc_unmask_usb_reset() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_UR ) -#define __udc_unmask_set_interface() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SI ) -#define __udc_unmask_set_config() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SC ) -#if 0 -#define __udc_unmask_all_dev_intrs() \ - ( REG_UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | \ - UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) ) -#else -#define __udc_unmask_all_dev_intrs() \ - ( REG_UDC_DevIntMR = 0x00000000 ) -#endif - - -#define __udc_ep0out_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 ) -#define __udc_ep5out_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 ) -#define __udc_ep6out_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 ) -#define __udc_ep7out_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 ) - -#define __udc_ep0in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 ) -#define __udc_ep1in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 ) -#define __udc_ep2in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 ) -#define __udc_ep3in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 ) -#define __udc_ep4in_irq_detected(epintr) \ - ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 ) - - -#define __udc_mask_ep0out_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) -#define __udc_mask_ep5out_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) -#define __udc_mask_ep6out_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) -#define __udc_mask_ep7out_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) - -#define __udc_unmask_ep0out_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) -#define __udc_unmask_ep5out_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) -#define __udc_unmask_ep6out_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) -#define __udc_unmask_ep7out_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) - -#define __udc_mask_ep0in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) ) -#define __udc_mask_ep1in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) ) -#define __udc_mask_ep2in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) ) -#define __udc_mask_ep3in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) ) -#define __udc_mask_ep4in_irq() \ - ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) ) - -#define __udc_unmask_ep0in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) ) -#define __udc_unmask_ep1in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) ) -#define __udc_unmask_ep2in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) ) -#define __udc_unmask_ep3in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) ) -#define __udc_unmask_ep4in_irq() \ - ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) ) - -#define __udc_mask_all_ep_intrs() \ - ( REG_UDC_EPIntMR = 0xffffffff ) -#define __udc_unmask_all_ep_intrs() \ - ( REG_UDC_EPIntMR = 0x00000000 ) - - -/* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */ -#define __udc_config_endpoint_type() \ -do { \ - REG_UDC_EP0InCR = (REG_UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ - REG_UDC_EP0OutCR = (REG_UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ - REG_UDC_EP1InCR = (REG_UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR; \ - REG_UDC_EP2InCR = (REG_UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ - REG_UDC_EP3InCR = (REG_UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ - REG_UDC_EP4InCR = (REG_UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ - REG_UDC_EP5OutCR = (REG_UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ - REG_UDC_EP6OutCR = (REG_UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ - REG_UDC_EP7OutCR = (REG_UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ -} while (0) - -#define __udc_enable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR |= UDC_EPCR_SN ) -#define __udc_enable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR |= UDC_EPCR_SN ) -#define __udc_enable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR |= UDC_EPCR_SN ) -#define __udc_enable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR |= UDC_EPCR_SN ) - -#define __udc_disable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_SN ) -#define __udc_disable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_SN ) -#define __udc_disable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_SN ) -#define __udc_disable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_SN ) - -#define __udc_flush_ep0in_fifo() ( REG_UDC_EP0InCR |= UDC_EPCR_F ) -#define __udc_flush_ep1in_fifo() ( REG_UDC_EP1InCR |= UDC_EPCR_F ) -#define __udc_flush_ep2in_fifo() ( REG_UDC_EP2InCR |= UDC_EPCR_F ) -#define __udc_flush_ep3in_fifo() ( REG_UDC_EP3InCR |= UDC_EPCR_F ) -#define __udc_flush_ep4in_fifo() ( REG_UDC_EP4InCR |= UDC_EPCR_F ) - -#define __udc_unflush_ep0in_fifo() ( REG_UDC_EP0InCR &= ~UDC_EPCR_F ) -#define __udc_unflush_ep1in_fifo() ( REG_UDC_EP1InCR &= ~UDC_EPCR_F ) -#define __udc_unflush_ep2in_fifo() ( REG_UDC_EP2InCR &= ~UDC_EPCR_F ) -#define __udc_unflush_ep3in_fifo() ( REG_UDC_EP3InCR &= ~UDC_EPCR_F ) -#define __udc_unflush_ep4in_fifo() ( REG_UDC_EP4InCR &= ~UDC_EPCR_F ) - -#define __udc_enable_ep0in_stall() ( REG_UDC_EP0InCR |= UDC_EPCR_S ) -#define __udc_enable_ep0out_stall() ( REG_UDC_EP0OutCR |= UDC_EPCR_S ) -#define __udc_enable_ep1in_stall() ( REG_UDC_EP1InCR |= UDC_EPCR_S ) -#define __udc_enable_ep2in_stall() ( REG_UDC_EP2InCR |= UDC_EPCR_S ) -#define __udc_enable_ep3in_stall() ( REG_UDC_EP3InCR |= UDC_EPCR_S ) -#define __udc_enable_ep4in_stall() ( REG_UDC_EP4InCR |= UDC_EPCR_S ) -#define __udc_enable_ep5out_stall() ( REG_UDC_EP5OutCR |= UDC_EPCR_S ) -#define __udc_enable_ep6out_stall() ( REG_UDC_EP6OutCR |= UDC_EPCR_S ) -#define __udc_enable_ep7out_stall() ( REG_UDC_EP7OutCR |= UDC_EPCR_S ) - -#define __udc_disable_ep0in_stall() ( REG_UDC_EP0InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep0out_stall() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep1in_stall() ( REG_UDC_EP1InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep2in_stall() ( REG_UDC_EP2InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep3in_stall() ( REG_UDC_EP3InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep4in_stall() ( REG_UDC_EP4InCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep5out_stall() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep6out_stall() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_S ) -#define __udc_disable_ep7out_stall() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_S ) - - -#define __udc_ep0out_packet_size() \ - ( (REG_UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) -#define __udc_ep5out_packet_size() \ - ( (REG_UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) -#define __udc_ep6out_packet_size() \ - ( (REG_UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) -#define __udc_ep7out_packet_size() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) - -#define __udc_ep0in_received_intoken() ( (REG_UDC_EP0InSR & UDC_EPSR_IN) ) -#define __udc_ep1in_received_intoken() ( (REG_UDC_EP1InSR & UDC_EPSR_IN) ) -#define __udc_ep2in_received_intoken() ( (REG_UDC_EP2InSR & UDC_EPSR_IN) ) -#define __udc_ep3in_received_intoken() ( (REG_UDC_EP3InSR & UDC_EPSR_IN) ) -#define __udc_ep4in_received_intoken() ( (REG_UDC_EP4InSR & UDC_EPSR_IN) ) - -#define __udc_ep0out_received_none() \ - ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) -#define __udc_ep0out_received_data() \ - ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) -#define __udc_ep0out_received_setup() \ - ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) - -#define __udc_ep5out_received_none() \ - ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) -#define __udc_ep5out_received_data() \ - ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) -#define __udc_ep5out_received_setup() \ - ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) - -#define __udc_ep6out_received_none() \ - ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) -#define __udc_ep6out_received_data() \ - ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) -#define __udc_ep6out_received_setup() \ - ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) - -#define __udc_ep7out_received_none() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) -#define __udc_ep7out_received_data() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) -#define __udc_ep7out_received_setup() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) - -/* ep7out ISO only */ -#define __udc_ep7out_get_pid() \ - ( (REG_UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT ) - - -#define __udc_ep0in_set_buffer_size(n) ( REG_UDC_EP0InBSR = (n) ) -#define __udc_ep1in_set_buffer_size(n) ( REG_UDC_EP1InBSR = (n) ) -#define __udc_ep2in_set_buffer_size(n) ( REG_UDC_EP2InBSR = (n) ) -#define __udc_ep3in_set_buffer_size(n) ( REG_UDC_EP3InBSR = (n) ) -#define __udc_ep4in_set_buffer_size(n) ( REG_UDC_EP4InBSR = (n) ) - -#define __udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR ) -#define __udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR ) -#define __udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR ) -#define __udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR ) - - -#define __udc_ep0in_set_max_packet_size(n) ( REG_UDC_EP0InMPSR = (n) ) -#define __udc_ep0out_set_max_packet_size(n) ( REG_UDC_EP0OutMPSR = (n) ) -#define __udc_ep1in_set_max_packet_size(n) ( REG_UDC_EP1InMPSR = (n) ) -#define __udc_ep2in_set_max_packet_size(n) ( REG_UDC_EP2InMPSR = (n) ) -#define __udc_ep3in_set_max_packet_size(n) ( REG_UDC_EP3InMPSR = (n) ) -#define __udc_ep4in_set_max_packet_size(n) ( REG_UDC_EP4InMPSR = (n) ) -#define __udc_ep5out_set_max_packet_size(n) ( REG_UDC_EP5OutMPSR = (n) ) -#define __udc_ep6out_set_max_packet_size(n) ( REG_UDC_EP6OutMPSR = (n) ) -#define __udc_ep7out_set_max_packet_size(n) ( REG_UDC_EP7OutMPSR = (n) ) - -/* set to 0xFFFF for UDC */ -#define __udc_set_setup_command_address(n) ( REG_UDC_STCMAR = (n) ) - -/* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7) - * c: Configuration number to which this endpoint belongs - * i: Interface number to which this endpoint belongs - * a: Alternate setting to which this endpoint belongs - * p: max Packet size of this endpoint - */ - -#define __udc_ep0info_init(c,i,a,p) \ -do { \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL; \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP0InfR |= UDC_EPInfR_EPD_OUT; \ - REG_UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep1info_init(c,i,a,p) \ -do { \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP1InfR |= UDC_EPInfR_EPT_INTR; \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP1InfR |= UDC_EPInfR_EPD_IN; \ - REG_UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep2info_init(c,i,a,p) \ -do { \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP2InfR |= UDC_EPInfR_EPT_BULK; \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP2InfR |= UDC_EPInfR_EPD_IN; \ - REG_UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep3info_init(c,i,a,p) \ -do { \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP3InfR |= UDC_EPInfR_EPT_BULK; \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP3InfR |= UDC_EPInfR_EPD_IN; \ - REG_UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep4info_init(c,i,a,p) \ -do { \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP4InfR |= UDC_EPInfR_EPT_ISO; \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP4InfR |= UDC_EPInfR_EPD_IN; \ - REG_UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep5info_init(c,i,a,p) \ -do { \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP5InfR |= UDC_EPInfR_EPT_BULK; \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP5InfR |= UDC_EPInfR_EPD_OUT; \ - REG_UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep6info_init(c,i,a,p) \ -do { \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP6InfR |= UDC_EPInfR_EPT_BULK; \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP6InfR |= UDC_EPInfR_EPD_OUT; \ - REG_UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT); \ -} while (0) - -#define __udc_ep7info_init(c,i,a,p) \ -do { \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK; \ - REG_UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK; \ - REG_UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK; \ - REG_UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK; \ - REG_UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK; \ - REG_UDC_EP7InfR |= UDC_EPInfR_EPT_ISO; \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_EPD; \ - REG_UDC_EP7InfR |= UDC_EPInfR_EPD_OUT; \ - REG_UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK; \ - REG_UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT); \ -} while (0) - - -/*************************************************************************** - * DMAC - ***************************************************************************/ - -/* n is the DMA channel (0 - 7) */ - -#define __dmac_enable_all_channels() \ - ( REG_DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN ) -#define __dmac_disable_all_channels() \ - ( REG_DMAC_DMACR &= ~DMAC_DMACR_DME ) - -/* p=0,1,2,3 */ -#define __dmac_set_priority(p) \ -do { \ - REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ - REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ -} while (0) - -#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HTR ) -#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AER ) - -#define __dmac_enable_channel(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE ) -#define __dmac_disable_channel(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE ) -#define __dmac_channel_enabled(n) \ - ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_CHDE ) - -#define __dmac_channel_enable_irq(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE ) -#define __dmac_channel_disable_irq(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE ) - -#define __dmac_channel_transmit_halt_detected(n) \ - ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_HLT ) -#define __dmac_channel_transmit_end_detected(n) \ - ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_TC ) -#define __dmac_channel_address_error_detected(n) \ - ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_AR ) - -#define __dmac_channel_clear_transmit_halt(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) -#define __dmac_channel_clear_transmit_end(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC ) -#define __dmac_channel_clear_address_error(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) - -#define __dmac_channel_set_single_mode(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM ) -#define __dmac_channel_set_block_mode(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TM ) - -#define __dmac_channel_set_transfer_unit_32bit(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32b; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_16bit(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16b; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_8bit(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_8b; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_16byte(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16B; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_32byte(n) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32B; \ -} while (0) - -/* w=8,16,32 */ -#define __dmac_channel_set_dest_port_width(n,w) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DWDH_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DWDH_##w; \ -} while (0) - -/* w=8,16,32 */ -#define __dmac_channel_set_src_port_width(n,w) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ - REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SWDH_##w; \ -} while (0) - -/* v=0-15 */ -#define __dmac_channel_set_rdil(n,v) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_RDIL_MASK; \ - REG_DMAC_DCCSR(n) |= ((v) << DMAC_DCCSR_RDIL_BIT); \ -} while (0) - -#define __dmac_channel_dest_addr_fixed(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM ) -#define __dmac_channel_dest_addr_increment(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DAM ) - -#define __dmac_channel_src_addr_fixed(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM ) -#define __dmac_channel_src_addr_increment(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SAM ) - -#define __dmac_channel_set_eop_high(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM ) -#define __dmac_channel_set_eop_low(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM ) - -#define __dmac_channel_set_erdm(n,m) \ -do { \ - REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ - REG_DMAC_DCCSR(n) |= ((m) << DMAC_DCCSR_ERDM_BIT); \ -} while (0) - -#define __dmac_channel_set_eackm(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM ) -#define __dmac_channel_clear_eackm(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM ) - -#define __dmac_channel_set_eacks(n) \ - ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS ) -#define __dmac_channel_clear_eacks(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS ) - - -#define __dmac_channel_irq_detected(n) \ - ( REG_DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) ) - -static __inline__ int __dmac_get_irq(void) -{ - int i; - for (i=0;i> AIC_SR_TFL_BIT ) -#define __aic_get_receive_count() \ - ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) - -#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) -#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) -#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) -#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) -#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) - -#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) - -#define CODEC_READ_CMD (1 << 19) -#define CODEC_WRITE_CMD (0 << 19) -#define CODEC_REG_INDEX_BIT 12 -#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ -#define CODEC_REG_DATA_BIT 4 -#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ - -#define __ac97_out_rcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ -} while (0) - -#define __ac97_out_wcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ -} while (0) - -#define __ac97_out_data(value) \ -do { \ - REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ -} while (0) - -#define __ac97_in_data() \ - ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) - -#define __ac97_in_status_addr() \ - ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) - -#define __i2s_set_sample_rate(i2sclk, sync) \ - ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) - -#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) -#define __aic_read_rfifo() ( REG_AIC_DR ) - -// -// Define next ops for AC97 compatible -// - -#define AC97_ACSR AIC_ACSR - -#define __ac97_enable() __aic_enable(); __aic_select_ac97() -#define __ac97_disable() __aic_disable() -#define __ac97_reset() __aic_reset() - -#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __ac97_enable_record() __aic_enable_record() -#define __ac97_disable_record() __aic_disable_record() -#define __ac97_enable_replay() __aic_enable_replay() -#define __ac97_disable_replay() __aic_disable_replay() -#define __ac97_enable_loopback() __aic_enable_loopback() -#define __ac97_disable_loopback() __aic_disable_loopback() - -#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() -#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() -#define __ac97_enable_receive_dma() __aic_enable_receive_dma() -#define __ac97_disable_receive_dma() __aic_disable_receive_dma() - -#define __ac97_transmit_request() __aic_transmit_request() -#define __ac97_receive_request() __aic_receive_request() -#define __ac97_transmit_underrun() __aic_transmit_underrun() -#define __ac97_receive_overrun() __aic_receive_overrun() - -#define __ac97_clear_errors() __aic_clear_errors() - -#define __ac97_get_transmit_resident() __aic_get_transmit_resident() -#define __ac97_get_receive_count() __aic_get_receive_count() - -#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() -#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() -#define __ac97_enable_receive_intr() __aic_enable_receive_intr() -#define __ac97_disable_receive_intr() __aic_disable_receive_intr() - -#define __ac97_write_tfifo(v) __aic_write_tfifo(v) -#define __ac97_read_rfifo() __aic_read_rfifo() - -// -// Define next ops for I2S compatible -// - -#define I2S_ACSR AIC_I2SSR - -#define __i2s_enable() __aic_enable(); __aic_select_i2s() -#define __i2s_disable() __aic_disable() -#define __i2s_reset() __aic_reset() - -#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __i2s_enable_record() __aic_enable_record() -#define __i2s_disable_record() __aic_disable_record() -#define __i2s_enable_replay() __aic_enable_replay() -#define __i2s_disable_replay() __aic_disable_replay() -#define __i2s_enable_loopback() __aic_enable_loopback() -#define __i2s_disable_loopback() __aic_disable_loopback() - -#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() -#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() -#define __i2s_enable_receive_dma() __aic_enable_receive_dma() -#define __i2s_disable_receive_dma() __aic_disable_receive_dma() - -#define __i2s_transmit_request() __aic_transmit_request() -#define __i2s_receive_request() __aic_receive_request() -#define __i2s_transmit_underrun() __aic_transmit_underrun() -#define __i2s_receive_overrun() __aic_receive_overrun() - -#define __i2s_clear_errors() __aic_clear_errors() - -#define __i2s_get_transmit_resident() __aic_get_transmit_resident() -#define __i2s_get_receive_count() __aic_get_receive_count() - -#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() -#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() -#define __i2s_enable_receive_intr() __aic_enable_receive_intr() -#define __i2s_disable_receive_intr() __aic_disable_receive_intr() - -#define __i2s_write_tfifo(v) __aic_write_tfifo(v) -#define __i2s_read_rfifo() __aic_read_rfifo() - -#define __i2s_reset_codec() \ - do { \ - __gpio_as_output(111); /* SDATA_OUT */ \ - __gpio_as_input(110); /* SDATA_IN */ \ - __gpio_as_output(112); /* SYNC */ \ - __gpio_as_output(114); /* RESET# */ \ - __gpio_clear_pin(111); \ - __gpio_clear_pin(110); \ - __gpio_clear_pin(112); \ - __gpio_clear_pin(114); \ - __gpio_as_i2s_master(); \ - } while (0) - - -/*************************************************************************** - * LCD - ***************************************************************************/ - -#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) -#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) - -#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) -#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) - -/* n=1,2,4,8,16 */ -#define __lcd_set_bpp(n) \ - ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) - -/* n=4,8,16 */ -#define __lcd_set_burst_length(n) \ -do { \ - REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ - REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ -} while (0) - -#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) -#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) - -#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) -#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) - -/* n=2,4,16 */ -#define __lcd_set_stn_frc(n) \ -do { \ - REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ - REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ -} while (0) - - -#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) -#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) - -#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) -#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) - -#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) -#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) - -#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) -#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) - -#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) -#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) - -#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) -#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) - -#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) -#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) - -#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) -#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) - -#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) -#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) - - -/* LCD status register indication */ - -#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) -#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) -#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) -#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) -#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) -#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) -#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) - -#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) -#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) -#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) - -#define __lcd_panel_white() ( REG_LCD_DEV |= LCD_DEV_WHITE ) -#define __lcd_panel_black() ( REG_LCD_DEV &= ~LCD_DEV_WHITE ) - -/* n=1,2,4,8 for single mono-STN - * n=4,8 for dual mono-STN - */ -#define __lcd_set_panel_datawidth(n) \ -do { \ - REG_LCD_DEV &= ~LCD_DEV_PDW_MASK; \ - REG_LCD_DEV |= LCD_DEV_PDW_n##; \ -} while (0) - -/* m=LCD_DEV_MODE_GENERUIC_TFT_xxx */ -#define __lcd_set_panel_mode(m) \ -do { \ - REG_LCD_DEV &= ~LCD_DEV_MODE_MASK; \ - REG_LCD_DEV |= (m); \ -} while(0) - -/* n = 0-255 */ -#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) -#define __lcd_set_ac_bias(n) \ -do { \ - REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ - REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ -} while(0) - -#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) -#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) - -#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) -#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) - -#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) -#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) - -#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) -#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) - -#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) -#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) - -#define __lcd_vsync_get_vps() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) - -#define __lcd_vsync_get_vpe() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) -#define __lcd_vsync_set_vpe(n) \ -do { \ - REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ - REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ -} while (0) - -#define __lcd_hsync_get_hps() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) -#define __lcd_hsync_set_hps(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ -} while (0) - -#define __lcd_hsync_get_hpe() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) -#define __lcd_hsync_set_hpe(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ -} while (0) - -#define __lcd_vat_get_ht() \ - ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) -#define __lcd_vat_set_ht(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ -} while (0) - -#define __lcd_vat_get_vt() \ - ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) -#define __lcd_vat_set_vt(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ -} while (0) - -#define __lcd_dah_get_hds() \ - ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) -#define __lcd_dah_set_hds(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ -} while (0) - -#define __lcd_dah_get_hde() \ - ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) -#define __lcd_dah_set_hde(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ -} while (0) - -#define __lcd_dav_get_vds() \ - ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) -#define __lcd_dav_set_vds(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ -} while (0) - -#define __lcd_dav_get_vde() \ - ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) -#define __lcd_dav_set_vde(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ -} while (0) - -#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) -#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) -#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) -#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) - -#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) -#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) -#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) -#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) - -#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) -#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) - -#define __lcd_cmd0_get_len() \ - ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) -#define __lcd_cmd1_get_len() \ - ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) - - - -/*************************************************************************** - * DES - ***************************************************************************/ - - -/*************************************************************************** - * CPM - ***************************************************************************/ -#define __cpm_plcr1_fd() \ - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT) -#define __cpm_plcr1_rd() \ - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT) -#define __cpm_plcr1_od() \ - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT) -#define __cpm_cfcr_mfr() \ - ((REG_CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT) -#define __cpm_cfcr_pfr() \ - ((REG_CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT) -#define __cpm_cfcr_sfr() \ - ((REG_CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT) -#define __cpm_cfcr_ifr() \ - ((REG_CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT) - -static __inline__ unsigned int __cpm_divisor_encode(unsigned int n) -{ - unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32}; - int i; - for (i=0;i<10;i++) - if (n < encode[i]) - break; - return i; -} - -#define __cpm_set_mclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_MFR_MASK) | \ - ((n) << (CPM_CFCR_MFR_BIT)); \ -} while (0) - -#define __cpm_set_pclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_PFR_MASK) | \ - ((n) << (CPM_CFCR_PFR_BIT)); \ -} while (0) - -#define __cpm_set_sclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_SFR_MASK) | \ - ((n) << (CPM_CFCR_SFR_BIT)); \ -} while (0) - -#define __cpm_set_iclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_IFR_MASK) | \ - ((n) << (CPM_CFCR_IFR_BIT)); \ -} while (0) - -#define __cpm_set_lcdclk_div(n) \ -do { \ - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_LFR_MASK) | \ - ((n) << (CPM_CFCR_LFR_BIT)); \ -} while (0) - -#define __cpm_enable_cko1() (REG_CPM_CFCR |= CPM_CFCR_CKOEN1) -#define __cpm_enable_cko2() (REG_CPM_CFCR |= CPM_CFCR_CKOEN2) -#define __cpm_disable_cko1() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN1) -#define __cpm_disable_cko2() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN2) - -#define __cpm_idle_mode() \ - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ - CPM_LPCR_LPM_IDLE) -#define __cpm_sleep_mode() \ - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ - CPM_LPCR_LPM_SLEEP) -#define __cpm_hibernate_mode() \ - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ - CPM_LPCR_LPM_HIBERNATE) - -#define __cpm_stop_uart(n) \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UART##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_pwm(n) \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_PWM##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_aic(n) \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_AIC##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_ost() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_OST << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_rtc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_RTC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_dmac() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_DMAC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_uhc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UHC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_lcd() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_LCD << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_i2c() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_I2C << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_ssi() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_SSI << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_msc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_MSC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_scc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_SCC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_fir() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_FIR << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_des() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_DES << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_eth() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_eth << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_ps2() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_PS2 << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_cim() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_CIM << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_udc() \ - (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UDC << CPM_MSCR_MSTP_BIT)) -#define __cpm_stop_all() (REG_CPM_MSCR = 0xffffffff) - -#define __cpm_start_uart(n) \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UART##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_pwm(n) \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_PWM##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_aic(n) \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_AIC##n << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_ost() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_OST << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_rtc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_RTC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_dmac() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_DMAC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_uhc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UHC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_lcd() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_LCD << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_i2c() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_I2C << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_ssi() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_SSI << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_msc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_MSC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_scc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_SCC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_fir() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_FIR << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_des() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_DES << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_eth() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_ETH << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_ps2() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_PS2 << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_cim() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_CIM << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_udc() \ - (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UDC << CPM_MSCR_MSTP_BIT)) -#define __cpm_start_all() (REG_CPM_MSCR = 0x00000000) - - -/*************************************************************************** - * SSI - ***************************************************************************/ - -#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) -#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) -#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) - -#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) - -#define __ssi_select_ce2() \ -do { \ - REG_SSI_CR0 |= SSI_CR0_FSEL; \ - REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ -} while (0) - -#define __ssi_select_gpc() \ -do { \ - REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ - REG_SSI_CR1 |= SSI_CR1_MULTS; \ -} while (0) - -#define __ssi_enable_tx_intr() \ - ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) - -#define __ssi_disable_tx_intr() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) - -#define __ssi_enable_rx_intr() \ - ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) - -#define __ssi_disable_rx_intr() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) - -#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) -#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) - -#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) -#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) - -#define __ssi_finish_receive() \ - ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) - -#define __ssi_disable_recvfinish() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) - -#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) -#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) - -#define __ssi_flush_fifo() \ - ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) - -#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) - -/* Motorola's SPI format, set 1 delay */ -#define __ssi_spi_format() \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ - REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ - REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ - REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ -} while (0) - -/* TI's SSP format, must clear SSI_CR1.UNFIN */ -#define __ssi_ssp_format() \ -do { \ - REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ - REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ -} while (0) - -/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ -#define __ssi_microwire_format() \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ - REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ - REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ - REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ - REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ -} while (0) - -/* CE# level (FRMHL), CE# in interval time (ITFRM), - clock phase and polarity (PHA POL), - interval time (SSIITR), interval characters/frame (SSIICR) */ - - /* frmhl,endian,mcom,flen,pha,pol MASK */ -#define SSICR1_MISC_MASK \ - ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ - | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ - -#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ -do { \ - REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ - REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ - (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ - ((pha) << 1) | (pol); \ -} while(0) - -/* Transfer with MSB or LSB first */ -#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) -#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) - -/* n = 2 - 17 */ -#define __ssi_set_frame_length(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | SSI_CR1_FLEN_##n##BIT) ) - -/* n = 1 - 16 */ -#define __ssi_set_microwire_command_length(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) - -/* Set the clock phase for SPI */ -#define __ssi_set_spi_clock_phase(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) - -/* Set the clock polarity for SPI */ -#define __ssi_set_spi_clock_polarity(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) - -/* n = 1,4,8,14 */ -#define __ssi_set_tx_trigger(n) \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ - REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ -} while (0) - -/* n = 1,4,8,14 */ -#define __ssi_set_rx_trigger(n) \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ - REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ -} while (0) - -#define __ssi_get_txfifo_count() \ - ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) - -#define __ssi_get_rxfifo_count() \ - ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) - -#define __ssi_clear_errors() \ - ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) - -#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) -#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) - -#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) -#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) -#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) - -#define __ssi_set_clk(dev_clk, ssi_clk) \ - ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) - -#define __ssi_receive_data() REG_SSI_DR -#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) - -/* - * CPU clocks - */ -#ifdef CFG_EXTAL -#define JZ_EXTAL CFG_EXTAL -#else -#define JZ_EXTAL 3686400 -#endif -#define JZ_EXTAL2 32768 /* RTC clock */ - -static __inline__ unsigned int __cpm_get_pllout(void) -{ - unsigned int nf, nr, no, pllout; - unsigned long plcr = REG_CPM_PLCR1; - unsigned long od[4] = {1, 2, 2, 4}; - if (plcr & CPM_PLCR1_PLL1EN) { - nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT; - nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT; - no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)]; - pllout = (JZ_EXTAL) / ((nr+2) * no) * (nf+2); - } else - pllout = JZ_EXTAL; - return pllout; -} - -static __inline__ unsigned int __cpm_get_iclk(void) -{ - unsigned int iclk; - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - unsigned long cfcr = REG_CPM_CFCR; - unsigned long plcr = REG_CPM_PLCR1; - if (plcr & CPM_PLCR1_PLL1EN) - iclk = __cpm_get_pllout() / - div[(cfcr & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT]; - else - iclk = JZ_EXTAL; - return iclk; -} - -static __inline__ unsigned int __cpm_get_sclk(void) -{ - unsigned int sclk; - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - unsigned long cfcr = REG_CPM_CFCR; - unsigned long plcr = REG_CPM_PLCR1; - if (plcr & CPM_PLCR1_PLL1EN) - sclk = __cpm_get_pllout() / - div[(cfcr & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT]; - else - sclk = JZ_EXTAL; - return sclk; -} - -static __inline__ unsigned int __cpm_get_mclk(void) -{ - unsigned int mclk; - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - unsigned long cfcr = REG_CPM_CFCR; - unsigned long plcr = REG_CPM_PLCR1; - if (plcr & CPM_PLCR1_PLL1EN) - mclk = __cpm_get_pllout() / - div[(cfcr & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT]; - else - mclk = JZ_EXTAL; - return mclk; -} - -static __inline__ unsigned int __cpm_get_devclk(void) -{ - unsigned int devclk; - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - unsigned long cfcr = REG_CPM_CFCR; - unsigned long plcr = REG_CPM_PLCR1; - if (plcr & CPM_PLCR1_PLL1EN) - devclk = __cpm_get_pllout() / - div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT]; - else - devclk = JZ_EXTAL; - return devclk; -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* __JZ4730_H__ */ diff --git a/nandprog/include/jz4740.h b/nandprog/include/jz4740.h deleted file mode 100644 index 3ae7142..0000000 --- a/nandprog/include/jz4740.h +++ /dev/null @@ -1,4525 +0,0 @@ -/* - * Include file for Ingenic Semiconductor's JZ4740 CPU. - */ -#ifndef __JZ4740_H__ -#define __JZ4740_H__ - -#ifndef __ASSEMBLY__ - -#define u32 unsigned int -#define u16 unsigned short -#define u8 unsigned char - -#define REG8(addr) *((volatile u8 *)(addr)) -#define REG16(addr) *((volatile u16 *)(addr)) -#define REG32(addr) *((volatile u32 *)(addr)) - -#else - -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) - -#endif /* !ASSEMBLY */ - -//---------------------------------------------------------------------- -// Boot ROM Specification -// - -/* NOR Boot config */ -#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ -#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ -#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ - -/* NAND Boot config */ -#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ -#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ -#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ -#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ - - -//---------------------------------------------------------------------- -// Register Definitions -// -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define TCU_BASE 0xB0002000 -#define WDT_BASE 0xB0002000 -#define RTC_BASE 0xB0003000 -//#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define ICDC_BASE 0xB0020000 -#define MSC_BASE 0xB0021000 -#define UART0_BASE 0xB0030000 -#define I2C_BASE 0xB0042000 -#define SSI_BASE 0xB0043000 -#define SADC_BASE 0xB0070000 -//#define EMC_BASE 0xB3010000 -#define DMAC_BASE 0xB3020000 -#define UHC_BASE 0xB3030000 -#define UDC_BASE 0xB3040000 -#define LCD_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define ETH_BASE 0xB3100000 - - -/************************************************************************* - * INTC (Interrupt Controller) - *************************************************************************/ -#define INTC_ISR (INTC_BASE + 0x00) -#define INTC_IMR (INTC_BASE + 0x04) -#define INTC_IMSR (INTC_BASE + 0x08) -#define INTC_IMCR (INTC_BASE + 0x0c) -#define INTC_IPR (INTC_BASE + 0x10) - -#define REG_INTC_ISR REG32(INTC_ISR) -#define REG_INTC_IMR REG32(INTC_IMR) -#define REG_INTC_IMSR REG32(INTC_IMSR) -#define REG_INTC_IMCR REG32(INTC_IMCR) -#define REG_INTC_IPR REG32(INTC_IPR) - -// 1st-level interrupts -#define IRQ_I2C 1 -#define IRQ_UHC 3 -#define IRQ_UART0 9 -#define IRQ_SADC 12 -#define IRQ_MSC 14 -#define IRQ_RTC 15 -#define IRQ_SSI 16 -#define IRQ_CIM 17 -#define IRQ_AIC 18 -#define IRQ_ETH 19 -#define IRQ_DMAC 20 -#define IRQ_TCU2 21 -#define IRQ_TCU1 22 -#define IRQ_TCU0 23 -#define IRQ_UDC 24 -#define IRQ_GPIO3 25 -#define IRQ_GPIO2 26 -#define IRQ_GPIO1 27 -#define IRQ_GPIO0 28 -#define IRQ_IPU 29 -#define IRQ_LCD 30 - -// 2nd-level interrupts -#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ -#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ - - -/************************************************************************* - * RTC - *************************************************************************/ -#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ -#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ -#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ -#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ - -#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ -#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ -#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ -#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ -#define RTC_HWSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ - -#define REG_RTC_RCR REG32(RTC_RCR) -#define REG_RTC_RSR REG32(RTC_RSR) -#define REG_RTC_RSAR REG32(RTC_RSAR) -#define REG_RTC_RGR REG32(RTC_RGR) -#define REG_RTC_HCR REG32(RTC_HCR) -#define REG_RTC_HWFCR REG32(RTC_HWFCR) -#define REG_RTC_HRCR REG32(RTC_HRCR) -#define REG_RTC_HWCR REG32(RTC_HWCR) -#define REG_RTC_HWSR REG32(RTC_HWSR) - -/* RTC Control Register */ -#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ -#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ -#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ -#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ -#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ -#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ -#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ - -/* RTC Regulator Register */ -#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ -#define RTC_RGR_ADJC_BIT 16 -#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) -#define RTC_RGR_NC1HZ_BIT 0 -#define RTC_REG_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) - -/* Hibernate Control Register */ -#define RTC_HCR_PD (1 << 0) /* Power Down */ - -/* Hibernate Wakeup Filter Counter Register */ -#define RTC_HWFCR_BIT 5 -#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) - -/* Hibernate Reset Counter Register */ -#define RTC_HRCR_BIT 5 -#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) - -/* Hibernate Wakeup Control Register */ -#define RTC_HWCR_WL (1 << 2) /* Wakeup pin level: 0-low 1-high */ -#define RTC_HWCR_EPIN (1 << 1) /* Wakeup pin wakeup enable */ -#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ - -/* Hibernate Wakeup Status Register */ -#define RTC_HWSR_HR (1 << 5) /* Hibernate reset */ -#define RTC_HWSR_POR (1 << 4) /* POR reset */ -#define RTC_HWSR_PIN (1 << 1) /* Wakeup pin status bit */ -#define RTC_HWSR_ALM (1 << 0) /* RTC alarm status bit */ - - -/************************************************************************* - * CPM (Clock reset and Power control Management) - *************************************************************************/ -#define CPM_CPCCR (CPM_BASE+0x00) -#define CPM_CPPCR (CPM_BASE+0x10) -#define CPM_I2SCDR (CPM_BASE+0x60) -#define CPM_LPCDR (CPM_BASE+0x64) -#define CPM_MSCCDR (CPM_BASE+0x68) -#define CPM_UHCCDR (CPM_BASE+0x6C) - -#define CPM_LCR (CPM_BASE+0x04) -#define CPM_CLKGR (CPM_BASE+0x20) -#define CPM_SCR (CPM_BASE+0x24) - -#define CPM_HCR (CPM_BASE+0x30) -#define CPM_HWFCR (CPM_BASE+0x34) -#define CPM_HRCR (CPM_BASE+0x38) -#define CPM_HWCR (CPM_BASE+0x3c) -#define CPM_HWSR (CPM_BASE+0x40) -#define CPM_HSPR (CPM_BASE+0x44) - -#define CPM_RSR (CPM_BASE+0x08) - - -#define REG_CPM_CPCCR REG32(CPM_CPCCR) -#define REG_CPM_CPPCR REG32(CPM_CPPCR) -#define REG_CPM_I2SCDR REG32(CPM_I2SCDR) -#define REG_CPM_LPCDR REG32(CPM_LPCDR) -#define REG_CPM_MSCCDR REG32(CPM_MSCCDR) -#define REG_CPM_UHCCDR REG32(CPM_UHCCDR) - -#define REG_CPM_LCR REG32(CPM_LCR) -#define REG_CPM_CLKGR REG32(CPM_CLKGR) -#define REG_CPM_SCR REG32(CPM_SCR) -#define REG_CPM_HCR REG32(CPM_HCR) -#define REG_CPM_HWFCR REG32(CPM_HWFCR) -#define REG_CPM_HRCR REG32(CPM_HRCR) -#define REG_CPM_HWCR REG32(CPM_HWCR) -#define REG_CPM_HWSR REG32(CPM_HWSR) -#define REG_CPM_HSPR REG32(CPM_HSPR) - -#define REG_CPM_RSR REG32(CPM_RSR) - - -/* Clock Control Register */ -#define CPM_CPCCR_I2CS (1 << 31) -#define CPM_CPCCR_CLKOEN (1 << 30) -#define CPM_CPCCR_UCS (1 << 29) -#define CPM_CPCCR_UDIV_BIT 23 -#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) -#define CPM_CPCCR_CE (1 << 22) -#define CPM_CPCCR_PCS (1 << 21) -#define CPM_CPCCR_LDIV_BIT 16 -#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) -#define CPM_CPCCR_MDIV_BIT 12 -#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) -#define CPM_CPCCR_PDIV_BIT 8 -#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) -#define CPM_CPCCR_HDIV_BIT 4 -#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) -#define CPM_CPCCR_CDIV_BIT 0 -#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) - -/* I2S Clock Divider Register */ -#define CPM_I2SCDR_I2SDIV_BIT 0 -#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) - -/* LCD Pixel Clock Divider Register */ -#define CPM_LPCDR_PIXDIV_BIT 0 -#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) - -/* MSC Clock Divider Register */ -#define CPM_MSCCDR_MSCDIV_BIT 0 -#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) - -/* PLL Control Register */ -#define CPM_CPPCR_PLLM_BIT 23 -#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) -#define CPM_CPPCR_PLLN_BIT 18 -#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) -#define CPM_CPPCR_PLLOD_BIT 16 -#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) -#define CPM_CPPCR_PLLS (1 << 10) -#define CPM_CPPCR_PLLBP (1 << 9) -#define CPM_CPPCR_PLLEN (1 << 8) -#define CPM_CPPCR_PLLST_BIT 0 -#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) - -/* Low Power Control Register */ -#define CPM_LCR_DOZE_DUTY_BIT 3 -#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) -#define CPM_LCR_DOZE_ON (1 << 2) -#define CPM_LCR_LPM_BIT 0 -#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) - #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) - #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) - -/* Clock Gate Register */ -#define CPM_CLKGR_UART1 (1 << 15) -#define CPM_CLKGR_UHC (1 << 14) -#define CPM_CLKGR_IPU (1 << 13) -#define CPM_CLKGR_DMAC (1 << 12) -#define CPM_CLKGR_UDC (1 << 11) -#define CPM_CLKGR_LCD (1 << 10) -#define CPM_CLKGR_CIM (1 << 9) -#define CPM_CLKGR_SADC (1 << 8) -#define CPM_CLKGR_MSC (1 << 7) -#define CPM_CLKGR_AIC1 (1 << 6) -#define CPM_CLKGR_AIC2 (1 << 5) -#define CPM_CLKGR_SSI (1 << 4) -#define CPM_CLKGR_I2C (1 << 3) -#define CPM_CLKGR_RTC (1 << 2) -#define CPM_CLKGR_TCU (1 << 1) -#define CPM_CLKGR_UART0 (1 << 0) - -/* Sleep Control Register */ -#define CPM_SCR_O1ST_BIT 8 -#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) -#define CPM_SCR_USBPHY_ENABLE (1 << 6) -#define CPM_SCR_OSC_ENABLE (1 << 4) - -/* Hibernate Control Register */ -#define CPM_HCR_PD (1 << 0) - -/* Wakeup Filter Counter Register in Hibernate Mode */ -#define CPM_HWFCR_TIME_BIT 0 -#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) - -/* Reset Counter Register in Hibernate Mode */ -#define CPM_HRCR_TIME_BIT 0 -#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) - -/* Wakeup Control Register in Hibernate Mode */ -#define CPM_HWCR_WLE_LOW (0 << 2) -#define CPM_HWCR_WLE_HIGH (1 << 2) -#define CPM_HWCR_PIN_WAKEUP (1 << 1) -#define CPM_HWCR_RTC_WAKEUP (1 << 0) - -/* Wakeup Status Register in Hibernate Mode */ -#define CPM_HWSR_WSR_PIN (1 << 1) -#define CPM_HWSR_WSR_RTC (1 << 0) - -/* Reset Status Register */ -#define CPM_RSR_HR (1 << 2) -#define CPM_RSR_WR (1 << 1) -#define CPM_RSR_PR (1 << 0) - - -/************************************************************************* - * TCU (Timer Counter Unit) - *************************************************************************/ -#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ -#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ -#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ -#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ -#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ -#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ -#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ -#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ -#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ -#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ -#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ -#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ -#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ -#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ -#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ -#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ -#define TCU_TDFR1 (TCU_BASE + 0x50) -#define TCU_TDHR1 (TCU_BASE + 0x54) -#define TCU_TCNT1 (TCU_BASE + 0x58) -#define TCU_TCSR1 (TCU_BASE + 0x5C) -#define TCU_TDFR2 (TCU_BASE + 0x60) -#define TCU_TDHR2 (TCU_BASE + 0x64) -#define TCU_TCNT2 (TCU_BASE + 0x68) -#define TCU_TCSR2 (TCU_BASE + 0x6C) -#define TCU_TDFR3 (TCU_BASE + 0x70) -#define TCU_TDHR3 (TCU_BASE + 0x74) -#define TCU_TCNT3 (TCU_BASE + 0x78) -#define TCU_TCSR3 (TCU_BASE + 0x7C) -#define TCU_TDFR4 (TCU_BASE + 0x80) -#define TCU_TDHR4 (TCU_BASE + 0x84) -#define TCU_TCNT4 (TCU_BASE + 0x88) -#define TCU_TCSR4 (TCU_BASE + 0x8C) -#define TCU_TDFR5 (TCU_BASE + 0x90) -#define TCU_TDHR5 (TCU_BASE + 0x94) -#define TCU_TCNT5 (TCU_BASE + 0x98) -#define TCU_TCSR5 (TCU_BASE + 0x9C) - -#define REG_TCU_TSR REG32(TCU_TSR) -#define REG_TCU_TSSR REG32(TCU_TSSR) -#define REG_TCU_TSCR REG32(TCU_TSCR) -#define REG_TCU_TER REG8(TCU_TER) -#define REG_TCU_TESR REG8(TCU_TESR) -#define REG_TCU_TECR REG8(TCU_TECR) -#define REG_TCU_TFR REG32(TCU_TFR) -#define REG_TCU_TFSR REG32(TCU_TFSR) -#define REG_TCU_TFCR REG32(TCU_TFCR) -#define REG_TCU_TMR REG32(TCU_TMR) -#define REG_TCU_TMSR REG32(TCU_TMSR) -#define REG_TCU_TMCR REG32(TCU_TMCR) -#define REG_TCU_TDFR0 REG16(TCU_TDFR0) -#define REG_TCU_TDHR0 REG16(TCU_TDHR0) -#define REG_TCU_TCNT0 REG16(TCU_TCNT0) -#define REG_TCU_TCSR0 REG16(TCU_TCSR0) -#define REG_TCU_TDFR1 REG16(TCU_TDFR1) -#define REG_TCU_TDHR1 REG16(TCU_TDHR1) -#define REG_TCU_TCNT1 REG16(TCU_TCNT1) -#define REG_TCU_TCSR1 REG16(TCU_TCSR1) -#define REG_TCU_TDFR2 REG16(TCU_TDFR2) -#define REG_TCU_TDHR2 REG16(TCU_TDHR2) -#define REG_TCU_TCNT2 REG16(TCU_TCNT2) -#define REG_TCU_TCSR2 REG16(TCU_TCSR2) -#define REG_TCU_TDFR3 REG16(TCU_TDFR3) -#define REG_TCU_TDHR3 REG16(TCU_TDHR3) -#define REG_TCU_TCNT3 REG16(TCU_TCNT3) -#define REG_TCU_TCSR3 REG16(TCU_TCSR3) -#define REG_TCU_TDFR4 REG16(TCU_TDFR4) -#define REG_TCU_TDHR4 REG16(TCU_TDHR4) -#define REG_TCU_TCNT4 REG16(TCU_TCNT4) -#define REG_TCU_TCSR4 REG16(TCU_TCSR4) - -// n = 0,1,2,3,4,5 -#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ -#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ -#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ -#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ - -#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) -#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) -#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) -#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) - -// Register definitions -#define TCU_TCSR_PWM_SD (1 << 9) -#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) -#define TCU_TCSR_PWM_EN (1 << 7) -#define TCU_TCSR_PRESCALE_BIT 3 -#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) - #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_EXT_EN (1 << 2) -#define TCU_TCSR_RTC_EN (1 << 1) -#define TCU_TCSR_PCK_EN (1 << 0) - -#define TCU_TER_TCEN5 (1 << 5) -#define TCU_TER_TCEN4 (1 << 4) -#define TCU_TER_TCEN3 (1 << 3) -#define TCU_TER_TCEN2 (1 << 2) -#define TCU_TER_TCEN1 (1 << 1) -#define TCU_TER_TCEN0 (1 << 0) - -#define TCU_TESR_TCST5 (1 << 5) -#define TCU_TESR_TCST4 (1 << 4) -#define TCU_TESR_TCST3 (1 << 3) -#define TCU_TESR_TCST2 (1 << 2) -#define TCU_TESR_TCST1 (1 << 1) -#define TCU_TESR_TCST0 (1 << 0) - -#define TCU_TECR_TCCL5 (1 << 5) -#define TCU_TECR_TCCL4 (1 << 4) -#define TCU_TECR_TCCL3 (1 << 3) -#define TCU_TECR_TCCL2 (1 << 2) -#define TCU_TECR_TCCL1 (1 << 1) -#define TCU_TECR_TCCL0 (1 << 0) - -#define TCU_TFR_HFLAG5 (1 << 21) -#define TCU_TFR_HFLAG4 (1 << 20) -#define TCU_TFR_HFLAG3 (1 << 19) -#define TCU_TFR_HFLAG2 (1 << 18) -#define TCU_TFR_HFLAG1 (1 << 17) -#define TCU_TFR_HFLAG0 (1 << 16) -#define TCU_TFR_FFLAG5 (1 << 5) -#define TCU_TFR_FFLAG4 (1 << 4) -#define TCU_TFR_FFLAG3 (1 << 3) -#define TCU_TFR_FFLAG2 (1 << 2) -#define TCU_TFR_FFLAG1 (1 << 1) -#define TCU_TFR_FFLAG0 (1 << 0) - -#define TCU_TFSR_HFLAG5 (1 << 21) -#define TCU_TFSR_HFLAG4 (1 << 20) -#define TCU_TFSR_HFLAG3 (1 << 19) -#define TCU_TFSR_HFLAG2 (1 << 18) -#define TCU_TFSR_HFLAG1 (1 << 17) -#define TCU_TFSR_HFLAG0 (1 << 16) -#define TCU_TFSR_FFLAG5 (1 << 5) -#define TCU_TFSR_FFLAG4 (1 << 4) -#define TCU_TFSR_FFLAG3 (1 << 3) -#define TCU_TFSR_FFLAG2 (1 << 2) -#define TCU_TFSR_FFLAG1 (1 << 1) -#define TCU_TFSR_FFLAG0 (1 << 0) - -#define TCU_TFCR_HFLAG5 (1 << 21) -#define TCU_TFCR_HFLAG4 (1 << 20) -#define TCU_TFCR_HFLAG3 (1 << 19) -#define TCU_TFCR_HFLAG2 (1 << 18) -#define TCU_TFCR_HFLAG1 (1 << 17) -#define TCU_TFCR_HFLAG0 (1 << 16) -#define TCU_TFCR_FFLAG5 (1 << 5) -#define TCU_TFCR_FFLAG4 (1 << 4) -#define TCU_TFCR_FFLAG3 (1 << 3) -#define TCU_TFCR_FFLAG2 (1 << 2) -#define TCU_TFCR_FFLAG1 (1 << 1) -#define TCU_TFCR_FFLAG0 (1 << 0) - -#define TCU_TMR_HMASK5 (1 << 21) -#define TCU_TMR_HMASK4 (1 << 20) -#define TCU_TMR_HMASK3 (1 << 19) -#define TCU_TMR_HMASK2 (1 << 18) -#define TCU_TMR_HMASK1 (1 << 17) -#define TCU_TMR_HMASK0 (1 << 16) -#define TCU_TMR_FMASK5 (1 << 5) -#define TCU_TMR_FMASK4 (1 << 4) -#define TCU_TMR_FMASK3 (1 << 3) -#define TCU_TMR_FMASK2 (1 << 2) -#define TCU_TMR_FMASK1 (1 << 1) -#define TCU_TMR_FMASK0 (1 << 0) - -#define TCU_TMSR_HMST5 (1 << 21) -#define TCU_TMSR_HMST4 (1 << 20) -#define TCU_TMSR_HMST3 (1 << 19) -#define TCU_TMSR_HMST2 (1 << 18) -#define TCU_TMSR_HMST1 (1 << 17) -#define TCU_TMSR_HMST0 (1 << 16) -#define TCU_TMSR_FMST5 (1 << 5) -#define TCU_TMSR_FMST4 (1 << 4) -#define TCU_TMSR_FMST3 (1 << 3) -#define TCU_TMSR_FMST2 (1 << 2) -#define TCU_TMSR_FMST1 (1 << 1) -#define TCU_TMSR_FMST0 (1 << 0) - -#define TCU_TMCR_HMCL5 (1 << 21) -#define TCU_TMCR_HMCL4 (1 << 20) -#define TCU_TMCR_HMCL3 (1 << 19) -#define TCU_TMCR_HMCL2 (1 << 18) -#define TCU_TMCR_HMCL1 (1 << 17) -#define TCU_TMCR_HMCL0 (1 << 16) -#define TCU_TMCR_FMCL5 (1 << 5) -#define TCU_TMCR_FMCL4 (1 << 4) -#define TCU_TMCR_FMCL3 (1 << 3) -#define TCU_TMCR_FMCL2 (1 << 2) -#define TCU_TMCR_FMCL1 (1 << 1) -#define TCU_TMCR_FMCL0 (1 << 0) - -#define TCU_TSR_WDTS (1 << 16) -#define TCU_TSR_STOP5 (1 << 5) -#define TCU_TSR_STOP4 (1 << 4) -#define TCU_TSR_STOP3 (1 << 3) -#define TCU_TSR_STOP2 (1 << 2) -#define TCU_TSR_STOP1 (1 << 1) -#define TCU_TSR_STOP0 (1 << 0) - -#define TCU_TSSR_WDTSS (1 << 16) -#define TCU_TSSR_STPS5 (1 << 5) -#define TCU_TSSR_STPS4 (1 << 4) -#define TCU_TSSR_STPS3 (1 << 3) -#define TCU_TSSR_STPS2 (1 << 2) -#define TCU_TSSR_STPS1 (1 << 1) -#define TCU_TSSR_STPS0 (1 << 0) - -#define TCU_TSSR_WDTSC (1 << 16) -#define TCU_TSSR_STPC5 (1 << 5) -#define TCU_TSSR_STPC4 (1 << 4) -#define TCU_TSSR_STPC3 (1 << 3) -#define TCU_TSSR_STPC2 (1 << 2) -#define TCU_TSSR_STPC1 (1 << 1) -#define TCU_TSSR_STPC0 (1 << 0) - - -/************************************************************************* - * WDT (WatchDog Timer) - *************************************************************************/ -#define WDT_TDR (WDT_BASE + 0x00) -#define WDT_TCER (WDT_BASE + 0x04) -#define WDT_TCNT (WDT_BASE + 0x08) -#define WDT_TCSR (WDT_BASE + 0x0C) - -#define REG_WDT_TDR REG16(WDT_TDR) -#define REG_WDT_TCER REG8(WDT_TCER) -#define REG_WDT_TCNT REG16(WDT_TCNT) -#define REG_WDT_TCSR REG16(WDT_TCSR) - -// Register definition -#define WDT_TCSR_PRESCALE_BIT 3 -#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - - -/************************************************************************* - * DMAC (DMA Controller) - *************************************************************************/ - -#define MAX_DMA_NUM 6 /* max 6 channels */ - -#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ -#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ -#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ -#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ -#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ -#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ -#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ -#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ -#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ -#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ -#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ - -// channel 0 -#define DMAC_DSAR0 DMAC_DSAR(0) -#define DMAC_DTAR0 DMAC_DTAR(0) -#define DMAC_DTCR0 DMAC_DTCR(0) -#define DMAC_DRSR0 DMAC_DRSR(0) -#define DMAC_DCCSR0 DMAC_DCCSR(0) -#define DMAC_DCMD0 DMAC_DCMD(0) -#define DMAC_DDA0 DMAC_DDA(0) - -// channel 1 -#define DMAC_DSAR1 DMAC_DSAR(1) -#define DMAC_DTAR1 DMAC_DTAR(1) -#define DMAC_DTCR1 DMAC_DTCR(1) -#define DMAC_DRSR1 DMAC_DRSR(1) -#define DMAC_DCCSR1 DMAC_DCCSR(1) -#define DMAC_DCMD1 DMAC_DCMD(1) -#define DMAC_DDA1 DMAC_DDA(1) - -// channel 2 -#define DMAC_DSAR2 DMAC_DSAR(2) -#define DMAC_DTAR2 DMAC_DTAR(2) -#define DMAC_DTCR2 DMAC_DTCR(2) -#define DMAC_DRSR2 DMAC_DRSR(2) -#define DMAC_DCCSR2 DMAC_DCCSR(2) -#define DMAC_DCMD2 DMAC_DCMD(2) -#define DMAC_DDA2 DMAC_DDA(2) - -// channel 3 -#define DMAC_DSAR3 DMAC_DSAR(3) -#define DMAC_DTAR3 DMAC_DTAR(3) -#define DMAC_DTCR3 DMAC_DTCR(3) -#define DMAC_DRSR3 DMAC_DRSR(3) -#define DMAC_DCCSR3 DMAC_DCCSR(3) -#define DMAC_DCMD3 DMAC_DCMD(3) -#define DMAC_DDA3 DMAC_DDA(3) - -// channel 4 -#define DMAC_DSAR4 DMAC_DSAR(4) -#define DMAC_DTAR4 DMAC_DTAR(4) -#define DMAC_DTCR4 DMAC_DTCR(4) -#define DMAC_DRSR4 DMAC_DRSR(4) -#define DMAC_DCCSR4 DMAC_DCCSR(4) -#define DMAC_DCMD4 DMAC_DCMD(4) -#define DMAC_DDA4 DMAC_DDA(4) - -// channel 5 -#define DMAC_DSAR5 DMAC_DSAR(5) -#define DMAC_DTAR5 DMAC_DTAR(5) -#define DMAC_DTCR5 DMAC_DTCR(5) -#define DMAC_DRSR5 DMAC_DRSR(5) -#define DMAC_DCCSR5 DMAC_DCCSR(5) -#define DMAC_DCMD5 DMAC_DCMD(5) -#define DMAC_DDA5 DMAC_DDA(5) - -#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) -#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) -#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) -#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) -#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) -#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) -#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) -#define REG_DMAC_DMACR REG32(DMAC_DMACR) -#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) -#define REG_DMAC_DMADBR REG32(DMAC_DMADBR) -#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) - -// DMA request source register -#define DMAC_DRSR_RS_BIT 0 -#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) - #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) - -// DMA channel control/status register -#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ -#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ -#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) -#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ -#define DMAC_DCCSR_AR (1 << 4) /* address error */ -#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ -#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ -#define DMAC_DCCSR_CT (1 << 1) /* count terminated */ -#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ - -// DMA channel command register -#define DMAC_DCMD_SAI (1 << 23) /* source address increment */ -#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ -#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ -#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) - #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) -#define DMAC_DCMD_SWDH_BIT 14 /* source port width */ -#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) - #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) - #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) - #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) -#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ -#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) - #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) - #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) - #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) -#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ -#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) - #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) -#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ -#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ -#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ -#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ -#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ -#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ - -// DMA descriptor address register -#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ -#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) -#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ -#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) - -// DMA control register -#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ -#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) - #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ -#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ -#define DMAC_DMACR_AR (1 << 2) /* address error flag */ -#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ - -// DMA doorbell register -#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ -#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ -#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ -#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ -#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ -#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ - -// DMA doorbell set register -#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ -#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ -#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ -#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ -#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ -#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ - -// DMA interrupt pending register -#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ -#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ -#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ -#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ -#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ -#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ - - -/************************************************************************* - * GPIO (General-Purpose I/O Ports) - *************************************************************************/ -#define MAX_GPIO_NUM 128 - -//n = 0,1,2,3 -#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ -#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ -#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ -#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ -#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ -#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ -#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ -#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ -#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ -#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ -#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ -#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ -#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ -#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ -#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ -#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ -#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ -#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ -#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ -#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ -#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ -#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ -#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ - -#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ -#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ -#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) -#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) -#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ -#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) -#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) -#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ -#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) -#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) -#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ -#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) -#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) -#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ -#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) -#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) -#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ -#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) -#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) -#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ -#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) -#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) -#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ - - -/************************************************************************* - * UART - *************************************************************************/ - -#define IRDA_BASE UART0_BASE -#define UART_BASE UART0_BASE -#define UART_OFF 0x1000 - -/* Register Offset */ -#define OFF_RDR (0x00) /* R 8b H'xx */ -#define OFF_TDR (0x00) /* W 8b H'xx */ -#define OFF_DLLR (0x00) /* RW 8b H'00 */ -#define OFF_DLHR (0x04) /* RW 8b H'00 */ -#define OFF_IER (0x04) /* RW 8b H'00 */ -#define OFF_ISR (0x08) /* R 8b H'01 */ -#define OFF_FCR (0x08) /* W 8b H'00 */ -#define OFF_LCR (0x0C) /* RW 8b H'00 */ -#define OFF_MCR (0x10) /* RW 8b H'00 */ -#define OFF_LSR (0x14) /* R 8b H'00 */ -#define OFF_MSR (0x18) /* R 8b H'00 */ -#define OFF_SPR (0x1C) /* RW 8b H'00 */ -#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ -#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ -#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ - -/* Register Address */ -#define UART0_RDR (UART0_BASE + OFF_RDR) -#define UART0_TDR (UART0_BASE + OFF_TDR) -#define UART0_DLLR (UART0_BASE + OFF_DLLR) -#define UART0_DLHR (UART0_BASE + OFF_DLHR) -#define UART0_IER (UART0_BASE + OFF_IER) -#define UART0_ISR (UART0_BASE + OFF_ISR) -#define UART0_FCR (UART0_BASE + OFF_FCR) -#define UART0_LCR (UART0_BASE + OFF_LCR) -#define UART0_MCR (UART0_BASE + OFF_MCR) -#define UART0_LSR (UART0_BASE + OFF_LSR) -#define UART0_MSR (UART0_BASE + OFF_MSR) -#define UART0_SPR (UART0_BASE + OFF_SPR) -#define UART0_SIRCR (UART0_BASE + OFF_SIRCR) -#define UART0_UMR (UART0_BASE + OFF_UMR) -#define UART0_UACR (UART0_BASE + OFF_UACR) - -/* - * Define macros for UART_IER - * UART Interrupt Enable Register - */ -#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ -#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ -#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ -#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ -#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ - -/* - * Define macros for UART_ISR - * UART Interrupt Status Register - */ -#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ -#define UART_ISR_IID (7 << 1) /* Source of Interrupt */ -#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ -#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ -#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ -#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ -#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ -#define UART_ISR_FFMS_NO_FIFO (0 << 6) -#define UART_ISR_FFMS_FIFO_MODE (3 << 6) - -/* - * Define macros for UART_FCR - * UART FIFO Control Register - */ -#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ -#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ -#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ -#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ -#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ -#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ -#define UART_FCR_RTRG_1 (0 << 6) -#define UART_FCR_RTRG_4 (1 << 6) -#define UART_FCR_RTRG_8 (2 << 6) -#define UART_FCR_RTRG_15 (3 << 6) - -/* - * Define macros for UART_LCR - * UART Line Control Register - */ -#define UART_LCR_WLEN (3 << 0) /* word length */ -#define UART_LCR_WLEN_5 (0 << 0) -#define UART_LCR_WLEN_6 (1 << 0) -#define UART_LCR_WLEN_7 (2 << 0) -#define UART_LCR_WLEN_8 (3 << 0) -#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ - -#define UART_LCR_PE (1 << 3) /* 0: parity disable */ -#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ -#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ -#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ -#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ - -/* - * Define macros for UART_LSR - * UART Line Status Register - */ -#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ -#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ -#define UART_LSR_PER (1 << 2) /* 0: no parity error */ -#define UART_LSR_FER (1 << 3) /* 0; no framing error */ -#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ -#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ -#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ -#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ - -/* - * Define macros for UART_MCR - * UART Modem Control Register - */ -#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ -#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ -#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ -#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ -#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ -#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ - -/* - * Define macros for UART_MSR - * UART Modem Status Register - */ -#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ -#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ -#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ -#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ -#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ -#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ -#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ -#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ - -/* - * Define macros for SIRCR - * Slow IrDA Control Register - */ -#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ -#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ -#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length - 1: 0 pulse width is 1.6us for 115.2Kbps */ -#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ -#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ - - -/************************************************************************* - * AIC (AC97/I2S Controller) - *************************************************************************/ -#define AIC_FR (AIC_BASE + 0x000) -#define AIC_CR (AIC_BASE + 0x004) -#define AIC_ACCR1 (AIC_BASE + 0x008) -#define AIC_ACCR2 (AIC_BASE + 0x00C) -#define AIC_I2SCR (AIC_BASE + 0x010) -#define AIC_SR (AIC_BASE + 0x014) -#define AIC_ACSR (AIC_BASE + 0x018) -#define AIC_I2SSR (AIC_BASE + 0x01C) -#define AIC_ACCAR (AIC_BASE + 0x020) -#define AIC_ACCDR (AIC_BASE + 0x024) -#define AIC_ACSAR (AIC_BASE + 0x028) -#define AIC_ACSDR (AIC_BASE + 0x02C) -#define AIC_I2SDIV (AIC_BASE + 0x030) -#define AIC_DR (AIC_BASE + 0x034) - -#define REG_AIC_FR REG32(AIC_FR) -#define REG_AIC_CR REG32(AIC_CR) -#define REG_AIC_ACCR1 REG32(AIC_ACCR1) -#define REG_AIC_ACCR2 REG32(AIC_ACCR2) -#define REG_AIC_I2SCR REG32(AIC_I2SCR) -#define REG_AIC_SR REG32(AIC_SR) -#define REG_AIC_ACSR REG32(AIC_ACSR) -#define REG_AIC_I2SSR REG32(AIC_I2SSR) -#define REG_AIC_ACCAR REG32(AIC_ACCAR) -#define REG_AIC_ACCDR REG32(AIC_ACCDR) -#define REG_AIC_ACSAR REG32(AIC_ACSAR) -#define REG_AIC_ACSDR REG32(AIC_ACSDR) -#define REG_AIC_I2SDIV REG32(AIC_I2SDIV) -#define REG_AIC_DR REG32(AIC_DR) - -/* AIC Controller Configuration Register (AIC_FR) */ - -#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ -#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) -#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ -#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) -#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ -#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ -#define AIC_FR_RST (1 << 3) /* AIC registers reset */ -#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ -#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ -#define AIC_FR_ENB (1 << 0) /* AIC enable bit */ - -/* AIC Controller Common Control Register (AIC_CR) */ - -#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ -#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) - #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) -#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ -#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) - #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) -#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ -#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ -#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ -#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ -#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ -#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ -#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ -#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ -#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ -#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ -#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ -#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ -#define AIC_CR_EREC (1 << 0) /* Enable Record Function */ - -/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ - -#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ -#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) - #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ - #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ - #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ - #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ - #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ - #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ - #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ - #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ - #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ - #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ -#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ -#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) - #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ - #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ - #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ - #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ - #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ - #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ - #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ - #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ - #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ - #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ - -/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ - -#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ -#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ -#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ -#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ -#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) - #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ - #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ - #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ - #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ -#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ -#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) - #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ - #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ - #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ - #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ -#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ -#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ -#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ -#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ - -/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ - -#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ -#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ -#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) - #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ - #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ - #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ - #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ - #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ -#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ - -/* AIC Controller FIFO Status Register (AIC_SR) */ - -#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ -#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) -#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ -#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) -#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ -#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ -#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ -#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ - -/* AIC Controller AC-link Status Register (AIC_ACSR) */ - -#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ -#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ -#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ -#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ -#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ -#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ - -/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ - -#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ - -/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ - -#define AIC_ACCAR_CAR_BIT 0 -#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) - -/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ - -#define AIC_ACCDR_CDR_BIT 0 -#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) - -/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ - -#define AIC_ACSAR_SAR_BIT 0 -#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) - -/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ - -#define AIC_ACSDR_SDR_BIT 0 -#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) - -/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ - -#define AIC_I2SDIV_DIV_BIT 0 -#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) - #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ - #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ - #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ - #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ - #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ - #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ - - -/************************************************************************* - * ICDC (Internal CODEC) - *************************************************************************/ -#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ -#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ -#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ -#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ -#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ -#define ICDC_CDCCR1 (ICDC_BASE + 0x0080) -#define ICDC_CDCCR2 (ICDC_BASE + 0x0084) - -#define REG_ICDC_CR REG32(ICDC_CR) -#define REG_ICDC_APWAIT REG32(ICDC_APWAIT) -#define REG_ICDC_APPRE REG32(ICDC_APPRE) -#define REG_ICDC_APHPEN REG32(ICDC_APHPEN) -#define REG_ICDC_APSR REG32(ICDC_APSR) -#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) -#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) - -/* ICDC Control Register */ -#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ -#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) -#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ -#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) - #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) -#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ -#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) - #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) - #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) - #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) - #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) -#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ -#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) - #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) - #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) - #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) - #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) -#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ -#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ -#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ -#define ICDC_CR_EADC (1 << 10) /* Enable ADC */ -#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ -#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ -#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ -#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ -#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ -#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ -#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ -#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ - -/* Anti-Pop WAIT Stage Timing Control Register */ -#define ICDC_APWAIT_WAITSN_BIT 0 -#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) - -/* Anti-Pop HPEN-PRE Stage Timing Control Register */ -#define ICDC_APPRE_PRESN_BIT 0 -#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) - -/* Anti-Pop HPEN Stage Timing Control Register */ -#define ICDC_APHPEN_HPENSN_BIT 0 -#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) - -/* Anti-Pop Status Register */ -#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ -#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) -#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ -#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ - #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ -#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ - #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ - #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ - #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ - #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ -#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ -#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) - - -/************************************************************************* - * I2C - *************************************************************************/ -#define I2C_DR (I2C_BASE + 0x000) -#define I2C_CR (I2C_BASE + 0x004) -#define I2C_SR (I2C_BASE + 0x008) -#define I2C_GR (I2C_BASE + 0x00C) - -#define REG_I2C_DR REG8(I2C_DR) -#define REG_I2C_CR REG8(I2C_CR) -#define REG_I2C_SR REG8(I2C_SR) -#define REG_I2C_GR REG16(I2C_GR) - -/* I2C Control Register (I2C_CR) */ - -#define I2C_CR_IEN (1 << 4) -#define I2C_CR_STA (1 << 3) -#define I2C_CR_STO (1 << 2) -#define I2C_CR_AC (1 << 1) -#define I2C_CR_I2CE (1 << 0) - -/* I2C Status Register (I2C_SR) */ - -#define I2C_SR_STX (1 << 4) -#define I2C_SR_BUSY (1 << 3) -#define I2C_SR_TEND (1 << 2) -#define I2C_SR_DRF (1 << 1) -#define I2C_SR_ACKF (1 << 0) - - -/************************************************************************* - * SSI - *************************************************************************/ -#define SSI_DR (SSI_BASE + 0x000) -#define SSI_CR0 (SSI_BASE + 0x004) -#define SSI_CR1 (SSI_BASE + 0x008) -#define SSI_SR (SSI_BASE + 0x00C) -#define SSI_ITR (SSI_BASE + 0x010) -#define SSI_ICR (SSI_BASE + 0x014) -#define SSI_GR (SSI_BASE + 0x018) - -#define REG_SSI_DR REG32(SSI_DR) -#define REG_SSI_CR0 REG16(SSI_CR0) -#define REG_SSI_CR1 REG32(SSI_CR1) -#define REG_SSI_SR REG32(SSI_SR) -#define REG_SSI_ITR REG16(SSI_ITR) -#define REG_SSI_ICR REG8(SSI_ICR) -#define REG_SSI_GR REG16(SSI_GR) - -/* SSI Data Register (SSI_DR) */ - -#define SSI_DR_GPC_BIT 0 -#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) - -/* SSI Control Register 0 (SSI_CR0) */ - -#define SSI_CR0_SSIE (1 << 15) -#define SSI_CR0_TIE (1 << 14) -#define SSI_CR0_RIE (1 << 13) -#define SSI_CR0_TEIE (1 << 12) -#define SSI_CR0_REIE (1 << 11) -#define SSI_CR0_LOOP (1 << 10) -#define SSI_CR0_RFINE (1 << 9) -#define SSI_CR0_RFINC (1 << 8) -#define SSI_CR0_FSEL (1 << 6) -#define SSI_CR0_TFLUSH (1 << 2) -#define SSI_CR0_RFLUSH (1 << 1) -#define SSI_CR0_DISREV (1 << 0) - -/* SSI Control Register 1 (SSI_CR1) */ - -#define SSI_CR1_FRMHL_BIT 30 -#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) - #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ - #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ - #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ - #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ -#define SSI_CR1_TFVCK_BIT 28 -#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) - #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) -#define SSI_CR1_TCKFI_BIT 26 -#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) - #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) -#define SSI_CR1_LFST (1 << 25) -#define SSI_CR1_ITFRM (1 << 24) -#define SSI_CR1_UNFIN (1 << 23) -#define SSI_CR1_MULTS (1 << 22) -#define SSI_CR1_FMAT_BIT 20 -#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) - #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ - #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ - #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ - #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ -#define SSI_CR1_MCOM_BIT 12 -#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) - #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ - #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ - #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ - #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ - #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ - #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ - #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ - #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ - #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ - #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ - #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ - #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ - #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ - #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ - #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ - #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ -#define SSI_CR1_TTRG_BIT 10 -#define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT) - #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */ - #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */ - #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */ - #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */ -#define SSI_CR1_RTRG_BIT 8 -#define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT) - #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */ - #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */ - #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */ - #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */ -#define SSI_CR1_FLEN_BIT 4 -#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) - #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) -#define SSI_CR1_PHA (1 << 1) -#define SSI_CR1_POL (1 << 0) - -/* SSI Status Register (SSI_SR) */ - -#define SSI_SR_TFIFONUM_BIT 13 -#define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT) -#define SSI_SR_RFIFONUM_BIT 8 -#define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT) -#define SSI_SR_END (1 << 7) -#define SSI_SR_BUSY (1 << 6) -#define SSI_SR_TFF (1 << 5) -#define SSI_SR_RFE (1 << 4) -#define SSI_SR_TFHE (1 << 3) -#define SSI_SR_RFHF (1 << 2) -#define SSI_SR_UNDR (1 << 1) -#define SSI_SR_OVER (1 << 0) - -/* SSI Interval Time Control Register (SSI_ITR) */ - -#define SSI_ITR_CNTCLK (1 << 15) -#define SSI_ITR_IVLTM_BIT 0 -#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) - - -/************************************************************************* - * MSC - *************************************************************************/ -#define MSC_STRPCL (MSC_BASE + 0x000) -#define MSC_STAT (MSC_BASE + 0x004) -#define MSC_CLKRT (MSC_BASE + 0x008) -#define MSC_CMDAT (MSC_BASE + 0x00C) -#define MSC_RESTO (MSC_BASE + 0x010) -#define MSC_RDTO (MSC_BASE + 0x014) -#define MSC_BLKLEN (MSC_BASE + 0x018) -#define MSC_NOB (MSC_BASE + 0x01C) -#define MSC_SNOB (MSC_BASE + 0x020) -#define MSC_IMASK (MSC_BASE + 0x024) -#define MSC_IREG (MSC_BASE + 0x028) -#define MSC_CMD (MSC_BASE + 0x02C) -#define MSC_ARG (MSC_BASE + 0x030) -#define MSC_RES (MSC_BASE + 0x034) -#define MSC_RXFIFO (MSC_BASE + 0x038) -#define MSC_TXFIFO (MSC_BASE + 0x03C) - -#define REG_MSC_STRPCL REG16(MSC_STRPCL) -#define REG_MSC_STAT REG32(MSC_STAT) -#define REG_MSC_CLKRT REG16(MSC_CLKRT) -#define REG_MSC_CMDAT REG32(MSC_CMDAT) -#define REG_MSC_RESTO REG16(MSC_RESTO) -#define REG_MSC_RDTO REG16(MSC_RDTO) -#define REG_MSC_BLKLEN REG16(MSC_BLKLEN) -#define REG_MSC_NOB REG16(MSC_NOB) -#define REG_MSC_SNOB REG16(MSC_SNOB) -#define REG_MSC_IMASK REG16(MSC_IMASK) -#define REG_MSC_IREG REG16(MSC_IREG) -#define REG_MSC_CMD REG8(MSC_CMD) -#define REG_MSC_ARG REG32(MSC_ARG) -#define REG_MSC_RES REG16(MSC_RES) -#define REG_MSC_RXFIFO REG32(MSC_RXFIFO) -#define REG_MSC_TXFIFO REG32(MSC_TXFIFO) - -/* MSC Clock and Control Register (MSC_STRPCL) */ - -#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) -#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) -#define MSC_STRPCL_START_READWAIT (1 << 5) -#define MSC_STRPCL_STOP_READWAIT (1 << 4) -#define MSC_STRPCL_RESET (1 << 3) -#define MSC_STRPCL_START_OP (1 << 2) -#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 -#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) - #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ - #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ - -/* MSC Status Register (MSC_STAT) */ - -#define MSC_STAT_IS_RESETTING (1 << 15) -#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) -#define MSC_STAT_PRG_DONE (1 << 13) -#define MSC_STAT_DATA_TRAN_DONE (1 << 12) -#define MSC_STAT_END_CMD_RES (1 << 11) -#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) -#define MSC_STAT_IS_READWAIT (1 << 9) -#define MSC_STAT_CLK_EN (1 << 8) -#define MSC_STAT_DATA_FIFO_FULL (1 << 7) -#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) -#define MSC_STAT_CRC_RES_ERR (1 << 5) -#define MSC_STAT_CRC_READ_ERROR (1 << 4) -#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 -#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) - #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ -#define MSC_STAT_TIME_OUT_RES (1 << 1) -#define MSC_STAT_TIME_OUT_READ (1 << 0) - -/* MSC Bus Clock Control Register (MSC_CLKRT) */ - -#define MSC_CLKRT_CLK_RATE_BIT 0 -#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ - #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ - -/* MSC Command Sequence Control Register (MSC_CMDAT) */ - -#define MSC_CMDAT_IO_ABORT (1 << 11) -#define MSC_CMDAT_BUS_WIDTH_BIT 9 -#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) - #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ - #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ - #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) - #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_DMA_EN (1 << 8) -#define MSC_CMDAT_INIT (1 << 7) -#define MSC_CMDAT_BUSY (1 << 6) -#define MSC_CMDAT_STREAM_BLOCK (1 << 5) -#define MSC_CMDAT_WRITE (1 << 4) -#define MSC_CMDAT_READ (0 << 4) -#define MSC_CMDAT_DATA_EN (1 << 3) -#define MSC_CMDAT_RESPONSE_BIT 0 -#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) - #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ - #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ - #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ - #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ - #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ - #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ - #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ - -#define CMDAT_DMA_EN (1 << 8) -#define CMDAT_INIT (1 << 7) -#define CMDAT_BUSY (1 << 6) -#define CMDAT_STREAM (1 << 5) -#define CMDAT_WRITE (1 << 4) -#define CMDAT_DATA_EN (1 << 3) - -/* MSC Interrupts Mask Register (MSC_IMASK) */ - -#define MSC_IMASK_SDIO (1 << 7) -#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) -#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) -#define MSC_IMASK_END_CMD_RES (1 << 2) -#define MSC_IMASK_PRG_DONE (1 << 1) -#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) - - -/* MSC Interrupts Status Register (MSC_IREG) */ - -#define MSC_IREG_SDIO (1 << 7) -#define MSC_IREG_TXFIFO_WR_REQ (1 << 6) -#define MSC_IREG_RXFIFO_RD_REQ (1 << 5) -#define MSC_IREG_END_CMD_RES (1 << 2) -#define MSC_IREG_PRG_DONE (1 << 1) -#define MSC_IREG_DATA_TRAN_DONE (1 << 0) - - -/************************************************************************* - * EMC (External Memory Controller) - *************************************************************************/ -#define EMC_BCR (EMC_BASE + 0x10) /* BCR */ - -#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ -#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ -#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ -#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ -#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ -#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ -#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ -#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ -#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ -#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ - -#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ -#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ -#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ -#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ -#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ -#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ -#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ -#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ -#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ -#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ -#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ -#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ - -#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ -#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ -#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ -#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ -#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ -#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ - -#define REG_EMC_BCR REG32(EMC_BCR) - -#define REG_EMC_SMCR0 REG32(EMC_SMCR0) -#define REG_EMC_SMCR1 REG32(EMC_SMCR1) -#define REG_EMC_SMCR2 REG32(EMC_SMCR2) -#define REG_EMC_SMCR3 REG32(EMC_SMCR3) -#define REG_EMC_SMCR4 REG32(EMC_SMCR4) -#define REG_EMC_SACR0 REG32(EMC_SACR0) -#define REG_EMC_SACR1 REG32(EMC_SACR1) -#define REG_EMC_SACR2 REG32(EMC_SACR2) -#define REG_EMC_SACR3 REG32(EMC_SACR3) -#define REG_EMC_SACR4 REG32(EMC_SACR4) - -#define REG_EMC_NFCSR REG32(EMC_NFCSR) -#define REG_EMC_NFECR REG32(EMC_NFECR) -#define REG_EMC_NFECC REG32(EMC_NFECC) -#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) -#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) -#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) -#define REG_EMC_NFINTS REG32(EMC_NFINTS) -#define REG_EMC_NFINTE REG32(EMC_NFINTE) -#define REG_EMC_NFERR0 REG32(EMC_NFERR0) -#define REG_EMC_NFERR1 REG32(EMC_NFERR1) -#define REG_EMC_NFERR2 REG32(EMC_NFERR2) -#define REG_EMC_NFERR3 REG32(EMC_NFERR3) - -#define REG_EMC_DMCR REG32(EMC_DMCR) -#define REG_EMC_RTCSR REG16(EMC_RTCSR) -#define REG_EMC_RTCNT REG16(EMC_RTCNT) -#define REG_EMC_RTCOR REG16(EMC_RTCOR) -#define REG_EMC_DMAR0 REG32(EMC_DMAR0) - -/* Static Memory Control Register */ -#define EMC_SMCR_STRV_BIT 24 -#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) -#define EMC_SMCR_TAW_BIT 20 -#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) -#define EMC_SMCR_TBP_BIT 16 -#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) -#define EMC_SMCR_TAH_BIT 12 -#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) -#define EMC_SMCR_TAS_BIT 8 -#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) -#define EMC_SMCR_BW_BIT 6 -#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) -#define EMC_SMCR_BL_BIT 1 -#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) - -/* Static Memory Bank Addr Config Reg */ -#define EMC_SACR_BASE_BIT 8 -#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) -#define EMC_SACR_MASK_BIT 0 -#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) - -/* NAND Flash Control/Status Register */ -#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ -#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ -#define EMC_NFCSR_NFCE3 (1 << 5) -#define EMC_NFCSR_NFE3 (1 << 4) -#define EMC_NFCSR_NFCE2 (1 << 3) -#define EMC_NFCSR_NFE2 (1 << 2) -#define EMC_NFCSR_NFCE1 (1 << 1) -#define EMC_NFCSR_NFE1 (1 << 0) - -/* NAND Flash ECC Control Register */ -#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ -#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ -#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ -#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ -#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ -#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ -#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ - -/* NAND Flash ECC Data Register */ -#define EMC_NFECC_ECC2_BIT 16 -#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) -#define EMC_NFECC_ECC1_BIT 8 -#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) -#define EMC_NFECC_ECC0_BIT 0 -#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) - -/* NAND Flash Interrupt Status Register */ -#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ -#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) -#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ -#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ -#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ -#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ -#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ - -/* NAND Flash Interrupt Enable Register */ -#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ -#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ -#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ -#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ -#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ - -/* NAND Flash RS Error Report Register */ -#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ -#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) -#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ -#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) - - -/* DRAM Control Register */ -#define EMC_DMCR_BW_BIT 31 -#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) -#define EMC_DMCR_CA_BIT 26 -#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) -#define EMC_DMCR_RMODE (1 << 25) -#define EMC_DMCR_RFSH (1 << 24) -#define EMC_DMCR_MRSET (1 << 23) -#define EMC_DMCR_RA_BIT 20 -#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) -#define EMC_DMCR_BA_BIT 19 -#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) -#define EMC_DMCR_PDM (1 << 18) -#define EMC_DMCR_EPIN (1 << 17) -#define EMC_DMCR_TRAS_BIT 13 -#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) -#define EMC_DMCR_RCD_BIT 11 -#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) -#define EMC_DMCR_TPC_BIT 8 -#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) -#define EMC_DMCR_TRWL_BIT 5 -#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) -#define EMC_DMCR_TRC_BIT 2 -#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) -#define EMC_DMCR_TCL_BIT 0 -#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) - -/* Refresh Time Control/Status Register */ -#define EMC_RTCSR_CMF (1 << 7) -#define EMC_RTCSR_CKS_BIT 0 -#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) - -/* SDRAM Bank Address Configuration Register */ -#define EMC_DMAR_BASE_BIT 8 -#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) -#define EMC_DMAR_MASK_BIT 0 -#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) - -/* Mode Register of SDRAM bank 0 */ -#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ -#define EMC_SDMR_OM_BIT 7 /* Operating Mode */ -#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) - #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) -#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ -#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) -#define EMC_SDMR_BT_BIT 3 /* Burst Type */ -#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ - #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ -#define EMC_SDMR_BL_BIT 0 /* Burst Length */ -#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) - -#define EMC_SDMR_CAS2_16BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS2_32BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) -#define EMC_SDMR_CAS3_16BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS3_32BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) - - -/************************************************************************* - * CIM - *************************************************************************/ -#define CIM_CFG (CIM_BASE + 0x0000) -#define CIM_CTRL (CIM_BASE + 0x0004) -#define CIM_STATE (CIM_BASE + 0x0008) -#define CIM_IID (CIM_BASE + 0x000C) -#define CIM_RXFIFO (CIM_BASE + 0x0010) -#define CIM_DA (CIM_BASE + 0x0020) -#define CIM_FA (CIM_BASE + 0x0024) -#define CIM_FID (CIM_BASE + 0x0028) -#define CIM_CMD (CIM_BASE + 0x002C) - -#define REG_CIM_CFG REG32(CIM_CFG) -#define REG_CIM_CTRL REG32(CIM_CTRL) -#define REG_CIM_STATE REG32(CIM_STATE) -#define REG_CIM_IID REG32(CIM_IID) -#define REG_CIM_RXFIFO REG32(CIM_RXFIFO) -#define REG_CIM_DA REG32(CIM_DA) -#define REG_CIM_FA REG32(CIM_FA) -#define REG_CIM_FID REG32(CIM_FID) -#define REG_CIM_CMD REG32(CIM_CMD) - -/* CIM Configuration Register (CIM_CFG) */ - -#define CIM_CFG_INV_DAT (1 << 15) -#define CIM_CFG_VSP (1 << 14) -#define CIM_CFG_HSP (1 << 13) -#define CIM_CFG_PCP (1 << 12) -#define CIM_CFG_DUMMY_ZERO (1 << 9) -#define CIM_CFG_EXT_VSYNC (1 << 8) -#define CIM_CFG_PACK_BIT 4 -#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) - #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) -#define CIM_CFG_DSM_BIT 0 -#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) - #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ - #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ - #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ - #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ - -/* CIM Control Register (CIM_CTRL) */ - -#define CIM_CTRL_MCLKDIV_BIT 24 -#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) -#define CIM_CTRL_FRC_BIT 16 -#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) - #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ - #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ - #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ - #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ - #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ - #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ - #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ - #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ - #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ - #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ - #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ - #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ - #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ - #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ - #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ - #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ -#define CIM_CTRL_VDDM (1 << 13) -#define CIM_CTRL_DMA_SOFM (1 << 12) -#define CIM_CTRL_DMA_EOFM (1 << 11) -#define CIM_CTRL_DMA_STOPM (1 << 10) -#define CIM_CTRL_RXF_TRIGM (1 << 9) -#define CIM_CTRL_RXF_OFM (1 << 8) -#define CIM_CTRL_RXF_TRIG_BIT 4 -#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) - #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ - #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ - #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ - #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ - #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ - #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ - #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ - #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ -#define CIM_CTRL_DMA_EN (1 << 2) -#define CIM_CTRL_RXF_RST (1 << 1) -#define CIM_CTRL_ENA (1 << 0) - -/* CIM State Register (CIM_STATE) */ - -#define CIM_STATE_DMA_SOF (1 << 6) -#define CIM_STATE_DMA_EOF (1 << 5) -#define CIM_STATE_DMA_STOP (1 << 4) -#define CIM_STATE_RXF_OF (1 << 3) -#define CIM_STATE_RXF_TRIG (1 << 2) -#define CIM_STATE_RXF_EMPTY (1 << 1) -#define CIM_STATE_VDD (1 << 0) - -/* CIM DMA Command Register (CIM_CMD) */ - -#define CIM_CMD_SOFINT (1 << 31) -#define CIM_CMD_EOFINT (1 << 30) -#define CIM_CMD_STOP (1 << 28) -#define CIM_CMD_LEN_BIT 0 -#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) - - -/************************************************************************* - * SADC (Smart A/D Controller) - *************************************************************************/ - -#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ -#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ -#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ -#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ -#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ -#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ -#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ -#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ -#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ - -#define REG_SADC_ENA REG8(SADC_ENA) -#define REG_SADC_CFG REG32(SADC_CFG) -#define REG_SADC_CTRL REG8(SADC_CTRL) -#define REG_SADC_STATE REG8(SADC_STATE) -#define REG_SADC_SAMETIME REG16(SADC_SAMETIME) -#define REG_SADC_WAITTIME REG16(SADC_WAITTIME) -#define REG_SADC_TSDAT REG32(SADC_TSDAT) -#define REG_SADC_BATDAT REG16(SADC_BATDAT) -#define REG_SADC_SADDAT REG16(SADC_SADDAT) - -/* ADC Enable Register */ -#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ -#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ -#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ -#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ - -/* ADC Configure Register */ -#define SADC_CFG_CLKOUT_NUM_BIT 16 -#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) -#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ -#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ -#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) - #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) - #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) - #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) -#define SADC_CFG_SNUM_BIT 10 /* Sample Number */ -#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) - #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) -#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ -#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) -#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ -#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ -#define SADC_CFG_CMD_BIT 0 /* ADC Command */ -#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) - #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ - #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ - #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ - #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ - #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ - #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ - #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ - #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ - #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ - #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ - #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ - #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ - #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ - -/* ADC Control Register */ -#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ -#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ -#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ -#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ -#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ - -/* ADC Status Register */ -#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ -#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ -#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ -#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ -#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ -#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ -#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ -#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ - -/* ADC Touch Screen Data Register */ -#define SADC_TSDAT_DATA0_BIT 0 -#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) -#define SADC_TSDAT_TYPE0 (1 << 15) -#define SADC_TSDAT_DATA1_BIT 16 -#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) -#define SADC_TSDAT_TYPE1 (1 << 31) - - -/************************************************************************* - * SLCD (Smart LCD Controller) - *************************************************************************/ - -#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ -#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ -#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ -#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ -#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ - -#define REG_SLCD_CFG REG32(SLCD_CFG) -#define REG_SLCD_CTRL REG8(SLCD_CTRL) -#define REG_SLCD_STATE REG8(SLCD_STATE) -#define REG_SLCD_DATA REG32(SLCD_DATA) -#define REG_SLCD_FIFO REG32(SLCD_FIFO) - -/* SLCD Configure Register */ -#define SLCD_CFG_BURST_BIT 14 -#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) - #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) - #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) -#define SLCD_CFG_DWIDTH_BIT 10 -#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) - #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) -#define SLCD_CFG_CWIDTH_16BIT (0 << 8) -#define SLCD_CFG_CWIDTH_8BIT (1 << 8) -#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) -#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) -#define SLCD_CFG_RS_CMD_LOW (0 << 3) -#define SLCD_CFG_RS_CMD_HIGH (1 << 3) -#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) -#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) -#define SLCD_CFG_TYPE_PARALLEL (0 << 0) -#define SLCD_CFG_TYPE_SERIAL (1 << 0) - -/* SLCD Control Register */ -#define SLCD_CTRL_DMA_EN (1 << 0) - -/* SLCD Status Register */ -#define SLCD_STATE_BUSY (1 << 0) - -/* SLCD Data Register */ -#define SLCD_DATA_RS_DATA (0 << 31) -#define SLCD_DATA_RS_COMMAND (1 << 31) - -/* SLCD FIFO Register */ -#define SLCD_FIFO_RS_DATA (0 << 31) -#define SLCD_FIFO_RS_COMMAND (1 << 31) - - -/************************************************************************* - * LCD (LCD Controller) - *************************************************************************/ -#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */ -#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */ -#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */ -#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */ -#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */ -#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */ -#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */ -#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */ -#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */ -#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */ -#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */ -#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */ -#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */ -#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */ -#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */ -#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */ -#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */ -#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */ -#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */ -#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */ -#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */ - -#define REG_LCD_CFG REG32(LCD_CFG) -#define REG_LCD_VSYNC REG32(LCD_VSYNC) -#define REG_LCD_HSYNC REG32(LCD_HSYNC) -#define REG_LCD_VAT REG32(LCD_VAT) -#define REG_LCD_DAH REG32(LCD_DAH) -#define REG_LCD_DAV REG32(LCD_DAV) -#define REG_LCD_PS REG32(LCD_PS) -#define REG_LCD_CLS REG32(LCD_CLS) -#define REG_LCD_SPL REG32(LCD_SPL) -#define REG_LCD_REV REG32(LCD_REV) -#define REG_LCD_CTRL REG32(LCD_CTRL) -#define REG_LCD_STATE REG32(LCD_STATE) -#define REG_LCD_IID REG32(LCD_IID) -#define REG_LCD_DA0 REG32(LCD_DA0) -#define REG_LCD_SA0 REG32(LCD_SA0) -#define REG_LCD_FID0 REG32(LCD_FID0) -#define REG_LCD_CMD0 REG32(LCD_CMD0) -#define REG_LCD_DA1 REG32(LCD_DA1) -#define REG_LCD_SA1 REG32(LCD_SA1) -#define REG_LCD_FID1 REG32(LCD_FID1) -#define REG_LCD_CMD1 REG32(LCD_CMD1) - -/* LCD Configure Register */ -#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ -#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) - #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) - #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) -#define LCD_CFG_PSM (1 << 23) /* PS signal mode */ -#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ -#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ -#define LCD_CFG_REVM (1 << 20) /* REV signal mode */ -#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ -#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ -#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ -#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ -#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ -#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ -#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ -#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ -#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ -#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ -#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ -#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ -#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ -#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) -#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ - #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ - #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ - #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ -#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ -#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ - #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) - /* JZ47XX defines */ - #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) - - - -/* Vertical Synchronize Register */ -#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ -#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) -#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ -#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) - -/* Horizontal Synchronize Register */ -#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ -#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) -#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ -#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) - -/* Virtual Area Setting Register */ -#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ -#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) -#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ -#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) - -/* Display Area Horizontal Start/End Point Register */ -#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ -#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) -#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ -#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) - -/* Display Area Vertical Start/End Point Register */ -#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ -#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) -#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ -#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) - -/* PS Signal Setting */ -#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ -#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) -#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ -#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) - -/* CLS Signal Setting */ -#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ -#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) -#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ -#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) - -/* SPL Signal Setting */ -#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ -#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) -#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ -#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) - -/* REV Signal Setting */ -#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ -#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) - -/* LCD Control Register */ -#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ -#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) - #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ - #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ - #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ -#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ -#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ -#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ -#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ -#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) - #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ - #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ - #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ -#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ -#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) -#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ -#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ -#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ -#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ -#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ -#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ -#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ -#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ -#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ -#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ -#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ -#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ -#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) - #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ - #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ - #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ - #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ - #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ - #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ - -/* LCD Status Register */ -#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ -#define LCD_STATE_EOF (1 << 5) /* EOF Flag */ -#define LCD_STATE_SOF (1 << 4) /* SOF Flag */ -#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ -#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ -#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ -#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ - -/* DMA Command Register */ -#define LCD_CMD_SOFINT (1 << 31) -#define LCD_CMD_EOFINT (1 << 30) -#define LCD_CMD_PAL (1 << 28) -#define LCD_CMD_LEN_BIT 0 -#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) - - -/************************************************************************* - * USB Device - *************************************************************************/ -#define USB_BASE UDC_BASE - -#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ -#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ -#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ -#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ -#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ -#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ -#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ -#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ -#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ -#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ -#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ - -#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ -#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ -#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ -#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ -#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ -#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ -#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ -#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ - -#define USB_FIFO_EP0 (USB_BASE + 0x20) -#define USB_FIFO_EP1 (USB_BASE + 0x24) -#define USB_FIFO_EP2 (USB_BASE + 0x28) - -#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ -#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ - -#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ -#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ -#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ -#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ -#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ -#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ -#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ - - -/* Power register bit masks */ -#define USB_POWER_SUSPENDM 0x01 -#define USB_POWER_RESUME 0x04 -#define USB_POWER_HSMODE 0x10 -#define USB_POWER_HSENAB 0x20 -#define USB_POWER_SOFTCONN 0x40 - -/* Interrupt register bit masks */ -#define USB_INTR_SUSPEND 0x01 -#define USB_INTR_RESUME 0x02 -#define USB_INTR_RESET 0x04 - -#define USB_INTR_EP0 0x0001 -#define USB_INTR_INEP1 0x0002 -#define USB_INTR_INEP2 0x0004 -#define USB_INTR_OUTEP1 0x0002 - -/* CSR0 bit masks */ -#define USB_CSR0_OUTPKTRDY 0x01 -#define USB_CSR0_INPKTRDY 0x02 -#define USB_CSR0_SENTSTALL 0x04 -#define USB_CSR0_DATAEND 0x08 -#define USB_CSR0_SETUPEND 0x10 -#define USB_CSR0_SENDSTALL 0x20 -#define USB_CSR0_SVDOUTPKTRDY 0x40 -#define USB_CSR0_SVDSETUPEND 0x80 - -/* Endpoint CSR register bits */ -#define USB_INCSRH_AUTOSET 0x80 -#define USB_INCSRH_ISO 0x40 -#define USB_INCSRH_MODE 0x20 -#define USB_INCSRH_DMAREQENAB 0x10 -#define USB_INCSRH_DMAREQMODE 0x04 -#define USB_INCSR_CDT 0x40 -#define USB_INCSR_SENTSTALL 0x20 -#define USB_INCSR_SENDSTALL 0x10 -#define USB_INCSR_FF 0x08 -#define USB_INCSR_UNDERRUN 0x04 -#define USB_INCSR_FFNOTEMPT 0x02 -#define USB_INCSR_INPKTRDY 0x01 -#define USB_OUTCSRH_AUTOCLR 0x80 -#define USB_OUTCSRH_ISO 0x40 -#define USB_OUTCSRH_DMAREQENAB 0x20 -#define USB_OUTCSRH_DNYT 0x10 -#define USB_OUTCSRH_DMAREQMODE 0x08 -#define USB_OUTCSR_CDT 0x80 -#define USB_OUTCSR_SENTSTALL 0x40 -#define USB_OUTCSR_SENDSTALL 0x20 -#define USB_OUTCSR_FF 0x10 -#define USB_OUTCSR_DATAERR 0x08 -#define USB_OUTCSR_OVERRUN 0x04 -#define USB_OUTCSR_FFFULL 0x02 -#define USB_OUTCSR_OUTPKTRDY 0x01 - -/* Testmode register bits */ -#define USB_TEST_SE0NAK 0x01 -#define USB_TEST_J 0x02 -#define USB_TEST_K 0x04 -#define USB_TEST_PACKET 0x08 - -/* DMA control bits */ -#define USB_CNTL_ENA 0x01 -#define USB_CNTL_DIR_IN 0x02 -#define USB_CNTL_MODE_1 0x04 -#define USB_CNTL_INTR_EN 0x08 -#define USB_CNTL_EP(n) ((n) << 4) -#define USB_CNTL_BURST_0 (0 << 9) -#define USB_CNTL_BURST_4 (1 << 9) -#define USB_CNTL_BURST_8 (2 << 9) -#define USB_CNTL_BURST_16 (3 << 9) - - -//---------------------------------------------------------------------- -// -// Module Operation Definitions -// -//---------------------------------------------------------------------- -#ifndef __ASSEMBLY__ - -/*************************************************************************** - * GPIO - ***************************************************************************/ - -//------------------------------------------------------ -// GPIO Pins Description -// -// PORT 0: -// -// PIN/BIT N FUNC0 FUNC1 -// 0 D0 - -// 1 D1 - -// 2 D2 - -// 3 D3 - -// 4 D4 - -// 5 D5 - -// 6 D6 - -// 7 D7 - -// 8 D8 - -// 9 D9 - -// 10 D10 - -// 11 D11 - -// 12 D12 - -// 13 D13 - -// 14 D14 - -// 15 D15 - -// 16 D16 - -// 17 D17 - -// 18 D18 - -// 19 D19 - -// 20 D20 - -// 21 D21 - -// 22 D22 - -// 23 D23 - -// 24 D24 - -// 25 D25 - -// 26 D26 - -// 27 D27 - -// 28 D28 - -// 29 D29 - -// 30 D30 - -// 31 D31 - -// -//------------------------------------------------------ -// PORT 1: -// -// PIN/BIT N FUNC0 FUNC1 -// 0 A0 - -// 1 A1 - -// 2 A2 - -// 3 A3 - -// 4 A4 - -// 5 A5 - -// 6 A6 - -// 7 A7 - -// 8 A8 - -// 9 A9 - -// 10 A10 - -// 11 A11 - -// 12 A12 - -// 13 A13 - -// 14 A14 - -// 15 A15/CL - -// 16 A16/AL - -// 17 LCD_CLS A21 -// 18 LCD_SPL A22 -// 19 DCS# - -// 20 RAS# - -// 21 CAS# - -// 22 RDWE#/BUFD# - -// 23 CKE - -// 24 CKO - -// 25 CS1# - -// 26 CS2# - -// 27 CS3# - -// 28 CS4# - -// 29 RD# - -// 30 WR# - -// 31 WE0# - -// -// Note: PIN15&16 are CL&AL when connecting to NAND flash. -//------------------------------------------------------ -// PORT 2: -// -// PIN/BIT N FUNC0 FUNC1 -// 0 LCD_D0 - -// 1 LCD_D1 - -// 2 LCD_D2 - -// 3 LCD_D3 - -// 4 LCD_D4 - -// 5 LCD_D5 - -// 6 LCD_D6 - -// 7 LCD_D7 - -// 8 LCD_D8 - -// 9 LCD_D9 - -// 10 LCD_D10 - -// 11 LCD_D11 - -// 12 LCD_D12 - -// 13 LCD_D13 - -// 14 LCD_D14 - -// 15 LCD_D15 - -// 16 LCD_D16 - -// 17 LCD_D17 - -// 18 LCD_PCLK - -// 19 LCD_HSYNC - -// 20 LCD_VSYNC - -// 21 LCD_DE - -// 22 LCD_PS A19 -// 23 LCD_REV A20 -// 24 WE1# - -// 25 WE2# - -// 26 WE3# - -// 27 WAIT# - -// 28 FRE# - -// 29 FWE# - -// 30(NOTE:FRB#) - - -// 31 - - -// -// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. -//------------------------------------------------------ -// PORT 3: -// -// PIN/BIT N FUNC0 FUNC1 -// 0 CIM_D0 - -// 1 CIM_D1 - -// 2 CIM_D2 - -// 3 CIM_D3 - -// 4 CIM_D4 - -// 5 CIM_D5 - -// 6 CIM_D6 - -// 7 CIM_D7 - -// 8 MSC_CMD - -// 9 MSC_CLK - -// 10 MSC_D0 - -// 11 MSC_D1 - -// 12 MSC_D2 - -// 13 MSC_D3 - -// 14 CIM_MCLK - -// 15 CIM_PCLK - -// 16 CIM_VSYNC - -// 17 CIM_HSYNC - -// 18 SSI_CLK SCLK_RSTN -// 19 SSI_CE0# BIT_CLK(AIC) -// 20 SSI_DT SDATA_OUT(AIC) -// 21 SSI_DR SDATA_IN(AIC) -// 22 SSI_CE1#&GPC SYNC(AIC) -// 23 PWM0 I2C_SDA -// 24 PWM1 I2C_SCK -// 25 PWM2 UART0_TxD -// 26 PWM3 UART0_RxD -// 27 PWM4 A17 -// 28 PWM5 A18 -// 29 - - -// 30 PWM6 UART0_CTS/UART1_RxD -// 31 PWM7 UART0_RTS/UART1_TxD -// -////////////////////////////////////////////////////////// - -/* - * p is the port number (0,1,2,3) - * o is the pin offset (0-31) inside the port - * n is the absolute number of a pin (0-127), regardless of the port - */ - -//------------------------------------------- -// Function Pins Mode - -#define __gpio_as_func0(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXFUNS(p) = (1 << o); \ - REG_GPIO_PXSELC(p) = (1 << o); \ -} while (0) - -#define __gpio_as_func1(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXFUNS(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ -} while (0) - -/* - * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, - * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# - */ -#define __gpio_as_sdram_32bit() \ -do { \ - REG_GPIO_PXFUNS(0) = 0xffffffff; \ - REG_GPIO_PXFUNS(0) = 0xffffffff; \ - REG_GPIO_PXPES(0) = 0xffffffff; \ - REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ - REG_GPIO_PXSELC(1) = 0x81f9ffff; \ - REG_GPIO_PXPES(1) = 0x81f9ffff; \ - REG_GPIO_PXFUNS(2) = 0x07000000; \ - REG_GPIO_PXSELC(2) = 0x07000000; \ - REG_GPIO_PXPES(1) = 0x07000000; \ -} while (0) - -/* - * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, - * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# - */ -#define __gpio_as_sdram_16bit() \ -do { \ - REG_GPIO_PXFUNS(0) = 0x0000ffff; \ - REG_GPIO_PXFUNS(0) = 0x0000ffff; \ - REG_GPIO_PXPES(0) = 0x0000ffff; \ - REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ - REG_GPIO_PXSELC(1) = 0x81f9ffff; \ - REG_GPIO_PXPES(1) = 0x81f9ffff; \ - REG_GPIO_PXFUNS(2) = 0x07000000; \ - REG_GPIO_PXSELC(2) = 0x07000000; \ - REG_GPIO_PXPES(1) = 0x07000000; \ -} while (0) - -/* - * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# - */ -#define __gpio_as_nand() \ -do { \ - REG_GPIO_PXFUNS(1) = 0x02018000; \ - REG_GPIO_PXSELC(1) = 0x02018000; \ - REG_GPIO_PXPES(1) = 0x02018000; \ - REG_GPIO_PXFUNS(2) = 0x30000000; \ - REG_GPIO_PXSELC(2) = 0x30000000; \ - REG_GPIO_PXPES(2) = 0x30000000; \ - REG_GPIO_PXFUNC(2) = 0x40000000; \ - REG_GPIO_PXSELC(2) = 0x40000000; \ - REG_GPIO_PXDIRC(2) = 0x40000000; \ - REG_GPIO_PXPES(2) = 0x40000000; \ - REG_GPIO_PXFUNS(1) = 0x00400000; \ - REG_GPIO_PXSELC(1) = 0x00400000; \ -} while (0) - -/* - * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 - */ -#define __gpio_as_nor_8bit() \ -do { \ - REG_GPIO_PXFUNS(0) = 0x000000ff; \ - REG_GPIO_PXSELC(0) = 0x000000ff; \ - REG_GPIO_PXPES(0) = 0x000000ff; \ - REG_GPIO_PXFUNS(1) = 0x7041ffff; \ - REG_GPIO_PXSELC(1) = 0x7041ffff; \ - REG_GPIO_PXPES(1) = 0x7041ffff; \ - REG_GPIO_PXFUNS(1) = 0x00060000; \ - REG_GPIO_PXSELS(1) = 0x00060000; \ - REG_GPIO_PXPES(1) = 0x00060000; \ - REG_GPIO_PXFUNS(2) = 0x08000000; \ - REG_GPIO_PXSELC(2) = 0x08000000; \ - REG_GPIO_PXPES(2) = 0x08000000; \ - REG_GPIO_PXFUNS(2) = 0x00c00000; \ - REG_GPIO_PXSELS(2) = 0x00c00000; \ - REG_GPIO_PXPES(2) = 0x00c00000; \ - REG_GPIO_PXFUNS(3) = 0x18000000; \ - REG_GPIO_PXSELS(3) = 0x18000000; \ - REG_GPIO_PXPES(3) = 0x18000000; \ -} while (0) - -/* - * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 - */ -#define __gpio_as_nor_16bit() \ -do { \ - REG_GPIO_PXFUNS(0) = 0x0000ffff; \ - REG_GPIO_PXSELC(0) = 0x0000ffff; \ - REG_GPIO_PXPES(0) = 0x0000ffff; \ - REG_GPIO_PXFUNS(1) = 0x7041ffff; \ - REG_GPIO_PXSELC(1) = 0x7041ffff; \ - REG_GPIO_PXPES(1) = 0x7041ffff; \ - REG_GPIO_PXFUNS(1) = 0x00060000; \ - REG_GPIO_PXSELS(1) = 0x00060000; \ - REG_GPIO_PXPES(1) = 0x00060000; \ - REG_GPIO_PXFUNS(2) = 0x08000000; \ - REG_GPIO_PXSELC(2) = 0x08000000; \ - REG_GPIO_PXPES(2) = 0x08000000; \ - REG_GPIO_PXFUNS(2) = 0x00c00000; \ - REG_GPIO_PXSELS(2) = 0x00c00000; \ - REG_GPIO_PXPES(2) = 0x00c00000; \ - REG_GPIO_PXFUNS(3) = 0x18000000; \ - REG_GPIO_PXSELS(3) = 0x18000000; \ - REG_GPIO_PXPES(3) = 0x18000000; \ -} while (0) - -/* - * UART0_TxD, UART_RxD0 - */ -#define __gpio_as_uart0() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x06000000; \ - REG_GPIO_PXSELS(3) = 0x06000000; \ - REG_GPIO_PXPES(3) = 0x06000000; \ -} while (0) - -/* - * UART1_TxD, UART1_RxD1 - */ -#define __gpio_as_uart1() \ -do { \ - REG_GPIO_PXFUNS(3) = 0xc0000000; \ - REG_GPIO_PXSELS(3) = 0xc0000000; \ - REG_GPIO_PXPES(3) = 0xc0000000; \ -} while (0) - -/* - * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE - */ -#define __gpio_as_lcd_16bit() \ -do { \ - REG_GPIO_PXFUNS(2) = 0x003cffff; \ - REG_GPIO_PXSELC(2) = 0x003cffff; \ - REG_GPIO_PXPES(2) = 0x003cffff; \ -} while (0) - -/* - * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE - */ -#define __gpio_as_lcd_18bit() \ -do { \ - REG_GPIO_PXFUNS(2) = 0x003fffff; \ - REG_GPIO_PXSELC(2) = 0x003fffff; \ - REG_GPIO_PXPES(2) = 0x003fffff; \ -} while (0) - -/* - * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC - */ -#define __gpio_as_cim() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ - REG_GPIO_PXSELC(3) = 0x0003c0ff; \ - REG_GPIO_PXPES(3) = 0x0003c0ff; \ -} while (0) - -/* - * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET - */ -#define __gpio_as_aic() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x007c0000; \ - REG_GPIO_PXSELS(3) = 0x007c0000; \ - REG_GPIO_PXPES(3) = 0x007c0000; \ -} while (0) - -/* - * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 - */ -#define __gpio_as_msc() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x00003f00; \ - REG_GPIO_PXSELC(3) = 0x00003f00; \ - REG_GPIO_PXPES(3) = 0x00003f00; \ -} while (0) - -/* - * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR - */ -#define __gpio_as_ssi() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x003c0000; \ - REG_GPIO_PXSELC(3) = 0x003c0000; \ - REG_GPIO_PXPES(3) = 0x003c0000; \ -} while (0) - -/* - * I2C_SCK, I2C_SDA - */ -#define __gpio_as_i2c() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x01800000; \ - REG_GPIO_PXSELS(3) = 0x01800000; \ - REG_GPIO_PXPES(3) = 0x01800000; \ -} while (0) - -/* - * PWM0 - */ -#define __gpio_as_pwm0() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x00800000; \ - REG_GPIO_PXSELC(3) = 0x00800000; \ - REG_GPIO_PXPES(3) = 0x00800000; \ -} while (0) - -/* - * PWM1 - */ -#define __gpio_as_pwm1() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x01000000; \ - REG_GPIO_PXSELC(3) = 0x01000000; \ - REG_GPIO_PXPES(3) = 0x01000000; \ -} while (0) - -/* - * PWM2 - */ -#define __gpio_as_pwm2() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x02000000; \ - REG_GPIO_PXSELC(3) = 0x02000000; \ - REG_GPIO_PXPES(3) = 0x02000000; \ -} while (0) - -/* - * PWM3 - */ -#define __gpio_as_pwm3() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x04000000; \ - REG_GPIO_PXSELC(3) = 0x04000000; \ - REG_GPIO_PXPES(3) = 0x04000000; \ -} while (0) - -/* - * PWM4 - */ -#define __gpio_as_pwm4() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x08000000; \ - REG_GPIO_PXSELC(3) = 0x08000000; \ - REG_GPIO_PXPES(3) = 0x08000000; \ -} while (0) - -/* - * PWM5 - */ -#define __gpio_as_pwm5() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x10000000; \ - REG_GPIO_PXSELC(3) = 0x10000000; \ - REG_GPIO_PXPES(3) = 0x10000000; \ -} while (0) - -/* - * PWM6 - */ -#define __gpio_as_pwm6() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x40000000; \ - REG_GPIO_PXSELC(3) = 0x40000000; \ - REG_GPIO_PXPES(3) = 0x40000000; \ -} while (0) - -/* - * PWM7 - */ -#define __gpio_as_pwm7() \ -do { \ - REG_GPIO_PXFUNS(3) = 0x80000000; \ - REG_GPIO_PXSELC(3) = 0x80000000; \ - REG_GPIO_PXPES(3) = 0x80000000; \ -} while (0) - -/* - * n = 0 ~ 7 - */ -#define __gpio_as_pwm(n) __gpio_as_pwm##n() - -//------------------------------------------- -// GPIO or Interrupt Mode - -#define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) - -#define __gpio_port_as_output(p, o) \ -do { \ - REG_GPIO_PXFUNC(p) = (1 << (o)); \ - REG_GPIO_PXSELC(p) = (1 << (o)); \ - REG_GPIO_PXDIRS(p) = (1 << (o)); \ -} while (0) - -#define __gpio_port_as_input(p, o) \ -do { \ - REG_GPIO_PXFUNC(p) = (1 << (o)); \ - REG_GPIO_PXSELC(p) = (1 << (o)); \ - REG_GPIO_PXDIRC(p) = (1 << (o)); \ -} while (0) - -#define __gpio_as_output(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_output(p, o); \ -} while (0) - -#define __gpio_as_input(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_input(p, o); \ -} while (0) - -#define __gpio_set_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXDATS(p) = (1 << o); \ -} while (0) - -#define __gpio_clear_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXDATC(p) = (1 << o); \ -} while (0) - -#define __gpio_get_pin(n) \ -({ \ - unsigned int p, o, v; \ - p = (n) / 32; \ - o = (n) % 32; \ - if (__gpio_get_port(p) & (1 << o)) \ - v = 1; \ - else \ - v = 0; \ - v; \ -}) - -#define __gpio_as_irq_high_level(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ - REG_GPIO_PXFUNC(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ - REG_GPIO_PXTRGC(p) = (1 << o); \ - REG_GPIO_PXDIRS(p) = (1 << o); \ - REG_GPIO_PXDATC(p) = (1 << o); \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_as_irq_low_level(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ - REG_GPIO_PXFUNC(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ - REG_GPIO_PXTRGC(p) = (1 << o); \ - REG_GPIO_PXDIRC(p) = (1 << o); \ - REG_GPIO_PXDATC(p) = (1 << o); \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_as_irq_rise_edge(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ - REG_GPIO_PXFUNC(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ - REG_GPIO_PXTRGS(p) = (1 << o); \ - REG_GPIO_PXDIRS(p) = (1 << o); \ - REG_GPIO_PXDATC(p) = (1 << o); \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_as_irq_fall_edge(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ - REG_GPIO_PXFUNC(p) = (1 << o); \ - REG_GPIO_PXSELS(p) = (1 << o); \ - REG_GPIO_PXTRGS(p) = (1 << o); \ - REG_GPIO_PXDIRC(p) = (1 << o); \ - REG_GPIO_PXDATC(p) = (1 << o); \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_mask_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMS(p) = (1 << o); \ -} while (0) - -#define __gpio_unmask_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXIMC(p) = (1 << o); \ -} while (0) - -#define __gpio_ack_irq(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXDATC(p) = (1 << o); \ -} while (0) - -#define __gpio_get_irq() \ -({ \ - unsigned int p, i, tmp, v = 0; \ - for (p = 3; p >= 0; p--) { \ - tmp = REG_GPIO_PXFLG(p); \ - for (i = 0; i < 32; i++) \ - if (tmp & (1 << i)) \ - v = (32*p + i); \ - } \ - v; \ -}) - -#define __gpio_group_irq(n) \ -({ \ - register int tmp, i; \ - tmp = REG_GPIO_PXFLG((n)); \ - for (i=31;i>=0;i--) \ - if (tmp & (1 << i)) \ - break; \ - i; \ -}) - -#define __gpio_enable_pull(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXPEC(p) = (1 << o); \ -} while (0) - -#define __gpio_disable_pull(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - REG_GPIO_PXPES(p) = (1 << o); \ -} while (0) - - -/*************************************************************************** - * CPM - ***************************************************************************/ -#define __cpm_get_pllm() \ - ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) -#define __cpm_get_plln() \ - ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) -#define __cpm_get_pllod() \ - ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) - -#define __cpm_get_cdiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) -#define __cpm_get_hdiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) -#define __cpm_get_pdiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) -#define __cpm_get_mdiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) -#define __cpm_get_ldiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) -#define __cpm_get_udiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) -#define __cpm_get_i2sdiv() \ - ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) -#define __cpm_get_pixdiv() \ - ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) -#define __cpm_get_mscdiv() \ - ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) - -#define __cpm_set_cdiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) -#define __cpm_set_hdiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) -#define __cpm_set_pdiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) -#define __cpm_set_mdiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) -#define __cpm_set_ldiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) -#define __cpm_set_udiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) -#define __cpm_set_i2sdiv(v) \ - (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) -#define __cpm_set_pixdiv(v) \ - (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) -#define __cpm_set_mscdiv(v) \ - (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) - -#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) -#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) -#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) -#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) -#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) -#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) -#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) -#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) - -#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) -#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) -#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) - -#define __cpm_get_cclk_doze_duty() \ - ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) -#define __cpm_set_cclk_doze_duty(v) \ - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) - -#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) -#define __cpm_idle_mode() \ - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) -#define __cpm_sleep_mode() \ - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) - -#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff) -#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) -#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) -#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) -#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) -#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) -#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) -#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) -#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) -#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) -#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) -#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) -#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) -#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) -#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) -#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) -#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) - -#define __cpm_start_all() (REG_CPM_CLKGR = 0x0) -#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) -#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) -#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) -#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) -#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) -#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) -#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) -#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) -#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) -#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) -#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) -#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) -#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) -#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) -#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) -#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) - -#define __cpm_get_o1st() \ - ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) -#define __cpm_set_o1st(v) \ - (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) -#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) -#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) - - -#ifdef CFG_EXTAL -#define JZ_EXTAL CFG_EXTAL -#else -#define JZ_EXTAL 3686400 -#endif -#define JZ_EXTAL2 32768 /* RTC clock */ - -/* PLL output frequency */ -static __inline__ unsigned int __cpm_get_pllout(void) -{ - unsigned long m, n, no, pllout; - unsigned long cppcr = REG_CPM_CPPCR; - unsigned long od[4] = {1, 2, 2, 4}; - if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { - m = __cpm_get_pllm() + 2; - n = __cpm_get_plln() + 2; - no = od[__cpm_get_pllod()]; - pllout = ((JZ_EXTAL) / (n * no)) * m; - } else - pllout = JZ_EXTAL; - return pllout; -} - -/* PLL output frequency for MSC/I2S/LCD/USB */ -static __inline__ unsigned int __cpm_get_pllout2(void) -{ - if (REG_CPM_CPCCR & CPM_CPCCR_PCS) - return __cpm_get_pllout(); - else - return __cpm_get_pllout()/2; -} - -/* CPU core clock */ -static __inline__ unsigned int __cpm_get_cclk(void) -{ - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - return __cpm_get_pllout() / div[__cpm_get_cdiv()]; -} - -/* AHB system bus clock */ -static __inline__ unsigned int __cpm_get_hclk(void) -{ - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - return __cpm_get_pllout() / div[__cpm_get_hdiv()]; -} - -/* Memory bus clock */ -static __inline__ unsigned int __cpm_get_mclk(void) -{ - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - return __cpm_get_pllout() / div[__cpm_get_mdiv()]; -} - -/* APB peripheral bus clock */ -static __inline__ unsigned int __cpm_get_pclk(void) -{ - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - return __cpm_get_pllout() / div[__cpm_get_pdiv()]; -} - -/* LCDC module clock */ -static __inline__ unsigned int __cpm_get_lcdclk(void) -{ - return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); -} - -/* LCD pixel clock */ -static __inline__ unsigned int __cpm_get_pixclk(void) -{ - return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); -} - -/* I2S clock */ -static __inline__ unsigned int __cpm_get_i2sclk(void) -{ - if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { - return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); - } - else { - return JZ_EXTAL; - } -} - -/* USB clock */ -static __inline__ unsigned int __cpm_get_usbclk(void) -{ - if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { - return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); - } - else { - return JZ_EXTAL; - } -} - -/* MSC clock */ -static __inline__ unsigned int __cpm_get_mscclk(void) -{ - return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); -} - -/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ -static __inline__ unsigned int __cpm_get_extalclk(void) -{ - return JZ_EXTAL; -} - -/* RTC clock for CPM,INTC,RTC,TCU,WDT */ -static __inline__ unsigned int __cpm_get_rtcclk(void) -{ - return JZ_EXTAL2; -} - -/* - * Output 24MHz for SD and 16MHz for MMC. - */ -static inline void __cpm_select_msc_clk(int sd) -{ - unsigned int pllout2 = __cpm_get_pllout2(); - unsigned int div = 0; - - if (sd) { - div = pllout2 / 24000000; - } - else { - div = pllout2 / 16000000; - } - - REG_CPM_MSCCDR = div - 1; -} - -/*************************************************************************** - * TCU - ***************************************************************************/ -// where 'n' is the TCU channel -#define __tcu_select_extalclk(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) -#define __tcu_select_rtcclk(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) -#define __tcu_select_pclk(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) - -#define __tcu_select_clk_div1(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) -#define __tcu_select_clk_div4(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) -#define __tcu_select_clk_div16(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) -#define __tcu_select_clk_div64(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) -#define __tcu_select_clk_div256(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) -#define __tcu_select_clk_div1024(n) \ - (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) - -#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) -#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) - -#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) -#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) - -#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) -#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) - -#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) -#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) - -#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) -#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) -#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) -#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) -#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) -#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) -#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) -#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) -#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) -#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) - -#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) -#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) - -#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) -#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) - -#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) -#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) - -#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) -#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) -#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) -#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) - - -/*************************************************************************** - * WDT - ***************************************************************************/ -#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) -#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) -#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) -#define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) - -#define __wdt_select_extalclk() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) -#define __wdt_select_rtcclk() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) -#define __wdt_select_pclk() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) - -#define __wdt_select_clk_div1() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) -#define __wdt_select_clk_div4() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) -#define __wdt_select_clk_div16() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) -#define __wdt_select_clk_div64() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) -#define __wdt_select_clk_div256() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) -#define __wdt_select_clk_div1024() \ - (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) - - -/*************************************************************************** - * UART - ***************************************************************************/ - -#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) -#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) - -#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) -#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) - -#define __uart_enable_receive_irq() \ - ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) -#define __uart_disable_receive_irq() \ - ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) - -#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) -#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) - -#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) - -#define __uart_set_baud(devclk, baud) \ - do { \ - REG8(UART0_LCR) |= UARTLCR_DLAB; \ - REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ - REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ - REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ - } while (0) - -#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) -#define __uart_clear_errors() \ - ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) - -#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) -#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) -#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) -#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) -#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) -#define __uart_receive_char() REG8(UART0_RDR) -#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) -#define __uart_enable_irda() \ - /* Tx high pulse as 0, Rx low pulse as 0 */ \ - ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) - - -/*************************************************************************** - * DMAC - ***************************************************************************/ - -/* n is the DMA channel (0 - 5) */ - -#define __dmac_enable_module() \ - ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) -#define __dmac_disable_module() \ - ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) - -/* p=0,1,2,3 */ -#define __dmac_set_priority(p) \ -do { \ - REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ - REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ -} while (0) - -#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) -#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) - -#define __dmac_enable_descriptor(n) \ - ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) -#define __dmac_disable_descriptor(n) \ - ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) - -#define __dmac_enable_channel(n) \ - ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) -#define __dmac_disable_channel(n) \ - ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) -#define __dmac_channel_enabled(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) - -#define __dmac_channel_enable_irq(n) \ - ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) -#define __dmac_channel_disable_irq(n) \ - ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) - -#define __dmac_channel_transmit_halt_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) -#define __dmac_channel_transmit_end_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) -#define __dmac_channel_address_error_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) -#define __dmac_channel_count_terminated_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) -#define __dmac_channel_descriptor_invalid_detected(n) \ - ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) - -#define __dmac_channel_clear_transmit_halt(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) -#define __dmac_channel_clear_transmit_end(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) -#define __dmac_channel_clear_address_error(n) \ - ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) -#define __dmac_channel_clear_count_terminated(n) \ - ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) -#define __dmac_channel_clear_descriptor_invalid(n) \ - ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) - -#define __dmac_channel_set_single_mode(n) \ - ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) -#define __dmac_channel_set_block_mode(n) \ - ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) - -#define __dmac_channel_set_transfer_unit_32bit(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_16bit(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_8bit(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_16byte(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ -} while (0) - -#define __dmac_channel_set_transfer_unit_32byte(n) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ -} while (0) - -/* w=8,16,32 */ -#define __dmac_channel_set_dest_port_width(n,w) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ -} while (0) - -/* w=8,16,32 */ -#define __dmac_channel_set_src_port_width(n,w) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ - REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ -} while (0) - -/* v=0-15 */ -#define __dmac_channel_set_rdil(n,v) \ -do { \ - REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ - REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ -} while (0) - -#define __dmac_channel_dest_addr_fixed(n) \ - ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) -#define __dmac_channel_dest_addr_increment(n) \ - ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) - -#define __dmac_channel_src_addr_fixed(n) \ - ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) -#define __dmac_channel_src_addr_increment(n) \ - ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) - -#define __dmac_channel_set_doorbell(n) \ - ( REG_DMAC_DMADBSR = (1 << (n)) ) - -#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) -#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) - -static __inline__ int __dmac_get_irq(void) -{ - int i; - for (i = 0; i < MAX_DMA_NUM; i++) - if (__dmac_channel_irq_detected(i)) - return i; - return -1; -} - - -/*************************************************************************** - * AIC (AC'97 & I2S Controller) - ***************************************************************************/ - -#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) -#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) - -#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) -#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) - -#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) -#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) -#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) - -#define __aic_reset() \ -do { \ - REG_AIC_FR |= AIC_FR_RST; \ -} while(0) - - -#define __aic_set_transmit_trigger(n) \ -do { \ - REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ - REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ -} while(0) - -#define __aic_set_receive_trigger(n) \ -do { \ - REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ - REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ -} while(0) - -#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) -#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) -#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) -#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) -#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) -#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) - -#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) -#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) - -#define __aic_enable_transmit_intr() \ - ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) -#define __aic_disable_transmit_intr() \ - ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) -#define __aic_enable_receive_intr() \ - ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) -#define __aic_disable_receive_intr() \ - ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) - -#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) -#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) -#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) -#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) - -#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) -#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) -#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) -#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) -#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) -#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) - -#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 -#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 -#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 -#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 -#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 -#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 - -#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 -#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 -#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 -#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 -#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 -#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 - -#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) -#define __ac97_set_xs_mono() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ -} while(0) -#define __ac97_set_xs_stereo() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ -} while(0) - -/* In fact, only stereo is support now. */ -#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) -#define __ac97_set_rs_mono() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ -} while(0) -#define __ac97_set_rs_stereo() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ -} while(0) - -#define __ac97_warm_reset_codec() \ - do { \ - REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ - REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ - udelay(2); \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ - } while (0) - -#define __ac97_cold_reset_codec() \ - do { \ - REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ - udelay(2); \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ - } while (0) - -/* n=8,16,18,20 */ -#define __ac97_set_iass(n) \ - ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) -#define __ac97_set_oass(n) \ - ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) - -#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) -#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) - -/* n=8,16,18,20,24 */ -/*#define __i2s_set_sample_size(n) \ - ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ - -#define __i2s_set_oss_sample_size(n) \ - ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) -#define __i2s_set_iss_sample_size(n) \ - ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) - -#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) -#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) - -#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) -#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) -#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) -#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) - -#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) - -#define __aic_get_transmit_resident() \ - ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) -#define __aic_get_receive_count() \ - ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) - -#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) -#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) -#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) -#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) -#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) -#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) -#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) - -#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) - -#define CODEC_READ_CMD (1 << 19) -#define CODEC_WRITE_CMD (0 << 19) -#define CODEC_REG_INDEX_BIT 12 -#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ -#define CODEC_REG_DATA_BIT 4 -#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ - -#define __ac97_out_rcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ -} while (0) - -#define __ac97_out_wcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ -} while (0) - -#define __ac97_out_data(value) \ -do { \ - REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ -} while (0) - -#define __ac97_in_data() \ - ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) - -#define __ac97_in_status_addr() \ - ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) - -#define __i2s_set_sample_rate(i2sclk, sync) \ - ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) - -#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) -#define __aic_read_rfifo() ( REG_AIC_DR ) - -#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) -#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) - -// -// Define next ops for AC97 compatible -// - -#define AC97_ACSR AIC_ACSR - -#define __ac97_enable() __aic_enable(); __aic_select_ac97() -#define __ac97_disable() __aic_disable() -#define __ac97_reset() __aic_reset() - -#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __ac97_enable_record() __aic_enable_record() -#define __ac97_disable_record() __aic_disable_record() -#define __ac97_enable_replay() __aic_enable_replay() -#define __ac97_disable_replay() __aic_disable_replay() -#define __ac97_enable_loopback() __aic_enable_loopback() -#define __ac97_disable_loopback() __aic_disable_loopback() - -#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() -#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() -#define __ac97_enable_receive_dma() __aic_enable_receive_dma() -#define __ac97_disable_receive_dma() __aic_disable_receive_dma() - -#define __ac97_transmit_request() __aic_transmit_request() -#define __ac97_receive_request() __aic_receive_request() -#define __ac97_transmit_underrun() __aic_transmit_underrun() -#define __ac97_receive_overrun() __aic_receive_overrun() - -#define __ac97_clear_errors() __aic_clear_errors() - -#define __ac97_get_transmit_resident() __aic_get_transmit_resident() -#define __ac97_get_receive_count() __aic_get_receive_count() - -#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() -#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() -#define __ac97_enable_receive_intr() __aic_enable_receive_intr() -#define __ac97_disable_receive_intr() __aic_disable_receive_intr() - -#define __ac97_write_tfifo(v) __aic_write_tfifo(v) -#define __ac97_read_rfifo() __aic_read_rfifo() - -// -// Define next ops for I2S compatible -// - -#define I2S_ACSR AIC_I2SSR - -#define __i2s_enable() __aic_enable(); __aic_select_i2s() -#define __i2s_disable() __aic_disable() -#define __i2s_reset() __aic_reset() - -#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __i2s_enable_record() __aic_enable_record() -#define __i2s_disable_record() __aic_disable_record() -#define __i2s_enable_replay() __aic_enable_replay() -#define __i2s_disable_replay() __aic_disable_replay() -#define __i2s_enable_loopback() __aic_enable_loopback() -#define __i2s_disable_loopback() __aic_disable_loopback() - -#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() -#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() -#define __i2s_enable_receive_dma() __aic_enable_receive_dma() -#define __i2s_disable_receive_dma() __aic_disable_receive_dma() - -#define __i2s_transmit_request() __aic_transmit_request() -#define __i2s_receive_request() __aic_receive_request() -#define __i2s_transmit_underrun() __aic_transmit_underrun() -#define __i2s_receive_overrun() __aic_receive_overrun() - -#define __i2s_clear_errors() __aic_clear_errors() - -#define __i2s_get_transmit_resident() __aic_get_transmit_resident() -#define __i2s_get_receive_count() __aic_get_receive_count() - -#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() -#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() -#define __i2s_enable_receive_intr() __aic_enable_receive_intr() -#define __i2s_disable_receive_intr() __aic_disable_receive_intr() - -#define __i2s_write_tfifo(v) __aic_write_tfifo(v) -#define __i2s_read_rfifo() __aic_read_rfifo() - -#define __i2s_reset_codec() \ - do { \ - } while (0) - - -/*************************************************************************** - * ICDC - ***************************************************************************/ -#define __i2s_internal_codec() __aic_internal_codec() -#define __i2s_external_codec() __aic_external_codec() - -/*************************************************************************** - * INTC - ***************************************************************************/ -#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) -#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) -#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) - - -/*************************************************************************** - * I2C - ***************************************************************************/ - -#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) -#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) - -#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) -#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) -#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) -#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) - -#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) -#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) -#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) - -#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) -#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) -#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) - -#define __i2c_set_clk(dev_clk, i2c_clk) \ - ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) - -#define __i2c_read() ( REG_I2C_DR ) -#define __i2c_write(val) ( REG_I2C_DR = (val) ) - - -/*************************************************************************** - * MSC - ***************************************************************************/ - -#define __msc_start_op() \ - ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) - -#define __msc_set_resto(to) ( REG_MSC_RESTO = to ) -#define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) -#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) -#define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) -#define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) -#define __msc_get_nob() ( REG_MSC_NOB ) -#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) -#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) -#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) -#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) - -#define __msc_set_cmdat_bus_width1() \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ - REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ -} while(0) - -#define __msc_set_cmdat_bus_width4() \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ - REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ -} while(0) - -#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) -#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) -#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) -#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) -#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) -#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) -#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) -#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) - -/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ -#define __msc_set_cmdat_res_format(r) \ -do { \ - REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ - REG_MSC_CMDAT |= (r); \ -} while(0) - -#define __msc_clear_cmdat() \ - REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ - MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ - MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) - -#define __msc_get_imask() ( REG_MSC_IMASK ) -#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) -#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) -#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) -#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) -#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) -#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) -#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) -#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) -#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) -#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) -#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) -#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) - -/* n=0,1,2,3,4,5,6,7 */ -#define __msc_set_clkrt(n) \ -do { \ - REG_MSC_CLKRT = n; \ -} while(0) - -#define __msc_get_ireg() ( REG_MSC_IREG ) -#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) -#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) -#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) -#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) -#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) -#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) -#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) -#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) - -#define __msc_get_stat() ( REG_MSC_STAT ) -#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) -#define __msc_stat_crc_err() \ - ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) -#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) -#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) -#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) -#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) -#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) - -#define __msc_rd_resfifo() ( REG_MSC_RES ) -#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) -#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) - -#define __msc_reset() \ -do { \ - REG_MSC_STRPCL = MSC_STRPCL_RESET; \ - while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ -} while (0) - -#define __msc_start_clk() \ -do { \ - REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ -} while (0) - -#define __msc_stop_clk() \ -do { \ - REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ -} while (0) - -#define MMC_CLK 19169200 -#define SD_CLK 24576000 - -/* msc_clk should little than pclk and little than clk retrieve from card */ -#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ -do { \ - unsigned int rate, pclk, i; \ - pclk = dev_clk; \ - rate = type?SD_CLK:MMC_CLK; \ - if (msc_clk && msc_clk < pclk) \ - pclk = msc_clk; \ - i = 0; \ - while (pclk < rate) \ - { \ - i ++; \ - rate >>= 1; \ - } \ - lv = i; \ -} while(0) - -/* divide rate to little than or equal to 400kHz */ -#define __msc_calc_slow_clk_divisor(type, lv) \ -do { \ - unsigned int rate, i; \ - rate = (type?SD_CLK:MMC_CLK)/1000/400; \ - i = 0; \ - while (rate > 0) \ - { \ - rate >>= 1; \ - i ++; \ - } \ - lv = i; \ -} while(0) - - -/*************************************************************************** - * SSI - ***************************************************************************/ - -#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) -#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) -#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) - -#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) - -#define __ssi_select_ce2() \ -do { \ - REG_SSI_CR0 |= SSI_CR0_FSEL; \ - REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ -} while (0) - -#define __ssi_select_gpc() \ -do { \ - REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ - REG_SSI_CR1 |= SSI_CR1_MULTS; \ -} while (0) - -#define __ssi_enable_tx_intr() \ - ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) - -#define __ssi_disable_tx_intr() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) - -#define __ssi_enable_rx_intr() \ - ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) - -#define __ssi_disable_rx_intr() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) - -#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) -#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) - -#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) -#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) - -#define __ssi_finish_receive() \ - ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) - -#define __ssi_disable_recvfinish() \ - ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) - -#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) -#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) - -#define __ssi_flush_fifo() \ - ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) - -#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) - -#define __ssi_spi_format() \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ - REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ - REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ - REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ -} while (0) - -/* TI's SSP format, must clear SSI_CR1.UNFIN */ -#define __ssi_ssp_format() \ -do { \ - REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ - REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ -} while (0) - -/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ -#define __ssi_microwire_format() \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ - REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ - REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ - REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ - REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ -} while (0) - -/* CE# level (FRMHL), CE# in interval time (ITFRM), - clock phase and polarity (PHA POL), - interval time (SSIITR), interval characters/frame (SSIICR) */ - - /* frmhl,endian,mcom,flen,pha,pol MASK */ -#define SSICR1_MISC_MASK \ - ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ - | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ - -#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ -do { \ - REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ - REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ - (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ - ((pha) << 1) | (pol); \ -} while(0) - -/* Transfer with MSB or LSB first */ -#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) -#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) - -#define __ssi_set_frame_length(n) \ - REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) - -/* n = 1 - 16 */ -#define __ssi_set_microwire_command_length(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) - -/* Set the clock phase for SPI */ -#define __ssi_set_spi_clock_phase(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) - -/* Set the clock polarity for SPI */ -#define __ssi_set_spi_clock_polarity(n) \ - ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) - -/* n = 1,4,8,14 */ -#define __ssi_set_tx_trigger(n) \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ - REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ -} while (0) - -/* n = 1,4,8,14 */ -#define __ssi_set_rx_trigger(n) \ -do { \ - REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ - REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ -} while (0) - -#define __ssi_get_txfifo_count() \ - ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) - -#define __ssi_get_rxfifo_count() \ - ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) - -#define __ssi_clear_errors() \ - ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) - -#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) -#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) - -#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) -#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) -#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) - -#define __ssi_set_clk(dev_clk, ssi_clk) \ - ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) - -#define __ssi_receive_data() REG_SSI_DR -#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) - - -/*************************************************************************** - * CIM - ***************************************************************************/ - -#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) -#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) - -#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) -#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) - -#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) -#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) - -#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) -#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) - -#define __cim_sample_data_at_pclk_falling_edge() \ - ( REG_CIM_CFG |= CIM_CFG_PCP ) -#define __cim_sample_data_at_pclk_rising_edge() \ - ( REG_CIM_CFG &= ~CIM_CFG_PCP ) - -#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) -#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) - -#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) -#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) - -/* n=0-7 */ -#define __cim_set_data_packing_mode(n) \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ - REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ -} while (0) - -#define __cim_enable_ccir656_progressive_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ -} while (0) - -#define __cim_enable_ccir656_interlace_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ -} while (0) - -#define __cim_enable_gated_clock_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ -} while (0) - -#define __cim_enable_nongated_clock_mode() \ -do { \ - REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ - REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ -} while (0) - -/* sclk:system bus clock - * mclk: CIM master clock - */ -#define __cim_set_master_clk(sclk, mclk) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ - REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ -} while (0) - -#define __cim_enable_sof_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) -#define __cim_disable_sof_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) - -#define __cim_enable_eof_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) -#define __cim_disable_eof_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) - -#define __cim_enable_stop_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) -#define __cim_disable_stop_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) - -#define __cim_enable_trig_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) -#define __cim_disable_trig_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) - -#define __cim_enable_rxfifo_overflow_intr() \ - ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) -#define __cim_disable_rxfifo_overflow_intr() \ - ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) - -/* n=1-16 */ -#define __cim_set_frame_rate(n) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ - REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ -} while (0) - -#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) -#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) - -#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) -#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) - -/* n=4,8,12,16,20,24,28,32 */ -#define __cim_set_rxfifo_trigger(n) \ -do { \ - REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ - REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ -} while (0) - -#define __cim_clear_state() ( REG_CIM_STATE = 0 ) - -#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) -#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) -#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) -#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) -#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) -#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) -#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) -#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) - -#define __cim_get_iid() ( REG_CIM_IID ) -#define __cim_get_image_data() ( REG_CIM_RXFIFO ) -#define __cim_get_dam_cmd() ( REG_CIM_CMD ) - -#define __cim_set_da(a) ( REG_CIM_DA = (a) ) - -/*************************************************************************** - * LCD - ***************************************************************************/ -#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<> LCD_VSYNC_VPS_BIT ) - -#define __lcd_vsync_get_vpe() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) -#define __lcd_vsync_set_vpe(n) \ -do { \ - REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ - REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ -} while (0) - -#define __lcd_hsync_get_hps() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) -#define __lcd_hsync_set_hps(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ -} while (0) - -#define __lcd_hsync_get_hpe() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) -#define __lcd_hsync_set_hpe(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ -} while (0) - -#define __lcd_vat_get_ht() \ - ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) -#define __lcd_vat_set_ht(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ -} while (0) - -#define __lcd_vat_get_vt() \ - ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) -#define __lcd_vat_set_vt(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ -} while (0) - -#define __lcd_dah_get_hds() \ - ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) -#define __lcd_dah_set_hds(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ -} while (0) - -#define __lcd_dah_get_hde() \ - ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) -#define __lcd_dah_set_hde(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ -} while (0) - -#define __lcd_dav_get_vds() \ - ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) -#define __lcd_dav_set_vds(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ -} while (0) - -#define __lcd_dav_get_vde() \ - ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) -#define __lcd_dav_set_vde(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ -} while (0) - -#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) -#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) -#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) -#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) - -#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) -#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) -#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) -#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) - -#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) -#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) - -#define __lcd_cmd0_get_len() \ - ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) -#define __lcd_cmd1_get_len() \ - ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) - -#endif /* !__ASSEMBLY__ */ - -#endif /* __JZ4740_H__ */ diff --git a/nandprog/include/nand_ecc.h b/nandprog/include/nand_ecc.h deleted file mode 100644 index ac8650e..0000000 --- a/nandprog/include/nand_ecc.h +++ /dev/null @@ -1,89 +0,0 @@ -#ifndef __NAND_ECC_H__ -#define __NAND_ECC_H__ - -#include "include.h" - -// This head file define these ecc position and ecc types -struct nand_oobinfo oob_64[] = -{ -{ - .eccname = JZ4730CPU, - .eccbytes = 24, - .eccpos = - { - 4, 5, 6, - 8, 9, 10, - 12,13,14, - 16,17,18, - 20,21,22, - 24,25,26, - 28,29,30, - 32,33,34, - }, -}, -{ - .eccname = LINUXHM, - .eccbytes = 24, - .eccpos = - { - 41, 40, 42, - 44, 43, 45, - 47, 46, 48, - 50, 49, 51, - 53, 52, 54, - 56, 55, 57, - 59, 58, 60, - 62, 61, 63 - -/* old need change position - 40, 41, 42, - 43, 44, 45, - 46, 47, 48, - 49, 50, 51, - 52, 53, 54, - 55, 56, 57, - 58, 59, 60, - 61, 62, 63 - - */ - }, -}, -{ - .eccname = JZ4740CPU, - .eccbytes = 36, - .eccpos = - { - 6, 7, 8, 9, 10,11,12,13,14, - 15,16,17,18,19,20,21,22,23, - 24,25,26,27,28,29,30,31,32, - 33,34,35,36,37,38,39,40,41 - }, - -}, -{ - .eccname = LINUXRS, - .eccbytes = 36, - .eccpos = - { - 28, 29, 30, 31, - 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63 - }, - -}, - -{ //this one must update by config file - .eccname = USERSPEC, - .eccbytes = 64, - .eccpos = - { - 0, 0, 0, 0, - }, - -}, - -}; - -#endif diff --git a/nandprog/jz4730/nandflash_4730.c b/nandprog/jz4730/nandflash_4730.c deleted file mode 100755 index e0a1eee..0000000 --- a/nandprog/jz4730/nandflash_4730.c +++ /dev/null @@ -1,606 +0,0 @@ -/* - * Common NAND Flash operations for JZ4730. - * - * This software is free. - */ - -#include "jz4730.h" -#include "include.h" - -unsigned int EMC_BASE; -extern struct nand_oobinfo oob_64[]; - -/* - * Standard NAND commands. - */ -#define CMD_READA 0x00 -#define CMD_READB 0x01 -#define CMD_READC 0x50 -#define CMD_ERASE_SETUP 0x60 -#define CMD_ERASE 0xD0 -#define CMD_READ_STATUS 0x70 -#define CMD_CONFIRM 0x30 -#define CMD_SEQIN 0x80 -#define CMD_PGPROG 0x10 -#define CMD_READID 0x90 -#define CMD_RESET 0xff - -#define ECC_BLOCK 256 /* 3-bytes HW ECC per 256-bytes data */ -#define ECC_OFFSET 4 /* ECC store location offset to the spare area */ - -/* - * NAND routines. - */ -#define nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE | EMC_NFCSR_FCE) -#define nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFE | EMC_NFCSR_FCE)) -#define nand_ecc_enable() (REG_EMC_NFCSR |= EMC_NFCSR_ECCE | EMC_NFCSR_ERST) -#define nand_ecc_disable() (REG_EMC_NFCSR &= ~EMC_NFCSR_ECCE) -#define nand_ready() (REG_EMC_NFCSR & EMC_NFCSR_RB) -#define nand_ecc() (REG_EMC_NFECC & 0x00ffffff) -#define nand_cmd(n) (REG8(cmdport+csn) = (n)) -#define nand_addr(n) (REG8(addrport+csn) = (n)) -#define nand_data8() REG8(dataport+csn) -#define nand_data16() REG16(dataport+csn) - -static inline void nand_wait_ready(void) -{ - u32 to = 1000; - while (nand_ready() && to--); - while (!nand_ready()); -} - -static volatile unsigned char *emcbase = 0; -static volatile unsigned char *addrport = 0; -static volatile unsigned char *dataport = 0; -static volatile unsigned char *cmdport = 0; - -static u32 bus = 8, row = 2, pagesize = 512, oobsize = 16, ppb = 32; -static u32 bad_block_pos = 0 , bad_block_page =0, csn =0; -static struct nand_oobinfo *oob_pos; -static np_data *np; - -/* - * notify(int param) - * - * param value: - * 0 : Ok - * -1: page op fail - * -2: hit bad block, skip it. - */ - -static int (*write_proc)(unsigned char *, int) = 0; -static int (*read_proc)(unsigned char *, int) = 0; - -static u8 badbuf[2048 + 64] = {0}; -static u8 oobbuf[64] = {0}; - - -/* - * I/O read/write interface. - */ -static inline int nand_data_write8(unsigned char *buf, int count) -{ - int i; - u8 *p = (u8 *)buf; - - for (i = 0; i < count; i++) - nand_data8() = *p++; - return 0; -} - -static inline int nand_data_write16(unsigned char *buf, int count) -{ - int i; - u16 *p = (u16 *)buf; - - for (i = 0; i < count/2; i++) - nand_data16() = *p++; - return 0; -} - -static inline int nand_data_read8(unsigned char *buf, int count) -{ - int i; - u8 *p = (u8 *)buf; - - for (i = 0; i < count; i++) - *p++ = nand_data8(); - return 0; -} - -static inline int nand_data_read16(unsigned char *buf, int count) -{ - int i; - u16 *p = (u16 *)buf; - - for (i = 0; i < count/2; i++) - *p++ = nand_data16(); - return 0; -} - -int chip_select_4730(u8 cs) -{ - csn = (u32)cs << 15; //modify this number for your board - return 0; -} - -/* - * Init nand parameters and enable nand controller. - */ -int nand_init_4730(np_data *npp) -{ - bus = npp->bw; - row = npp->rc; - pagesize = npp->ps; - oobsize = npp->os; - ppb = npp->ppb; - bad_block_pos = npp->bbp; - bad_block_page = npp->bba; - - if (bus == 8) { - write_proc = nand_data_write8; - read_proc = nand_data_read8; - } else { - write_proc = nand_data_write16; - read_proc = nand_data_read16; - } - emcbase = (u8 *)npp->base_map; - dataport = (u8 *)npp->port_map; - addrport = (u8 *)((u32)dataport + npp->ap_offset); - cmdport = (u8 *)((u32)dataport + npp->cp_offset); - - EMC_BASE = (u32)emcbase; - oob_pos = &oob_64[npp->ep]; - np = npp; - nand_enable(); - chip_select_4730(npp->cs); - return 0; -} - -/* - * Disable nand operation. - */ -int nand_fini_4730(void) -{ - nand_disable(); - return 0; -} - -/* - * Read ID. - */ -unsigned int nand_query_4730(void) -{ - u16 vid, did; - - nand_cmd(CMD_READID); - nand_addr(0); - - vid = nand_data8(); - did = nand_data8(); - - return (vid << 16) | did; -} - -/* - * Read oob data for 512B pagesize. - */ -static void read_oob_512(void *buf, u32 oobsize, u32 pg) -{ - int i; - u32 rowaddr; - - rowaddr = pg; - - nand_cmd(0x50); - nand_addr(0); - for (i = 0; i < row; i++) { - nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - nand_wait_ready(); - - read_proc(buf, oobsize); -} - -/* - * Read oob data for 2KB pagesize. - */ -static void read_oob_2048(u8 *buf, u32 oobsize, u32 pg) -{ - u32 i, coladdr, rowaddr; - - - coladdr = 2048; - rowaddr = pg; - - nand_cmd(CMD_READA); - nand_addr(coladdr & 0xff); - nand_addr(coladdr >> 8); - for (i = 0; i < row; i++) { - nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - nand_cmd(CMD_CONFIRM); - nand_wait_ready(); - read_proc(buf, oobsize); -} - -/* - * Read oob data. - */ -static void read_oob(u8 *buf, int oobsize, int pg) -{ - if (pagesize == 2048) - read_oob_2048(buf, oobsize, pg); - else - read_oob_512(buf, oobsize, pg); -} - -/* - * Return 1 if the block is bad block, else return 0. - */ -int nand_check_block(u32 block) -{ - u32 pg; - -// pg = block * ppb; - pg = block * ppb + bad_block_page; - //bad block ID locate No.bad_block_page - read_oob(oobbuf, oobsize, pg); - if (oobbuf[bad_block_pos] != 0xff) - return -1; - read_oob(oobbuf, oobsize, pg + 1); - if (oobbuf[bad_block_pos] != 0xff) - return -1; - - return 0; -} - -/* - * Mark a block bad. - */ -void nand_block_markbad(u32 block) -{ - u32 i, rowaddr; - - for (i = 0; i < pagesize + oobsize; i++) - badbuf[i] = 0xff; - badbuf[pagesize + bad_block_pos] = 0; /* bad block flag */ - - rowaddr = block * ppb + bad_block_page; - //bad block ID locate No.bad_block_page - - nand_cmd(CMD_READA); - nand_cmd(CMD_SEQIN); - - nand_addr(0); - if (pagesize == 2048) - nand_addr(0); - for (i = 0; i < row; i++) { - nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - write_proc((unsigned char *)badbuf, pagesize + oobsize); - nand_cmd(CMD_PGPROG); - nand_wait_ready(); -} - -/* - * Erase blocks from block . - */ -int nand_erase_4730(int blk_num, int sblk, int force) -{ - int i, cnt; - u32 cur_blk, rowaddr; - - force = 0; - /* Send reset command to nand */ - nand_cmd(CMD_RESET); - nand_wait_ready(); - - cur_blk = sblk; - cnt = 0; - while (cnt < blk_num) { - /* - * if force flag was not set, check for bad block. - * if force flag was set, erase anything. - */ -#if 1 - //we do force erase for ever?? - if (!force) { - if (nand_check_block(cur_blk)) { - cur_blk ++; /* Bad block, set to next block */ - continue; - } - } -#endif - nand_cmd(CMD_ERASE_SETUP); - - rowaddr = cur_blk * ppb; - for (i = 0; i < row; i++) { - nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - nand_cmd(CMD_ERASE); - nand_wait_ready(); - - nand_cmd(CMD_READ_STATUS); - nand_wait_ready(); - - if (nand_data8() & 0x01) { - /* Erase Error, mark it as bad block */ - nand_block_markbad(cur_blk); - - } else { - /* Erase OK */ - cnt++; - } - cur_blk++; - } - - return 0; -} - - -/* - * Do nand hw ecc correction. - */ -int nand_hw_ecc_correct(u8 *buf, u8 *stored_ecc, u8 *calc_ecc, int eccblock) -{ - u32 i, j, ecc_bit,a,b,c,tmp; - int res = 0; - - for (i = 0; i < eccblock; i++) { - a=stored_ecc[oob_pos->eccpos[i*3+0]] ^ calc_ecc[i*4+0]; - b=stored_ecc[oob_pos->eccpos[i*3+1]] ^ calc_ecc[i*4+1]; - c=stored_ecc[oob_pos->eccpos[i*3+2]] ^ calc_ecc[i*4+2]; - tmp = (c<<16) + (b<<8) +a; -#if 0 - printf("AAAAAAAA %x %x %x : %x %x %x %x\n", - stored_ecc[oob_pos->eccpos[i*3+0]], - stored_ecc[oob_pos->eccpos[i*3+1]], - stored_ecc[oob_pos->eccpos[i*3+2]], - calc_ecc[i*4+0], - calc_ecc[i*4+1], - calc_ecc[i*4+2], - tmp); -#endif - if (tmp) { /* ECC error */ - ecc_bit = 0; - for (j = 0; j < 24; j++) - if ((tmp >> j) & 0x01) - ecc_bit ++; - if (ecc_bit == 11) { /* Correctable error */ - u8 idx; - - ecc_bit = 0; - for (j = 12; j >= 1; j--) { - ecc_bit <<= 1; - ecc_bit |= ((tmp >> (j*2-1)) & 0x01); - } - idx = ecc_bit & 0x07; - - buf[i * ECC_BLOCK + (ecc_bit >> 3)] ^= (1 << idx); - } - else { /* Fatal error */ - //if ecc all ff means this page no data! - if (stored_ecc[oob_pos->eccpos[i*3+0]]==0xff - &&stored_ecc[oob_pos->eccpos[i*3+1]]==0xff - &&stored_ecc[oob_pos->eccpos[i*3+2]]==0xff ) - return res; -// printf("Uncorrectable ecc error!\n"); - res = -1; - } - } - } - return res; -} - -/* - * Read data pages from page. - * Skip bad block if detected. - * HW ECC is used. - */ -int nand_read_4730(u8 *buf, u32 startpage, u32 pagenum) -{ - u32 cnt, i; - u32 cur_page, rowaddr, eccblock; - u32 calc_ecc[8]; - u8 *tmpbuf,*stored_ecc; - - eccblock = pagesize / ECC_BLOCK; - cur_page = startpage; - cnt = 0; - while (cnt < pagenum) { - - //we do not check bad block here! -#if 0 - if ((cur_page % ppb) == 0) { - cur_blk = cur_page / ppb; - if (nand_check_block(cur_blk)) { - cur_page += ppb; /* Bad block, set to next block */ - continue; - } - } -#endif - nand_cmd(CMD_READA); - nand_addr(0); - if (pagesize == 2048) - nand_addr(0); - - rowaddr = cur_page; - for (i = 0; i < row; i++) { - nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - if (pagesize == 2048) - nand_cmd(CMD_CONFIRM); - - nand_wait_ready(); - tmpbuf = (u8 *)((u32)buf + cnt * (pagesize + oobsize)); - for (i = 0; i < eccblock; i++) { - nand_ecc_enable(); - read_proc(tmpbuf, ECC_BLOCK); - nand_ecc_disable(); - calc_ecc[i] = nand_ecc(); - if (oob_pos->eccname == LINUXHM) - calc_ecc[i] = ~(calc_ecc[i]) | 0x00030000; - tmpbuf += ECC_BLOCK; - } - read_proc((u8 *)tmpbuf, oobsize); - tmpbuf = (u8 *)((u32)buf + cnt * (pagesize + oobsize)); - //read ecc from oob - stored_ecc = (u8 *)(((u32)tmpbuf) + pagesize ); - - /* Check ECC */ - nand_hw_ecc_correct(tmpbuf, stored_ecc, (u8 *)calc_ecc, eccblock); - cur_page++; - cnt++; - } - return 0; -} - -/* - * Read data pages from page. - * Don't skip bad block. - * Don't use HW ECC. - */ -int nand_read_raw_4730(u8 *buf, u32 startpage, u32 pagenum) -{ - u32 cnt, i; - u32 cur_page, rowaddr; - u8 *tmpbuf; - - tmpbuf = (u8 *)buf; - - cur_page = startpage; - cnt = 0; - while (cnt < pagenum) { - nand_cmd(CMD_READA); - nand_addr(0); - if (pagesize == 2048) - nand_addr(0); - - rowaddr = cur_page; - for (i = 0; i < row; i++) { - nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - if (pagesize == 2048) - nand_cmd(CMD_CONFIRM); - - nand_wait_ready(); - - read_proc(tmpbuf, pagesize); - - tmpbuf += pagesize; - cur_page++; - cnt++; - } - - return 0; -} - -/* - * Read oob pages from page. - * Don't skip bad block. - * Don't use HW ECC. - */ -int nand_read_oob_4730(u8 *buf, u32 startpage, u32 pagenum) -{ - u32 cnt, cur_page; - u8 *tmpbuf; - - tmpbuf = (u8 *)buf; - - cur_page = startpage; - cnt = 0; - while (cnt < pagenum) { - read_oob((void *)tmpbuf, oobsize, cur_page); - - tmpbuf += oobsize; - cur_page++; - cnt++; - } - - return 0; -} - -/* - * Write pages from page. - * Skip bad block if detected. - */ -int nand_program_4730(u8 *buf, int startpage, int pagenum) -{ - u32 cnt, i,j; - u32 cur_page, rowaddr, eccblock; - u8 *tmpbuf; - - tmpbuf = (u8 *)buf; - - eccblock = pagesize / ECC_BLOCK; - - cur_page = startpage; - cnt = 0; - while (cnt < pagenum) { - //do not check bad block here! check uplayer! - - for (j=0;jos;j++) - { - if (tmpbuf[j+np->ps]!=0xff) - break; - } - - if (j==np->os) - { - tmpbuf += np->ps+np->os; - cur_page ++; - cnt ++; - continue; - } - -// nand_wait_ready(); - nand_cmd(CMD_READA); - nand_cmd(CMD_SEQIN); - - nand_addr(0); - if (pagesize == 2048) - nand_addr(0); - - rowaddr = cur_page; - for (i = 0; i < row; i++) { - nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - /* Write out data and oob*/ - // we don't need work out ecc - //because it already exist in image file - - write_proc(tmpbuf, np->ps+np->os); - tmpbuf += np->ps+np->os; - nand_cmd(CMD_PGPROG); - nand_wait_ready(); - - nand_cmd(CMD_READ_STATUS); -// nand_wait_ready(); - - if (nand_data8() & 0x01) { - /* Page program error. - * Note: we should mark this block bad, and copy data of this - * block to a new block. - */ - ; - } else { - ; - } - - cur_page ++; - cnt ++; - } - return cnt; -} diff --git a/nandprog/jz4740/nandflash_4740.c b/nandprog/jz4740/nandflash_4740.c deleted file mode 100755 index 05ae9a7..0000000 --- a/nandprog/jz4740/nandflash_4740.c +++ /dev/null @@ -1,734 +0,0 @@ -/* - * Common NAND Flash operations for JZ4740. - * - * This software is free. - */ - -#include "jz4740.h" -#include "include.h" - -extern struct nand_oobinfo oob_64[]; - -#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1) -#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1|EMC_NFCSR_NFE1 )) -#define __nand_ecc_rs_encoding() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING) -#define __nand_ecc_rs_decoding() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING) -#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) -#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF)) -#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF)) -#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST ) -#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) - -#define __nand_select_hm_ecc() (REG_EMC_NFECR &= ~EMC_NFECR_RS ) -#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS) - -#define __nand_read_hm_ecc() (REG_EMC_NFECC & 0x00ffffff) - -#define __nand_ecc() (REG_EMC_NFECC & 0x00ffffff) -#define __nand_cmd(n) (REG8(cmdport+csn) = (n)) -#define __nand_addr(n) (REG8(addrport+csn) = (n)) -#define __nand_data8() REG8(dataport+csn) -#define __nand_data16() REG16(dataport+csn) - -#define CMD_READA 0x00 -#define CMD_READB 0x01 -#define CMD_READC 0x50 -#define CMD_ERASE_SETUP 0x60 -#define CMD_ERASE 0xD0 -#define CMD_READ_STATUS 0x70 -#define CMD_CONFIRM 0x30 -#define CMD_SEQIN 0x80 -#define CMD_PGPROG 0x10 -#define CMD_READID 0x90 - -#define OOB_BAD_OFF 0x00 -#define OOB_ECC_OFF 0x04 - -#define OP_ERASE 0 -#define OP_WRITE 1 -#define OP_READ 2 - -#define ECC_BLOCK 512 -#define ECC_POS 6 -#define PAR_SIZE 9 - -static volatile unsigned char *gpio_base; -static volatile unsigned char *emc_base; -static volatile unsigned char *addrport; -static volatile unsigned char *dataport; -static volatile unsigned char *cmdport; -unsigned int EMC_BASE; -unsigned int GPIO_BASE; - -static int bus = 8, row = 2, pagesize = 512, oobsize = 16, ppb = 32; -static u32 bad_block_pos = 0,bad_block_page=0, csn = 0; -static u8 badbuf[2048 + 64] = {0}; -static u8 data_buf[2048] = {0}; -static u8 oob_buf[128] = {0}; -static struct nand_oobinfo *oob_pos; -static np_data *np; - -static inline void __nand_sync(void) -{ - unsigned int timeout = 1000; - while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--); - while (!(REG_GPIO_PXPIN(2) & 0x40000000)); -} - -static int read_oob(u8 *buf, u32 size, u32 pg); -static int nand_data_write8(unsigned char *buf, int count); -static int nand_data_write16(unsigned char *buf, int count); -static int nand_data_read8(unsigned char *buf, int count); -static int nand_data_read16(unsigned char *buf, int count); - -static int (*write_proc)(unsigned char *, int) = 0; -static int (*read_proc)(unsigned char *, int) = 0; - -extern void dumpbuf(u8 *p, int count); - -unsigned int nand_query_4740(void) -{ - u16 vid, did; - - __nand_sync(); - __nand_cmd(CMD_READID); - __nand_addr(0); - - vid = __nand_data8(); - did = __nand_data8(); - - return (vid << 16) | did; -} - -int chip_select_4740(u8 cs) -{ - csn = (u32)cs << 15; // modify this number for your board - return 0; -} - -int nand_init_4740(np_data *npp) -{ - bus = npp->bw; - row = npp->rc; - pagesize = npp->ps; - oobsize = npp->os; - ppb = npp->ppb; - bad_block_pos = npp->bbp; - bad_block_page = npp->bba; - gpio_base = (u8 *)npp->gpio_map; - emc_base = (u8 *)npp->base_map; - dataport = (u8 *)npp->port_map; - addrport = (u8 *)((u32)dataport + npp->ap_offset); - cmdport = (u8 *)((u32)dataport + npp->cp_offset); - - EMC_BASE = (u32)emc_base; - GPIO_BASE = (u32)gpio_base; - - /* Initialize NAND Flash Pins */ -// __gpio_as_nand(); -// __nand_enable(); - - chip_select_4740(npp->cs); - if (bus == 8) { - write_proc = nand_data_write8; - read_proc = nand_data_read8; - } else { - write_proc = nand_data_write16; - read_proc = nand_data_read16; - } - - oob_pos = &oob_64[npp->ep]; -// REG_EMC_SMCR1 = 0x0fff7700; - np = npp; - return 0; -} - -int nand_fini_4740(void) -{ - __nand_disable(); - return 0; -} - -/* - * Read oob pages from page. - * Don't skip bad block. - * Don't use HW ECC. - */ -int nand_read_oob_4740(u8 *buf, u32 startpage, u32 pagenum) -{ - u32 cnt, cur_page; - u8 *tmpbuf; - - tmpbuf = (u8 *)buf; - - cur_page = startpage; - cnt = 0; - while (cnt < pagenum) { - read_oob((void *)tmpbuf, oobsize, cur_page); - - tmpbuf += oobsize; - cur_page++; - cnt++; - } - - return 0; -} - -int nand_check_block_4740(u32 block) -{ - u32 pg; - - pg = block * ppb + bad_block_page; - read_oob(oob_buf, oobsize, pg); - if (oob_buf[bad_block_pos] != 0xff) - return -1; - read_oob(oob_buf, oobsize, pg + 1); - if (oob_buf[bad_block_pos] != 0xff) - return -1; - - return 0; -} - -/* - * Mark a block bad. - */ -void nand_block_markbad_4740(u32 block) -{ - u32 i, rowaddr; - - for (i = 0; i < pagesize + oobsize; i++) - badbuf[i] = 0x00; - badbuf[pagesize + bad_block_pos] = 0; /* bad block flag */ - - rowaddr = block * ppb + bad_block_page; - //bad block ID locate No.bad_block_page page - - __nand_cmd(CMD_READA); - __nand_cmd(CMD_SEQIN); - - __nand_addr(0); - if (pagesize == 2048) - __nand_addr(0); - for (i = 0; i < row; i++) { - __nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - write_proc((unsigned char *)badbuf, pagesize + oobsize); - __nand_cmd(CMD_PGPROG); - __nand_sync(); -} - -/* - * Read data pages from page. - * Don't skip bad block. - * Don't use HW ECC. - */ -int nand_read_raw_4740(u8 *buf, u32 startpage, u32 pagenum) -{ - u32 cnt, j; - u32 cur_page, rowaddr; - u8 *tmpbuf; - - tmpbuf = (u8 *)buf; - - cur_page = startpage; - cnt = 0; - while (cnt < pagenum) { - __nand_sync(); - __nand_cmd(CMD_READA); - __nand_addr(0); - if (pagesize == 2048) - __nand_addr(0); - - rowaddr = cur_page; - for (j = 0; j < row; j++) { - __nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - if (pagesize == 2048) - __nand_cmd(CMD_CONFIRM); - - __nand_sync(); - read_proc(tmpbuf, pagesize); - - tmpbuf += pagesize; - cur_page++; - cnt++; - } - - return 0; -} - - -int nand_erase_4740(int blk_num, int sblk, int force) -{ - int i, j; - u32 cur, rowaddr; - - cur = sblk * ppb; - for (i = 0; i < blk_num; i++) { - rowaddr = cur; - - if (!force) { /* if set, erase anything */ - /* test Badflag. */ - __nand_sync(); - - __nand_cmd(CMD_READA); - - __nand_addr(0); - if (pagesize == 2048) - __nand_addr(0); - for (j=0;j>= 8; - } - - if (pagesize == 2048) - __nand_cmd(CMD_CONFIRM); - - __nand_sync(); - - read_proc((u8 *)data_buf, pagesize); - read_proc((u8 *)oob_buf, oobsize); - - if (oob_buf[0] != 0xff) { /* Bad block, skip */ - cur += ppb; - continue; - } - rowaddr = cur; - } - - __nand_cmd(CMD_ERASE_SETUP); - - for (j = 0; j < row; j++) { - __nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - __nand_cmd(CMD_ERASE); - - __nand_sync(); - - __nand_cmd(CMD_READ_STATUS); - - if (__nand_data8() & 0x01) - { - /* Erase Error, mark it as bad block */ - nand_block_markbad(cur); - - } else ; - - cur += ppb; - } - - return 0; -} - -static int read_oob(u8 *buf, u32 size, u32 pg) -{ - u32 i, coladdr, rowaddr; - - if (pagesize == 512) - coladdr = 0; - else - coladdr = pagesize; - - if (pagesize == 512) - /* Send READOOB command */ - __nand_cmd(CMD_READC); - else - /* Send READ0 command */ - __nand_cmd(CMD_READA); - - /* Send column address */ - __nand_addr(coladdr & 0xff); - if (pagesize != 512) - __nand_addr(coladdr >> 8); - - /* Send page address */ - rowaddr = pg; - for (i = 0; i < row; i++) { - __nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - /* Send READSTART command for 2048 ps NAND */ - if (pagesize != 512) - __nand_cmd(CMD_CONFIRM); - - /* Wait for device ready */ - __nand_sync(); - - /* Read oob data */ - read_proc(buf, size); - - return 0; -} - -/* Correct 1~9-bit errors in 512-bytes data */ -static void rs_correct(unsigned char *dat, int idx, int mask) -{ - int i; - - idx--; - - i = idx + (idx >> 3); - if (i >= 512) - return; - - mask <<= (idx & 0x7); - - dat[i] ^= mask & 0xff; - if (i < 511) - dat[i+1] ^= (mask >> 8) & 0xff; -} - -static int nand_hm_correct_data(u8 *dat, u8 *oob_s, u8 *calc_ecc,u8 p) -{ - u8 a, b, c, d1, d2, d3, add, bit, i; - u8 *e1,*e2,*e3; - - e1 = &oob_s[oob_pos->eccpos[p+0]]; - e2 = &oob_s[oob_pos->eccpos[p+1]]; - e3 = &oob_s[oob_pos->eccpos[p+2]]; -// printf("read ecc :%x %x %x %d %d\n",*e1,*e2,*e3, -// oob_pos->eccpos[p+0],oob_pos->eccpos[p+1]); - - d1 = calc_ecc[0] ^ *e1; - d2 = calc_ecc[1] ^ *e2; - d3 = calc_ecc[2] ^ *e3; - - if ((d1 | d2 | d3) == 0) { - /* No errors */ - return 0; - } - else { - a = (d1 ^ (d1 >> 1)) & 0x55; - b = (d2 ^ (d2 >> 1)) & 0x55; - c = (d3 ^ (d3 >> 1)) & 0x54; - - /* Found and will correct single bit error in the data */ - if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { - c = 0x80; - add = 0; - a = 0x80; - for (i=0; i<4; i++) { - if (d1 & c) - add |= a; - c >>= 2; - a >>= 1; - } - c = 0x80; - for (i=0; i<4; i++) { - if (d2 & c) - add |= a; - c >>= 2; - a >>= 1; - } - bit = 0; - b = 0x04; - c = 0x80; - for (i=0; i<3; i++) { - if (d3 & c) - bit |= b; - c >>= 2; - b >>= 1; - } - b = 0x01; - a = dat[add]; - a ^= (b << bit); - dat[add] = a; - return 0; - } - else { - i = 0; - while (d1) { - if (d1 & 0x01) - ++i; - d1 >>= 1; - } - while (d2) { - if (d2 & 0x01) - ++i; - d2 >>= 1; - } - while (d3) { - if (d3 & 0x01) - ++i; - d3 >>= 1; - } - if (i == 1) { - /* ECC Code Error Correction */ - *e1 = calc_ecc[0]; - *e2 = calc_ecc[1]; - *e3 = calc_ecc[2]; - return 0; - } - else { - /* Uncorrectable Error */ -// printf("uncorrectable ECC error\n"); - return -1; - } - } - } - - /* Should never happen */ - return -1; -} - - /* - * Read data pages from page. - * HW ECC is used. - */ -int nand_read_4740_hm(u8 *buf, u32 startpage, u32 pagenum) -{ - u32 j, calc_ecc; - u32 cur_page, cnt, rowaddr, ecccnt; - u8 *tmpbuf; - ecccnt = pagesize / 256; - - cur_page = startpage; - cnt = 0; - while (cnt < pagenum) { - /* read oob first */ - read_oob(oob_buf, oobsize, cur_page); - - __nand_sync(); - __nand_cmd(CMD_READA); - - __nand_addr(0); - if (pagesize == 2048) - __nand_addr(0); - - rowaddr = cur_page; - for (j = 0; j < row; j++) { - __nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - if (pagesize == 2048) - __nand_cmd(CMD_CONFIRM); - __nand_sync(); - tmpbuf = (u8 *)((u32)buf + cnt * ( pagesize+oobsize)); - - for (j = 0; j < ecccnt ; j++) - { - __nand_ecc_enable(); - __nand_select_hm_ecc(); - read_proc(tmpbuf, 256); - __nand_ecc_disable(); - calc_ecc = __nand_read_hm_ecc(); - if (oob_pos->eccname == LINUXHM) - calc_ecc = ~calc_ecc | 0x00030000; - - nand_hm_correct_data(tmpbuf,oob_buf,(u8*)&calc_ecc,j*3); - tmpbuf += 256; - } - - for (j = 0; j < oobsize; j++) - tmpbuf[j] = oob_buf[j]; - - cur_page++; - cnt++; - - } - return 0; -} - - /* - * Read data pages from page. - * HW ECC is used. - */ -int nand_read_4740_rs(u8 *buf, u32 startpage, u32 pagenum) -{ - u32 j, k; - u32 cur_page, cnt, rowaddr, ecccnt; - u8 *tmpbuf; - ecccnt = pagesize / ECC_BLOCK; - - cur_page = startpage; - cnt = 0; - while (cnt < pagenum) { - /* read oob first */ - read_oob(oob_buf, oobsize, cur_page); - - __nand_sync(); - __nand_cmd(CMD_READA); - - __nand_addr(0); - if (pagesize == 2048) - __nand_addr(0); - - rowaddr = cur_page; - for (j = 0; j < row; j++) { - __nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - if (pagesize == 2048) - __nand_cmd(CMD_CONFIRM); - __nand_sync(); - tmpbuf = (u8 *)((u32)buf + cnt * ( pagesize+oobsize)); - - for (j = 0; j < ecccnt ; j++) { - volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0; - u32 stat; - - /* Read data */ - REG_EMC_NFINTS = 0x0; - __nand_ecc_rs_decoding(); - read_proc(tmpbuf, ECC_BLOCK); - - /* Set PAR values */ - for (k = 0; k < PAR_SIZE; k++) { - *paraddr++ = oob_buf[oob_pos->eccpos[j*PAR_SIZE + k]]; - } - - /* Set PRDY */ - REG_EMC_NFECR |= EMC_NFECR_PRDY; - - /* Wait for completion */ - __nand_ecc_decode_sync(); - __nand_ecc_disable(); - - /* Check decoding */ - stat = REG_EMC_NFINTS; - - if (stat & EMC_NFINTS_ERR) { -// printf("Error occured!\n"); - if (stat & EMC_NFINTS_UNCOR) { - int t; - for (t = 0; t < oob_pos->eccbytes; t++) - if (oob_buf[oob_pos->eccpos[t]] != 0xff) break; - if (t < oob_pos->eccbytes-1) { -// printf("Uncorrectable error occurred\n"); - } - } - else { - u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT; - switch (errcnt) { - case 4: - rs_correct(tmpbuf, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); - case 3: - rs_correct(tmpbuf, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); - case 2: - rs_correct(tmpbuf, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); - case 1: - rs_correct(tmpbuf, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); - break; - default: - break; - } - - } - } - /* increment pointer */ - tmpbuf += ECC_BLOCK ; - } - - for (j = 0; j < oobsize; j++) - tmpbuf[j] = oob_buf[j]; - - cur_page++; - cnt++; - } - - return 0; -} - -int nand_program_4740(u8 *context, int spage, int pages) -{ - u32 i, j, cur, rowaddr; - u8 *tmpbuf; - - tmpbuf = (u8 *)context; - i = 0; - cur = spage; - - while (i < pages) { - - for (j=0;jos;j++) - { - if (tmpbuf[j+np->ps]!=0xff) - break; - } - - if (j==np->os) - { - tmpbuf += np->ps+np->os; - i ++; - cur ++; - continue; - } - if (pagesize != 2048) - __nand_cmd(CMD_READA); - - __nand_cmd(CMD_SEQIN); - - __nand_addr(0); - if (pagesize == 2048) - __nand_addr(0); - rowaddr = cur; - for (j = 0; j < row; j++) { - __nand_addr(rowaddr & 0xff); - rowaddr >>= 8; - } - - write_proc(tmpbuf, np->ps+np->os); - tmpbuf += np->ps+np->os; - - /* send program confirm command */ - __nand_cmd(CMD_PGPROG); - __nand_sync(); - - __nand_cmd(CMD_READ_STATUS); -// __nand_sync(); - - if (__nand_data8() & 0x01) { /* page program error */ - return -1; - } else ; - - i ++; - cur ++; - } - return 0; -} - -static int nand_data_write8(unsigned char *buf, int count) -{ - int i; - u8 *p = (u8 *)buf; - for (i=0;i - -# LAYOUT (if partition parameter is not specified) -# Partition table, then -# VFAT takes up remaining space here -# then... -# -EXT3_ROOTFS_SECTORS=$(( 256 * 1024 * 2 )) -EXT3_BACKUP_FS_SECTORS=$(( 8 * 1024 * 2 )) -QI_ALLOCATION=$(( 256 * 2 )) -# -# lastly fixed stuff: 8KByte initial boot, sig, padding -# -# ---------------------- - -echo "s3c6410 bootable SD partitioning utility" -echo "(C) Openmoko, Inc Andy Green " -echo - -# these are fixed in iROM -QI_INITIAL=$(( 8 * 2 )) -SIG=1 - - -# display usage message and exit -# any arguments are displayed as an error message -USAGE() -{ - echo - [ -z "$1" ] || echo ERROR: $* - echo - echo 'This formats a SD card for usage on SD Card boot' - echo ' on 6410 based systems' - echo - echo Usage: $(basename "$0") ' ' - echo ' device = disk device name for SD Card, e.g. sde /dev/sdf' - echo ' card = sd | sdhc' - echo ' bootloader = /path/to/qi-binary' - echo ' partition = vfat | NN | NN,NN | NN,NN,NN | NN,NN,NN,NN | no' - echo ' * vfat -> main-vfat[rest] + rootfs[256M] + backupfs[8M]' - echo ' NN -> rootfs1[NN%] + .. + rootfs4[NN%]' - echo ' NN=0 -> will skip the partition' - echo ' no -> leave partitions alone' - echo - echo 'Note: * => default action if no parameter specified' - echo ' sum(NN) must be in [1..100]' - echo - echo 'e.g. '$(basename "$0")' sdb sdhc images/qi 0,30,0,45' - echo ' will format an SDHC with partition 2 receiving 20% and partition 4' - echo ' receiving 45% of the disk capacity and the remaining 35% will be' - echo ' unused.' - echo ' Capacity is calculated after subtracting the space reserved for Qi.' - echo ' Partitions 1 and 3 will not be used.' - exit 1 -} - -[ -z "$1" -o -z "$2" -o -z "$3" ] && USAGE 'Missing arguments' - -dev="$1" -card="$2" -qi="$3" -partition="$4" - -case "${card}" in - [sS][dD][hH][cC]) - PADDING=1025 - ;; - [sS][dD]) - PADDING=1 - ;; - *) - USAGE "${card} is an unknown card type" -esac - -# the amount of space that must remain unused at the end of the disk -REAR_SECTORS=$(( $QI_ALLOCATION + $QI_INITIAL + $SIG + $PADDING )) - -# validate parameters -[ -b "${dev}" ] || dev="/dev/${dev}" -[ -b "${dev}" ] || USAGE "${dev} is not a valid block device" -[ X"${dev}" = X"${dev%%[0-9]}" ] || USAGE "${dev} is a partition, please use device: perhaps ${dev%%[0-9]}" - -echo "Checking for mounted partitions..." -grep "${dev}" /proc/mounts && USAGE "partitions on ${dev} are mounted, please unmount them" -[ -e "${qi}" ] || USAGE "bootloader file: ${qi} does not exist" - -# get size of device -bytes=$(echo p | fdisk "${dev}" 2>&1 | sed '/^Disk.*, \([0-9]*\) bytes/s//\1/p;d') -SECTORS=$(($bytes / 512)) - -[ -z "$SECTORS" ] && USAGE "could not find size for ${dev}" -[ "$SECTORS" -le 0 ] && USAGE "invalid size: '${SECTORS}' for ${dev}" - -echo "${dev} is $SECTORS 512-byte blocks" - - -# Partition and format a disk (or SD card) -# Parameters to format function are: -# -# device -> device to partition e.g. /dev/sdX -# -# Partition 1 parameters: -# -# label -> file system volume label e.g. rootfs -# sizeMB -> size of the partition in MB e.g. 256 -# fstype -> filesystem type e.g. ext2, ext3, vfat (look at /sbin/mkfs.* for others) -# -# Notes: 1. Repeat "label, sizeMB, fstype" for partitions 2..4 -# 2. Partitions 2..4 are optional -# 3. Do not repeat device parameter -# 4. To skip a partition use: 'null 0 none' for that partition - -FORMAT() -{ - local device label sizeMB fstype p partition flag skip - device="$1"; shift - ( - p=0 - flag=0 - echo o - while [ $# -gt 0 ] - do - label="$1"; shift - sizeMB="$1"; shift - fstype="$1"; shift - p=$((${p} + 1)) - skip=NO - [ ${sizeMB} -le 0 ] && skip=YES - case "${label}" in - [nN][uU][lL][lL]) - skip=YES - ;; - *) - ;; - esac - case "${skip}" in - [yY][eE][sS]|[yY]) - ;; - *) - echo n - echo p - echo ${p} - echo - echo +${sizeMB}M - case "${fstype}" in - [vV][fF][aA][tT]|[mM][sS][dD][oO][sS]) - echo t - # fdisk is "helpful" & will auto select partition if there is only one - # so do not output partition number if this is the first partition - [ "${flag}" -eq 1 ] && echo ${p} - echo 0b - ;; - *) - ;; - esac - flag=1 - ;; - esac - done - echo p - echo w - echo q - ) | fdisk "${device}" - p=0 - while [ $# -gt 0 ] - do - label="$1"; shift - sizeMB="$1"; shift - fstype="$1"; shift - p=$((${p} + 1)) - partition="${dev}${p}" - skip=NO - [ ${sizeMB} -eq 0 ] && skip=YES - case "${label}" in - [nN][uU][lL][lL]) - skip=YES - ;; - esac - - case "${skip}" in - [yY][eE][sS]|[yY]) - echo "Skipping: ${partition}" - ;; - *) - echo "Formatting: ${partition} -> ${fstype}[${sizeMB}MB]" - case "${fstype}" in - [vV][fF][aA][tT]|[mM][sS][dD][oO][sS]) - mkfs.${fstype} -n "${label}" "${partition}" - ;; - *) - mkfs.${fstype} -L "${label}" "${partition}" - ;; - esac - ;; - esac - done -} - -# format the disk -case "${partition}" in - - # this case also hadles the default case (i.e. empty string: "") - [vV][fF][aA][tT]|"") - EXT3_TOTAL_SECTORS=$(( $EXT3_ROOTFS_SECTORS + $EXT3_BACKUP_FS_SECTORS )) - FAT_SECTORS=$(( $SECTORS - $EXT3_TOTAL_SECTORS - $REAR_SECTORS )) - FAT_MB=$(( $FAT_SECTORS / 2048 )) - EXT3_ROOTFS_MB=$(( ${EXT3_ROOTFS_SECTORS} / 2048 )) - EXT3_BACKUP_FS_MB=$(( ${EXT3_BACKUP_FS_SECTORS} / 2048 )) - - echo Creating VFAT partition of ${FAT_MB} MB - echo Creating Linux partition of ${EXT3_ROOTFS_MB} MB - echo Creating backup Linux partition of ${EXT3_BACKUP_FS_MB} MB - FORMAT "${dev}" \ - main-vfat "${FAT_MB}" vfat \ - rootfs "${EXT3_ROOTFS_MB}" ext3 \ - backupfs "${EXT3_BACKUP_FS_MB}" ext3 - ;; - - # decode partition or partition list - *,*|100|[1-9][0-9]|[1-9]) - arg="${partition}," - for v in 1 2 3 4 - do - eval n${v}="\${arg%%,*}" - eval n${v}="\${n${v}:-0}" - arg="${arg#*,}," - done - total=$(( ${n1} + ${n2} + ${n3} + ${n4} )) - echo Percentage of disk partitioned = ${total}% - [ ${total} -gt 100 -o ${total} -lt 1 ] && USAGE partition: "'${partition}' => ${total}% outside [1..100]" - - EXT3_TOTAL_SECTORS=$(( $SECTORS - $REAR_SECTORS )) - EXT3_ROOTFS1_SECTORS=$(( $EXT3_TOTAL_SECTORS * $n1 / 100 )) - EXT3_ROOTFS2_SECTORS=$(( $EXT3_TOTAL_SECTORS * $n2 / 100 )) - EXT3_ROOTFS3_SECTORS=$(( $EXT3_TOTAL_SECTORS * $n3 / 100 )) - EXT3_ROOTFS4_SECTORS=$(( $EXT3_TOTAL_SECTORS * $n4 / 100 )) - EXT3_ROOTFS1_MB=$(( ${EXT3_ROOTFS1_SECTORS} / 2048 )) - EXT3_ROOTFS2_MB=$(( ${EXT3_ROOTFS2_SECTORS} / 2048 )) - EXT3_ROOTFS3_MB=$(( ${EXT3_ROOTFS3_SECTORS} / 2048 )) - EXT3_ROOTFS4_MB=$(( ${EXT3_ROOTFS4_SECTORS} / 2048 )) - - echo Creating Linux partition 1 of ${EXT3_ROOTFS1_MB} MB - echo Creating Linux partition 2 of ${EXT3_ROOTFS2_MB} MB - echo Creating Linux partition 3 of ${EXT3_ROOTFS3_MB} MB - echo Creating Linux partition 4 of ${EXT3_ROOTFS4_MB} MB - - FORMAT "${dev}" \ - rootfs1 "${EXT3_ROOTFS1_MB}" ext3 \ - rootfs2 "${EXT3_ROOTFS2_MB}" ext3 \ - rootfs3 "${EXT3_ROOTFS3_MB}" ext3 \ - rootfs4 "${EXT3_ROOTFS4_MB}" ext3 - ;; - - [Nn]*) - # do not format - ;; - - *) - USAGE "'${partition}' is an unknown partition config" - ;; -esac - - -# copy the full bootloader image to the right place after the -# partitioned area -echo -echo Installing Qi bootloader from: ${qi} - -dd if="${qi}" of="${dev}" bs=512 count=512 \ - seek=$(( $SECTORS - $REAR_SECTORS )) -dd if="${qi}" of="${dev}" bs=512 \ - seek=$(( $SECTORS - $REAR_SECTORS + $QI_ALLOCATION )) \ - count=$QI_INITIAL -dd if=/dev/zero of="${dev}" bs=512 \ - seek=$(( $SECTORS - $REAR_SECTORS + $QI_ALLOCATION + $QI_INITIAL )) \ - count=$(( $SIG + $PADDING )) - -# done -echo -echo "**** completed" diff --git a/qiboot/Makefile b/qiboot/Makefile deleted file mode 100644 index 5e04f75..0000000 --- a/qiboot/Makefile +++ /dev/null @@ -1,92 +0,0 @@ -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include config.mk - -BUILD_DATE := $(shell date) -BUILD_HOST := $(shell hostname) -BUILD_BRANCH := $(shell git branch | grep ^\* | cut -d' ' -f2) -BUILD_HEAD := $(shell git show --pretty=oneline | head -n1 | cut -d' ' -f1 | cut -b1-16) -BUILD_VERSION := ${BUILD_BRANCH}_${BUILD_HEAD} - -LDS = src/cpu/$(CPU)/qi.lds -INCLUDE = include -IMAGE_DIR = image -TOOLS = tools -CFLAGS = -Wall -Werror -I $(INCLUDE) -g -c -Os -fno-strict-aliasing -mlong-calls \ - -fno-common -ffixed-r8 -msoft-float -fno-builtin -ffreestanding \ - -march=armv4t -mno-thumb-interwork -Wstrict-prototypes \ - -DBUILD_HOST="${BUILD_HOST}" -DBUILD_VERSION="${BUILD_VERSION}" \ - -DBUILD_DATE="${BUILD_DATE}" -DQI_CPU="${CPU}" -LDFLAGS = - -S_SRCS = $(wildcard src/cpu/$(CPU)/*.S) -S_OBJS = $(patsubst %.S,%.o, $(S_SRCS)) -C_SRCS = $(wildcard src/*.c) \ - $(wildcard src/drivers/*.c) $(wildcard src/fs/*.c) \ - $(wildcard src/cpu/$(CPU)/*.c) -C_OBJS = $(patsubst %.c,%.o, $(C_SRCS)) - -SRCS = ${S_SRCS} ${C_SRCS} -OBJS = ${S_OBJS} ${C_OBJS} -LIBS = -L${COMPILER_LIB_PATH} -lgcc - -ifeq ($(CPU),s3c2410) - # GTA01 U-Boot IDs - UDFU_VID = 0x1457 - UDFU_PID = 0x5119 - UDFU_REV = 0x0240 -else - # GTA02 A5 and A6 U-Boot will eat these for DFU action - UDFU_VID = 0x1d50 - UDFU_PID = 0x5119 - UDFU_REV = 0x350 -endif - -TARGET = $(IMAGE_DIR)/start_qi_all-$(CPU) -IMAGE = $(IMAGE_DIR)/qi-$(CPU)-$(BUILD_VERSION) -UDFU_IMAGE = $(IMAGE_DIR)/qi-$(CPU)-$(BUILD_VERSION).udfu - -MKUDFU = $(TOOLS)/mkudfu - -%.o: %.S - @$(CC) $(CFLAGS) -o $@ $< - -%.o: %.c - @$(CC) $(CFLAGS) -o $@ $< - -all:${UDFU_IMAGE} - -${OBJS}:${SRCS} ${INCLUDE}/*.h - -${MKUDFU}: - make -C $(TOOLS) - -${UDFU_IMAGE}:${OBJS} ${MKUDFU} - mkdir -p image - @$(LD) ${LDFLAGS} -T$(LDS) -g $(OBJS) -o ${TARGET} ${LIBS} - @$(OBJCOPY) -O binary -S ${TARGET} ${IMAGE} - @$(MKUDFU) -v ${UDFU_VID} -p ${UDFU_PID} -r ${UDFU_REV} \ - -d ${IMAGE} ${UDFU_IMAGE} - @$(OBJDUMP) -d ${TARGET} >${IMAGE}.dis - -clean: - @rm -f *~ src/*.o src/*~ - @rm -f src/cpu/*/*.o src/cpu/*/*~ - @rm -f src/drivers/*.o src/drivers/*~ - @rm -f src/fs/*.o src/fs/*~ - @rm -f include/*~ ${IMAGE_DIR}/* - @make clean -C $(TOOLS) diff --git a/qiboot/README b/qiboot/README deleted file mode 100644 index 0ab7a3f..0000000 --- a/qiboot/README +++ /dev/null @@ -1,149 +0,0 @@ -Qi -== - -Qi (named by Alan Cox on Openmoko kernel list) is a minimal bootloader that -"breathes life" into Linux. Its goal is to stay close to the minimum needed -to "load" and then "boot" Linux -- no boot menus, additional peripheral init -or private states. - - -What's wrong with U-Boot, they keep telling people to not reinvent the wheel? -============================================================================= - -U-Boot is gradually becoming a simplified knockoff of Linux. After using it a -while, it became clear we were cutting and pasting drivers into U-Boot from -Linux, cutting them down and not having a plan to maintain the U-Boot versions -as the Linux ones were changed. - -We decided that we would use full Linux for things that Linux is good at and -only have the bootloader do the device init that is absolutely required before -Linux can be pulled into memory and started. In practice since we had a working -U-Boot implementation it meant cutting that right down to the bone (start.S -mainly for s3c2442) and then building it up from scratch optimized to just do -load and boot. - - -Samsung - specific boot sequence -================================ - -Right now Qi supports Samsung "steppingstone" scheme devices, but in fact it's -the same in processors like iMX31 that there is a small area of SRAM that is -prepped with NAND content via ROM on the device. There's nothing that stops Qi -use on processors without steppingstone, although the ATAG stuff assumes we deal -with ARM based processor. - - -Per-CPU Qi -========== - -Qi has a concept of a single bootloader binary created per CPU type. The -different devices that use that CPU are all supported in the same binary. At -runtime after the common init is done, Qi asks each supported device code in -turn if it recognizes the device as being handled by it, the first one to reply -that it knows the device gets to control the rest of the process. - -Consequently, there is NO build-time configuration file as found on U-Boot -except a make env var that sets the CPU type being built, eg: - - make CPU=s3c6410 - - -Booting Heuristics -================== - -Qi has one or more ways to fetch a kernel depending on the device it finds it is -running on, for example on GTA02 it can use NAND and SD card devices. It goes -through these device-specific storage devices in order and tries to boot the -first viable kernel it finds, usually /boot/.bin for example -/boot/uImage-GTA02.bin. - -The default order for GTA02 is: 1st SD primary partition, 2nd primary -partition, 3rd primary partition, NAND kernel partition. - -You can disable a rootfs for consideration for boot if you add a file -/boot/noboot-, eg, /boot/noboot-GTA02. This differs from renaming or -deleting the kernel image because updating the kernel package would give you a -working kernel again and allow boot, whereas the noboot indication will remain -until you remove it. - -The kernel commandline used is associated with the storage device and partition, -this allows the correct root= line to be arrived at without any work. - -If no kernel image can be found, Qi falls back to doing a memory test. - - -Appending to commandline -======================== - -You can append to the Qi commandline by creating a file /boot/append-, -eg, /boot/append-GTA02 containing the additional kernel commandline you want. - -This means you can affect the boot per-rootfs, but that if you reimage the -rootfs you at the same time define what is appeneded. Because these files are -looked for with the name in them, options can be selected depending on -the device the rootfs is run on. - - -Initrd support -============== - -Initrd or initramfs in separate file is supported to be loaded at given -memory address in addition to kernel image. The ATAGs are issued accordingly. - - -Interactive UI -============== - -Being minimalistic by its nature, Qi has very limited abilities to -interact with a user. On GTA02 the red LED and the vibrator are used -(if the battery is in good condition) to notify user of the following -actions: - -The LED is turned on either on: - - Successful partition mount - - Successful kernel pull - - Successful initramfs pull - -The LED is turned off and vibrator runs briefly either on: - - Fail of kernel pull - - Fail of initramfs pull - - Fail of mount partition - - Skipping of current boot possibility - -The LED is turned off either on: - - Start of the kernel - - Start of the mem test - - Start of the kernel pull - - Start of the initramfs pull - -If a user presses the AUX button after successful partition mount and -before start of the kernel pull (that is, while the red LED is on), -this boot possibility is skipped (and GTA02 owners can feel -vibration). If a user holds the POWER button just before start of the -kernel, debugging parameters are added to the kernel command line -and a lot of information is output to the screen. - -Functional Differences from U-Boot on GTA02 -=========================================== - - - Backlight and USB is not enabled until Linux starts after a few seconds - - - No startup splash screen - - - by default there is no boot spew on the LCM - - - On GTAxx boots from first uSD ext2 / 3 partition containing - /boot/uImage-.bin present, eg, /boot/uImage-GTA02.bin, it checks - first three partitions in turn - - - On GTA01 and 02 if nothing is workable on the SD Card, or it is not present, - Qi will try to boot from NAND - - - You can disable a partition for boot by creating /boot/noboot-, - eg, /boot/noboot-GTA02, it will skip it and check the next partition - - - Way faster - - - There is no concept of "staying in the bootloader". The bootloader exits to - Linux as fast as possible, that's all it does. - diff --git a/qiboot/build b/qiboot/build deleted file mode 100755 index 87684bb..0000000 --- a/qiboot/build +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -make clean && \ -make CPU=s3c6410 && \ -make CPU=s3c2442 && \ -make CPU=s3c2410 - -# as root then... -# -# ./6410-partition-sd.sh sde sdhc image/qi-s3c6410-andy_???????????????? x -# mount /dev/sde2 /mnt ; cp ../kernel/linux-2.6/uImage.bin /mnt/boot ; umount /dev/sde2 - diff --git a/qiboot/config.mk b/qiboot/config.mk deleted file mode 100644 index 1fee1a3..0000000 --- a/qiboot/config.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# Include the make variables (CC, etc...) -# - -CROSS_PATH=/usr/local/openmoko/arm -CROSS_COMPILE=${CROSS_PATH}/bin/arm-angstrom-linux-gnueabi- - -#### -COMPILER_LIB_PATH_PRE=${CROSS_PATH}/lib/gcc/arm-angstrom-linux-gnueabi -COMPILER_LIB_PATH=${COMPILER_LIB_PATH_PRE}/`ls ${COMPILER_LIB_PATH_PRE}` - -AS = $(CROSS_COMPILE)as -LD = $(CROSS_COMPILE)ld -CC = $(CROSS_COMPILE)gcc -OBJCOPY = $(CROSS_COMPILE)objcopy -OBJDUMP = $(CROSS_COMPILE)objdump -HOSTCC = gcc - -# we need the mkudfu tool from U-Boot build -#MKUDFU = ../uboot/u-boot/tools/mkudfu - -export CROSS_COMPILE AD LD CC OBJCOPY OBJDUMP MKUDFU diff --git a/qiboot/dfu-qi b/qiboot/dfu-qi deleted file mode 100755 index f5e6e1e..0000000 --- a/qiboot/dfu-qi +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/bash -../dfu-util/src/dfu-util -a 1 -d 0x1d50:0x5119 -D image/qi-s3c2442*.udfu -if [ $? -eq 1 ] ; then -../dfu-util/src/dfu-util -a 1 -d 0x1d50:0x5120 -D image/qi-s3c2442*.udfu -../dfu-util/src/dfu-util -a 1 -d 0x1d50:0x5119 -D image/qi-s3c2442*.udfu -fi - diff --git a/qiboot/gta02-qi.ocd b/qiboot/gta02-qi.ocd deleted file mode 100755 index 9d2cf1f..0000000 --- a/qiboot/gta02-qi.ocd +++ /dev/null @@ -1,34 +0,0 @@ -# gta02 Qi script -# Andy Green - -reset halt -wait_halt -sleep 2000 - -# bring the steppingstone part of qi image into steppingstone -# -load_binary /projects/openmoko/bootloader/image/qi 0x0 -# -# mark ourselves as JTAG load -# -mww 0x4 0xffffffff - -# -# we have to run that so SDRAM exists in a usable way -# fixed jumpthrough at 0x8 is executed after steppingstone -# init (including RAM) has completed -# -bp 0x8 4 hw -resume 0x0 -wait_halt -rbp 0x8 - -# -# now prep the SDRAM -# -load_binary /projects/openmoko/bootloader/image/qi 0x33000000 -# -# and continue... -resume 0x8 -# - diff --git a/qiboot/include/ext2.h b/qiboot/include/ext2.h deleted file mode 100644 index 85b0860..0000000 --- a/qiboot/include/ext2.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * GRUB -- GRand Unified Bootloader - * Copyright (C) 2000, 2001 Free Software Foundation, Inc. - * - * (C) Copyright 2003 Sysgo Real-Time Solutions, AG - * Pavel Bartusek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* An implementation for the Ext2FS filesystem ported from GRUB. - * Some parts of this code (mainly the structures and defines) are - * from the original ext2 fs code, as found in the linux kernel. - */ - - -#define SECTOR_SIZE 0x200 -#define SECTOR_BITS 9 - -/* Error codes */ -typedef enum -{ - ERR_NONE = 0, - ERR_BAD_FILENAME, - ERR_BAD_FILETYPE, - ERR_BAD_GZIP_DATA, - ERR_BAD_GZIP_HEADER, - ERR_BAD_PART_TABLE, - ERR_BAD_VERSION, - ERR_BELOW_1MB, - ERR_BOOT_COMMAND, - ERR_BOOT_FAILURE, - ERR_BOOT_FEATURES, - ERR_DEV_FORMAT, - ERR_DEV_VALUES, - ERR_EXEC_FORMAT, - ERR_FILELENGTH, - ERR_FILE_NOT_FOUND, - ERR_FSYS_CORRUPT, - ERR_FSYS_MOUNT, - ERR_GEOM, - ERR_NEED_LX_KERNEL, - ERR_NEED_MB_KERNEL, - ERR_NO_DISK, - ERR_NO_PART, - ERR_NUMBER_PARSING, - ERR_OUTSIDE_PART, - ERR_READ, - ERR_SYMLINK_LOOP, - ERR_UNRECOGNIZED, - ERR_WONT_FIT, - ERR_WRITE, - ERR_BAD_ARGUMENT, - ERR_UNALIGNED, - ERR_PRIVILEGED, - ERR_DEV_NEED_INIT, - ERR_NO_DISK_SPACE, - ERR_NUMBER_OVERFLOW, - - MAX_ERR_NUM -} ext2fs_error_t; - - -extern int ext2fs_ls(char *dirname); -extern int ext2fs_open(const char *filename); -extern int ext2fs_read(char *buf, unsigned len); -extern int ext2fs_mount(void); -extern int ext2fs_close(void); diff --git a/qiboot/include/fat.h b/qiboot/include/fat.h deleted file mode 100644 index f993cca..0000000 --- a/qiboot/include/fat.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg - * - * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 - * 2003-03-10 - kharris@nexus-tech.net - ported to u-boot - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _FAT_H_ -#define _FAT_H_ - -#include - -#define CONFIG_SUPPORT_VFAT - -#define SECTOR_SIZE FS_BLOCK_SIZE - -#define FS_BLOCK_SIZE 512 - -#if FS_BLOCK_SIZE != SECTOR_SIZE -#error FS_BLOCK_SIZE != SECTOR_SIZE - This code needs to be fixed! -#endif - -#define MAX_CLUSTSIZE 65536 -#define DIRENTSPERBLOCK (FS_BLOCK_SIZE/sizeof(dir_entry)) -#define DIRENTSPERCLUST ((mydata->clust_size*SECTOR_SIZE)/sizeof(dir_entry)) - -#define FATBUFBLOCKS 6 -#define FATBUFSIZE (FS_BLOCK_SIZE*FATBUFBLOCKS) -#define FAT12BUFSIZE ((FATBUFSIZE*2)/3) -#define FAT16BUFSIZE (FATBUFSIZE/2) -#define FAT32BUFSIZE (FATBUFSIZE/4) - - -/* Filesystem identifiers */ -#define FAT12_SIGN "FAT12 " -#define FAT16_SIGN "FAT16 " -#define FAT32_SIGN "FAT32 " -#define SIGNLEN 8 - -/* File attributes */ -#define ATTR_RO 1 -#define ATTR_HIDDEN 2 -#define ATTR_SYS 4 -#define ATTR_VOLUME 8 -#define ATTR_DIR 16 -#define ATTR_ARCH 32 - -#define ATTR_VFAT (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME) - -#define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */ -#define aRING 0x05 /* Used to represent 'å' in name[0] */ - -/* Indicates that the entry is the last long entry in a set of long - * dir entries - */ -#define LAST_LONG_ENTRY_MASK 0x40 - -/* Flags telling whether we should read a file or list a directory */ -#define LS_NO 0 -#define LS_YES 1 -#define LS_DIR 1 -#define LS_ROOT 2 - -#ifdef DEBUG -#define FAT_DPRINT(args...) printf(args) -#else -#define FAT_DPRINT(args...) -#endif -#define FAT_ERROR(arg) printf(arg) - -#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\') - -#define FSTYPE_NONE (-1) - -#if defined(__linux__) && defined(__KERNEL__) -#define FAT2CPU16 le16_to_cpu -#define FAT2CPU32 le32_to_cpu -#else -#if __LITTLE_ENDIAN -#define FAT2CPU16(x) (x) -#define FAT2CPU32(x) (x) -#else -#define FAT2CPU16(x) ((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8)) -#define FAT2CPU32(x) ((((x) & 0x000000ff) << 24) | \ - (((x) & 0x0000ff00) << 8) | \ - (((x) & 0x00ff0000) >> 8) | \ - (((x) & 0xff000000) >> 24)) -#endif -#endif - -#define TOLOWER(c) if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');} -#define START(dent) (FAT2CPU16((dent)->start) \ - + (mydata->fatsize != 32 ? 0 : \ - (FAT2CPU16((dent)->starthi) << 16))) -#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \ - (x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0)) - -typedef struct boot_sector { - __u8 ignored[3]; /* Bootstrap code */ - char system_id[8]; /* Name of fs */ - __u8 sector_size[2]; /* Bytes/sector */ - __u8 cluster_size; /* Sectors/cluster */ - __u16 reserved; /* Number of reserved sectors */ - __u8 fats; /* Number of FATs */ - __u8 dir_entries[2]; /* Number of root directory entries */ - __u8 sectors[2]; /* Number of sectors */ - __u8 media; /* Media code */ - __u16 fat_length; /* Sectors/FAT */ - __u16 secs_track; /* Sectors/track */ - __u16 heads; /* Number of heads */ - __u32 hidden; /* Number of hidden sectors */ - __u32 total_sect; /* Number of sectors (if sectors == 0) */ - - /* FAT32 only */ - __u32 fat32_length; /* Sectors/FAT */ - __u16 flags; /* Bit 8: fat mirroring, low 4: active fat */ - __u8 version[2]; /* Filesystem version */ - __u32 root_cluster; /* First cluster in root directory */ - __u16 info_sector; /* Filesystem info sector */ - __u16 backup_boot; /* Backup boot sector */ - __u16 reserved2[6]; /* Unused */ -} boot_sector; - -typedef struct volume_info -{ - __u8 drive_number; /* BIOS drive number */ - __u8 reserved; /* Unused */ - __u8 ext_boot_sign; /* 0x29 if fields below exist (DOS 3.3+) */ - __u8 volume_id[4]; /* Volume ID number */ - char volume_label[11]; /* Volume label */ - char fs_type[8]; /* Typically FAT12, FAT16, or FAT32 */ - /* Boot code comes next, all but 2 bytes to fill up sector */ - /* Boot sign comes last, 2 bytes */ -} volume_info; - -typedef struct dir_entry { - char name[8],ext[3]; /* Name and extension */ - __u8 attr; /* Attribute bits */ - __u8 lcase; /* Case for base and extension */ - __u8 ctime_ms; /* Creation time, milliseconds */ - __u16 ctime; /* Creation time */ - __u16 cdate; /* Creation date */ - __u16 adate; /* Last access date */ - __u16 starthi; /* High 16 bits of cluster in FAT32 */ - __u16 time,date,start;/* Time, date and first cluster */ - __u32 size; /* File size in bytes */ -} dir_entry; - -typedef struct dir_slot { - __u8 id; /* Sequence number for slot */ - __u8 name0_4[10]; /* First 5 characters in name */ - __u8 attr; /* Attribute byte */ - __u8 reserved; /* Unused */ - __u8 alias_checksum;/* Checksum for 8.3 alias */ - __u8 name5_10[12]; /* 6 more characters in name */ - __u16 start; /* Unused */ - __u8 name11_12[4]; /* Last 2 characters in name */ -} dir_slot; - -/* Private filesystem parameters - * - * Note: FAT buffer has to be 32 bit aligned - * (see FAT32 accesses) - */ -typedef struct { - __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ - int fatsize; /* Size of FAT in bits */ - __u16 fatlength; /* Length of FAT in sectors */ - __u16 fat_sect; /* Starting sector of the FAT */ - __u16 rootdir_sect; /* Start sector of root directory */ - __u16 clust_size; /* Size of clusters in sectors */ - short data_begin; /* The sector of the first cluster, can be negative */ - int fatbufnum; /* Used by get_fatent, init to -1 */ -} fsdata; - -typedef int (file_detectfs_func)(void); -typedef int (file_ls_func)(const char *dir); -typedef long (file_read_func)(const char *filename, void *buffer, - unsigned long maxsize); - -struct filesystem { - file_detectfs_func *detect; - file_ls_func *ls; - file_read_func *read; - const char name[12]; -}; - -/* FAT tables */ -file_detectfs_func file_fat_detectfs; -file_ls_func file_fat_ls; -file_read_func file_fat_read; - -/* Currently this doesn't check if the dir exists or is valid... */ -int file_cd(const char *path); -int file_fat_detectfs(void); -int file_fat_ls(const char *dir); -long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); -const char *file_getfsname(int idx); -int fat_register_device(block_dev_desc_t *dev_desc, int part_no); - -#endif /* _FAT_H_ */ diff --git a/qiboot/include/glamo-init.h b/qiboot/include/glamo-init.h deleted file mode 100644 index ca43d8a..0000000 --- a/qiboot/include/glamo-init.h +++ /dev/null @@ -1 +0,0 @@ -extern void glamo_core_init(void); diff --git a/qiboot/include/glamo-mmc.h b/qiboot/include/glamo-mmc.h deleted file mode 100644 index 48e8161..0000000 --- a/qiboot/include/glamo-mmc.h +++ /dev/null @@ -1,149 +0,0 @@ -#ifndef __GLAMO_MMC_H__ -#define __GLAMO_MMC_H__ - -/* Standard MMC commands (4.1) type argument response */ - /* class 1 */ -#define MMC_GO_IDLE_STATE 0 /* bc */ -#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ -#define MMC_ALL_SEND_CID 2 /* bcr R2 */ -#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ -#define MMC_SET_DSR 4 /* bc [31:16] RCA */ -#define MMC_SWITCH 6 /* ac [31:0] See below R1b */ -#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ -#define MMC_SEND_EXT_CSD 8 /* adtc R1 */ -#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ -#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ -#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ -#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ -#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ -#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ -#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ -#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ - -#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */ -#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ - - /* class 2 */ -#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ -#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ -#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ - - /* class 3 */ -#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ - - /* class 4 */ -#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ -#define MMC_PROGRAM_CID 26 /* adtc R1 */ -#define MMC_PROGRAM_CSD 27 /* adtc R1 */ - - /* class 6 */ -#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ -#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ -#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ - - /* class 5 */ -#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ -#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ -#define MMC_ERASE 38 /* ac R1b */ - - /* class 9 */ -#define MMC_FAST_IO 39 /* ac R4 */ -#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ - - /* class 7 */ -#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ - - /* class 8 */ -#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ -#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ - -#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ -#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */ -#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ -#define SD_APP_SEND_SCR 51 /* adtc R1 */ - - -#define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ - -#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ -#define MMC_CMD_AC (0 << 5) -#define MMC_CMD_ADTC (1 << 5) -#define MMC_CMD_BC (2 << 5) -#define MMC_CMD_BCR (3 << 5) - -#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ -#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ -#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ -#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ - -/* - * These are the native response types, and correspond to valid bit - * patterns of the above flags. One additional valid pattern - * is all zeros, which means we don't expect a response. - */ -#define MMC_RSP_NONE (0) -#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) -#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) -#define MMC_RSP_R3 (MMC_RSP_PRESENT) -#define MMC_RSP_R4 (MMC_RSP_PRESENT) -#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) - -#define mmc_resp_type(f) ((f) & (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC |\ - MMC_RSP_BUSY | MMC_RSP_OPCODE)) -#define mmc_cmd_type(f) ((f) & MMC_CMD_MASK) - -/* - * These are the SPI response types for MMC, SD, and SDIO cards. - * Commands return R1, with maybe more info. Zero is an error type; - * callers must always provide the appropriate MMC_RSP_SPI_Rx flags. - */ -#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1) -#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY) -#define MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2) -#define MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) -#define MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) -#define MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2) -#define MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) - -#define MMC_DATA_WRITE (1 << 8) -#define MMC_DATA_READ (1 << 9) -#define MMC_DATA_STREAM (1 << 10) - -struct sd_cid { - char pnm_0; /* product name */ - char oid_1; /* OEM/application ID */ - char oid_0; - u8 mid; /* manufacturer ID */ - char pnm_4; - char pnm_3; - char pnm_2; - char pnm_1; - u8 psn_2; /* product serial number */ - u8 psn_1; - u8 psn_0; /* MSB */ - u8 prv; /* product revision */ - u8 crc; /* CRC7 checksum, b0 is unused and set to 1 */ - u8 mdt_1; /* manufacturing date, LSB, RRRRyyyy yyyymmmm */ - u8 mdt_0; /* MSB */ - u8 psn_3; /* LSB */ -}; - -enum card_type { - CARDTYPE_NONE = 0, - CARDTYPE_MMC, - CARDTYPE_SD, - CARDTYPE_SD20, - CARDTYPE_SDHC -}; - - -#endif /* __GLAMO_MMC_H__ */ diff --git a/qiboot/include/glamo-regs.h b/qiboot/include/glamo-regs.h deleted file mode 100644 index bfc3919..0000000 --- a/qiboot/include/glamo-regs.h +++ /dev/null @@ -1,628 +0,0 @@ -#ifndef _GLAMO_REGS_H -#define _GLAMO_REGS_H - -/* Smedia Glamo 336x/337x driver - * - * (C) 2007 by OpenMoko, Inc. - * Author: Harald Welte - * All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -enum glamo_regster_offsets { - GLAMO_REGOFS_GENERIC = 0x0000, - GLAMO_REGOFS_HOSTBUS = 0x0200, - GLAMO_REGOFS_MEMORY = 0x0300, - GLAMO_REGOFS_VIDCAP = 0x0400, - GLAMO_REGOFS_ISP = 0x0500, - GLAMO_REGOFS_JPEG = 0x0800, - GLAMO_REGOFS_MPEG = 0x0c00, - GLAMO_REGOFS_LCD = 0x1100, - GLAMO_REGOFS_MMC = 0x1400, - GLAMO_REGOFS_MPROC0 = 0x1500, - GLAMO_REGOFS_MPROC1 = 0x1580, - GLAMO_REGOFS_CMDQUEUE = 0x1600, - GLAMO_REGOFS_RISC = 0x1680, - GLAMO_REGOFS_2D = 0x1700, - GLAMO_REGOFS_3D = 0x1b00, - GLAMO_REGOFS_END = 0x2400, -}; - - -enum glamo_register_generic { - GLAMO_REG_GCONF1 = 0x0000, - GLAMO_REG_GCONF2 = 0x0002, -#define GLAMO_REG_DEVICE_ID GLAMO_REG_GCONF2 - GLAMO_REG_GCONF3 = 0x0004, -#define GLAMO_REG_REVISION_ID GLAMO_REG_GCONF3 - GLAMO_REG_IRQ_GEN1 = 0x0006, -#define GLAMO_REG_IRQ_ENABLE GLAMO_REG_IRQ_GEN1 - GLAMO_REG_IRQ_GEN2 = 0x0008, -#define GLAMO_REG_IRQ_SET GLAMO_REG_IRQ_GEN2 - GLAMO_REG_IRQ_GEN3 = 0x000a, -#define GLAMO_REG_IRQ_CLEAR GLAMO_REG_IRQ_GEN3 - GLAMO_REG_IRQ_GEN4 = 0x000c, -#define GLAMO_REG_IRQ_STATUS GLAMO_REG_IRQ_GEN4 - GLAMO_REG_CLOCK_HOST = 0x0010, - GLAMO_REG_CLOCK_MEMORY = 0x0012, - GLAMO_REG_CLOCK_LCD = 0x0014, - GLAMO_REG_CLOCK_MMC = 0x0016, - GLAMO_REG_CLOCK_ISP = 0x0018, - GLAMO_REG_CLOCK_JPEG = 0x001a, - GLAMO_REG_CLOCK_3D = 0x001c, - GLAMO_REG_CLOCK_2D = 0x001e, - GLAMO_REG_CLOCK_RISC1 = 0x0020, /* 3365 only? */ - GLAMO_REG_CLOCK_RISC2 = 0x0022, /* 3365 only? */ - GLAMO_REG_CLOCK_MPEG = 0x0024, - GLAMO_REG_CLOCK_MPROC = 0x0026, - - GLAMO_REG_CLOCK_GEN5_1 = 0x0030, - GLAMO_REG_CLOCK_GEN5_2 = 0x0032, - GLAMO_REG_CLOCK_GEN6 = 0x0034, - GLAMO_REG_CLOCK_GEN7 = 0x0036, - GLAMO_REG_CLOCK_GEN8 = 0x0038, - GLAMO_REG_CLOCK_GEN9 = 0x003a, - GLAMO_REG_CLOCK_GEN10 = 0x003c, - GLAMO_REG_CLOCK_GEN11 = 0x003e, - GLAMO_REG_PLL_GEN1 = 0x0040, - GLAMO_REG_PLL_GEN2 = 0x0042, - GLAMO_REG_PLL_GEN3 = 0x0044, - GLAMO_REG_PLL_GEN4 = 0x0046, - GLAMO_REG_PLL_GEN5 = 0x0048, - GLAMO_REG_GPIO_GEN1 = 0x0050, - GLAMO_REG_GPIO_GEN2 = 0x0052, - GLAMO_REG_GPIO_GEN3 = 0x0054, - GLAMO_REG_GPIO_GEN4 = 0x0056, - GLAMO_REG_GPIO_GEN5 = 0x0058, - GLAMO_REG_GPIO_GEN6 = 0x005a, - GLAMO_REG_GPIO_GEN7 = 0x005c, - GLAMO_REG_GPIO_GEN8 = 0x005e, - GLAMO_REG_GPIO_GEN9 = 0x0060, - GLAMO_REG_GPIO_GEN10 = 0x0062, - GLAMO_REG_DFT_GEN1 = 0x0070, - GLAMO_REG_DFT_GEN2 = 0x0072, - GLAMO_REG_DFT_GEN3 = 0x0074, - GLAMO_REG_DFT_GEN4 = 0x0076, - - GLAMO_REG_PLL_GEN6 = 0x01e0, - GLAMO_REG_PLL_GEN7 = 0x01f0, -}; - -#define GLAMO_REG_HOSTBUS(x) (GLAMO_REGOFS_HOSTBUS-2+(x*2)) - -#define REG_MEM(x) (GLAMO_REGOFS_MEMORY+(x)) -#define GLAMO_REG_MEM_TIMING(x) (GLAMO_REG_MEM_TIMING1-2+(x*2)) - -enum glamo_register_mem { - GLAMO_REG_MEM_TYPE = REG_MEM(0x00), - GLAMO_REG_MEM_GEN = REG_MEM(0x02), - GLAMO_REG_MEM_TIMING1 = REG_MEM(0x04), - GLAMO_REG_MEM_TIMING2 = REG_MEM(0x06), - GLAMO_REG_MEM_TIMING3 = REG_MEM(0x08), - GLAMO_REG_MEM_TIMING4 = REG_MEM(0x0a), - GLAMO_REG_MEM_TIMING5 = REG_MEM(0x0c), - GLAMO_REG_MEM_TIMING6 = REG_MEM(0x0e), - GLAMO_REG_MEM_TIMING7 = REG_MEM(0x10), - GLAMO_REG_MEM_TIMING8 = REG_MEM(0x12), - GLAMO_REG_MEM_TIMING9 = REG_MEM(0x14), - GLAMO_REG_MEM_TIMING10 = REG_MEM(0x16), - GLAMO_REG_MEM_TIMING11 = REG_MEM(0x18), - GLAMO_REG_MEM_POWER1 = REG_MEM(0x1a), - GLAMO_REG_MEM_POWER2 = REG_MEM(0x1c), - GLAMO_REG_MEM_LCD_BUF1 = REG_MEM(0x1e), - GLAMO_REG_MEM_LCD_BUF2 = REG_MEM(0x20), - GLAMO_REG_MEM_LCD_BUF3 = REG_MEM(0x22), - GLAMO_REG_MEM_LCD_BUF4 = REG_MEM(0x24), - GLAMO_REG_MEM_BIST1 = REG_MEM(0x26), - GLAMO_REG_MEM_BIST2 = REG_MEM(0x28), - GLAMO_REG_MEM_BIST3 = REG_MEM(0x2a), - GLAMO_REG_MEM_BIST4 = REG_MEM(0x2c), - GLAMO_REG_MEM_BIST5 = REG_MEM(0x2e), - GLAMO_REG_MEM_MAH1 = REG_MEM(0x30), - GLAMO_REG_MEM_MAH2 = REG_MEM(0x32), - GLAMO_REG_MEM_DRAM1 = REG_MEM(0x34), - GLAMO_REG_MEM_DRAM2 = REG_MEM(0x36), - GLAMO_REG_MEM_CRC = REG_MEM(0x38), -}; - -#define GLAMO_MEM_TYPE_MASK 0x03 - -enum glamo_reg_mem_dram1 { - GLAMO_MEM_DRAM1_EN_SDRAM_CLK = (1 << 11), - GLAMO_MEM_DRAM1_SELF_REFRESH = (1 << 12), -}; - -enum glamo_reg_mem_dram2 { - GLAMO_MEM_DRAM2_DEEP_PWRDOWN = (1 << 12), -}; - -enum glamo_irq_index { - GLAMO_IRQIDX_HOSTBUS = 0, - GLAMO_IRQIDX_JPEG = 1, - GLAMO_IRQIDX_MPEG = 2, - GLAMO_IRQIDX_MPROC1 = 3, - GLAMO_IRQIDX_MPROC0 = 4, - GLAMO_IRQIDX_CMDQUEUE = 5, - GLAMO_IRQIDX_2D = 6, - GLAMO_IRQIDX_MMC = 7, - GLAMO_IRQIDX_RISC = 8, -}; - -enum glamo_irq { - GLAMO_IRQ_HOSTBUS = (1 << GLAMO_IRQIDX_HOSTBUS), - GLAMO_IRQ_JPEG = (1 << GLAMO_IRQIDX_JPEG), - GLAMO_IRQ_MPEG = (1 << GLAMO_IRQIDX_MPEG), - GLAMO_IRQ_MPROC1 = (1 << GLAMO_IRQIDX_MPROC1), - GLAMO_IRQ_MPROC0 = (1 << GLAMO_IRQIDX_MPROC0), - GLAMO_IRQ_CMDQUEUE = (1 << GLAMO_IRQIDX_CMDQUEUE), - GLAMO_IRQ_2D = (1 << GLAMO_IRQIDX_2D), - GLAMO_IRQ_MMC = (1 << GLAMO_IRQIDX_MMC), - GLAMO_IRQ_RISC = (1 << GLAMO_IRQIDX_RISC), -}; - -enum glamo_reg_clock_host { - GLAMO_CLOCK_HOST_DG_BCLK = 0x0001, - GLAMO_CLOCK_HOST_DG_M0CLK = 0x0004, - GLAMO_CLOCK_HOST_RESET = 0x1000, -}; - -enum glamo_reg_clock_mem { - GLAMO_CLOCK_MEM_DG_M1CLK = 0x0001, - GLAMO_CLOCK_MEM_EN_M1CLK = 0x0002, - GLAMO_CLOCK_MEM_DG_MOCACLK = 0x0004, - GLAMO_CLOCK_MEM_EN_MOCACLK = 0x0008, - GLAMO_CLOCK_MEM_RESET = 0x1000, - GLAMO_CLOCK_MOCA_RESET = 0x2000, -}; - -enum glamo_reg_clock_lcd { - GLAMO_CLOCK_LCD_DG_DCLK = 0x0001, - GLAMO_CLOCK_LCD_EN_DCLK = 0x0002, - GLAMO_CLOCK_LCD_DG_DMCLK = 0x0004, - GLAMO_CLOCK_LCD_EN_DMCLK = 0x0008, - // - GLAMO_CLOCK_LCD_EN_DHCLK = 0x0020, - GLAMO_CLOCK_LCD_DG_M5CLK = 0x0040, - GLAMO_CLOCK_LCD_EN_M5CLK = 0x0080, - GLAMO_CLOCK_LCD_RESET = 0x1000, -}; - -enum glamo_reg_clock_mmc { - GLAMO_CLOCK_MMC_DG_TCLK = 0x0001, - GLAMO_CLOCK_MMC_EN_TCLK = 0x0002, - GLAMO_CLOCK_MMC_DG_M9CLK = 0x0004, - GLAMO_CLOCK_MMC_EN_M9CLK = 0x0008, - GLAMO_CLOCK_MMC_RESET = 0x1000, -}; - -enum glamo_reg_basic_mmc { - /* set to disable CRC error rejection */ - GLAMO_BASIC_MMC_DISABLE_CRC = 0x0001, - /* enable completion interrupt */ - GLAMO_BASIC_MMC_EN_COMPL_INT = 0x0002, - /* stop MMC clock while enforced idle waiting for data from card */ - GLAMO_BASIC_MMC_NO_CLK_RD_WAIT = 0x0004, - /* 0 = 1-bit bus to card, 1 = use 4-bit bus (has to be negotiated) */ - GLAMO_BASIC_MMC_EN_4BIT_DATA = 0x0008, - /* enable 75K pullups on D3..D0 */ - GLAMO_BASIC_MMC_EN_DATA_PUPS = 0x0010, - /* enable 75K pullup on CMD */ - GLAMO_BASIC_MMC_EN_CMD_PUP = 0x0020, - /* IO drive strength 00=weak -> 11=strongest */ - GLAMO_BASIC_MMC_EN_DR_STR0 = 0x0040, - GLAMO_BASIC_MMC_EN_DR_STR1 = 0x0080, - /* TCLK delay stage A, 0000 = 500ps --> 1111 = 8ns */ - GLAMO_BASIC_MMC_EN_TCLK_DLYA0 = 0x0100, - GLAMO_BASIC_MMC_EN_TCLK_DLYA1 = 0x0200, - GLAMO_BASIC_MMC_EN_TCLK_DLYA2 = 0x0400, - GLAMO_BASIC_MMC_EN_TCLK_DLYA3 = 0x0800, - /* TCLK delay stage B (cumulative), 0000 = 500ps --> 1111 = 8ns */ - GLAMO_BASIC_MMC_EN_TCLK_DLYB0 = 0x1000, - GLAMO_BASIC_MMC_EN_TCLK_DLYB1 = 0x2000, - GLAMO_BASIC_MMC_EN_TCLK_DLYB2 = 0x4000, - GLAMO_BASIC_MMC_EN_TCLK_DLYB3 = 0x8000, -}; - -enum glamo_reg_stat1_mmc { - /* command "counter" (really: toggle) */ - GLAMO_STAT1_MMC_CMD_CTR = 0x8000, - /* engine is idle */ - GLAMO_STAT1_MMC_IDLE = 0x4000, - /* readback response is ready */ - GLAMO_STAT1_MMC_RB_RRDY = 0x0200, - /* readback data is ready */ - GLAMO_STAT1_MMC_RB_DRDY = 0x0100, - /* no response timeout */ - GLAMO_STAT1_MMC_RTOUT = 0x0020, - /* no data timeout */ - GLAMO_STAT1_MMC_DTOUT = 0x0010, - /* CRC error on block write */ - GLAMO_STAT1_MMC_BWERR = 0x0004, - /* CRC error on block read */ - GLAMO_STAT1_MMC_BRERR = 0x0002 -}; - -enum glamo_reg_fire_mmc { - /* command "counter" (really: toggle) - * the STAT1 register reflects this so you can ensure you don't look - * at status for previous command - */ - GLAMO_FIRE_MMC_CMD_CTR = 0x8000, - /* sets kind of response expected */ - GLAMO_FIRE_MMC_RES_MASK = 0x0700, - /* sets command type */ - GLAMO_FIRE_MMC_TYP_MASK = 0x00C0, - /* sets command class */ - GLAMO_FIRE_MMC_CLS_MASK = 0x000F, -}; - -enum glamo_fire_mmc_response_types { - GLAMO_FIRE_MMC_RSPT_R1 = 0x0000, - GLAMO_FIRE_MMC_RSPT_R1b = 0x0100, - GLAMO_FIRE_MMC_RSPT_R2 = 0x0200, - GLAMO_FIRE_MMC_RSPT_R3 = 0x0300, - GLAMO_FIRE_MMC_RSPT_R4 = 0x0400, - GLAMO_FIRE_MMC_RSPT_R5 = 0x0500, -}; - -enum glamo_fire_mmc_command_types { - /* broadcast, no response */ - GLAMO_FIRE_MMC_CMDT_BNR = 0x0000, - /* broadcast, with response */ - GLAMO_FIRE_MMC_CMDT_BR = 0x0040, - /* addressed, no data */ - GLAMO_FIRE_MMC_CMDT_AND = 0x0080, - /* addressed, with data */ - GLAMO_FIRE_MMC_CMDT_AD = 0x00C0, -}; - -enum glamo_fire_mmc_command_class { - /* "Stream Read" */ - GLAMO_FIRE_MMC_CC_STRR = 0x0000, - /* Single Block Read */ - GLAMO_FIRE_MMC_CC_SBR = 0x0001, - /* Multiple Block Read With Stop */ - GLAMO_FIRE_MMC_CC_MBRS = 0x0002, - /* Multiple Block Read No Stop */ - GLAMO_FIRE_MMC_CC_MBRNS = 0x0003, - /* RESERVED for "Stream Write" */ - GLAMO_FIRE_MMC_CC_STRW = 0x0004, - /* "Stream Write" */ - GLAMO_FIRE_MMC_CC_SBW = 0x0005, - /* RESERVED for Multiple Block Write With Stop */ - GLAMO_FIRE_MMC_CC_MBWS = 0x0006, - /* Multiple Block Write No Stop */ - GLAMO_FIRE_MMC_CC_MBWNS = 0x0007, - /* STOP command */ - GLAMO_FIRE_MMC_CC_STOP = 0x0008, - /* Cancel on Running Command */ - GLAMO_FIRE_MMC_CC_CANCL = 0x0009, - /* "Basic Command" */ - GLAMO_FIRE_MMC_CC_BASIC = 0x000a, -}; - -/* these are offsets from the start of the MMC register region */ -enum glamo_register_mmc { - /* MMC command, b15..8 = cmd arg b7..0; b7..1 = CRC; b0 = end bit */ - GLAMO_REG_MMC_CMD_REG1 = 0x00, - /* MMC command, b15..0 = cmd arg b23 .. 8 */ - GLAMO_REG_MMC_CMD_REG2 = 0x02, - /* MMC command, b15=start, b14=transmission, - * b13..8=cmd idx, b7..0=cmd arg b31..24 - */ - GLAMO_REG_MMC_CMD_REG3 = 0x04, - GLAMO_REG_MMC_CMD_FIRE = 0x06, - GLAMO_REG_MMC_CMD_RSP1 = 0x10, - GLAMO_REG_MMC_CMD_RSP2 = 0x12, - GLAMO_REG_MMC_CMD_RSP3 = 0x14, - GLAMO_REG_MMC_CMD_RSP4 = 0x16, - GLAMO_REG_MMC_CMD_RSP5 = 0x18, - GLAMO_REG_MMC_CMD_RSP6 = 0x1a, - GLAMO_REG_MMC_CMD_RSP7 = 0x1c, - GLAMO_REG_MMC_CMD_RSP8 = 0x1e, - GLAMO_REG_MMC_RB_STAT1 = 0x20, - GLAMO_REG_MMC_RB_BLKCNT = 0x22, - GLAMO_REG_MMC_RB_BLKLEN = 0x24, - GLAMO_REG_MMC_BASIC = 0x30, - GLAMO_REG_MMC_RDATADS1 = 0x34, - GLAMO_REG_MMC_RDATADS2 = 0x36, - GLAMO_REG_MMC_WDATADS1 = 0x38, - GLAMO_REG_MMC_WDATADS2 = 0x3a, - GLAMO_REG_MMC_DATBLKCNT = 0x3c, - GLAMO_REG_MMC_DATBLKLEN = 0x3e, - GLAMO_REG_MMC_TIMEOUT = 0x40, - -}; - -enum glamo_reg_clock_isp { - GLAMO_CLOCK_ISP_DG_I1CLK = 0x0001, - GLAMO_CLOCK_ISP_EN_I1CLK = 0x0002, - GLAMO_CLOCK_ISP_DG_CCLK = 0x0004, - GLAMO_CLOCK_ISP_EN_CCLK = 0x0008, - // - GLAMO_CLOCK_ISP_EN_SCLK = 0x0020, - GLAMO_CLOCK_ISP_DG_M2CLK = 0x0040, - GLAMO_CLOCK_ISP_EN_M2CLK = 0x0080, - GLAMO_CLOCK_ISP_DG_M15CLK = 0x0100, - GLAMO_CLOCK_ISP_EN_M15CLK = 0x0200, - GLAMO_CLOCK_ISP1_RESET = 0x1000, - GLAMO_CLOCK_ISP2_RESET = 0x2000, -}; - -enum glamo_reg_clock_jpeg { - GLAMO_CLOCK_JPEG_DG_JCLK = 0x0001, - GLAMO_CLOCK_JPEG_EN_JCLK = 0x0002, - GLAMO_CLOCK_JPEG_DG_M3CLK = 0x0004, - GLAMO_CLOCK_JPEG_EN_M3CLK = 0x0008, - GLAMO_CLOCK_JPEG_RESET = 0x1000, -}; - -enum glamo_reg_clock_2d { - GLAMO_CLOCK_2D_DG_GCLK = 0x0001, - GLAMO_CLOCK_2D_EN_GCLK = 0x0002, - GLAMO_CLOCK_2D_DG_M7CLK = 0x0004, - GLAMO_CLOCK_2D_EN_M7CLK = 0x0008, - GLAMO_CLOCK_2D_DG_M6CLK = 0x0010, - GLAMO_CLOCK_2D_EN_M6CLK = 0x0020, - GLAMO_CLOCK_2D_RESET = 0x1000, - GLAMO_CLOCK_2D_CQ_RESET = 0x2000, -}; - -enum glamo_reg_clock_3d { - GLAMO_CLOCK_3D_DG_ECLK = 0x0001, - GLAMO_CLOCK_3D_EN_ECLK = 0x0002, - GLAMO_CLOCK_3D_DG_RCLK = 0x0004, - GLAMO_CLOCK_3D_EN_RCLK = 0x0008, - GLAMO_CLOCK_3D_DG_M8CLK = 0x0010, - GLAMO_CLOCK_3D_EN_M8CLK = 0x0020, - GLAMO_CLOCK_3D_BACK_RESET = 0x1000, - GLAMO_CLOCK_3D_FRONT_RESET = 0x2000, -}; - -enum glamo_reg_clock_mpeg { - GLAMO_CLOCK_MPEG_DG_X0CLK = 0x0001, - GLAMO_CLOCK_MPEG_EN_X0CLK = 0x0002, - GLAMO_CLOCK_MPEG_DG_X1CLK = 0x0004, - GLAMO_CLOCK_MPEG_EN_X1CLK = 0x0008, - GLAMO_CLOCK_MPEG_DG_X2CLK = 0x0010, - GLAMO_CLOCK_MPEG_EN_X2CLK = 0x0020, - GLAMO_CLOCK_MPEG_DG_X3CLK = 0x0040, - GLAMO_CLOCK_MPEG_EN_X3CLK = 0x0080, - GLAMO_CLOCK_MPEG_DG_X4CLK = 0x0100, - GLAMO_CLOCK_MPEG_EN_X4CLK = 0x0200, - GLAMO_CLOCK_MPEG_DG_X6CLK = 0x0400, - GLAMO_CLOCK_MPEG_EN_X6CLK = 0x0800, - GLAMO_CLOCK_MPEG_ENC_RESET = 0x1000, - GLAMO_CLOCK_MPEG_DEC_RESET = 0x2000, -}; - -enum glamo_reg_clock51 { - GLAMO_CLOCK_GEN51_EN_DIV_MCLK = 0x0001, - GLAMO_CLOCK_GEN51_EN_DIV_SCLK = 0x0002, - GLAMO_CLOCK_GEN51_EN_DIV_JCLK = 0x0004, - GLAMO_CLOCK_GEN51_EN_DIV_DCLK = 0x0008, - GLAMO_CLOCK_GEN51_EN_DIV_DMCLK = 0x0010, - GLAMO_CLOCK_GEN51_EN_DIV_DHCLK = 0x0020, - GLAMO_CLOCK_GEN51_EN_DIV_GCLK = 0x0040, - GLAMO_CLOCK_GEN51_EN_DIV_TCLK = 0x0080, - /* FIXME: higher bits */ -}; - -enum glamo_reg_hostbus2 { - GLAMO_HOSTBUS2_MMIO_EN_ISP = 0x0001, - GLAMO_HOSTBUS2_MMIO_EN_JPEG = 0x0002, - GLAMO_HOSTBUS2_MMIO_EN_MPEG = 0x0004, - GLAMO_HOSTBUS2_MMIO_EN_LCD = 0x0008, - GLAMO_HOSTBUS2_MMIO_EN_MMC = 0x0010, - GLAMO_HOSTBUS2_MMIO_EN_MICROP0 = 0x0020, - GLAMO_HOSTBUS2_MMIO_EN_MICROP1 = 0x0040, - GLAMO_HOSTBUS2_MMIO_EN_CQ = 0x0080, - GLAMO_HOSTBUS2_MMIO_EN_RISC = 0x0100, - GLAMO_HOSTBUS2_MMIO_EN_2D = 0x0200, - GLAMO_HOSTBUS2_MMIO_EN_3D = 0x0400, -}; - -/* LCD Controller */ - -#define REG_LCD(x) (x) -enum glamo_reg_lcd { - GLAMO_REG_LCD_MODE1 = REG_LCD(0x00), - GLAMO_REG_LCD_MODE2 = REG_LCD(0x02), - GLAMO_REG_LCD_MODE3 = REG_LCD(0x04), - GLAMO_REG_LCD_WIDTH = REG_LCD(0x06), - GLAMO_REG_LCD_HEIGHT = REG_LCD(0x08), - GLAMO_REG_LCD_POLARITY = REG_LCD(0x0a), - GLAMO_REG_LCD_A_BASE1 = REG_LCD(0x0c), - GLAMO_REG_LCD_A_BASE2 = REG_LCD(0x0e), - GLAMO_REG_LCD_B_BASE1 = REG_LCD(0x10), - GLAMO_REG_LCD_B_BASE2 = REG_LCD(0x12), - GLAMO_REG_LCD_C_BASE1 = REG_LCD(0x14), - GLAMO_REG_LCD_C_BASE2 = REG_LCD(0x16), - GLAMO_REG_LCD_PITCH = REG_LCD(0x18), - /* RES */ - GLAMO_REG_LCD_HORIZ_TOTAL = REG_LCD(0x1c), - /* RES */ - GLAMO_REG_LCD_HORIZ_RETR_START = REG_LCD(0x20), - /* RES */ - GLAMO_REG_LCD_HORIZ_RETR_END = REG_LCD(0x24), - /* RES */ - GLAMO_REG_LCD_HORIZ_DISP_START = REG_LCD(0x28), - /* RES */ - GLAMO_REG_LCD_HORIZ_DISP_END = REG_LCD(0x2c), - /* RES */ - GLAMO_REG_LCD_VERT_TOTAL = REG_LCD(0x30), - /* RES */ - GLAMO_REG_LCD_VERT_RETR_START = REG_LCD(0x34), - /* RES */ - GLAMO_REG_LCD_VERT_RETR_END = REG_LCD(0x38), - /* RES */ - GLAMO_REG_LCD_VERT_DISP_START = REG_LCD(0x3c), - /* RES */ - GLAMO_REG_LCD_VERT_DISP_END = REG_LCD(0x40), - /* RES */ - GLAMO_REG_LCD_POL = REG_LCD(0x44), - GLAMO_REG_LCD_DATA_START = REG_LCD(0x46), - GLAMO_REG_LCD_FRATE_CONTRO = REG_LCD(0x48), - GLAMO_REG_LCD_DATA_CMD_HDR = REG_LCD(0x4a), - GLAMO_REG_LCD_SP_START = REG_LCD(0x4c), - GLAMO_REG_LCD_SP_END = REG_LCD(0x4e), - GLAMO_REG_LCD_CURSOR_BASE1 = REG_LCD(0x50), - GLAMO_REG_LCD_CURSOR_BASE2 = REG_LCD(0x52), - GLAMO_REG_LCD_CURSOR_PITCH = REG_LCD(0x54), - GLAMO_REG_LCD_CURSOR_X_SIZE = REG_LCD(0x56), - GLAMO_REG_LCD_CURSOR_Y_SIZE = REG_LCD(0x58), - GLAMO_REG_LCD_CURSOR_X_POS = REG_LCD(0x5a), - GLAMO_REG_LCD_CURSOR_Y_POS = REG_LCD(0x5c), - GLAMO_REG_LCD_CURSOR_PRESET = REG_LCD(0x5e), - GLAMO_REG_LCD_CURSOR_FG_COLOR = REG_LCD(0x60), - /* RES */ - GLAMO_REG_LCD_CURSOR_BG_COLOR = REG_LCD(0x64), - /* RES */ - GLAMO_REG_LCD_CURSOR_DST_COLOR = REG_LCD(0x68), - /* RES */ - GLAMO_REG_LCD_STATUS1 = REG_LCD(0x80), - GLAMO_REG_LCD_STATUS2 = REG_LCD(0x82), - GLAMO_REG_LCD_STATUS3 = REG_LCD(0x84), - GLAMO_REG_LCD_STATUS4 = REG_LCD(0x86), - /* RES */ - GLAMO_REG_LCD_COMMAND1 = REG_LCD(0xa0), - GLAMO_REG_LCD_COMMAND2 = REG_LCD(0xa2), - /* RES */ - GLAMO_REG_LCD_WFORM_DELAY1 = REG_LCD(0xb0), - GLAMO_REG_LCD_WFORM_DELAY2 = REG_LCD(0xb2), - /* RES */ - GLAMO_REG_LCD_GAMMA_CORR = REG_LCD(0x100), - /* RES */ - GLAMO_REG_LCD_GAMMA_R_ENTRY01 = REG_LCD(0x110), - GLAMO_REG_LCD_GAMMA_R_ENTRY23 = REG_LCD(0x112), - GLAMO_REG_LCD_GAMMA_R_ENTRY45 = REG_LCD(0x114), - GLAMO_REG_LCD_GAMMA_R_ENTRY67 = REG_LCD(0x116), - GLAMO_REG_LCD_GAMMA_R_ENTRY8 = REG_LCD(0x118), - /* RES */ - GLAMO_REG_LCD_GAMMA_G_ENTRY01 = REG_LCD(0x130), - GLAMO_REG_LCD_GAMMA_G_ENTRY23 = REG_LCD(0x132), - GLAMO_REG_LCD_GAMMA_G_ENTRY45 = REG_LCD(0x134), - GLAMO_REG_LCD_GAMMA_G_ENTRY67 = REG_LCD(0x136), - GLAMO_REG_LCD_GAMMA_G_ENTRY8 = REG_LCD(0x138), - /* RES */ - GLAMO_REG_LCD_GAMMA_B_ENTRY01 = REG_LCD(0x150), - GLAMO_REG_LCD_GAMMA_B_ENTRY23 = REG_LCD(0x152), - GLAMO_REG_LCD_GAMMA_B_ENTRY45 = REG_LCD(0x154), - GLAMO_REG_LCD_GAMMA_B_ENTRY67 = REG_LCD(0x156), - GLAMO_REG_LCD_GAMMA_B_ENTRY8 = REG_LCD(0x158), - /* RES */ - GLAMO_REG_LCD_SRAM_DRIVING1 = REG_LCD(0x160), - GLAMO_REG_LCD_SRAM_DRIVING2 = REG_LCD(0x162), - GLAMO_REG_LCD_SRAM_DRIVING3 = REG_LCD(0x164), -}; - -enum glamo_reg_lcd_mode1 { - GLAMO_LCD_MODE1_PWRSAVE = 0x0001, - GLAMO_LCD_MODE1_PARTIAL_PRT = 0x0002, - GLAMO_LCD_MODE1_HWFLIP = 0x0004, - GLAMO_LCD_MODE1_LCD2 = 0x0008, - /* RES */ - GLAMO_LCD_MODE1_PARTIAL_MODE = 0x0020, - GLAMO_LCD_MODE1_CURSOR_DSTCOLOR = 0x0040, - GLAMO_LCD_MODE1_PARTIAL_ENABLE = 0x0080, - GLAMO_LCD_MODE1_TVCLK_IN_ENABLE = 0x0100, - GLAMO_LCD_MODE1_HSYNC_HIGH_ACT = 0x0200, - GLAMO_LCD_MODE1_VSYNC_HIGH_ACT = 0x0400, - GLAMO_LCD_MODE1_HSYNC_FLIP = 0x0800, - GLAMO_LCD_MODE1_GAMMA_COR_EN = 0x1000, - GLAMO_LCD_MODE1_DITHER_EN = 0x2000, - GLAMO_LCD_MODE1_CURSOR_EN = 0x4000, - GLAMO_LCD_MODE1_ROTATE_EN = 0x8000, -}; - -enum glamo_reg_lcd_mode2 { - GLAMO_LCD_MODE2_CRC_CHECK_EN = 0x0001, - GLAMO_LCD_MODE2_DCMD_PER_LINE = 0x0002, - GLAMO_LCD_MODE2_NOUSE_BDEF = 0x0004, - GLAMO_LCD_MODE2_OUT_POS_MODE = 0x0008, - GLAMO_LCD_MODE2_FRATE_CTRL_EN = 0x0010, - GLAMO_LCD_MODE2_SINGLE_BUFFER = 0x0020, - GLAMO_LCD_MODE2_SER_LSB_TO_MSB = 0x0040, - /* FIXME */ -}; - -enum glamo_reg_lcd_mode3 { - /* LCD color source data format */ - GLAMO_LCD_SRC_RGB565 = 0x0000, - GLAMO_LCD_SRC_ARGB1555 = 0x4000, - GLAMO_LCD_SRC_ARGB4444 = 0x8000, - /* interface type */ - GLAMO_LCD_MODE3_LCD = 0x1000, - GLAMO_LCD_MODE3_RGB = 0x0800, - GLAMO_LCD_MODE3_CPU = 0x0000, - /* mode */ - GLAMO_LCD_MODE3_RGB332 = 0x0000, - GLAMO_LCD_MODE3_RGB444 = 0x0100, - GLAMO_LCD_MODE3_RGB565 = 0x0200, - GLAMO_LCD_MODE3_RGB666 = 0x0300, - /* depth */ - GLAMO_LCD_MODE3_6BITS = 0x0000, - GLAMO_LCD_MODE3_8BITS = 0x0010, - GLAMO_LCD_MODE3_9BITS = 0x0020, - GLAMO_LCD_MODE3_16BITS = 0x0030, - GLAMO_LCD_MODE3_18BITS = 0x0040, -}; - -enum glamo_lcd_rot_mode { - GLAMO_LCD_ROT_MODE_0 = 0x0000, - GLAMO_LCD_ROT_MODE_180 = 0x2000, - GLAMO_LCD_ROT_MODE_MIRROR = 0x4000, - GLAMO_LCD_ROT_MODE_FLIP = 0x6000, - GLAMO_LCD_ROT_MODE_90 = 0x8000, - GLAMO_LCD_ROT_MODE_270 = 0xa000, -}; -#define GLAMO_LCD_ROT_MODE_MASK 0xe000 - -enum glamo_lcd_cmd_type { - GLAMO_LCD_CMD_TYPE_DISP = 0x0000, - GLAMO_LCD_CMD_TYPE_PARALLEL = 0x4000, - GLAMO_LCD_CMD_TYPE_SERIAL = 0x8000, - GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000, -}; -#define GLAMO_LCD_CMD_TYPE_MASK 0xc000 - -enum glamo_lcd_cmds { - GLAMO_LCD_CMD_DATA_DISP_FIRE = 0x00, - GLAMO_LCD_CMD_DATA_DISP_SYNC = 0x01, /* RGB only */ - /* switch to command mode, no display */ - GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02, - /* display until VSYNC, switch to command */ - GLAMO_LCD_CMD_DATA_FIRE_VSYNC = 0x11, - /* display until HSYNC, switch to command */ - GLAMO_LCD_CMD_DATA_FIRE_HSYNC = 0x12, - /* display until VSYNC, 1 black frame, VSYNC, switch to command */ - GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13, - /* don't care about display and switch to command */ - GLAMO_LCD_CMD_DATA_FIRE_FREE = 0x14, /* RGB only */ - /* don't care about display, keep data display but disable data, - * and switch to command */ - GLAMO_LCD_CMD_DATA_FIRE_FREE_D = 0x15, /* RGB only */ -}; - -enum glamo_core_revisions { - GLAMO_CORE_REV_A0 = 0x0000, - GLAMO_CORE_REV_A1 = 0x0001, - GLAMO_CORE_REV_A2 = 0x0002, - GLAMO_CORE_REV_A3 = 0x0003, -}; - -#endif /* _GLAMO_REGS_H */ diff --git a/qiboot/include/i2c-bitbang-s3c24xx.h b/qiboot/include/i2c-bitbang-s3c24xx.h deleted file mode 100644 index 6be18b9..0000000 --- a/qiboot/include/i2c-bitbang-s3c24xx.h +++ /dev/null @@ -1,3 +0,0 @@ -#include - -extern struct i2c_bitbang bb_s3c24xx; diff --git a/qiboot/include/i2c-bitbang-s3c6410.h b/qiboot/include/i2c-bitbang-s3c6410.h deleted file mode 100644 index b1c3ed5..0000000 --- a/qiboot/include/i2c-bitbang-s3c6410.h +++ /dev/null @@ -1,3 +0,0 @@ -#include - -extern struct i2c_bitbang bb_s3c6410; diff --git a/qiboot/include/i2c-bitbang.h b/qiboot/include/i2c-bitbang.h deleted file mode 100644 index f5b86ef..0000000 --- a/qiboot/include/i2c-bitbang.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: Andy Green - * - * Generic i2c bitbang state machine - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* controls symbol sequencing on i2c */ - -enum i2c_bitbang_control { - IBCONTROL_DO_START = -1, - IBCONTROL_DO_STOP = -2, - IBCONTROL_DO_READ = -3, - IBCONTROL_COMPLETE = -4 -}; - -/* control intra-bit and byte states */ - -enum i2c_bitbang_states { - IBS_INIT, - - IBS_START1, - IBS_START2, - - IBS_ADS_TX_S, - IBS_ADS_TX_H, - IBS_ADS_TX_L, - IBS_ADS_TX_ACK_H, - IBS_ADS_TX_ACK_L, - - IBS_DATA_RX_S, - IBS_DATA_RX_H, - IBS_DATA_RX_L, - - IBS_DATA_RX_ACK_H, - IBS_DATA_RX_ACK_L, - - IBS_STOP1, - IBS_STOP2, - IBS_STOP3, - IBS_STOP4 -}; - -/* context for bitbang GPIO pins and transaction */ - -struct i2c_bitbang { - - enum i2c_bitbang_states state; - int count; - unsigned int data[8]; /* read result found here */ - int index; - int index_read; - - char (*read_sda)(void); - /* data = 0 = op low, 1 == inp */ - void (*set)(char clock, char data); - /* delay > 1 half-bit time, used by i2c_complete_synchronously() */ - void (*spin)(void); - void (*close)(void); -}; - -/* synchronous read and write functions spin until completed or failed - * i2c_read_sync returns -1 for fail or byte result from device - */ - -extern int i2c_read_sync(struct i2c_bitbang * bb, unsigned char ads7, - unsigned char reg); -extern void i2c_write_sync(struct i2c_bitbang * bb, unsigned char ads7, - unsigned char reg, unsigned char data); - - -/* - * set up an asynchronous read or write transaction - */ -extern void i2c_read(struct i2c_bitbang * bb, unsigned char ads7, - unsigned char reg); -extern void i2c_write(struct i2c_bitbang * bb, unsigned char ads7, - unsigned char reg, unsigned char data); - -/* - * after setting up a read or write transaction above, you loop calling this - * with >= 1.25us (400kHz) or >= 5us (100kHz) delay between calls. You don't - * have to spin but can do something useful if you know it will take more than - * an i2c bit-time, hiding the time for the i2c transaction completely. - */ -extern int i2c_next_state(struct i2c_bitbang * bb); /* return !=0 = completed */ diff --git a/qiboot/include/image.h b/qiboot/include/image.h deleted file mode 100644 index af9ecda..0000000 --- a/qiboot/include/image.h +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2008 Semihalf - * - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef __IMAGE_H__ -#define __IMAGE_H__ - -/* - * Operating System Codes - */ -#define IH_OS_INVALID 0 /* Invalid OS */ -#define IH_OS_OPENBSD 1 /* OpenBSD */ -#define IH_OS_NETBSD 2 /* NetBSD */ -#define IH_OS_FREEBSD 3 /* FreeBSD */ -#define IH_OS_4_4BSD 4 /* 4.4BSD */ -#define IH_OS_LINUX 5 /* Linux */ -#define IH_OS_SVR4 6 /* SVR4 */ -#define IH_OS_ESIX 7 /* Esix */ -#define IH_OS_SOLARIS 8 /* Solaris */ -#define IH_OS_IRIX 9 /* Irix */ -#define IH_OS_SCO 10 /* SCO */ -#define IH_OS_DELL 11 /* Dell */ -#define IH_OS_NCR 12 /* NCR */ -#define IH_OS_LYNXOS 13 /* LynxOS */ -#define IH_OS_VXWORKS 14 /* VxWorks */ -#define IH_OS_PSOS 15 /* pSOS */ -#define IH_OS_QNX 16 /* QNX */ -#define IH_OS_U_BOOT 17 /* Firmware */ -#define IH_OS_RTEMS 18 /* RTEMS */ -#define IH_OS_ARTOS 19 /* ARTOS */ -#define IH_OS_UNITY 20 /* Unity OS */ - -/* - * CPU Architecture Codes (supported by Linux) - */ -#define IH_ARCH_INVALID 0 /* Invalid CPU */ -#define IH_ARCH_ALPHA 1 /* Alpha */ -#define IH_ARCH_ARM 2 /* ARM */ -#define IH_ARCH_I386 3 /* Intel x86 */ -#define IH_ARCH_IA64 4 /* IA64 */ -#define IH_ARCH_MIPS 5 /* MIPS */ -#define IH_ARCH_MIPS64 6 /* MIPS 64 Bit */ -#define IH_ARCH_PPC 7 /* PowerPC */ -#define IH_ARCH_S390 8 /* IBM S390 */ -#define IH_ARCH_SH 9 /* SuperH */ -#define IH_ARCH_SPARC 10 /* Sparc */ -#define IH_ARCH_SPARC64 11 /* Sparc 64 Bit */ -#define IH_ARCH_M68K 12 /* M68K */ -#define IH_ARCH_NIOS 13 /* Nios-32 */ -#define IH_ARCH_MICROBLAZE 14 /* MicroBlaze */ -#define IH_ARCH_NIOS2 15 /* Nios-II */ -#define IH_ARCH_BLACKFIN 16 /* Blackfin */ -#define IH_ARCH_AVR32 17 /* AVR32 */ -#define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */ - -/* - * Image Types - * - * "Standalone Programs" are directly runnable in the environment - * provided by U-Boot; it is expected that (if they behave - * well) you can continue to work in U-Boot after return from - * the Standalone Program. - * "OS Kernel Images" are usually images of some Embedded OS which - * will take over control completely. Usually these programs - * will install their own set of exception handlers, device - * drivers, set up the MMU, etc. - this means, that you cannot - * expect to re-enter U-Boot except by resetting the CPU. - * "RAMDisk Images" are more or less just data blocks, and their - * parameters (address, size) are passed to an OS kernel that is - * being started. - * "Multi-File Images" contain several images, typically an OS - * (Linux) kernel image and one or more data images like - * RAMDisks. This construct is useful for instance when you want - * to boot over the network using BOOTP etc., where the boot - * server provides just a single image file, but you want to get - * for instance an OS kernel and a RAMDisk image. - * - * "Multi-File Images" start with a list of image sizes, each - * image size (in bytes) specified by an "uint32_t" in network - * byte order. This list is terminated by an "(uint32_t)0". - * Immediately after the terminating 0 follow the images, one by - * one, all aligned on "uint32_t" boundaries (size rounded up to - * a multiple of 4 bytes - except for the last file). - * - * "Firmware Images" are binary images containing firmware (like - * U-Boot or FPGA images) which usually will be programmed to - * flash memory. - * - * "Script files" are command sequences that will be executed by - * U-Boot's command interpreter; this feature is especially - * useful when you configure U-Boot to use a real shell (hush) - * as command interpreter (=> Shell Scripts). - */ - -#define IH_TYPE_INVALID 0 /* Invalid Image */ -#define IH_TYPE_STANDALONE 1 /* Standalone Program */ -#define IH_TYPE_KERNEL 2 /* OS Kernel Image */ -#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */ -#define IH_TYPE_MULTI 4 /* Multi-File Image */ -#define IH_TYPE_FIRMWARE 5 /* Firmware Image */ -#define IH_TYPE_SCRIPT 6 /* Script file */ -#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ -#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ - -/* - * Compression Types - */ -#define IH_COMP_NONE 0 /* No Compression Used */ -#define IH_COMP_GZIP 1 /* gzip Compression Used */ -#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ - -#define IH_MAGIC 0x27051956 /* Image Magic Number */ -#define IH_NMLEN 32 /* Image Name Length */ - -/* - * Legacy format image header, - * all data in network byte order (aka natural aka bigendian). - */ -typedef struct image_header { - uint32_t ih_magic; /* Image Header Magic Number */ - uint32_t ih_hcrc; /* Image Header CRC Checksum */ - uint32_t ih_time; /* Image Creation Timestamp */ - uint32_t ih_size; /* Image Data Size */ - uint32_t ih_load; /* Data Load Address */ - uint32_t ih_ep; /* Entry Point Address */ - uint32_t ih_dcrc; /* Image Data CRC Checksum */ - uint8_t ih_os; /* Operating System */ - uint8_t ih_arch; /* CPU architecture */ - uint8_t ih_type; /* Image Type */ - uint8_t ih_comp; /* Compression Type */ - uint8_t ih_name[IH_NMLEN]; /* Image Name */ -} image_header_t; - -/* - * Legacy and FIT format headers used by do_bootm() and do_bootm_() - * routines. - */ -typedef struct bootm_headers { - /* - * Legacy os image header, if it is a multi component image - * then boot_get_ramdisk() and get_fdt() will attempt to get - * data from second and third component accordingly. - */ - image_header_t *legacy_hdr_os; - ulong legacy_hdr_valid; - -#if defined(CONFIG_FIT) - const char *fit_uname_cfg; /* configuration node unit name */ - - void *fit_hdr_os; /* os FIT image header */ - const char *fit_uname_os; /* os subimage node unit name */ - int fit_noffset_os; /* os subimage node offset */ - - void *fit_hdr_rd; /* init ramdisk FIT image header */ - const char *fit_uname_rd; /* init ramdisk subimage node unit name */ - int fit_noffset_rd; /* init ramdisk subimage node offset */ - -#if defined(CONFIG_PPC) - void *fit_hdr_fdt; /* FDT blob FIT image header */ - const char *fit_uname_fdt; /* FDT blob subimage node unit name */ - int fit_noffset_fdt;/* FDT blob subimage node offset */ -#endif -#endif - - int verify; /* getenv("verify")[0] != 'n' */ - int autostart; /* getenv("autostart")[0] != 'n' */ - struct lmb *lmb; /* for memory mgmt */ -} bootm_headers_t; - -/* - * Some systems (for example LWMON) have very short watchdog periods; - * we must make sure to split long operations like memmove() or - * crc32() into reasonable chunks. - */ -#define CHUNKSZ (64 * 1024) - -#define uimage_to_cpu(x) __be32_to_cpu(x) -#define cpu_to_uimage(x) __cpu_to_be32(x) - -const char *genimg_get_os_name (uint8_t os); -const char *genimg_get_arch_name (uint8_t arch); -const char *genimg_get_type_name (uint8_t type); -const char *genimg_get_comp_name (uint8_t comp); -int genimg_get_os_id (const char *name); -int genimg_get_arch_id (const char *name); -int genimg_get_type_id (const char *name); -int genimg_get_comp_id (const char *name); - -#ifndef USE_HOSTCC -/* Image format types, returned by _get_format() routine */ -#define IMAGE_FORMAT_INVALID 0x00 -#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ -#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ - -int genimg_get_format (void *img_addr); -int genimg_has_config (bootm_headers_t *images); -ulong genimg_get_image (ulong img_addr); - -int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images, - uint8_t arch, ulong *rd_start, ulong *rd_end); - -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) -int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len, - ulong *initrd_start, ulong *initrd_end); - -int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end, - ulong bootmap_base); -int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base); -#endif /* CONFIG_PPC || CONFIG_M68K */ -#endif /* !USE_HOSTCC */ - -/*******************************************************************/ -/* Legacy format specific code (prefixed with image_) */ -/*******************************************************************/ -static inline uint32_t image_get_header_size (void) -{ - return (sizeof (image_header_t)); -} - -#define image_get_hdr_l(f) \ - static inline uint32_t image_get_##f(image_header_t *hdr) \ - { \ - return uimage_to_cpu (hdr->ih_##f); \ - } -image_get_hdr_l (magic); -image_get_hdr_l (hcrc); -image_get_hdr_l (time); -image_get_hdr_l (size); -image_get_hdr_l (load); -image_get_hdr_l (ep); -image_get_hdr_l (dcrc); - -#define image_get_hdr_b(f) \ - static inline uint8_t image_get_##f(image_header_t *hdr) \ - { \ - return hdr->ih_##f; \ - } -image_get_hdr_b (os); -image_get_hdr_b (arch); -image_get_hdr_b (type); -image_get_hdr_b (comp); - -static inline char *image_get_name (image_header_t *hdr) -{ - return (char *)hdr->ih_name; -} - -static inline uint32_t image_get_data_size (image_header_t *hdr) -{ - return image_get_size (hdr); -} - -/** - * image_get_data - get image payload start address - * @hdr: image header - * - * image_get_data() returns address of the image payload. For single - * component images it is image data start. For multi component - * images it points to the null terminated table of sub-images sizes. - * - * returns: - * image payload data start address - */ -static inline ulong image_get_data (image_header_t *hdr) -{ - return ((ulong)hdr + image_get_header_size ()); -} - -static inline uint32_t image_get_image_size (image_header_t *hdr) -{ - return (image_get_size (hdr) + image_get_header_size ()); -} -static inline ulong image_get_image_end (image_header_t *hdr) -{ - return ((ulong)hdr + image_get_image_size (hdr)); -} - -#define image_set_hdr_l(f) \ - static inline void image_set_##f(image_header_t *hdr, uint32_t val) \ - { \ - hdr->ih_##f = cpu_to_uimage (val); \ - } -image_set_hdr_l (magic); -image_set_hdr_l (hcrc); -image_set_hdr_l (time); -image_set_hdr_l (size); -image_set_hdr_l (load); -image_set_hdr_l (ep); -image_set_hdr_l (dcrc); - -#define image_set_hdr_b(f) \ - static inline void image_set_##f(image_header_t *hdr, uint8_t val) \ - { \ - hdr->ih_##f = val; \ - } -image_set_hdr_b (os); -image_set_hdr_b (arch); -image_set_hdr_b (type); -image_set_hdr_b (comp); - -static inline void image_set_name (image_header_t *hdr, const char *name) -{ - strncpy (image_get_name (hdr), name, IH_NMLEN); -} - -int image_check_hcrc (image_header_t *hdr); -int image_check_dcrc (image_header_t *hdr); -#ifndef USE_HOSTCC -int image_check_dcrc_wd (image_header_t *hdr, ulong chunksize); -int getenv_verify (void); -int getenv_autostart (void); -ulong getenv_bootm_low(void); -ulong getenv_bootm_size(void); -void memmove_wd (void *to, void *from, size_t len, ulong chunksz); -#endif - -static inline int image_check_magic (image_header_t *hdr) -{ - return (image_get_magic (hdr) == IH_MAGIC); -} -static inline int image_check_type (image_header_t *hdr, uint8_t type) -{ - return (image_get_type (hdr) == type); -} -static inline int image_check_arch (image_header_t *hdr, uint8_t arch) -{ - return (image_get_arch (hdr) == arch); -} -static inline int image_check_os (image_header_t *hdr, uint8_t os) -{ - return (image_get_os (hdr) == os); -} - -ulong image_multi_count (image_header_t *hdr); -void image_multi_getimg (image_header_t *hdr, ulong idx, - ulong *data, ulong *len); - -inline void image_print_contents (image_header_t *hdr); -inline void image_print_contents_noindent (image_header_t *hdr); - -#ifndef USE_HOSTCC -static inline int image_check_target_arch (image_header_t *hdr) -{ -#if defined(__ARM__) - if (!image_check_arch (hdr, IH_ARCH_ARM)) -#elif defined(__avr32__) - if (!image_check_arch (hdr, IH_ARCH_AVR32)) -#elif defined(__bfin__) - if (!image_check_arch (hdr, IH_ARCH_BLACKFIN)) -#elif defined(__I386__) - if (!image_check_arch (hdr, IH_ARCH_I386)) -#elif defined(__M68K__) - if (!image_check_arch (hdr, IH_ARCH_M68K)) -#elif defined(__microblaze__) - if (!image_check_arch (hdr, IH_ARCH_MICROBLAZE)) -#elif defined(__mips__) - if (!image_check_arch (hdr, IH_ARCH_MIPS)) -#elif defined(__nios__) - if (!image_check_arch (hdr, IH_ARCH_NIOS)) -#elif defined(__nios2__) - if (!image_check_arch (hdr, IH_ARCH_NIOS2)) -#elif defined(__PPC__) - if (!image_check_arch (hdr, IH_ARCH_PPC)) -#elif defined(__sh__) - if (!image_check_arch (hdr, IH_ARCH_SH)) -#else -# error Unknown CPU type -#endif - return 0; - - return 1; -} -#endif /* USE_HOSTCC */ - -/*******************************************************************/ -/* New uImage format specific code (prefixed with fit_) */ -/*******************************************************************/ -#if defined(CONFIG_FIT) - -#define FIT_IMAGES_PATH "/images" -#define FIT_CONFS_PATH "/configurations" - -/* hash node */ -#define FIT_HASH_NODENAME "hash" -#define FIT_ALGO_PROP "algo" -#define FIT_VALUE_PROP "value" - -/* image node */ -#define FIT_DATA_PROP "data" -#define FIT_TIMESTAMP_PROP "timestamp" -#define FIT_DESC_PROP "description" -#define FIT_ARCH_PROP "arch" -#define FIT_TYPE_PROP "type" -#define FIT_OS_PROP "os" -#define FIT_COMP_PROP "compression" -#define FIT_ENTRY_PROP "entry" -#define FIT_LOAD_PROP "load" - -/* configuration node */ -#define FIT_KERNEL_PROP "kernel" -#define FIT_RAMDISK_PROP "ramdisk" -#define FIT_FDT_PROP "fdt" -#define FIT_DEFAULT_PROP "default" - -#define FIT_MAX_HASH_LEN 20 /* max(crc32_len(4), sha1_len(20)) */ - -/* cmdline argument format parsing */ -inline int fit_parse_conf (const char *spec, ulong addr_curr, - ulong *addr, const char **conf_name); -inline int fit_parse_subimage (const char *spec, ulong addr_curr, - ulong *addr, const char **image_name); - -inline void fit_print_contents (const void *fit); -inline void fit_print_contents_noindent (const void *fit); -void fit_image_print (const void *fit, int noffset, const char *p); -void fit_image_print_hash (const void *fit, int noffset, const char *p); - -/** - * fit_get_end - get FIT image size - * @fit: pointer to the FIT format image header - * - * returns: - * size of the FIT image (blob) in memory - */ -static inline ulong fit_get_size (const void *fit) -{ - return fdt_totalsize (fit); -} - -/** - * fit_get_end - get FIT image end - * @fit: pointer to the FIT format image header - * - * returns: - * end address of the FIT image (blob) in memory - */ -static inline ulong fit_get_end (const void *fit) -{ - return (ulong)fit + fdt_totalsize (fit); -} - -/** - * fit_get_name - get FIT node name - * @fit: pointer to the FIT format image header - * - * returns: - * NULL, on error - * pointer to node name, on success - */ -static inline const char *fit_get_name (const void *fit_hdr, - int noffset, int *len) -{ - return fdt_get_name (fit_hdr, noffset, len); -} - -int fit_get_desc (const void *fit, int noffset, char **desc); -int fit_get_timestamp (const void *fit, int noffset, time_t *timestamp); - -int fit_image_get_node (const void *fit, const char *image_uname); -int fit_image_get_os (const void *fit, int noffset, uint8_t *os); -int fit_image_get_arch (const void *fit, int noffset, uint8_t *arch); -int fit_image_get_type (const void *fit, int noffset, uint8_t *type); -int fit_image_get_comp (const void *fit, int noffset, uint8_t *comp); -int fit_image_get_load (const void *fit, int noffset, ulong *load); -int fit_image_get_entry (const void *fit, int noffset, ulong *entry); -int fit_image_get_data (const void *fit, int noffset, - const void **data, size_t *size); - -int fit_image_hash_get_algo (const void *fit, int noffset, char **algo); -int fit_image_hash_get_value (const void *fit, int noffset, uint8_t **value, - int *value_len); - -int fit_set_timestamp (void *fit, int noffset, time_t timestamp); -int fit_set_hashes (void *fit); -int fit_image_set_hashes (void *fit, int image_noffset); -int fit_image_hash_set_value (void *fit, int noffset, uint8_t *value, - int value_len); - -int fit_image_check_hashes (const void *fit, int noffset); -int fit_image_check_os (const void *fit, int noffset, uint8_t os); -int fit_image_check_arch (const void *fit, int noffset, uint8_t arch); -int fit_image_check_type (const void *fit, int noffset, uint8_t type); -int fit_image_check_comp (const void *fit, int noffset, uint8_t comp); -int fit_check_format (const void *fit); - -int fit_conf_get_node (const void *fit, const char *conf_uname); -int fit_conf_get_kernel_node (const void *fit, int noffset); -int fit_conf_get_ramdisk_node (const void *fit, int noffset); -int fit_conf_get_fdt_node (const void *fit, int noffset); - -void fit_conf_print (const void *fit, int noffset, const char *p); - -#ifndef USE_HOSTCC -static inline int fit_image_check_target_arch (const void *fdt, int node) -{ -#if defined(__ARM__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_ARM)) -#elif defined(__avr32__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_AVR32)) -#elif defined(__bfin__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_BLACKFIN)) -#elif defined(__I386__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_I386)) -#elif defined(__M68K__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_M68K)) -#elif defined(__microblaze__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_MICROBLAZE)) -#elif defined(__mips__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_MIPS)) -#elif defined(__nios__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_NIOS)) -#elif defined(__nios2__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_NIOS2)) -#elif defined(__PPC__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_PPC)) -#elif defined(__sh__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_SH)) -#else -# error Unknown CPU type -#endif - return 0; - - return 1; -} -#endif /* USE_HOSTCC */ - -#ifdef CONFIG_FIT_VERBOSE -#define fit_unsupported(msg) printf ("! %s:%d " \ - "FIT images not supported for '%s'\n", \ - __FILE__, __LINE__, (msg)) - -#define fit_unsupported_reset(msg) printf ("! %s:%d " \ - "FIT images not supported for '%s' " \ - "- must reset board to recover!\n", \ - __FILE__, __LINE__, (msg)) -#else -#define fit_unsupported(msg) -#define fit_unsupported_reset(msg) -#endif /* CONFIG_FIT_VERBOSE */ -#endif /* CONFIG_FIT */ - -#endif /* __IMAGE_H__ */ diff --git a/qiboot/include/linux-mmc-protocol.h b/qiboot/include/linux-mmc-protocol.h deleted file mode 100644 index 2d90273..0000000 --- a/qiboot/include/linux-mmc-protocol.h +++ /dev/null @@ -1,382 +0,0 @@ -/* - * Header for MultiMediaCard (MMC) - * - * Copyright 2002 Hewlett-Packard Company - * - * Use consistent with the GNU GPL is permitted, - * provided that this copyright notice is - * preserved in its entirety in all copies and derived works. - * - * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, - * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS - * FITNESS FOR ANY PARTICULAR PURPOSE. - * - * Many thanks to Alessandro Rubini and Jonathan Corbet! - * - * Based strongly on code by: - * - * Author: Yong-iL Joh - * Date : $Date: 2006/12/06 02:50:52 $ - * - * Author: Andrew Christian - * 15 May 2002 - */ - -#ifndef MMC_MMC_PROTOCOL_H -#define MMC_MMC_PROTOCOL_H - -#ifdef CONFIG_SUPPORT_MMC_PLUS -/* Standard MMC commands (4.2) type argument response */ -#else -/* Standard MMC commands (3.1) type argument response */ -#endif - /* class 1 */ -#define MMC_GO_IDLE_STATE 0 /* bc */ -#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ -#define MMC_ALL_SEND_CID 2 /* bcr R2 */ -#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ -#define MMC_SET_DSR 4 /* bc [31:16] RCA */ -#define MMC_SWITCH 6 /* ac R1b */ -#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ -#define MMC_SEND_EXT_CSD 8 /* adtc R1 */ -#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ -#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ -#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ -#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ -#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ -#define MMC_BUSTEST_R 14 /* adtc R1 */ -#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ -#define MMC_BUSTEST_W 19 /* adtc R1 */ - - /* class 2 */ -#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ -#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ -#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ - - /* class 3 */ -#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ - - /* class 4 */ -#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ -#define MMC_PROGRAM_CID 26 /* adtc R1 */ -#define MMC_PROGRAM_CSD 27 /* adtc R1 */ - - /* class 6 */ -#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ -#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ -#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ - - /* class 5 */ -#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ -#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ -#define MMC_ERASE 38 /* ac R1b */ - - /* class 9 */ -#define MMC_FAST_IO 39 /* ac R4 */ -#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ - - /* class 7 */ -#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ - - /* class 8 */ -#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ -#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ - -/* SD commands type argument response */ - /* class 8 */ -/* This is basically the same command as for MMC with some quirks. */ -#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */ - - /* Application commands */ -#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ -#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ -#define SD_APP_SEND_SCR 51 /* adtc R1 */ - -/* - MMC status in R1 - Type - e : error bit - s : status bit - r : detected and set for the actual command response - x : detected and set during command execution. the host must poll - the card by sending status command in order to read these bits. - Clear condition - a : according to the card state - b : always related to the previous command. Reception of - a valid command will clear it (with a delay of one command) - c : clear by read - */ - -#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ -#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ -#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ -#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ -#define R1_ERASE_PARAM (1 << 27) /* ex, c */ -#define R1_WP_VIOLATION (1 << 26) /* erx, c */ -#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ -#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ -#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ -#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ -#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ -#define R1_CC_ERROR (1 << 20) /* erx, c */ -#define R1_ERROR (1 << 19) /* erx, c */ -#define R1_UNDERRUN (1 << 18) /* ex, c */ -#define R1_OVERRUN (1 << 17) /* ex, c */ -#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ -#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ -#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ -#define R1_ERASE_RESET (1 << 13) /* sr, c */ -#define R1_STATUS(x) (x & 0xFFFFE000) -#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ -#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ -#define R1_APP_CMD (1 << 5) /* sr, c */ - -/* - MMC CURRENT_STATE in R1 [12:9] - */ -#define STATE_IDLE (0x0 << 9) /* 0 */ -#define STATE_READY (0x1 << 9) /* 1 */ -#define STATE_IDENT (0x2 << 9) /* 2 */ -#define STATE_STBY (0x3 << 9) /* 3 */ -#define STATE_TRAN (0x4 << 9) /* 4 */ -#define STATE_DATA (0x5 << 9) /* 5 */ -#define STATE_RCV (0x6 << 9) /* 6 */ -#define STATE_PRG (0x7 << 9) /* 7 */ -#define STATE_DIS (0x8 << 9) /* 8 */ -#define STATE_BTST (0x9 << 9) /* 9 */ - -/* These are unpacked versions of the actual responses */ - -struct _mmc_csd { - u8 csd_structure; - u8 spec_vers; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc; - u8 read_bl_len; - u8 read_bl_partial; - u8 write_blk_misalign; - u8 read_blk_misalign; - u8 dsr_imp; - u16 c_size; - u8 vdd_r_curr_min; - u8 vdd_r_curr_max; - u8 vdd_w_curr_min; - u8 vdd_w_curr_max; - u8 c_size_mult; - union { - struct { /* MMC system specification version 3.1 */ - u8 erase_grp_size; - u8 erase_grp_mult; - } v31; - struct { /* MMC system specification version 2.2 */ - u8 sector_size; - u8 erase_grp_size; - } v22; - } erase; - u8 wp_grp_size; - u8 wp_grp_enable; - u8 default_ecc; - u8 r2w_factor; - u8 write_bl_len; - u8 write_bl_partial; - u8 file_format_grp; - u8 copy; - u8 perm_write_protect; - u8 tmp_write_protect; - u8 file_format; - u8 ecc; -}; - -struct _mmc_ext_csd { - u8 s_cmd_set; - u32 sec_count; - u8 MIN_PERF_W_8_52; - u8 MIN_PERF_R_8_52; - u8 MIN_PERF_W_8_26_4_52; - u8 MIN_PERF_R_8_26_4_52; - u8 MIN_PERF_W_4_26; - u8 MIN_PERF_R_4_26; - u8 PWR_CL_26_360; - u8 PWR_CL_52_360; - u8 PWR_CL_26_195; - u8 PWR_CL_52_195; - u8 card_type; - u8 csd_structure; - u8 ext_csd_rev; - u8 cmd_set; - u8 cmd_set_rev; - u8 power_class; - u8 hs_timing; - u8 bus_width; -}; - -#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */ -#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */ -#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */ -#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */ -#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */ -#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */ -#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */ -#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */ -#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ -#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ -#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ -#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ -#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ -#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ -#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ -#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ -#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ -#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ -#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ -#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ -#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ -#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ -#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ -#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ -#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ - -/* - * Card Command Classes (CCC) - */ -#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ - /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ -#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ - /* (CMD11) */ -#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ - /* (CMD16,17,18) */ -#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ - /* (CMD20) */ -#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ - /* (CMD16,24,25,26,27) */ -#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ - /* (CMD32,33,34,35,36,37,38,39) */ -#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ - /* (CMD28,29,30) */ -#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ - /* (CMD16,CMD42) */ -#define CCC_APP_SPEC (1<<8) /* (8) Application specific */ - /* (CMD55,56,57,ACMD*) */ -#define CCC_IO_MODE (1<<9) /* (9) I/O mode */ - /* (CMD5,39,40,52,53) */ -#define CCC_SWITCH (1<<10) /* (10) High speed switch */ - /* (CMD6,34,35,36,37,50) */ - /* (11) Reserved */ - /* (CMD?) */ - -/* - * CSD field definitions - */ - -#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ -#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ -#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */ - -#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ -#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ -#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ -#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */ -#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 ~ 4.2 */ - -/* - * SD bus widths - */ -#define SD_BUS_WIDTH_1 0 -#define SD_BUS_WIDTH_4 2 - -/* - * EXT_CSD field definitions - */ - -/* - * S_CMD_SET - */ - -#define STANDARD_MMC 0 /* Standard MMC */ -#define SECURE_MMC 1 /* Secure MMC */ -#define CPS_MMC 2 /* Content Protection Secure MMC */ -#define SECURE_MMC_2 3 /* Secure MMC 2.0 */ -#define ATA_MMC 4 /* ATA on MMC */ - -/* - * MIN_PERF_a_b_ff - */ -#define NO_CLASS 0x0 /* For cards not reaching the 2.4MB/s minimum value */ -#define CLASS_A 0x08 /* Class A */ -#define CLASS_B 0x0A /* Class B */ -#define CLASS_C 0x0F /* Class C */ -#define CLASS_D 0x14 /* Class D */ -#define CLASS_E 0x1E /* Class E */ -#define CLASS_F 0x28 /* Class F */ -#define CLASS_G 0x32 /* Class G */ -#define CLASS_H 0x3c /* Class H */ -#define CLASS_J 0x46 /* Class J */ -#define CLASS_K 0x50 /* Class E */ -#define CLASS_M 0x64 /* Class M */ -#define CLASS_O 0x78 /* Class O */ -#define CLASS_R 0x8c /* Class R */ -#define CLASS_T 0xa0 /* Class T */ - -/* - * CARD_TYPE - */ - -#define MMCPLUS_26MHZ (1<<0) -#define MMCPLUS_52MHZ (1<<1) - -/* - * EXT_CSD_REV - */ - -#define EXT_CSD_REV_1_0 0 -#define EXT_CSD_REV_1_1 1 -#define EXT_CSD_REV_1_2 2 - -/* - * HS_TIMING - */ -#define HS_TIMING_LOW 0 -#define HS_TIMING_HIGH 1 - -/* - * BUS_WIDTH - */ -#define MMCPLUS_BUS_WIDTH_1 0 -#define MMCPLUS_BUS_WIDTH_4 1 -#define MMCPLUS_BUS_WIDTH_8 2 - - -/* - * ERASED_MEM_CONT - */ - -#define ERASED_MEM_CONT_0 0 -#define ERASED_MEM_CONT_1 1 - -/* - * Argument for CMD6 - */ - -/* - * EXT_CSD Access Modes - */ - -#define EXT_CSD_COMMAND_SET 0 -#define EXT_CSD_SET_BITS 1 -#define EXT_CSD_CLEAR_BITS 2 -#define EXT_CSD_WRITE_BYTE 3 - -/* - * EXT_CSD Argument Byte - */ - -#define EXT_CSD_POWER_CLASS 187 -#define EXT_CSD_BUS_WIDTH 183 -#define EXT_CSD_HS_TIMING 185 - -#endif /* MMC_MMC_PROTOCOL_H */ - diff --git a/qiboot/include/linux-mmc.h b/qiboot/include/linux-mmc.h deleted file mode 100644 index 2750a51..0000000 --- a/qiboot/include/linux-mmc.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * linux/include/linux/mmc/mmc.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef MMC_H -#define MMC_H - -/* removed by scsuh */ -#if 0 -#include -#include -#include - -struct request; -struct mmc_data; -struct mmc_request; -#endif - -#define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ -#define MMC_CMD_MASK (3 << 5) /* command type */ -#define MMC_CMD_AC (0 << 5) -#define MMC_CMD_ADTC (1 << 5) -#define MMC_CMD_BC (2 << 5) -#define MMC_CMD_BCR (3 << 5) - -/* - * These are the response types, and correspond to valid bit - * patterns of the above flags. One additional valid pattern - * is all zeros, which means we don't expect a response. - */ -#define MMC_RSP_NONE (0) -#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) -#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) -#define MMC_RSP_R3 (MMC_RSP_PRESENT) -#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC) - -#define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE)) - -/* - * These are the command types. - */ -#define mmc_cmd_type(cmd) ((cmd)->flags & MMC_CMD_MASK) - -#define MMC_ERR_NONE 0 -#define MMC_ERR_TIMEOUT 1 -#define MMC_ERR_BADCRC 2 -#define MMC_ERR_FIFO 3 -#define MMC_ERR_FAILED 4 -#define MMC_ERR_INVALID 5 - -struct mmc_command { - u32 opcode; - u32 arg; - u32 resp[4]; - unsigned int flags; /* expected response type */ - struct mmc_data *data; /* data segment associated with cmd */ - struct mmc_request *mrq; /* associated request */ - unsigned int retries; /* max number of retries */ - unsigned int error; /* command error */ - -}; - -struct mmc_data { - unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */ - unsigned int timeout_clks; /* data timeout (in clocks) */ - unsigned int blksz_bits; /* data block size */ - unsigned int blksz; /* data block size */ - unsigned int blocks; /* number of blocks */ - unsigned int error; /* data error */ - unsigned int flags; - -#define MMC_DATA_WRITE (1 << 8) -#define MMC_DATA_READ (1 << 9) -#define MMC_DATA_STREAM (1 << 10) -#define MMC_DATA_MULTI (1 << 11) - - unsigned int bytes_xfered; - - struct mmc_command *stop; /* stop command */ - struct mmc_request *mrq; /* associated request */ - - unsigned int sg_len; /* size of scatter list */ - struct scatterlist *sg; /* I/O scatter list */ -}; - -struct mmc_request { - struct mmc_command *cmd; - struct mmc_data *data; - struct mmc_command *stop; - - void *done_data; /* completion data */ - void (*done)(struct mmc_request *);/* completion function */ -}; - -struct mmc_host; -struct mmc_card; - -extern int mmc_wait_for_req(struct mmc_host *, struct mmc_request *); -extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int); -extern int mmc_wait_for_app_cmd(struct mmc_host *, unsigned int, - struct mmc_command *, int); - -extern int __mmc_claim_host(struct mmc_host *host, struct mmc_card *card); - -static inline void mmc_claim_host(struct mmc_host *host) -{ - __mmc_claim_host(host, (struct mmc_card *)-1); -} - -extern void mmc_release_host(struct mmc_host *host); - -#endif diff --git a/qiboot/include/mmc.h b/qiboot/include/mmc.h deleted file mode 100644 index 1a81f2a..0000000 --- a/qiboot/include/mmc.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * linux/drivers/mmc/mmc_pxa.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_PXA_P_H__ -#define __MMC_PXA_P_H__ - -#define MMC_DEFAULT_RCA (1<<16) - -#define MMC_BLOCK_SIZE 512 -#define MMC_CMD_RESET 0 -#define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 -#define MMC_CMD_SET_RCA 3 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 -#define MMC_CMD_SEND_STATUS 13 -#define MMC_CMD_SET_BLOCKLEN 16 -#define MMC_CMD_READ_BLOCK 17 -#define MMC_CMD_RD_BLK_MULTI 18 -#define MMC_CMD_WRITE_BLOCK 24 - -#define MMC_MAX_BLOCK_SIZE 512 - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -typedef struct mmc_cid -{ - /* FIXME: BYTE_ORDER */ - u8 year:4, - month:4; - u8 sn[3]; - u8 fwrev:4, - hwrev:4; - u8 name[6]; - u8 id[3]; -} mmc_cid_t; - -typedef struct mmc_csd -{ - u8 ecc:2, - file_format:2, - tmp_write_protect:1, - perm_write_protect:1, - copy:1, - file_format_grp:1; - unsigned long long content_prot_app:1, - rsvd3:4, - write_bl_partial:1, - write_bl_len:4, - r2w_factor:3, - default_ecc:2, - wp_grp_enable:1, - wp_grp_size:5, - erase_grp_mult:5, - erase_grp_size:5, - c_size_mult1:3, - vdd_w_curr_max:3, - vdd_w_curr_min:3, - vdd_r_curr_max:3, - vdd_r_curr_min:3, - c_size:12, - rsvd2:2, - dsr_imp:1, - read_blk_misalign:1, - write_blk_misalign:1, - read_bl_partial:1; - - u16 read_bl_len:4, - ccc:12; - u8 tran_speed; - u8 nsac; - u8 taac; - u8 rsvd1:2, - spec_vers:4, - csd_structure:2; -} mmc_csd_t; - - -#endif /* __MMC_PXA_P_H__ */ diff --git a/qiboot/include/neo_gta01.h b/qiboot/include/neo_gta01.h deleted file mode 100644 index 6b4b174..0000000 --- a/qiboot/include/neo_gta01.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -#ifndef __ASM_MODE__ -#include -extern const struct board_api board_api_gta01; -#endif - -#define TEXT_BASE 0x33000000 - -#endif /* __CONFIG_H */ diff --git a/qiboot/include/neo_gta02.h b/qiboot/include/neo_gta02.h deleted file mode 100644 index 7492630..0000000 --- a/qiboot/include/neo_gta02.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -#ifndef __ASM_MODE__ -#include -extern const struct board_api board_api_gta02; -#endif - -#define TEXT_BASE 0x33000000 - -#endif /* __CONFIG_H */ diff --git a/qiboot/include/neo_om_3d7k.h b/qiboot/include/neo_om_3d7k.h deleted file mode 100644 index 141b390..0000000 --- a/qiboot/include/neo_om_3d7k.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_MODE__ -#include -extern const struct board_api board_api_om_3d7k; -#endif - -#define TEXT_BASE_OM_3D7K 0x53000000 diff --git a/qiboot/include/neo_smdk6410.h b/qiboot/include/neo_smdk6410.h deleted file mode 100644 index a438170..0000000 --- a/qiboot/include/neo_smdk6410.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_MODE__ -#include -extern const struct board_api board_api_smdk6410; -#endif - -#define TEXT_BASE_SMDK6410 0x53000000 diff --git a/qiboot/include/pcf50606.h b/qiboot/include/pcf50606.h deleted file mode 100644 index b0a1807..0000000 --- a/qiboot/include/pcf50606.h +++ /dev/null @@ -1,260 +0,0 @@ -#ifndef _PCF50606_H -#define _PCF50606_H - -/* Philips PCF50606 Power Managemnt Unit (PMU) driver - * (C) 2006-2007 by OpenMoko, Inc. - * Author: Harald Welte - * - */ - -enum pfc50606_regs { - PCF50606_REG_ID = 0x00, - PCF50606_REG_OOCS = 0x01, - PCF50606_REG_INT1 = 0x02, /* Interrupt Status */ - PCF50606_REG_INT2 = 0x03, /* Interrupt Status */ - PCF50606_REG_INT3 = 0x04, /* Interrupt Status */ - PCF50606_REG_INT1M = 0x05, /* Interrupt Mask */ - PCF50606_REG_INT2M = 0x06, /* Interrupt Mask */ - PCF50606_REG_INT3M = 0x07, /* Interrupt Mask */ - PCF50606_REG_OOCC1 = 0x08, - PCF50606_REG_OOCC2 = 0x09, - PCF50606_REG_RTCSC = 0x0a, /* Second */ - PCF50606_REG_RTCMN = 0x0b, /* Minute */ - PCF50606_REG_RTCHR = 0x0c, /* Hour */ - PCF50606_REG_RTCWD = 0x0d, /* Weekday */ - PCF50606_REG_RTCDT = 0x0e, /* Day */ - PCF50606_REG_RTCMT = 0x0f, /* Month */ - PCF50606_REG_RTCYR = 0x10, /* Year */ - PCF50606_REG_RTCSCA = 0x11, /* Alarm Second */ - PCF50606_REG_RTCMNA = 0x12, /* Alarm Minute */ - PCF50606_REG_RTCHRA = 0x13, /* Alarm Hour */ - PCF50606_REG_RTCWDA = 0x14, /* Alarm Weekday */ - PCF50606_REG_RTCDTA = 0x15, /* Alarm Day */ - PCF50606_REG_RTCMTA = 0x16, /* Alarm Month */ - PCF50606_REG_RTCYRA = 0x17, /* Alarm Year */ - PCF50606_REG_PSSC = 0x18, /* Power sequencing */ - PCF50606_REG_PWROKM = 0x19, /* PWROK mask */ - PCF50606_REG_PWROKS = 0x1a, /* PWROK status */ - PCF50606_REG_DCDC1 = 0x1b, - PCF50606_REG_DCDC2 = 0x1c, - PCF50606_REG_DCDC3 = 0x1d, - PCF50606_REG_DCDC4 = 0x1e, - PCF50606_REG_DCDEC1 = 0x1f, - PCF50606_REG_DCDEC2 = 0x20, - PCF50606_REG_DCUDC1 = 0x21, - PCF50606_REG_DCUDC2 = 0x22, - PCF50606_REG_IOREGC = 0x23, - PCF50606_REG_D1REGC1 = 0x24, - PCF50606_REG_D2REGC1 = 0x25, - PCF50606_REG_D3REGC1 = 0x26, - PCF50606_REG_LPREGC1 = 0x27, - PCF50606_REG_LPREGC2 = 0x28, - PCF50606_REG_MBCC1 = 0x29, - PCF50606_REG_MBCC2 = 0x2a, - PCF50606_REG_MBCC3 = 0x2b, - PCF50606_REG_MBCS1 = 0x2c, - PCF50606_REG_BBCC = 0x2d, - PCF50606_REG_ADCC1 = 0x2e, - PCF50606_REG_ADCC2 = 0x2f, - PCF50606_REG_ADCS1 = 0x30, - PCF50606_REG_ADCS2 = 0x31, - PCF50606_REG_ADCS3 = 0x32, - PCF50606_REG_ACDC1 = 0x33, - PCF50606_REG_BVMC = 0x34, - PCF50606_REG_PWMC1 = 0x35, - PCF50606_REG_LEDC1 = 0x36, - PCF50606_REG_LEDC2 = 0x37, - PCF50606_REG_GPOC1 = 0x38, - PCF50606_REG_GPOC2 = 0x39, - PCF50606_REG_GPOC3 = 0x3a, - PCF50606_REG_GPOC4 = 0x3b, - PCF50606_REG_GPOC5 = 0x3c, - __NUM_PCF50606_REGS -}; - -enum pcf50606_reg_oocs { - PFC50606_OOCS_ONKEY = 0x01, - PCF50606_OOCS_EXTON = 0x02, - PCF50606_OOCS_PWROKRST = 0x04, - PCF50606_OOCS_BATOK = 0x08, - PCF50606_OOCS_BACKOK = 0x10, - PCF50606_OOCS_CHGOK = 0x20, - PCF50606_OOCS_TEMPOK = 0x40, - PCF50606_OOCS_WDTEXP = 0x80, -}; - -enum pcf50606_reg_oocc1 { - PCF50606_OOCC1_GOSTDBY = 0x01, - PCF50606_OOCC1_TOTRST = 0x02, - PCF50606_OOCC1_CLK32ON = 0x04, - PCF50606_OOCC1_WDTRST = 0x08, - PCF50606_OOCC1_RTCWAK = 0x10, - PCF50606_OOCC1_CHGWAK = 0x20, - PCF50606_OOCC1_EXTONWAK_HIGH = 0x40, - PCF50606_OOCC1_EXTONWAK_LOW = 0x80, - PCF50606_OOCC1_EXTONWAK_NO_WAKEUP = 0x3f, -}; - -enum pcf50606_reg_oocc2 { - PCF50606_OOCC2_ONKEYDB_NONE = 0x00, - PCF50606_OOCC2_ONKEYDB_14ms = 0x01, - PCF50606_OOCC2_ONKEYDB_62ms = 0x02, - PCF50606_OOCC2_ONKEYDB_500ms = 0x03, - PCF50606_OOCC2_EXTONDB_NONE = 0x00, - PCF50606_OOCC2_EXTONDB_14ms = 0x04, - PCF50606_OOCC2_EXTONDB_62ms = 0x08, - PCF50606_OOCC2_EXTONDB_500ms = 0x0c, -}; - -enum pcf50606_reg_int1 { - PCF50606_INT1_ONKEYR = 0x01, /* ONKEY rising edge */ - PCF50606_INT1_ONKEYF = 0x02, /* ONKEY falling edge */ - PCF50606_INT1_ONKEY1S = 0x04, /* OMKEY at least 1sec low */ - PCF50606_INT1_EXTONR = 0x08, /* EXTON rising edge */ - PCF50606_INT1_EXTONF = 0x10, /* EXTON falling edge */ - PCF50606_INT1_SECOND = 0x40, /* RTC periodic second interrupt */ - PCF50606_INT1_ALARM = 0x80, /* RTC alarm time is reached */ -}; - -enum pcf50606_reg_int2 { - PCF50606_INT2_CHGINS = 0x01, /* Charger inserted */ - PCF50606_INT2_CHGRM = 0x02, /* Charger removed */ - PCF50606_INT2_CHGFOK = 0x04, /* Fast charging OK */ - PCF50606_INT2_CHGERR = 0x08, /* Error in charging mode */ - PCF50606_INT2_CHGFRDY = 0x10, /* Fast charge completed */ - PCF50606_INT2_CHGPROT = 0x20, /* Charging protection interrupt */ - PCF50606_INT2_CHGWD10S = 0x40, /* Charger watchdig expires in 10s */ - PCF50606_INT2_CHGWDEXP = 0x80, /* Charger watchdog expires */ -}; - -enum pcf50606_reg_int3 { - PCF50606_INT3_ADCRDY = 0x01, /* ADC conversion finished */ - PCF50606_INT3_ACDINS = 0x02, /* Accessory inserted */ - PCF50606_INT3_ACDREM = 0x04, /* Accessory removed */ - PCF50606_INT3_TSCPRES = 0x08, /* Touch screen pressed */ - PCF50606_INT3_LOWBAT = 0x40, /* Low battery voltage */ - PCF50606_INT3_HIGHTMP = 0x80, /* High temperature */ -}; - -/* used by PSSC, PWROKM, PWROKS, */ -enum pcf50606_regu { - PCF50606_REGU_DCD = 0x01, /* DCD in phase 2 */ - PCF50606_REGU_DCDE = 0x02, /* DCDE in phase 2 */ - PCF50606_REGU_DCUD = 0x04, /* DCDU in phase 2 */ - PCF50606_REGU_IO = 0x08, /* IO in phase 2 */ - PCF50606_REGU_D1 = 0x10, /* D1 in phase 2 */ - PCF50606_REGU_D2 = 0x20, /* D2 in phase 2 */ - PCF50606_REGU_D3 = 0x40, /* D3 in phase 2 */ - PCF50606_REGU_LP = 0x80, /* LP in phase 2 */ -}; - -enum pcf50606_reg_dcdc4 { - PCF50606_DCDC4_MODE_AUTO = 0x00, - PCF50606_DCDC4_MODE_PWM = 0x01, - PCF50606_DCDC4_MODE_PCF = 0x02, - PCF50606_DCDC4_OFF_FLOAT = 0x00, - PCF50606_DCDC4_OFF_BYPASS = 0x04, - PCF50606_DCDC4_OFF_PULLDOWN = 0x08, - PCF50606_DCDC4_CURLIM_500mA = 0x00, - PCF50606_DCDC4_CURLIM_750mA = 0x10, - PCF50606_DCDC4_CURLIM_1000mA = 0x20, - PCF50606_DCDC4_CURLIM_1250mA = 0x30, - PCF50606_DCDC4_TOGGLE = 0x40, - PCF50606_DCDC4_REGSEL_DCDC2 = 0x80, -}; - -enum pcf50606_reg_dcdec2 { - PCF50606_DCDEC2_MODE_AUTO = 0x00, - PCF50606_DCDEC2_MODE_PWM = 0x01, - PCF50606_DCDEC2_MODE_PCF = 0x02, - PCF50606_DCDEC2_OFF_FLOAT = 0x00, - PCF50606_DCDEC2_OFF_BYPASS = 0x04, -}; - -enum pcf50606_reg_dcudc2 { - PCF50606_DCUDC2_MODE_AUTO = 0x00, - PCF50606_DCUDC2_MODE_PWM = 0x01, - PCF50606_DCUDC2_MODE_PCF = 0x02, - PCF50606_DCUDC2_OFF_FLOAT = 0x00, - PCF50606_DCUDC2_OFF_BYPASS = 0x04, -}; - -enum pcf50606_reg_adcc1 { - PCF50606_ADCC1_TSCMODACT = 0x01, - PCF50606_ADCC1_TSCMODSTB = 0x02, - PCF50606_ADCC1_TRATSET = 0x04, - PCF50606_ADCC1_NTCSWAPE = 0x08, - PCF50606_ADCC1_NTCSWAOFF = 0x10, - PCF50606_ADCC1_EXTSYNCBREAK = 0x20, - /* reserved */ - PCF50606_ADCC1_TSCINT = 0x80, -}; - -enum pcf50606_reg_adcc2 { - PCF50606_ADCC2_ADCSTART = 0x01, - /* see enum pcf50606_adcc2_adcmux */ - PCF50606_ADCC2_SYNC_NONE = 0x00, - PCF50606_ADCC2_SYNC_TXON = 0x20, - PCF50606_ADCC2_SYNC_PWREN1 = 0x40, - PCF50606_ADCC2_SYNC_PWREN2 = 0x60, - PCF50606_ADCC2_RES_10BIT = 0x00, - PCF50606_ADCC2_RES_8BIT = 0x80, -}; - -#define PCF50606_ADCC2_ADCMUX_MASK (0xf << 1) - -#define ADCMUX_SHIFT 1 -enum pcf50606_adcc2_adcmux { - PCF50606_ADCMUX_BATVOLT_RES = 0x0 << ADCMUX_SHIFT, - PCF50606_ADCMUX_BATVOLT_SUBTR = 0x1 << ADCMUX_SHIFT, - PCF50606_ADCMUX_ADCIN1_RES = 0x2 << ADCMUX_SHIFT, - PCF50606_ADCMUX_ADCIN1_SUBTR = 0x3 << ADCMUX_SHIFT, - PCF50606_ADCMUX_BATTEMP = 0x4 << ADCMUX_SHIFT, - PCF50606_ADCMUX_ADCIN2 = 0x5 << ADCMUX_SHIFT, - PCF50606_ADCMUX_ADCIN3 = 0x6 << ADCMUX_SHIFT, - PCF50606_ADCMUX_ADCIN3_RATIO = 0x7 << ADCMUX_SHIFT, - PCF50606_ADCMUX_XPOS = 0x8 << ADCMUX_SHIFT, - PCF50606_ADCMUX_YPOS = 0x9 << ADCMUX_SHIFT, - PCF50606_ADCMUX_P1 = 0xa << ADCMUX_SHIFT, - PCF50606_ADCMUX_P2 = 0xb << ADCMUX_SHIFT, - PCF50606_ADCMUX_BATVOLT_ADCIN1 = 0xc << ADCMUX_SHIFT, - PCF50606_ADCMUX_XY_SEQUENCE = 0xe << ADCMUX_SHIFT, - PCF50606_P1_P2_RESISTANCE = 0xf << ADCMUX_SHIFT, -}; - -enum pcf50606_adcs2 { - PCF50606_ADCS2_ADCRDY = 0x80, -}; - -enum pcf50606_reg_mbcc1 { - PCF50606_MBCC1_CHGAPE = 0x01, - PCF50606_MBCC1_AUTOFST = 0x02, -#define PCF50606_MBCC1_CHGMOD_MASK 0x1c -#define PCF50606_MBCC1_CHGMOD_SHIFT 2 - PCF50606_MBCC1_CHGMOD_QUAL = 0x00, - PCF50606_MBCC1_CHGMOD_PRE = 0x04, - PCF50606_MBCC1_CHGMOD_TRICKLE = 0x08, - PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c, - PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10, - PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14, - PCF50606_MBCC1_CHGMOD_FAST_SW = 0x18, - PCF50606_MBCC1_CHGMOD_IDLE = 0x1c, - PCF50606_MBCC1_DETMOD_LOWCHG = 0x20, - PCF50606_MBCC1_DETMOD_WDRST = 0x40, -}; - -enum pcf50606_reg_bvmc { - PCF50606_BVMC_LOWBAT = 0x01, - PCF50606_BVMC_THRSHLD_NULL = 0x00, - PCF50606_BVMC_THRSHLD_2V8 = 0x02, - PCF50606_BVMC_THRSHLD_2V9 = 0x04, - PCF50606_BVMC_THRSHLD_3V = 0x08, - PCF50606_BVMC_THRSHLD_3V1 = 0x08, - PCF50606_BVMC_THRSHLD_3V2 = 0x0a, - PCF50606_BVMC_THRSHLD_3V3 = 0x0c, - PCF50606_BVMC_THRSHLD_3V4 = 0x0e, - PCF50606_BVMC_DISDB = 0x10, -}; - -#endif /* _PCF50606_H */ - diff --git a/qiboot/include/pcf50633.h b/qiboot/include/pcf50633.h deleted file mode 100644 index 51da119..0000000 --- a/qiboot/include/pcf50633.h +++ /dev/null @@ -1,392 +0,0 @@ -#ifndef _PCF50633_H -#define _PCF50633_H - -/* Philips PCF50633 Power Managemnt Unit (PMU) driver - * (C) 2006-2007 by OpenMoko, Inc. - * Author: Harald Welte - * - */ - -enum pfc50633_regs { - PCF50633_REG_VERSION = 0x00, - PCF50633_REG_VARIANT = 0x01, - PCF50633_REG_INT1 = 0x02, /* Interrupt Status */ - PCF50633_REG_INT2 = 0x03, /* Interrupt Status */ - PCF50633_REG_INT3 = 0x04, /* Interrupt Status */ - PCF50633_REG_INT4 = 0x05, /* Interrupt Status */ - PCF50633_REG_INT5 = 0x06, /* Interrupt Status */ - PCF50633_REG_INT1M = 0x07, /* Interrupt Mask */ - PCF50633_REG_INT2M = 0x08, /* Interrupt Mask */ - PCF50633_REG_INT3M = 0x09, /* Interrupt Mask */ - PCF50633_REG_INT4M = 0x0a, /* Interrupt Mask */ - PCF50633_REG_INT5M = 0x0b, /* Interrupt Mask */ - PCF50633_REG_OOCSHDWN = 0x0c, - PCF50633_REG_OOCWAKE = 0x0d, - PCF50633_REG_OOCTIM1 = 0x0e, - PCF50633_REG_OOCTIM2 = 0x0f, - PCF50633_REG_OOCMODE = 0x10, - PCF50633_REG_OOCCTL = 0x11, - PCF50633_REG_OOCSTAT = 0x12, - PCF50633_REG_GPIOCTL = 0x13, - PCF50633_REG_GPIO1CFG = 0x14, - PCF50633_REG_GPIO2CFG = 0x15, - PCF50633_REG_GPIO3CFG = 0x16, - PCF50633_REG_GPOCFG = 0x17, - PCF50633_REG_BVMCTL = 0x18, - PCF50633_REG_SVMCTL = 0x19, - PCF50633_REG_AUTOOUT = 0x1a, - PCF50633_REG_AUTOENA = 0x1b, - PCF50633_REG_AUTOCTL = 0x1c, - PCF50633_REG_AUTOMXC = 0x1d, - PCF50633_REG_DOWN1OUT = 0x1e, - PCF50633_REG_DOWN1ENA = 0x1f, - PCF50633_REG_DOWN1CTL = 0x20, - PCF50633_REG_DOWN1MXC = 0x21, - PCF50633_REG_DOWN2OUT = 0x22, - PCF50633_REG_DOWN2ENA = 0x23, - PCF50633_REG_DOWN2CTL = 0x24, - PCF50633_REG_DOWN2MXC = 0x25, - PCF50633_REG_MEMLDOOUT = 0x26, - PCF50633_REG_MEMLDOENA = 0x27, - PCF50633_REG_LEDOUT = 0x28, - PCF50633_REG_LEDENA = 0x29, - PCF50633_REG_LEDCTL = 0x2a, - PCF50633_REG_LEDDIM = 0x2b, - /* reserved */ - PCF50633_REG_LDO1OUT = 0x2d, - PCF50633_REG_LDO1ENA = 0x2e, - PCF50633_REG_LDO2OUT = 0x2f, - PCF50633_REG_LDO2ENA = 0x30, - PCF50633_REG_LDO3OUT = 0x31, - PCF50633_REG_LDO3ENA = 0x32, - PCF50633_REG_LDO4OUT = 0x33, - PCF50633_REG_LDO4ENA = 0x34, - PCF50633_REG_LDO5OUT = 0x35, - PCF50633_REG_LDO5ENA = 0x36, - PCF50633_REG_LDO6OUT = 0x37, - PCF50633_REG_LDO6ENA = 0x38, - PCF50633_REG_HCLDOOUT = 0x39, - PCF50633_REG_HCLDOENA = 0x3a, - PCF50633_REG_STBYCTL1 = 0x3b, - PCF50633_REG_STBYCTL2 = 0x3c, - PCF50633_REG_DEBPF1 = 0x3d, - PCF50633_REG_DEBPF2 = 0x3e, - PCF50633_REG_DEBPF3 = 0x3f, - PCF50633_REG_HCLDOOVL = 0x40, - PCF50633_REG_DCDCSTAT = 0x41, - PCF50633_REG_LDOSTAT = 0x42, - PCF50633_REG_MBCC1 = 0x43, - PCF50633_REG_MBCC2 = 0x44, - PCF50633_REG_MBCC3 = 0x45, - PCF50633_REG_MBCC4 = 0x46, - PCF50633_REG_MBCC5 = 0x47, - PCF50633_REG_MBCC6 = 0x48, - PCF50633_REG_MBCC7 = 0x49, - PCF50633_REG_MBCC8 = 0x4a, - PCF50633_REG_MBCS1 = 0x4b, - PCF50633_REG_MBCS2 = 0x4c, - PCF50633_REG_MBCS3 = 0x4d, - PCF50633_REG_BBCCTL = 0x4e, - PCF50633_REG_ALMGAIN = 0x4f, - PCF50633_REG_ALMDATA = 0x50, - /* reserved */ - PCF50633_REG_ADCC3 = 0x52, - PCF50633_REG_ADCC2 = 0x53, - PCF50633_REG_ADCC1 = 0x54, - PCF50633_REG_ADCS1 = 0x55, - PCF50633_REG_ADCS2 = 0x56, - PCF50633_REG_ADCS3 = 0x57, - /* reserved */ - PCF50633_REG_RTCSC = 0x59, /* Second */ - PCF50633_REG_RTCMN = 0x5a, /* Minute */ - PCF50633_REG_RTCHR = 0x5b, /* Hour */ - PCF50633_REG_RTCWD = 0x5c, /* Weekday */ - PCF50633_REG_RTCDT = 0x5d, /* Day */ - PCF50633_REG_RTCMT = 0x5e, /* Month */ - PCF50633_REG_RTCYR = 0x5f, /* Year */ - PCF50633_REG_RTCSCA = 0x60, /* Alarm Second */ - PCF50633_REG_RTCMNA = 0x61, /* Alarm Minute */ - PCF50633_REG_RTCHRA = 0x62, /* Alarm Hour */ - PCF50633_REG_RTCWDA = 0x63, /* Alarm Weekday */ - PCF50633_REG_RTCDTA = 0x64, /* Alarm Day */ - PCF50633_REG_RTCMTA = 0x65, /* Alarm Month */ - PCF50633_REG_RTCYRA = 0x66, /* Alarm Year */ - - PCF50633_REG_MEMBYTE0 = 0x67, - PCF50633_REG_MEMBYTE1 = 0x68, - PCF50633_REG_MEMBYTE2 = 0x69, - PCF50633_REG_MEMBYTE3 = 0x6a, - PCF50633_REG_MEMBYTE4 = 0x6b, - PCF50633_REG_MEMBYTE5 = 0x6c, - PCF50633_REG_MEMBYTE6 = 0x6d, - PCF50633_REG_MEMBYTE7 = 0x6e, - /* reserved */ - PCF50633_REG_DCDCPFM = 0x84, - __NUM_PCF50633_REGS -}; - -enum pcf50633_reg_int1 { - PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ - PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ - PCF50633_INT1_USBINS = 0x04, /* USB inserted */ - PCF50633_INT1_USBREM = 0x08, /* USB removed */ - /* reserved */ - PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ - PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ -}; - -enum pcf50633_reg_int2 { - PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ - PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ - PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ - PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ - PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ - PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ - PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ - PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ -}; - -enum pcf50633_reg_int3 { - PCF50633_INT3_BATFULL = 0x01, /* Battery full */ - PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ - PCF50633_INT3_THLIMON = 0x04, - PCF50633_INT3_THLIMOFF = 0x08, - PCF50633_INT3_USBLIMON = 0x10, - PCF50633_INT3_USBLIMOFF = 0x20, - PCF50633_INT3_ADCRDY = 0x40, /* ADC conversion finished */ - PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ -}; - -enum pcf50633_reg_int4 { - PCF50633_INT4_LOWSYS = 0x01, - PCF50633_INT4_LOWBAT = 0x02, - PCF50633_INT4_HIGHTMP = 0x04, - PCF50633_INT4_AUTOPWRFAIL = 0x08, - PCF50633_INT4_DWN1PWRFAIL = 0x10, - PCF50633_INT4_DWN2PWRFAIL = 0x20, - PCF50633_INT4_LEDPWRFAIL = 0x40, - PCF50633_INT4_LEDOVP = 0x80, -}; - -enum pcf50633_reg_int5 { - PCF50633_INT4_LDO1PWRFAIL = 0x01, - PCF50633_INT4_LDO2PWRFAIL = 0x02, - PCF50633_INT4_LDO3PWRFAIL = 0x04, - PCF50633_INT4_LDO4PWRFAIL = 0x08, - PCF50633_INT4_LDO5PWRFAIL = 0x10, - PCF50633_INT4_LDO6PWRFAIL = 0x20, - PCF50633_INT4_HCLDOPWRFAIL = 0x40, - PCF50633_INT4_HCLDOOVL = 0x80, -}; - -enum pcf50633_reg_oocwake { - PCF50633_OOCWAKE_ONKEY = 0x01, - PCF50633_OOCWAKE_EXTON1 = 0x02, - PCF50633_OOCWAKE_EXTON2 = 0x04, - PCF50633_OOCWAKE_EXTON3 = 0x08, - PCF50633_OOCWAKE_RTC = 0x10, - /* reserved */ - PCF50633_OOCWAKE_USB = 0x40, - PCF50633_OOCWAKE_ADP = 0x80, -}; - -enum pcf50633_reg_mbcc1 { - PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */ - PCF50633_MBCC1_AUTOSTOP = 0x02, - PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */ - PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */ - PCF50633_MBCC1_RESTART = 0x10, /* restart charging */ - PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */ - PCF50633_MBCC1_WDTIME_1H = 0x00, - PCF50633_MBCC1_WDTIME_2H = 0x40, - PCF50633_MBCC1_WDTIME_4H = 0x80, - PCF50633_MBCC1_WDTIME_6H = 0xc0, -}; -#define PCF50633_MBCC1_WDTIME_MASK 0xc0 - -enum pcf50633_reg_mbcc2 { - PCF50633_MBCC2_VBATCOND_2V7 = 0x00, - PCF50633_MBCC2_VBATCOND_2V85 = 0x01, - PCF50633_MBCC2_VBATCOND_3V = 0x02, - PCF50633_MBCC2_VBATCOND_3V15 = 0x03, - PCF50633_MBCC2_VMAX_4V = 0x00, - PCF50633_MBCC2_VMAX_4V20 = 0x28, - PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */ -}; -#define PCF50633_MBCC2_VBATCOND_MASK 0x03 -#define PCF50633_MBCC2_VMAX_MASK 0x3c - -#define PCF50633_OOCSTAT_ONKEY 0x01 - - -enum pcf50633_reg_adcc1 { - PCF50633_ADCC1_ADCSTART = 0x01, - PCF50633_ADCC1_RES_10BIT = 0x02, - PCF50633_ADCC1_AVERAGE_NO = 0x00, - PCF50633_ADCC1_AVERAGE_4 = 0x04, - PCF50633_ADCC1_AVERAGE_8 = 0x08, - PCF50633_ADCC1_AVERAGE_16 = 0x0c, - - PCF50633_ADCC1_MUX_BATSNS_RES = 0x00, - PCF50633_ADCC1_MUX_BATSNS_SUBTR = 0x10, - PCF50633_ADCC1_MUX_ADCIN2_RES = 0x20, - PCF50633_ADCC1_MUX_ADCIN2_SUBTR = 0x30, - PCF50633_ADCC1_MUX_BATTEMP = 0x60, - PCF50633_ADCC1_MUX_ADCIN1 = 0x70, -}; -#define PCF50633_ADCC1_AVERAGE_MASK 0x0c -#define PCF50633_ADCC1_ADCMUX_MASK 0xf0 - -enum pcf50633_reg_adcc2 { - PCF50633_ADCC2_RATIO_NONE = 0x00, - PCF50633_ADCC2_RATIO_BATTEMP = 0x01, - PCF50633_ADCC2_RATIO_ADCIN1 = 0x02, - PCF50633_ADCC2_RATIO_BOTH = 0x03, - PCF50633_ADCC2_RATIOSETTL_100US = 0x04, -}; -#define PCF50633_ADCC2_RATIO_MASK 0x03 - -enum pcf50633_reg_adcc3 { - PCF50633_ADCC3_ACCSW_EN = 0x01, - PCF50633_ADCC3_NTCSW_EN = 0x04, - PCF50633_ADCC3_RES_DIV_TWO = 0x10, - PCF50633_ADCC3_RES_DIV_THREE = 0x00, -}; - -enum pcf50633_reg_adcs3 { - PCF50633_ADCS3_REF_NTCSW = 0x00, - PCF50633_ADCS3_REF_ACCSW = 0x10, - PCF50633_ADCS3_REF_2V0 = 0x20, - PCF50633_ADCS3_REF_VISA = 0x30, - PCF50633_ADCS3_REF_2V0_2 = 0x70, - PCF50633_ADCS3_ADCRDY = 0x80, -}; -#define PCF50633_ADCS3_ADCDAT1L_MASK 0x03 -#define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c -#define PCF50633_ADCS3_ADCDAT2L_SHIFT 2 -#define PCF50633_ASCS3_REF_MASK 0x70 - -enum pcf50633_regulator_enable { - PCF50633_REGULATOR_ON = 0x01, - PCF50633_REGULATOR_ON_GPIO1 = 0x02, - PCF50633_REGULATOR_ON_GPIO2 = 0x04, - PCF50633_REGULATOR_ON_GPIO3 = 0x08, -}; -#define PCF50633_REGULATOR_ON_MASK 0x0f - -enum pcf50633_regulator_phase { - PCF50633_REGULATOR_ACTPH1 = 0x00, - PCF50633_REGULATOR_ACTPH2 = 0x10, - PCF50633_REGULATOR_ACTPH3 = 0x20, - PCF50633_REGULATOR_ACTPH4 = 0x30, -}; -#define PCF50633_REGULATOR_ACTPH_MASK 0x30 - -enum pcf50633_reg_gpocfg { - PCF50633_GPOCFG_GPOSEL_0 = 0x00, - PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01, - PCF50633_GPOCFG_GPOSEL_SYSxOK = 0x02, - PCF50633_GPOCFG_GPOSEL_CLK32K = 0x03, - PCF50633_GPOCFG_GPOSEL_ADAPUSB = 0x04, - PCF50633_GPOCFG_GPOSEL_USBxOK = 0x05, - PCF50633_GPOCFG_GPOSEL_ACTPH4 = 0x06, - PCF50633_GPOCFG_GPOSEL_1 = 0x07, - PCF50633_GPOCFG_GPOSEL_INVERSE = 0x08, -}; -#define PCF50633_GPOCFG_GPOSEL_MASK 0x07 - -#if 0 -enum pcf50633_reg_mbcc1 { - PCF50633_MBCC1_CHGENA = 0x01, - PCF50633_MBCC1_AUTOSTOP = 0x02, - PCF50633_MBCC1_AUTORES = 0x04, - PCF50633_MBCC1_RESUME = 0x08, - PCF50633_MBCC1_RESTART = 0x10, - PCF50633_MBCC1_PREWDTIME_30MIN = 0x00, - PCF50633_MBCC1_PREWDTIME_60MIN = 0x20, - PCF50633_MBCC1_WDTIME_2HRS = 0x40, - PCF50633_MBCC1_WDTIME_4HRS = 0x80, - PCF50633_MBCC1_WDTIME_6HRS = 0xc0, -}; - -enum pcf50633_reg_mbcc2 { - PCF50633_MBCC2_VBATCOND_2V7 = 0x00, - PCF50633_MBCC2_VBATCOND_2V85 = 0x01, - PCF50633_MBCC2_VBATCOND_3V0 = 0x02, - PCF50633_MBCC2_VBATCOND_3V15 = 0x03, - PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, -}; -#define PCF50633_MBCC2_VMAX_MASK 0x3c -#endif - -enum pcf50633_reg_mbcc7 { - PCF50633_MBCC7_USB_100mA = 0x00, - PCF50633_MBCC7_USB_500mA = 0x01, - PCF50633_MBCC7_USB_1000mA = 0x02, - PCF50633_MBCC7_USB_SUSPEND = 0x03, - PCF50633_MBCC7_BATTEMP_EN = 0x04, - PCF50633_MBCC7_BATSYSIMAX_1A6 = 0x00, - PCF50633_MBCC7_BATSYSIMAX_1A8 = 0x40, - PCF50633_MBCC7_BATSYSIMAX_2A0 = 0x80, - PCF50633_MBCC7_BATSYSIMAX_2A2 = 0xc0, -}; -#define PCF56033_MBCC7_USB_MASK 0x03 - -enum pcf50633_reg_mbcc8 { - PCF50633_MBCC8_USBENASUS = 0x10, -}; - -enum pcf50633_reg_mbcs1 { - PCF50633_MBCS1_USBPRES = 0x01, - PCF50633_MBCS1_USBOK = 0x02, - PCF50633_MBCS1_ADAPTPRES = 0x04, - PCF50633_MBCS1_ADAPTOK = 0x08, - PCF50633_MBCS1_TBAT_OK = 0x00, - PCF50633_MBCS1_TBAT_ABOVE = 0x10, - PCF50633_MBCS1_TBAT_BELOW = 0x20, - PCF50633_MBCS1_TBAT_UNDEF = 0x30, - PCF50633_MBCS1_PREWDTEXP = 0x40, - PCF50633_MBCS1_WDTEXP = 0x80, -}; - -enum pcf50633_reg_mbcs2_mbcmod { - PCF50633_MBCS2_MBC_PLAY = 0x00, - PCF50633_MBCS2_MBC_USB_PRE = 0x01, - PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02, - PCF50633_MBCS2_MBC_USB_FAST = 0x03, - PCF50633_MBCS2_MBC_USB_FAST_WAIT= 0x04, - PCF50633_MBCS2_MBC_USB_SUSPEND = 0x05, - PCF50633_MBCS2_MBC_ADP_PRE = 0x06, - PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07, - PCF50633_MBCS2_MBC_ADP_FAST = 0x08, - PCF50633_MBCS2_MBC_ADP_FAST_WAIT= 0x09, - PCF50633_MBCS2_MBC_BAT_FULL = 0x0a, - PCF50633_MBCS2_MBC_HALT = 0x0b, -}; -#define PCF50633_MBCS2_MBC_MASK 0x0f -enum pcf50633_reg_mbcs2_chgstat { - PCF50633_MBCS2_CHGS_NONE = 0x00, - PCF50633_MBCS2_CHGS_ADAPTER = 0x10, - PCF50633_MBCS2_CHGS_USB = 0x20, - PCF50633_MBCS2_CHGS_BOTH = 0x30, -}; -#define PCF50633_MBCS2_RESSTAT_AUTO 0x40 - -enum pcf50633_reg_mbcs3 { - PCF50633_MBCS3_USBLIM_PLAY = 0x01, - PCF50633_MBCS3_USBLIM_CGH = 0x02, - PCF50633_MBCS3_TLIM_PLAY = 0x04, - PCF50633_MBCS3_TLIM_CHG = 0x08, - PCF50633_MBCS3_ILIM = 0x10, /* 1: Ibat > Icutoff */ - PCF50633_MBCS3_VLIM = 0x20, /* 1: Vbat == Vmax */ - PCF50633_MBCS3_VBATSTAT = 0x40, /* 1: Vbat > Vbatcond */ - PCF50633_MBCS3_VRES = 0x80, /* 1: Vbat > Vth(RES) */ -}; - -struct pcf50633_init { - u8 index; - u8 value; -}; - -#endif /* _PCF50633_H */ - diff --git a/qiboot/include/ports-s3c24xx.h b/qiboot/include/ports-s3c24xx.h deleted file mode 100644 index e784d85..0000000 --- a/qiboot/include/ports-s3c24xx.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef __PORTS_S3C24XX_H__ -#define __PORTS_S3C24XX_H__ - - -// I/O PORT -#define rGPACON (*(volatile unsigned *)0x56000000) -#define rGPADAT (*(volatile unsigned *)0x56000004) - -#define rGPBCON (*(volatile unsigned *)0x56000010) -#define rGPBDAT (*(volatile unsigned *)0x56000014) -#define rGPBUP (*(volatile unsigned *)0x56000018) - -#define rGPCCON (*(volatile unsigned *)0x56000020) -#define rGPCDAT (*(volatile unsigned *)0x56000024) -#define rGPCUP (*(volatile unsigned *)0x56000028) - -#define rGPDCON (*(volatile unsigned *)0x56000030) -#define rGPDDAT (*(volatile unsigned *)0x56000034) -#define rGPDUP (*(volatile unsigned *)0x56000038) - -#define rGPECON (*(volatile unsigned *)0x56000040) -#define rGPEDAT (*(volatile unsigned *)0x56000044) -#define rGPEUP (*(volatile unsigned *)0x56000048) - -#define rGPFCON (*(volatile unsigned *)0x56000050) -#define rGPFDAT (*(volatile unsigned *)0x56000054) -#define rGPFUP (*(volatile unsigned *)0x56000058) - -#define rGPGCON (*(volatile unsigned *)0x56000060) -#define rGPGDAT (*(volatile unsigned *)0x56000064) -#define rGPGUP (*(volatile unsigned *)0x56000068) - -#define rGPHCON (*(volatile unsigned *)0x56000070) -#define rGPHDAT (*(volatile unsigned *)0x56000074) -#define rGPHUP (*(volatile unsigned *)0x56000078) - -#define rGPJCON (*(volatile unsigned *)0x560000d0) //Port J control -#define rGPJDAT (*(volatile unsigned *)0x560000d4) //Port J data -#define rGPJUP (*(volatile unsigned *)0x560000d8) //Port J data - -#endif diff --git a/qiboot/include/qi-ctype.h b/qiboot/include/qi-ctype.h deleted file mode 100644 index ed65522..0000000 --- a/qiboot/include/qi-ctype.h +++ /dev/null @@ -1,45 +0,0 @@ -#define _U 0x01 /* upper */ -#define _L 0x02 /* lower */ -#define _D 0x04 /* digit */ -#define _C 0x08 /* cntrl */ -#define _P 0x10 /* punct */ -#define _S 0x20 /* white space (space/lf/tab) */ -#define _X 0x40 /* hex digit */ -#define _SP 0x80 /* hard space (0x20) */ - -extern unsigned char _ctype[]; - -#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) - -#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) -#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) -#define iscntrl(c) ((__ismask(c)&(_C)) != 0) -#define isdigit(c) ((__ismask(c)&(_D)) != 0) -#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) -#define islower(c) ((__ismask(c)&(_L)) != 0) -#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) -#define ispunct(c) ((__ismask(c)&(_P)) != 0) -#define isspace(c) ((__ismask(c)&(_S)) != 0) -#define isupper(c) ((__ismask(c)&(_U)) != 0) -#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) - -#define isascii(c) (((unsigned char)(c))<=0x7f) -#define toascii(c) (((unsigned char)(c))&0x7f) - -static inline unsigned char __tolower(unsigned char c) -{ - if (isupper(c)) - c -= 'A'-'a'; - return c; -} - -static inline unsigned char __toupper(unsigned char c) -{ - if (islower(c)) - c -= 'a'-'A'; - return c; -} - -#define tolower(c) __tolower(c) -#define toupper(c) __toupper(c) - diff --git a/qiboot/include/qi.h b/qiboot/include/qi.h deleted file mode 100644 index b99695d..0000000 --- a/qiboot/include/qi.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2008 Openmoko, Inc. - * Author: Andy Green - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __QI_H__ -#define __QI_H__ - -#include -#include -#include - -#define MALLOC_POOL_EXTENT (100 * 1024) - -#define u32 unsigned int -#define u16 unsigned short -#define u8 unsigned char -typedef unsigned int uint32_t; -typedef unsigned short uint16_t; -typedef unsigned char uint8_t; - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) - -enum filesystem { - FS_RAW, - FS_FAT, - FS_EXT2 -}; - -enum ui_actions { - UI_ACTION_ADD_DEBUG = (1 << 0), - UI_ACTION_SKIPKERNEL = (1 << 1), -}; - -enum ui_indication { - UI_IND_UPDATE_ONLY, - UI_IND_MOUNT_PART, - UI_IND_MOUNT_FAIL, - UI_IND_SKIPPING, - UI_IND_KERNEL_PULL, - UI_IND_KERNEL_PULL_OK, - UI_IND_KERNEL_PULL_FAIL, - UI_IND_INITRAMFS_PULL, - UI_IND_INITRAMFS_PULL_OK, - UI_IND_INITRAMFS_PULL_FAIL, - UI_IND_KERNEL_START, - UI_IND_MEM_TEST -}; - -/* describes a source for getting kernel image */ - -struct kernel_source { - const char *name; /* NULL name means invalid */ - const char *filepath; - const char *initramfs_filepath; - int (*block_init)(void); - int (*block_read)(unsigned char * buf, unsigned long start512, - int blocks512); - int partition_index; /* -1 means no partition table */ - int offset_blocks512_if_no_partition; /* used if partition_index is -1 */ - enum filesystem filesystem; - const char * commandline_append; -}; - -/* describes a board variant, eg, PCB revision */ - -struct board_variant { - const char * name; - int machine_revision; /* passed in revision tag to linux */ -}; - -/* describes a "board", ie, a device like GTA02 including revisions */ - -struct board_api { - const char * name; - int linux_machine_id; - unsigned long linux_mem_start; - unsigned long linux_mem_size; - unsigned long linux_tag_placement; - const char *commandline_board; - const char *commandline_board_debug; - const char *noboot; - const char *append; - - const struct board_variant const * (*get_board_variant)(void); - int (*is_this_board)(void); - void (*early_port_init)(void); - void (*port_init)(void); - void (*post_serial_init)(void); /* print device-specific things */ - char * (*append_device_specific_cmdline)(char *); - void (*putc)(char); - void (*close)(void); - u8 (*get_ui_keys)(void); - u8 (*get_ui_debug)(void); - void (*set_ui_indication)(enum ui_indication); - - struct kernel_source kernel_source[8]; -}; - -/* this is the board we are running on */ - -extern struct board_api const * this_board; -extern struct kernel_source const * this_kernel; - -int printk(const char *fmt, ...); -int vsprintf(char *buf, const char *fmt, va_list args); -int puts(const char *string); -void printhex(unsigned char v); -void print8(unsigned char u); -void print32(unsigned int u); -void printdec(int n); -void hexdump(unsigned char *start, int len); -void udelay(int n); - -/* phase2 only */ -void setnybble(char *p, unsigned char n); -void set8(char *p, unsigned char n); -void set32(char *p, unsigned int u); - -unsigned long crc32(unsigned long crc, const unsigned char *buf, - unsigned int len); -int nand_read_ll(unsigned char *buf, unsigned long start512, int blocks512); - -extern void memory_test(void * start, unsigned int length); - -void set_putc_func(void (*p)(char)); - -#endif - diff --git a/qiboot/include/s3c24xx-mci.h b/qiboot/include/s3c24xx-mci.h deleted file mode 100644 index 7abeb1f..0000000 --- a/qiboot/include/s3c24xx-mci.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _S3C24XX_MMC_H_ -#define _S3C24XX_MMC_H_ -#include - -int s3c24xx_mmc_init(int verbose); -u32 s3c24xx_mmc_bread(int dev_num, u32 blknr, u32 blkcnt, void *dst); -int s3c24xx_mmc_read(u32 src, u8 *dst, int size); -int s3c24xx_mmc_write(u8 *src, u32 dst, int size); - -#endif /* _MMC_H_ */ diff --git a/qiboot/include/s3c24xx-regs-sdi.h b/qiboot/include/s3c24xx-regs-sdi.h deleted file mode 100644 index 9597542..0000000 --- a/qiboot/include/s3c24xx-regs-sdi.h +++ /dev/null @@ -1,110 +0,0 @@ -/* linux/include/asm/arch-s3c2410/regs-sdi.h - * - * Copyright (c) 2004 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 MMC/SDIO register definitions - * - * Changelog: - * 18-Aug-2004 Ben Dooks Created initial file - * 29-Nov-2004 Koen Martens Added some missing defines, fixed duplicates - * 29-Nov-2004 Ben Dooks Updated Koen's patch -*/ - -#ifndef __ASM_ARM_REGS_SDI -#define __ASM_ARM_REGS_SDI "regs-sdi.h" - -#define S3C2440_SDICON_SDRESET (1<<8) -#define S3C2440_SDICON_MMCCLOCK (1<<5) -#define S3C2410_SDICON_BYTEORDER (1<<4) -#define S3C2410_SDICON_SDIOIRQ (1<<3) -#define S3C2410_SDICON_RWAITEN (1<<2) -#define S3C2410_SDICON_FIFORESET (1<<1) -#define S3C2410_SDICON_CLOCKTYPE (1<<0) - -#define S3C2410_SDICMDCON_ABORT (1<<12) -#define S3C2410_SDICMDCON_WITHDATA (1<<11) -#define S3C2410_SDICMDCON_LONGRSP (1<<10) -#define S3C2410_SDICMDCON_WAITRSP (1<<9) -#define S3C2410_SDICMDCON_CMDSTART (1<<8) -#define S3C2410_SDICMDCON_SENDERHOST (1<<6) -#define S3C2410_SDICMDCON_INDEX (0x3f) - -#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) -#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) -#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) -#define S3C2410_SDICMDSTAT_RSPFIN (1<<9) -#define S3C2410_SDICMDSTAT_XFERING (1<<8) -#define S3C2410_SDICMDSTAT_INDEX (0xff) - -#define S3C2440_SDIDCON_DS_BYTE (0<<22) -#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) -#define S3C2440_SDIDCON_DS_WORD (2<<22) -#define S3C2410_SDIDCON_IRQPERIOD (1<<21) -#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) -#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) -#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) -#define S3C2410_SDIDCON_BLOCKMODE (1<<17) -#define S3C2410_SDIDCON_WIDEBUS (1<<16) -#define S3C2410_SDIDCON_DMAEN (1<<15) -#define S3C2410_SDIDCON_STOP (1<<14) -#define S3C2440_SDIDCON_DATSTART (1<<14) -#define S3C2410_SDIDCON_DATMODE (3<<12) -#define S3C2410_SDIDCON_BLKNUM (0x7ff) - -/* constants for S3C2410_SDIDCON_DATMODE */ -#define S3C2410_SDIDCON_XFER_READY (0<<12) -#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) -#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) -#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) - -#define S3C2410_SDIDCNT_BLKNUM_MASK (0xFFF) -#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) - -#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) -#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) -#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ -#define S3C2410_SDIDSTA_CRCFAIL (1<<7) -#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) -#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) -#define S3C2410_SDIDSTA_XFERFINISH (1<<4) -#define S3C2410_SDIDSTA_BUSYFINISH (1<<3) -#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ -#define S3C2410_SDIDSTA_TXDATAON (1<<1) -#define S3C2410_SDIDSTA_RXDATAON (1<<0) - -#define S3C2440_SDIFSTA_FIFORESET (1<<16) -#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ -#define S3C2410_SDIFSTA_TFDET (1<<13) -#define S3C2410_SDIFSTA_RFDET (1<<12) -#define S3C2410_SDIFSTA_TFHALF (1<<11) -#define S3C2410_SDIFSTA_TFEMPTY (1<<10) -#define S3C2410_SDIFSTA_RFLAST (1<<9) -#define S3C2410_SDIFSTA_RFFULL (1<<8) -#define S3C2410_SDIFSTA_RFHALF (1<<7) -#define S3C2410_SDIFSTA_COUNTMASK (0x7f) - -#define S3C2410_SDIIMSK_RESPONSECRC (1<<17) -#define S3C2410_SDIIMSK_CMDSENT (1<<16) -#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) -#define S3C2410_SDIIMSK_RESPONSEND (1<<14) -#define S3C2410_SDIIMSK_READWAIT (1<<13) -#define S3C2410_SDIIMSK_SDIOIRQ (1<<12) -#define S3C2410_SDIIMSK_FIFOFAIL (1<<11) -#define S3C2410_SDIIMSK_CRCSTATUS (1<<10) -#define S3C2410_SDIIMSK_DATACRC (1<<9) -#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) -#define S3C2410_SDIIMSK_DATAFINISH (1<<7) -#define S3C2410_SDIIMSK_BUSYFINISH (1<<6) -#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ -#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) -#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) -#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) -#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) -#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) - -#endif /* __ASM_ARM_REGS_SDI */ diff --git a/qiboot/include/s3c6410.h b/qiboot/include/s3c6410.h deleted file mode 100644 index 6689bfa..0000000 --- a/qiboot/include/s3c6410.h +++ /dev/null @@ -1,1394 +0,0 @@ -/* - * (C) Copyright 2007 - * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. - * - only support for S3C6400 - * $Id: s3c6410.h,v 1.6 2008/07/02 11:01:48 jsgood Exp $ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c6400.h - * - * Based on S3C6400 User's manual Rev 0.0 - ************************************************/ - -#ifndef __S3C6410_H__ -#define __S3C6410_H__ - -#ifndef CONFIG_S3C6410 -#define CONFIG_S3C6410 1 -#endif - -#define S3C64XX_UART_CHANNELS 4 -#define S3C64XX_SPI_CHANNELS 2 - -#define HSMMC_CHANNEL 0 -#define MOVI_INIT_REQUIRED 0 -#define TCM_BASE 0x0C004000 -#define BL2_BASE 0x57E00000 -#define CopyMovitoMem(a,b,c,d,e) (((int(*)(int, uint, ushort, uint *, int))(*((uint *)(TCM_BASE + 0x8))))(a,b,c,d,e)) -#define SS_SIZE (8 * 1024) -#define eFUSE_SIZE (1 * 1024) // 0.5k eFuse, 0.5k reserved` -#define PART_UBOOT_OFFSET 0x0 -#define PART_ZIMAGE_OFFSET 0x40000 -#define PART_ROOTFS_OFFSET 0x200000 -#define PART_EXTRA_OFFSET 0x3200000 - -/* movinand definitions */ -#define MOVI_BLKSIZE 512 - -#define MOVI_TOTAL_BLKCNT 7864320 // 7864320 // 3995648 // 1003520 /* static movinand total block count: for writing to movinand when nand boot */ -#define MOVI_HIGH_CAPACITY 0 - -#define MOVI_LAST_BLKPOS (MOVI_TOTAL_BLKCNT - (eFUSE_SIZE / MOVI_BLKSIZE)) -#define MOVI_BL1_BLKCNT (SS_SIZE / MOVI_BLKSIZE) -#define MOVI_ENV_BLKCNT (CFG_ENV_SIZE / MOVI_BLKSIZE) -#define MOVI_BL2_BLKCNT (((PART_ZIMAGE_OFFSET - PART_UBOOT_OFFSET) / MOVI_BLKSIZE) - MOVI_ENV_BLKCNT) -#define MOVI_ZIMAGE_BLKCNT ((PART_ROOTFS_OFFSET - PART_ZIMAGE_OFFSET) / MOVI_BLKSIZE) -#define MOVI_BL2_POS (MOVI_LAST_BLKPOS - MOVI_BL1_BLKCNT - MOVI_BL2_BLKCNT - MOVI_ENV_BLKCNT) -#ifndef __ASSEMBLY__ - -struct movi_offset_t { - uint last; - uint bl1; - uint env; - uint bl2; - uint zimage; -}; - -/* external functions */ -extern void hsmmc_set_gpio(void); -extern void hsmmc_reset (void); -extern int hsmmc_init (void); - -extern void test_hsmmc (uint width, uint test, uint start_blk, uint blknum); - - -typedef enum { - S3C64XX_UART0, - S3C64XX_UART1, - S3C64XX_UART2, - S3C64XX_UART3, -} S3C64XX_UARTS_NR; - -#define __REG(x) (*((volatile unsigned int *)(x))) - -//#include -#endif - -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#define ROM_BASE0 0x00000000 /* base address of rom bank 0 */ -#define ROM_BASE1 0x04000000 /* base address of rom bank 1 */ -#define DRAM_BASE0 0x40000000 /* base address of dram bank 0 */ -#define DRAM_BASE1 0x50000000 /* base address of dram bank 1 */ - - -/* S3C6400 device base addresses */ -#define ELFIN_DMA_BASE 0x75000000 -#define ELFIN_LCD_BASE 0x77100000 -#define ELFIN_USB_HOST_BASE 0x74300000 -#define ELFIN_I2C_BASE 0x7f004000 -#define ELFIN_I2S_BASE 0x7f002000 -#define ELFIN_ADC_BASE 0x7e00b000 -#define ELFIN_SPI_BASE 0x7f00b000 -#define ELFIN_HSMMC_0_BASE 0x7c200000 -#define ELFIN_HSMMC_1_BASE 0x7c300000 -#define ELFIN_HSMMC_2_BASE 0x7c400000 - -#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 - -/* Clock & Power Controller for mDirac3*/ -#define APLL_LOCK_OFFSET 0x00 -#define MPLL_LOCK_OFFSET 0x04 -#define EPLL_LOCK_OFFSET 0x08 -#define APLL_CON_OFFSET 0x0C -#define MPLL_CON_OFFSET 0x10 -#define EPLL_CON0_OFFSET 0x14 -#define EPLL_CON1_OFFSET 0x18 -#define CLK_SRC_OFFSET 0x1C -#define CLK_DIV0_OFFSET 0x20 -#define CLK_DIV1_OFFSET 0x24 -#define CLK_DIV2_OFFSET 0x28 -#define CLK_OUT_OFFSET 0x2C -#define HCLK_GATE_OFFSET 0x30 -#define PCLK_GATE_OFFSET 0x34 -#define SCLK_GATE_OFFSET 0x38 -#define AHB_CON0_OFFSET 0x100 -#define AHB_CON1_OFFSET 0x104 -#define AHB_CON2_OFFSET 0x108 -#define SELECT_DMA_OFFSET 0x110 -#define SW_RST_OFFSET 0x114 -#define SYS_ID_OFFSET 0x118 -#define MEM_SYS_CFG_OFFSET 0x120 -#define QOS_OVERRIDE0_OFFSET 0x124 -#define QOS_OVERRIDE1_OFFSET 0x128 -#define MEM_CFG_STAT_OFFSET 0x12C -#define PWR_CFG_OFFSET 0x804 -#define EINT_MASK_OFFSET 0x808 -#define NOR_CFG_OFFSET 0x810 -#define STOP_CFG_OFFSET 0x814 -#define SLEEP_CFG_OFFSET 0x818 -#define STOP_MEM_CFG_OFFSET 0x81c -#define OSC_FREQ_OFFSET 0x820 -#define OSC_STABLE_OFFSET 0x824 -#define PWR_STABLE_OFFSET 0x828 -#define FPC_STABLE_OFFSET 0x82C -#define MTC_STABLE_OFFSET 0x830 -#define OTHERS_OFFSET 0x900 -#define RST_STAT_OFFSET 0x904 -#define WAKEUP_STAT_OFFSET 0x908 -#define BLK_PWR_STAT_OFFSET 0x90C -#define INF_REG0_OFFSET 0xA00 -#define INF_REG1_OFFSET 0xA04 -#define INF_REG2_OFFSET 0xA08 -#define INF_REG3_OFFSET 0xA0C -#define INF_REG4_OFFSET 0xA10 -#define INF_REG5_OFFSET 0xA14 -#define INF_REG6_OFFSET 0xA18 -#define INF_REG7_OFFSET 0xA1C - -#define OSC_CNT_VAL_OFFSET 0x824 -#define PWR_CNT_VAL_OFFSET 0x828 -#define FPC_CNT_VAL_OFFSET 0x82C -#define MTC_CNT_VAL_OFFSET 0x830 - - -#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET) -#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET) -#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET) -#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET) -#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET) -#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET) -#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET) -#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET) -#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET) -#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET) -#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET) -#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET) -#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET) -#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET) -#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET) -#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET) -#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET) -#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET) -#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET) -#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET) -#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET) -#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET) -#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET) -#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET) -#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET) -#define STOP_MEM_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+STOP_MEM_CFG_OFFSET) -#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET) -#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET) -#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET) -#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET) -#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) -#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET) -#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) -#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET) -#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET) -#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET) -#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET) -#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET) -#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET) -#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET) - -#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET) -#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET) -#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET) -#define APLL_CON (ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET) -#define MPLL_CON (ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET) -#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET) -#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET) -#define CLK_SRC (ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET) -#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET) -#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET) -#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET) -#define CLK_OUT (ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET) -#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET) -#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET) -#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET) -#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET) -#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET) -#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET) -#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET) -#define SW_RST (ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET) -#define SYS_ID (ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET) -#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET) -#define PWR_CFG (ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET) -#define EINT_MASK (ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET) -#define NOR_CFG (ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET) -#define STOP_CFG (ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET) -#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET) -#define STOP_MEM_CFG (ELFIN_CLOCK_POWER_BASE+STOP_MEM_CFG_OFFSET) -#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET) -#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET) -#define OTHERS (ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET) -#define RST_STAT (ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) -#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET) -#define INF_REG0 (ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) -#define INF_REG1 (ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET) -#define INF_REG2 (ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET) -#define INF_REG3 (ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET) -#define INF_REG4 (ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET) -#define INF_REG5 (ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET) -#define INF_REG6 (ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET) -#define INF_REG7 (ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET) - - -/* - * GPIO - */ -#define ELFIN_GPIO_BASE 0x7f008000 - -#define GPACON_OFFSET 0x00 -#define GPADAT_OFFSET 0x04 -#define GPAPUD_OFFSET 0x08 -#define GPACONSLP_OFFSET 0x0C -#define GPAPUDSLP_OFFSET 0x10 -#define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x24 -#define GPBPUD_OFFSET 0x28 -#define GPBCONSLP_OFFSET 0x2C -#define GPBPUDSLP_OFFSET 0x30 -#define GPCCON_OFFSET 0x40 -#define GPCDAT_OFFSET 0x44 -#define GPCPUD_OFFSET 0x48 -#define GPCCONSLP_OFFSET 0x4C -#define GPCPUDSLP_OFFSET 0x50 -#define GPDCON_OFFSET 0x60 -#define GPDDAT_OFFSET 0x64 -#define GPDPUD_OFFSET 0x68 -#define GPDCONSLP_OFFSET 0x6C -#define GPDPUDSLP_OFFSET 0x70 -#define GPECON_OFFSET 0x80 -#define GPEDAT_OFFSET 0x84 -#define GPEPUD_OFFSET 0x88 -#define GPECONSLP_OFFSET 0x8C -#define GPEPUDSLP_OFFSET 0x90 -#define GPFCON_OFFSET 0xA0 -#define GPFDAT_OFFSET 0xA4 -#define GPFPUD_OFFSET 0xA8 -#define GPFCONSLP_OFFSET 0xAC -#define GPFPUDSLP_OFFSET 0xB0 -#define GPGCON_OFFSET 0xC0 -#define GPGDAT_OFFSET 0xC4 -#define GPGPUD_OFFSET 0xC8 -#define GPGCONSLP_OFFSET 0xCC -#define GPGPUDSLP_OFFSET 0xD0 -#define GPHCON0_OFFSET 0xE0 -#define GPHCON1_OFFSET 0xE4 -#define GPHDAT_OFFSET 0xE8 -#define GPHPUD_OFFSET 0xEC -#define GPHCONSLP_OFFSET 0xF0 -#define GPHPUDSLP_OFFSET 0xF4 -#define GPICON_OFFSET 0x100 -#define GPIDAT_OFFSET 0x104 -#define GPIPUD_OFFSET 0x108 -#define GPICONSLP_OFFSET 0x10C -#define GPIPUDSLP_OFFSET 0x110 -#define GPJCON_OFFSET 0x120 -#define GPJDAT_OFFSET 0x124 -#define GPJPUD_OFFSET 0x128 -#define GPJCONSLP_OFFSET 0x12C -#define GPJPUDSLP_OFFSET 0x130 -#define SPCON_OFFSET 0x1A0 -#define MEM0DRVCON_OFFSET 0x1D0 -#define MEM1DRVCON_OFFSET 0x1D4 -#define GPKCON0_OFFSET 0x800 -#define GPKCON1_OFFSET 0x804 -#define GPKDAT_OFFSET 0x808 -#define GPKPUD_OFFSET 0x80C -#define GPLCON0_OFFSET 0x810 -#define GPLCON1_OFFSET 0x814 -#define GPLDAT_OFFSET 0x818 -#define GPLPUD_OFFSET 0x81C -#define GPMCON_OFFSET 0x820 -#define GPMDAT_OFFSET 0x824 -#define GPMPUD_OFFSET 0x828 -#define GPNCON_OFFSET 0x830 -#define GPNDAT_OFFSET 0x834 -#define GPNPUD_OFFSET 0x838 -#define GPOCON_OFFSET 0x140 -#define GPODAT_OFFSET 0x144 -#define GPOPUD_OFFSET 0x148 -#define GPOCONSLP_OFFSET 0x14C -#define GPOPUDSLP_OFFSET 0x150 -#define GPPCON_OFFSET 0x160 -#define GPPDAT_OFFSET 0x164 -#define GPPPUD_OFFSET 0x168 -#define GPPCONSLP_OFFSET 0x16C -#define GPPPUDSLP_OFFSET 0x170 -#define GPQCON_OFFSET 0x180 -#define GPQDAT_OFFSET 0x184 -#define GPQPUD_OFFSET 0x188 -#define GPQCONSLP_OFFSET 0x18C -#define GPQPUDSLP_OFFSET 0x190 - -#define EINTPEND_OFFSET 0x924 - -#define GPACON_REG __REG(ELFIN_GPIO_BASE+GPACON_OFFSET) -#define GPADAT_REG __REG(ELFIN_GPIO_BASE+GPADAT_OFFSET) -#define GPAPUD_REG __REG(ELFIN_GPIO_BASE+GPAPUD_OFFSET) -#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE+GPACONSLP_OFFSET) -#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPAPUDSLP_OFFSET) -#define GPBCON_REG __REG(ELFIN_GPIO_BASE+GPBCON_OFFSET) -#define GPBDAT_REG __REG(ELFIN_GPIO_BASE+GPBDAT_OFFSET) -#define GPBPUD_REG __REG(ELFIN_GPIO_BASE+GPBPUD_OFFSET) -#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE+GPBCONSLP_OFFSET) -#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPBPUDSLP_OFFSET) -#define GPCCON_REG __REG(ELFIN_GPIO_BASE+GPCCON_OFFSET) -#define GPCDAT_REG __REG(ELFIN_GPIO_BASE+GPCDAT_OFFSET) -#define GPCPUD_REG __REG(ELFIN_GPIO_BASE+GPCPUD_OFFSET) -#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE+GPCCONSLP_OFFSET) -#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPCPUDSLP_OFFSET) -#define GPDCON_REG __REG(ELFIN_GPIO_BASE+GPDCON_OFFSET) -#define GPDDAT_REG __REG(ELFIN_GPIO_BASE+GPDDAT_OFFSET) -#define GPDPUD_REG __REG(ELFIN_GPIO_BASE+GPDPUD_OFFSET) -#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE+GPDCONSLP_OFFSET) -#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPDPUDSLP_OFFSET) -#define GPECON_REG __REG(ELFIN_GPIO_BASE+GPECON_OFFSET) -#define GPEDAT_REG __REG(ELFIN_GPIO_BASE+GPEDAT_OFFSET) -#define GPEPUD_REG __REG(ELFIN_GPIO_BASE+GPEPUD_OFFSET) -#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE+GPECONSLP_OFFSET) -#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPEPUDSLP_OFFSET) -#define GPFCON_REG __REG(ELFIN_GPIO_BASE+GPFCON_OFFSET) -#define GPFDAT_REG __REG(ELFIN_GPIO_BASE+GPFDAT_OFFSET) -#define GPFPUD_REG __REG(ELFIN_GPIO_BASE+GPFPUD_OFFSET) -#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE+GPFCONSLP_OFFSET) -#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPFPUDSLP_OFFSET) -#define GPGCON_REG __REG(ELFIN_GPIO_BASE+GPGCON_OFFSET) -#define GPGDAT_REG __REG(ELFIN_GPIO_BASE+GPGDAT_OFFSET) -#define GPGPUD_REG __REG(ELFIN_GPIO_BASE+GPGPUD_OFFSET) -#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE+GPGCONSLP_OFFSET) -#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPGPUDSLP_OFFSET) -#define GPHCON0_REG __REG(ELFIN_GPIO_BASE+GPHCON0_OFFSET) -#define GPHCON1_REG __REG(ELFIN_GPIO_BASE+GPHCON1_OFFSET) -#define GPHDAT_REG __REG(ELFIN_GPIO_BASE+GPHDAT_OFFSET) -#define GPHPUD_REG __REG(ELFIN_GPIO_BASE+GPHPUD_OFFSET) -#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE+GPHCONSLP_OFFSET) -#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPHPUDSLP_OFFSET) -#define GPICON_REG __REG(ELFIN_GPIO_BASE+GPICON_OFFSET) -#define GPIDAT_REG __REG(ELFIN_GPIO_BASE+GPIDAT_OFFSET) -#define GPIPUD_REG __REG(ELFIN_GPIO_BASE+GPIPUD_OFFSET) -#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE+GPICONSLP_OFFSET) -#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPIPUDSLP_OFFSET) -#define GPJCON_REG __REG(ELFIN_GPIO_BASE+GPJCON_OFFSET) -#define GPJDAT_REG __REG(ELFIN_GPIO_BASE+GPJDAT_OFFSET) -#define GPJPUD_REG __REG(ELFIN_GPIO_BASE+GPJPUD_OFFSET) -#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE+GPJCONSLP_OFFSET) -#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPJPUDSLP_OFFSET) -#define GPKCON0_REG __REG(ELFIN_GPIO_BASE+GPKCON0_OFFSET) -#define GPKCON1_REG __REG(ELFIN_GPIO_BASE+GPKCON1_OFFSET) -#define GPKDAT_REG __REG(ELFIN_GPIO_BASE+GPKDAT_OFFSET) -#define GPKPUD_REG __REG(ELFIN_GPIO_BASE+GPKPUD_OFFSET) -#define GPLCON0_REG __REG(ELFIN_GPIO_BASE+GPLCON0_OFFSET) -#define GPLCON1_REG __REG(ELFIN_GPIO_BASE+GPLCON1_OFFSET) -#define GPLDAT_REG __REG(ELFIN_GPIO_BASE+GPLDAT_OFFSET) -#define GPLPUD_REG __REG(ELFIN_GPIO_BASE+GPLPUD_OFFSET) -#define GPMCON_REG __REG(ELFIN_GPIO_BASE+GPMCON_OFFSET) -#define GPMDAT_REG __REG(ELFIN_GPIO_BASE+GPMDAT_OFFSET) -#define GPMPUD_REG __REG(ELFIN_GPIO_BASE+GPMPUD_OFFSET) -#define GPNCON_REG __REG(ELFIN_GPIO_BASE+GPNCON_OFFSET) -#define GPNDAT_REG __REG(ELFIN_GPIO_BASE+GPNDAT_OFFSET) -#define GPNPUD_REG __REG(ELFIN_GPIO_BASE+GPNPUD_OFFSET) -#define GPOCON_REG __REG(ELFIN_GPIO_BASE+GPOCON_OFFSET) -#define GPODAT_REG __REG(ELFIN_GPIO_BASE+GPODAT_OFFSET) -#define GPOPUD_REG __REG(ELFIN_GPIO_BASE+GPOPUD_OFFSET) -#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE+GPOCONSLP_OFFSET) -#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPOPUDSLP_OFFSET) -#define GPPCON_REG __REG(ELFIN_GPIO_BASE+GPPCON_OFFSET) -#define GPPDAT_REG __REG(ELFIN_GPIO_BASE+GPPDAT_OFFSET) -#define GPPPUD_REG __REG(ELFIN_GPIO_BASE+GPPPUD_OFFSET) -#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE+GPPCONSLP_OFFSET) -#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPPPUDSLP_OFFSET) -#define GPQCON_REG __REG(ELFIN_GPIO_BASE+GPQCON_OFFSET) -#define GPQDAT_REG __REG(ELFIN_GPIO_BASE+GPQDAT_OFFSET) -#define GPQPUD_REG __REG(ELFIN_GPIO_BASE+GPQPUD_OFFSET) -#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE+GPQCONSLP_OFFSET) -#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPQPUDSLP_OFFSET) - -#define GPACON (ELFIN_GPIO_BASE+GPACON_OFFSET) -#define GPADAT (ELFIN_GPIO_BASE+GPADAT_OFFSET) -#define GPAPUD (ELFIN_GPIO_BASE+GPAPUD_OFFSET) -#define GPACONSLP (ELFIN_GPIO_BASE+GPACONSLP_OFFSET) -#define GPAPUDSLP (ELFIN_GPIO_BASE+GPAPUDSLP_OFFSET) -#define GPBCON (ELFIN_GPIO_BASE+GPBCON_OFFSET) -#define GPBDAT (ELFIN_GPIO_BASE+GPBDAT_OFFSET) -#define GPBPUD (ELFIN_GPIO_BASE+GPBPUD_OFFSET) -#define GPBCONSLP (ELFIN_GPIO_BASE+GPBCONSLP_OFFSET) -#define GPBPUDSLP (ELFIN_GPIO_BASE+GPBPUDSLP_OFFSET) -#define GPCCON (ELFIN_GPIO_BASE+GPCCON_OFFSET) -#define GPCDAT (ELFIN_GPIO_BASE+GPCDAT_OFFSET) -#define GPCPUD (ELFIN_GPIO_BASE+GPCPUD_OFFSET) -#define GPCCONSLP (ELFIN_GPIO_BASE+GPCCONSLP_OFFSET) -#define GPCPUDSLP (ELFIN_GPIO_BASE+GPCPUDSLP_OFFSET) -#define GPDCON (ELFIN_GPIO_BASE+GPDCON_OFFSET) -#define GPDDAT (ELFIN_GPIO_BASE+GPDDAT_OFFSET) -#define GPDPUD (ELFIN_GPIO_BASE+GPDPUD_OFFSET) -#define GPDCONSLP (ELFIN_GPIO_BASE+GPDCONSLP_OFFSET) -#define GPDPUDSLP (ELFIN_GPIO_BASE+GPDPUDSLP_OFFSET) -#define GPECON (ELFIN_GPIO_BASE+GPECON_OFFSET) -#define GPEDAT (ELFIN_GPIO_BASE+GPEDAT_OFFSET) -#define GPEPUD (ELFIN_GPIO_BASE+GPEPUD_OFFSET) -#define GPECONSLP (ELFIN_GPIO_BASE+GPECONSLP_OFFSET) -#define GPEPUDSLP (ELFIN_GPIO_BASE+GPEPUDSLP_OFFSET) -#define GPFCON (ELFIN_GPIO_BASE+GPFCON_OFFSET) -#define GPFDAT (ELFIN_GPIO_BASE+GPFDAT_OFFSET) -#define GPFPUD (ELFIN_GPIO_BASE+GPFPUD_OFFSET) -#define GPFCONSLP (ELFIN_GPIO_BASE+GPFCONSLP_OFFSET) -#define GPFPUDSLP (ELFIN_GPIO_BASE+GPFPUDSLP_OFFSET) -#define GPGCON (ELFIN_GPIO_BASE+GPGCON_OFFSET) -#define GPGDAT (ELFIN_GPIO_BASE+GPGDAT_OFFSET) -#define GPGPUD (ELFIN_GPIO_BASE+GPGPUD_OFFSET) -#define GPGCONSLP (ELFIN_GPIO_BASE+GPGCONSLP_OFFSET) -#define GPGPUDSLP (ELFIN_GPIO_BASE+GPGPUDSLP_OFFSET) -#define GPHCON0 (ELFIN_GPIO_BASE+GPHCON0_OFFSET) -#define GPHCON1 (ELFIN_GPIO_BASE+GPHCON1_OFFSET) -#define GPHDAT (ELFIN_GPIO_BASE+GPHDAT_OFFSET) -#define GPHPUD (ELFIN_GPIO_BASE+GPHPUD_OFFSET) -#define GPHCONSLP (ELFIN_GPIO_BASE+GPHCONSLP_OFFSET) -#define GPHPUDSLP (ELFIN_GPIO_BASE+GPHPUDSLP_OFFSET) -#define GPICON (ELFIN_GPIO_BASE+GPICON_OFFSET) -#define GPIDAT (ELFIN_GPIO_BASE+GPIDAT_OFFSET) -#define GPIPUD (ELFIN_GPIO_BASE+GPIPUD_OFFSET) -#define GPICONSLP (ELFIN_GPIO_BASE+GPICONSLP_OFFSET) -#define GPIPUDSLP (ELFIN_GPIO_BASE+GPIPUDSLP_OFFSET) -#define GPJCON (ELFIN_GPIO_BASE+GPJCON_OFFSET) -#define GPJDAT (ELFIN_GPIO_BASE+GPJDAT_OFFSET) -#define GPJPUD (ELFIN_GPIO_BASE+GPJPUD_OFFSET) -#define GPJCONSLP (ELFIN_GPIO_BASE+GPJCONSLP_OFFSET) -#define GPJPUDSLP (ELFIN_GPIO_BASE+GPJPUDSLP_OFFSET) -#define GPKCON0 (ELFIN_GPIO_BASE+GPKCON0_OFFSET) -#define GPKCON1 (ELFIN_GPIO_BASE+GPKCON1_OFFSET) -#define GPKDAT (ELFIN_GPIO_BASE+GPKDAT_OFFSET) -#define GPKPUD (ELFIN_GPIO_BASE+GPKPUD_OFFSET) -#define GPLCON0 (ELFIN_GPIO_BASE+GPLCON0_OFFSET) -#define GPLCON1 (ELFIN_GPIO_BASE+GPLCON1_OFFSET) -#define GPLDAT (ELFIN_GPIO_BASE+GPLDAT_OFFSET) -#define GPLPUD (ELFIN_GPIO_BASE+GPLPUD_OFFSET) -#define GPMCON (ELFIN_GPIO_BASE+GPMCON_OFFSET) -#define GPMDAT (ELFIN_GPIO_BASE+GPMDAT_OFFSET) -#define GPMPUD (ELFIN_GPIO_BASE+GPMPUD_OFFSET) -#define GPNCON (ELFIN_GPIO_BASE+GPNCON_OFFSET) -#define GPNDAT (ELFIN_GPIO_BASE+GPNDAT_OFFSET) -#define GPNPUD (ELFIN_GPIO_BASE+GPNPUD_OFFSET) -#define GPOCON (ELFIN_GPIO_BASE+GPOCON_OFFSET) -#define GPODAT (ELFIN_GPIO_BASE+GPODAT_OFFSET) -#define GPOPUD (ELFIN_GPIO_BASE+GPOPUD_OFFSET) -#define GPOCONSLP (ELFIN_GPIO_BASE+GPOCONSLP_OFFSET) -#define GPOPUDSLP (ELFIN_GPIO_BASE+GPOPUDSLP_OFFSET) -#define GPPCON (ELFIN_GPIO_BASE+GPPCON_OFFSET) -#define GPPDAT (ELFIN_GPIO_BASE+GPPDAT_OFFSET) -#define GPPPUD (ELFIN_GPIO_BASE+GPPPUD_OFFSET) -#define GPPCONSLP (ELFIN_GPIO_BASE+GPPCONSLP_OFFSET) -#define GPPPUDSLP (ELFIN_GPIO_BASE+GPPPUDSLP_OFFSET) -#define GPQCON (ELFIN_GPIO_BASE+GPQCON_OFFSET) -#define GPQDAT (ELFIN_GPIO_BASE+GPQDAT_OFFSET) -#define GPQPUD (ELFIN_GPIO_BASE+GPQPUD_OFFSET) -#define GPQCONSLP (ELFIN_GPIO_BASE+GPQCONSLP_OFFSET) -#define GPQPUDSLP (ELFIN_GPIO_BASE+GPQPUDSLP_OFFSET) - -/* - * Bus Matrix - */ -#define ELFIN_MEM_SYS_CFG 0x7e00f120 - - - -/* - * Memory controller - */ -#define ELFIN_SROM_BASE 0x70000000 - -#define SROM_BW_REG __REG(ELFIN_SROM_BASE+0x0) -#define SROM_BC0_REG __REG(ELFIN_SROM_BASE+0x4) -#define SROM_BC1_REG __REG(ELFIN_SROM_BASE+0x8) -#define SROM_BC2_REG __REG(ELFIN_SROM_BASE+0xC) -#define SROM_BC3_REG __REG(ELFIN_SROM_BASE+0x10) -#define SROM_BC4_REG __REG(ELFIN_SROM_BASE+0x14) -#define SROM_BC5_REG __REG(ELFIN_SROM_BASE+0x18) - - - -/* - * SDRAM Controller - */ -#define ELFIN_DMC0_BASE 0x7e000000 -#define ELFIN_DMC1_BASE 0x7e001000 - -#define INDEX_DMC_MEMC_STATUS (0x00) -#define INDEX_DMC_MEMC_CMD (0x04) -#define INDEX_DMC_DIRECT_CMD (0x08) -#define INDEX_DMC_MEMORY_CFG (0x0C) -#define INDEX_DMC_REFRESH_PRD (0x10) -#define INDEX_DMC_CAS_LATENCY (0x14) -#define INDEX_DMC_T_DQSS (0x18) -#define INDEX_DMC_T_MRD (0x1C) -#define INDEX_DMC_T_RAS (0x20) -#define INDEX_DMC_T_RC (0x24) -#define INDEX_DMC_T_RCD (0x28) -#define INDEX_DMC_T_RFC (0x2C) -#define INDEX_DMC_T_RP (0x30) -#define INDEX_DMC_T_RRD (0x34) -#define INDEX_DMC_T_WR (0x38) -#define INDEX_DMC_T_WTR (0x3C) -#define INDEX_DMC_T_XP (0x40) -#define INDEX_DMC_T_XSR (0x44) -#define INDEX_DMC_T_ESR (0x48) -#define INDEX_DMC_MEMORY_CFG2 (0x4C) -#define INDEX_DMC_CHIP_0_CFG (0x200) -#define INDEX_DMC_CHIP_1_CFG (0x204) -#define INDEX_DMC_CHIP_2_CFG (0x208) -#define INDEX_DMC_CHIP_3_CFG (0x20C) -#define INDEX_DMC_USER_STATUS (0x300) -#define INDEX_DMC_USER_CONFIG (0x304) - -/* -* Memory Chip direct command -*/ -#define DMC_NOP0 0x0c0000 -#define DMC_NOP1 0x1c0000 -#define DMC_PA0 0x000000 //Precharge all -#define DMC_PA1 0x100000 -#define DMC_AR0 0x040000 //Autorefresh -#define DMC_AR1 0x140000 -#define DMC_SDR_MR0 0x080032 //MRS, CAS 3, Burst Length 4 -#define DMC_SDR_MR1 0x180032 -#define DMC_DDR_MR0 0x080162 -#define DMC_DDR_MR1 0x180162 -#define DMC_mDDR_MR0 0x080032 //CAS 3, Burst Length 4 -#define DMC_mDDR_MR1 0x180032 -#define DMC_mSDR_EMR0 0x0a0000 //EMRS, DS:Full, PASR:Full Array -#define DMC_mSDR_EMR1 0x1a0000 -#define DMC_DDR_EMR0 0x090000 -#define DMC_DDR_EMR1 0x190000 -#define DMC_mDDR_EMR0 0x0a0000 // DS:Full, PASR:Full Array -#define DMC_mDDR_EMR1 0x1a0000 - - -/**************************************************************** - Definitions for memory configuration - Set memory configuration - active_chips = 1'b0 (1 chip) - qos_master_chip = 3'b000(ARID[3:0]) - memory burst = 3'b010(burst 4) - stop_mem_clock = 1'b0(disable dynamical stop) - auto_power_down = 1'b0(disable auto power-down mode) - power_down_prd = 6'b00_0000(0 cycle for auto power-down) - ap_bit = 1'b0 (bit position of auto-precharge is 10) - row_bits = 3'b010(# row address 13) - column_bits = 3'b010(# column address 10 ) - - Set user configuration - 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR - - Set chip select for chip [n] - row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff - CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] -******************************************************************/ - -/* - * HS MMC Interface - */ -#define ELFIN_HSMMC_BASE 0x7C200000 - -#define HM_SYSAD (0x00) -#define HM_BLKSIZE (0x04) -#define HM_BLKCNT (0x06) -#define HM_ARGUMENT (0x08) -#define HM_TRNMOD (0x0c) -#define HM_CMDREG (0x0e) -#define HM_RSPREG0 (0x10) -#define HM_RSPREG1 (0x14) -#define HM_RSPREG2 (0x18) -#define HM_RSPREG3 (0x1c) -#define HM_BDATA (0x20) -#define HM_PRNSTS (0x24) -#define HM_HOSTCTL (0x28) -#define HM_PWRCON (0x29) -#define HM_BLKGAP (0x2a) -#define HM_WAKCON (0x2b) -#define HM_CLKCON (0x2c) -#define HM_TIMEOUTCON (0x2e) -#define HM_SWRST (0x2f) -#define HM_NORINTSTS (0x30) -#define HM_ERRINTSTS (0x32) -#define HM_NORINTSTSEN (0x34) -#define HM_ERRINTSTSEN (0x36) -#define HM_NORINTSIGEN (0x38) -#define HM_ERRINTSIGEN (0x3a) -#define HM_ACMD12ERRSTS (0x3c) -#define HM_CAPAREG (0x40) -#define HM_MAXCURR (0x48) -#define HM_CONTROL2 (0x80) -#define HM_CONTROL3 (0x84) -#define HM_CONTROL4 (0x8c) -#define HM_HCVER (0xfe) - -/* - * Nand flash controller - */ -#define ELFIN_NAND_BASE 0x70200000 - -#define NFCONF_OFFSET 0x00 -#define NFCONT_OFFSET 0x04 -#define NFCMMD_OFFSET 0x08 -#define NFADDR_OFFSET 0x0c -#define NFDATA_OFFSET 0x10 -#define NFMECCDATA0_OFFSET 0x14 -#define NFMECCDATA1_OFFSET 0x18 -#define NFSECCDATA0_OFFSET 0x1c -#define NFSBLK_OFFSET 0x20 -#define NFEBLK_OFFSET 0x24 -#define NFSTAT_OFFSET 0x28 -#define NFESTAT0_OFFSET 0x2c -#define NFESTAT1_OFFSET 0x30 -#define NFMECC0_OFFSET 0x34 -#define NFMECC1_OFFSET 0x38 -#define NFSECC_OFFSET 0x3c -#define NFMLCBITPT_OFFSET 0x40 -#define NF8ECCERR0_OFFSET 0x44 -#define NF8ECCERR1_OFFSET 0x48 -#define NF8ECCERR2_OFFSET 0x4c -#define NFM8ECC0_OFFSET 0x50 -#define NFM8ECC1_OFFSET 0x54 -#define NFM8ECC2_OFFSET 0x58 -#define NFM8ECC3_OFFSET 0x5c -#define NFMLC8BITPT0_OFFSET 0x60 -#define NFMLC8BITPT1_OFFSET 0x64 - -#define NFCONF (ELFIN_NAND_BASE+NFCONF_OFFSET) -#define NFCONT (ELFIN_NAND_BASE+NFCONT_OFFSET) -#define NFCMMD (ELFIN_NAND_BASE+NFCMMD_OFFSET) -#define NFADDR (ELFIN_NAND_BASE+NFADDR_OFFSET) -#define NFDATA (ELFIN_NAND_BASE+NFDATA_OFFSET) -#define NFMECCDATA0 (ELFIN_NAND_BASE+NFMECCDATA0_OFFSET) -#define NFMECCDATA1 (ELFIN_NAND_BASE+NFMECCDATA1_OFFSET) -#define NFSECCDATA0 (ELFIN_NAND_BASE+NFSECCDATA0_OFFSET) -#define NFSBLK (ELFIN_NAND_BASE+NFSBLK_OFFSET) -#define NFEBLK (ELFIN_NAND_BASE+NFEBLK_OFFSET) -#define NFSTAT (ELFIN_NAND_BASE+NFSTAT_OFFSET) -#define NFESTAT0 (ELFIN_NAND_BASE+NFESTAT0_OFFSET) -#define NFESTAT1 (ELFIN_NAND_BASE+NFESTAT1_OFFSET) -#define NFMECC0 (ELFIN_NAND_BASE+NFMECC0_OFFSET) -#define NFMECC1 (ELFIN_NAND_BASE+NFMECC1_OFFSET) -#define NFSECC (ELFIN_NAND_BASE+NFSECC_OFFSET) -#define NFMLCBITPT (ELFIN_NAND_BASE+NFMLCBITPT_OFFSET) -#define NF8ECCERR0 (ELFIN_NAND_BASE+NF8ECCERR0_OFFSET) -#define NF8ECCERR1 (ELFIN_NAND_BASE+NF8ECCERR1_OFFSET) -#define NF8ECCERR2 (ELFIN_NAND_BASE+NF8ECCERR2_OFFSET) -#define NFM8ECC0 (ELFIN_NAND_BASE+NFM8ECC0_OFFSET) -#define NFM8ECC1 (ELFIN_NAND_BASE+NFM8ECC1_OFFSET) -#define NFM8ECC2 (ELFIN_NAND_BASE+NFM8ECC2_OFFSET) -#define NFM8ECC3 (ELFIN_NAND_BASE+NFM8ECC3_OFFSET) -#define NFMLC8BITPT0 (ELFIN_NAND_BASE+NFMLC8BITPT0_OFFSET) -#define NFMLC8BITPT1 (ELFIN_NAND_BASE+NFMLC8BITPT1_OFFSET) - -#define NFCONF_REG __REG(ELFIN_NAND_BASE+NFCONF_OFFSET) -#define NFCONT_REG __REG(ELFIN_NAND_BASE+NFCONT_OFFSET) -#define NFCMD_REG __REG(ELFIN_NAND_BASE+NFCMMD_OFFSET) -#define NFADDR_REG __REG(ELFIN_NAND_BASE+NFADDR_OFFSET) -#define NFDATA_REG __REG(ELFIN_NAND_BASE+NFDATA_OFFSET) -#define NFDATA8_REG __REGb(ELFIN_NAND_BASE+NFDATA_OFFSET) -#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE+NFMECCDATA0_OFFSET) -#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE+NFMECCDATA1_OFFSET) -#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE+NFSECCDATA0_OFFSET) -#define NFSBLK_REG __REG(ELFIN_NAND_BASE+NFSBLK_OFFSET) -#define NFEBLK_REG __REG(ELFIN_NAND_BASE+NFEBLK_OFFSET) -#define NFSTAT_REG __REG(ELFIN_NAND_BASE+NFSTAT_OFFSET) -#define NFESTAT0_REG __REG(ELFIN_NAND_BASE+NFESTAT0_OFFSET) -#define NFESTAT1_REG __REG(ELFIN_NAND_BASE+NFESTAT1_OFFSET) -#define NFMECC0_REG __REG(ELFIN_NAND_BASE+NFMECC0_OFFSET) -#define NFMECC1_REG __REG(ELFIN_NAND_BASE+NFMECC1_OFFSET) -#define NFSECC_REG __REG(ELFIN_NAND_BASE+NFSECC_OFFSET) -#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE+NFMLCBITPT_OFFSET) - -#define NFCONF_ECC_MLC (1<<24) -#define NFCONT_ECC_ENC (1<<18) -#define NFCONT_WP (1<<16) -#define NFCONT_MECCLOCK (1<<7) -#define NFCONT_SECCLOCK (1<<6) -#define NFCONT_INITMECC (1<<5) -#define NFCONT_INITSECC (1<<4) -#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) -#define NFCONT_CS_ALT (1<<1) -#define NFCONT_CS (1<<1) -#define NFSTAT_ECCENCDONE (1<<7) -#define NFSTAT_ECCDECDONE (1<<6) -#define NFSTAT_RnB (1<<0) -#define NFESTAT0_ECCBUSY (1<<31) - - - -/************************************************************* - * OneNAND Controller - *************************************************************/ - -/* - * S3C6400 SFRs - */ -#define ONENAND_REG_MEM_CFG (0x000) -#define ONENAND_REG_BURST_LEN (0x010) -#define ONENAND_REG_MEM_RESET (0x020) -#define ONENAND_REG_INT_ERR_STAT (0x030) -#define ONENAND_REG_INT_ERR_MASK (0x040) -#define ONENAND_REG_INT_ERR_ACK (0x050) -#define ONENAND_REG_ECC_ERR_STAT (0x060) -#define ONENAND_REG_MANUFACT_ID (0x070) -#define ONENAND_REG_DEVICE_ID (0x080) -#define ONENAND_REG_DATA_BUF_SIZE (0x090) -#define ONENAND_REG_BOOT_BUF_SIZE (0x0A0) -#define ONENAND_REG_BUF_AMOUNT (0x0B0) -#define ONENAND_REG_TECH (0x0C0) -#define ONENAND_REG_FBA_WIDTH (0x0D0) -#define ONENAND_REG_FPA_WIDTH (0x0E0) -#define ONENAND_REG_FSA_WIDTH (0x0F0) -#define ONENAND_REG_REVISION (0x100) -#define ONENAND_REG_DATARAM0 (0x110) -#define ONENAND_REG_DATARAM1 (0x120) -#define ONENAND_REG_SYNC_MODE (0x130) -#define ONENAND_REG_TRANS_SPARE (0x140) -#define ONENAND_REG_LOCK_BIT (0x150) -#define ONENAND_REG_DBS_DFS_WIDTH (0x160) -#define ONENAND_REG_PAGE_CNT (0x170) -#define ONENAND_REG_ERR_PAGE_ADDR (0x180) -#define ONENAND_REG_BURST_RD_LAT (0x190) -#define ONENAND_REG_INT_PIN_ENABLE (0x1A0) -#define ONENAND_REG_INT_MON_CYC (0x1B0) -#define ONENAND_REG_ACC_CLOCK (0x1C0) -#define ONENAND_REG_SLOW_RD_PATH (0x1D0) -#define ONENAND_REG_ERR_BLK_ADDR (0x1E0) -#define ONENAND_REG_FLASH_VER_ID (0x1F0) -#define ONENAND_REG_FLASH_AUX_CNTRL (0x300) - -/* - * S3C6400 SFR values - */ -#define ONENAND_MEM_CFG_SYNC_READ (1 << 15) -#define ONENAND_MEM_CFG_BRL_7 (7 << 12) -#define ONENAND_MEM_CFG_BRL_6 (6 << 12) -#define ONENAND_MEM_CFG_BRL_5 (5 << 12) -#define ONENAND_MEM_CFG_BRL_4 (4 << 12) -#define ONENAND_MEM_CFG_BRL_3 (3 << 12) -#define ONENAND_MEM_CFG_BRL_10 (2 << 12) -#define ONENAND_MEM_CFG_BRL_9 (1 << 12) -#define ONENAND_MEM_CFG_BRL_8 (0 << 12) -#define ONENAND_MEM_CFG_BRL_SHIFT (12) -#define ONENAND_MEM_CFG_BL_1K (5 << 9) -#define ONENAND_MEM_CFG_BL_32 (4 << 9) -#define ONENAND_MEM_CFG_BL_16 (3 << 9) -#define ONENAND_MEM_CFG_BL_8 (2 << 9) -#define ONENAND_MEM_CFG_BL_4 (1 << 9) -#define ONENAND_MEM_CFG_BL_CONT (0 << 9) -#define ONENAND_MEM_CFG_BL_SHIFT (9) -#define ONENAND_MEM_CFG_NO_ECC (1 << 8) -#define ONENAND_MEM_CFG_RDY_HIGH (1 << 7) -#define ONENAND_MEM_CFG_INT_HIGH (1 << 6) -#define ONENAND_MEM_CFG_IOBE (1 << 5) -#define ONENAND_MEM_CFG_RDY_CONF (1 << 4) -#define ONENAND_MEM_CFG_HF (1 << 2) -#define ONENAND_MEM_CFG_WM_SYNC (1 << 1) -#define ONENAND_MEM_CFG_BWPS_UNLOCK (1 << 0) - -#define ONENAND_BURST_LEN_CONT (0) -#define ONENAND_BURST_LEN_4 (4) -#define ONENAND_BURST_LEN_8 (8) -#define ONENAND_BURST_LEN_16 (16) - -#define ONENAND_MEM_RESET_WARM (0x1) -#define ONENAND_MEM_RESET_COLD (0x2) -#define ONENAND_MEM_RESET_HOT (0x3) - -#define ONENAND_INT_ERR_CACHE_OP_ERR (1 << 13) -#define ONENAND_INT_ERR_RST_CMP (1 << 12) -#define ONENAND_INT_ERR_RDY_ACT (1 << 11) -#define ONENAND_INT_ERR_INT_ACT (1 << 10) -#define ONENAND_INT_ERR_UNSUP_CMD (1 << 9) -#define ONENAND_INT_ERR_LOCKED_BLK (1 << 8) -#define ONENAND_INT_ERR_BLK_RW_CMP (1 << 7) -#define ONENAND_INT_ERR_ERS_CMP (1 << 6) -#define ONENAND_INT_ERR_PGM_CMP (1 << 5) -#define ONENAND_INT_ERR_LOAD_CMP (1 << 4) -#define ONENAND_INT_ERR_ERS_FAIL (1 << 3) -#define ONENAND_INT_ERR_PGM_FAIL (1 << 2) -#define ONENAND_INT_ERR_INT_TO (1 << 1) -#define ONENAND_INT_ERR_LD_FAIL_ECC_ERR (1 << 0) - -#define ONENAND_DEVICE_DENSITY_SHIFT (4) -#define ONENAND_DEVICE_IS_DDP (1 << 3) -#define ONENAND_DEVICE_IS_DEMUX (1 << 2) -#define ONENAND_DEVICE_VCC_MASK (0x3) -#define ONENAND_DEVICE_DENSITY_128Mb (0x000) -#define ONENAND_DEVICE_DENSITY_256Mb (0x001) -#define ONENAND_DEVICE_DENSITY_512Mb (0x002) -#define ONENAND_DEVICE_DENSITY_1Gb (0x003) -#define ONENAND_DEVICE_DENSITY_2Gb (0x004) -#define ONENAND_DEVICE_DENSITY_4Gb (0x005) - -#define ONENAND_SYNC_MODE_RM_SYNC (1 << 1) -#define ONENAND_SYNC_MODE_WM_SYNC (1 << 0) - -#define ONENAND_TRANS_SPARE_TSRF_INC (1 << 0) - -#define ONENAND_INT_PIN_ENABLE (1 << 0) - -#define ONENAND_ACC_CLOCK_266_133 (0x5) -#define ONENAND_ACC_CLOCK_166_83 (0x3) -#define ONENAND_ACC_CLOCK_134_67 (0x3) -#define ONENAND_ACC_CLOCK_100_50 (0x2) -#define ONENAND_ACC_CLOCK_60_30 (0x2) - -#define ONENAND_FLASH_AUX_WD_DISABLE (1 << 0) - -/* - * Datain values for mapped commands - */ -#define ONENAND_DATAIN_ERASE_STATUS (0x00) -#define ONENAND_DATAIN_ERASE_MULTI (0x01) -#define ONENAND_DATAIN_ERASE_SINGLE (0x03) -#define ONENAND_DATAIN_ERASE_VERIFY (0x15) -#define ONENAND_DATAIN_UNLOCK_START (0x08) -#define ONENAND_DATAIN_UNLOCK_END (0x09) -#define ONENAND_DATAIN_LOCK_START (0x0A) -#define ONENAND_DATAIN_LOCK_END (0x0B) -#define ONENAND_DATAIN_LOCKTIGHT_START (0x0C) -#define ONENAND_DATAIN_LOCKTIGHT_END (0x0D) -#define ONENAND_DATAIN_UNLOCK_ALL (0x0E) -#define ONENAND_DATAIN_COPYBACK_SRC (0x1000) -#define ONENAND_DATAIN_COPYBACK_DST (0x2000) -#define ONENAND_DATAIN_ACCESS_OTP (0x12) -#define ONENAND_DATAIN_ACCESS_MAIN (0x14) -#define ONENAND_DATAIN_PIPELINE_READ (0x4000) -#define ONENAND_DATAIN_PIPELINE_WRITE (0x4100) -#define ONENAND_DATAIN_RMW_LOAD (0x10) -#define ONENAND_DATAIN_RMW_MODIFY (0x11) - -/* - * Device ID Register F001h (R) - */ -#define ONENAND_DEVICE_DENSITY_SHIFT (4) -#define ONENAND_DEVICE_IS_DDP (1 << 3) -#define ONENAND_DEVICE_IS_DEMUX (1 << 2) -#define ONENAND_DEVICE_VCC_MASK (0x3) - -/* - * Version ID Register F002h (R) - */ -#define ONENAND_VERSION_PROCESS_SHIFT (8) - -/* - * Start Address 1 F100h (R/W) - */ -#define ONENAND_DDP_SHIFT (15) -#define ONENAND_DDP_CHIP0 (0) -#define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT) - -/* - * Start Buffer Register F200h (R/W) - */ -#define ONENAND_BSA_MASK (0x03) -#define ONENAND_BSA_SHIFT (8) -#define ONENAND_BSA_BOOTRAM (0 << 2) -#define ONENAND_BSA_DATARAM0 (2 << 2) -#define ONENAND_BSA_DATARAM1 (3 << 2) -#define ONENAND_BSC_MASK (0x03) - -/* - * Command Register F220h (R/W) - */ -#define ONENAND_CMD_READ (0x00) -#define ONENAND_CMD_READOOB (0x13) -#define ONENAND_CMD_PROG (0x80) -#define ONENAND_CMD_PROGOOB (0x1A) -#define ONENAND_CMD_UNLOCK (0x23) -#define ONENAND_CMD_LOCK (0x2A) -#define ONENAND_CMD_LOCK_TIGHT (0x2C) -#define ONENAND_CMD_UNLOCK_ALL (0x27) -#define ONENAND_CMD_ERASE (0x94) -#define ONENAND_CMD_RESET (0xF0) -#define ONENAND_CMD_OTP_ACCESS (0x65) -#define ONENAND_CMD_READID (0x90) -#define ONENAND_CMD_STARTADDR1 (0xE0) -#define ONENAND_CMD_WP_STATUS (0xE1) -#define ONENAND_CMD_PIPELINE_READ (0x01) -#define ONENAND_CMD_PIPELINE_WRITE (0x81) - -/* - * Command Mapping for S3C6400 OneNAND Controller - */ -#define ONENAND_AHB_ADDR (0x20000000) -#define ONENAND_DUMMY_ADDR (0x20400000) -#define ONENAND_CMD_SHIFT (24) -#define ONENAND_CMD_MAP_00 (0x0) -#define ONENAND_CMD_MAP_01 (0x1) -#define ONENAND_CMD_MAP_10 (0x2) -#define ONENAND_CMD_MAP_11 (0x3) -#define ONENAND_CMD_MAP_FF (0xF) - -/* - * Mask for Mapping table - */ -#define ONENAND_MEM_ADDR_MASK (0xffffff) -#define ONENAND_DDP_SHIFT_1Gb (21) -#define ONENAND_DDP_SHIFT_2Gb (22) -#define ONENAND_DDP_SHIFT_4Gb (23) -#define ONENAND_FBA_SHIFT (12) -#define ONENAND_FPA_SHIFT (6) -#define ONENAND_FSA_SHIFT (4) -#define ONENAND_FBA_MASK_128Mb (0xff) -#define ONENAND_FBA_MASK_256Mb (0x1ff) -#define ONENAND_FBA_MASK_512Mb (0x1ff) -#define ONENAND_FBA_MASK_1Gb_DDP (0x1ff) -#define ONENAND_FBA_MASK_1Gb (0x3ff) -#define ONENAND_FBA_MASK_2Gb_DDP (0x3ff) -#define ONENAND_FBA_MASK_2Gb (0x7ff) -#define ONENAND_FBA_MASK_4Gb_DDP (0x7ff) -#define ONENAND_FBA_MASK_4Gb (0xfff) -#define ONENAND_FPA_MASK (0x3f) -#define ONENAND_FSA_MASK (0x3) - -/* - * System Configuration 1 Register F221h (R, R/W) - */ -#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15) -#define ONENAND_SYS_CFG1_BRL_7 (7 << 12) -#define ONENAND_SYS_CFG1_BRL_6 (6 << 12) -#define ONENAND_SYS_CFG1_BRL_5 (5 << 12) -#define ONENAND_SYS_CFG1_BRL_4 (4 << 12) -#define ONENAND_SYS_CFG1_BRL_3 (3 << 12) -#define ONENAND_SYS_CFG1_BRL_10 (2 << 12) -#define ONENAND_SYS_CFG1_BRL_9 (1 << 12) -#define ONENAND_SYS_CFG1_BRL_8 (0 << 12) -#define ONENAND_SYS_CFG1_BRL_SHIFT (12) -#define ONENAND_SYS_CFG1_BL_32 (4 << 9) -#define ONENAND_SYS_CFG1_BL_16 (3 << 9) -#define ONENAND_SYS_CFG1_BL_8 (2 << 9) -#define ONENAND_SYS_CFG1_BL_4 (1 << 9) -#define ONENAND_SYS_CFG1_BL_CONT (0 << 9) -#define ONENAND_SYS_CFG1_BL_SHIFT (9) -#define ONENAND_SYS_CFG1_NO_ECC (1 << 8) -#define ONENAND_SYS_CFG1_RDY (1 << 7) -#define ONENAND_SYS_CFG1_INT (1 << 6) -#define ONENAND_SYS_CFG1_IOBE (1 << 5) -#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) - -/* - * Controller Status Register F240h (R) - */ -#define ONENAND_CTRL_ONGO (1 << 15) -#define ONENAND_CTRL_LOCK (1 << 14) -#define ONENAND_CTRL_LOAD (1 << 13) -#define ONENAND_CTRL_PROGRAM (1 << 12) -#define ONENAND_CTRL_ERASE (1 << 11) -#define ONENAND_CTRL_ERROR (1 << 10) -#define ONENAND_CTRL_RSTB (1 << 7) -#define ONENAND_CTRL_OTP_L (1 << 6) -#define ONENAND_CTRL_OTP_BL (1 << 5) - -/* - * Interrupt Status Register F241h (R) - */ -#define ONENAND_INT_MASTER (1 << 15) -#define ONENAND_INT_READ (1 << 7) -#define ONENAND_INT_WRITE (1 << 6) -#define ONENAND_INT_ERASE (1 << 5) -#define ONENAND_INT_RESET (1 << 4) -#define ONENAND_INT_CLEAR (0 << 0) - -/* - * NAND Flash Write Protection Status Register F24Eh (R) - */ -#define ONENAND_WP_US (1 << 2) -#define ONENAND_WP_LS (1 << 1) -#define ONENAND_WP_LTS (1 << 0) - -/* - * ECC Status Register FF00h (R) - */ -#define ONENAND_ECC_1BIT (1 << 0) -#define ONENAND_ECC_1BIT_ALL (0x5555) -#define ONENAND_ECC_2BIT (1 << 1) -#define ONENAND_ECC_2BIT_ALL (0xAAAA) - -/* - * One-Time Programmable (OTP) - */ -#define ONENAND_OTP_LOCK_OFFSET (14) - -/************************************************************* - * End of OneNAND Controller - *************************************************************/ - - -/* - * Interrupt - */ -#define ELFIN_VIC0_BASE_ADDR (0x71200000) -#define ELFIN_VIC1_BASE_ADDR (0x71300000) -#define oINTMOD (0x0C) // VIC INT SELECT (IRQ or FIQ) -#define oINTUNMSK (0x10) // VIC INT EN (Unmask by writing 1) -#define oINTMSK (0x14) // VIC INT EN CLEAR (Mask by writing 1) -#define oINTSUBMSK (0x1C) // VIC SOFT INT CLEAR -#define oVECTADDR (0xF00) // VIC ADDRESS - - - -/* - * Watchdog timer - */ -#define ELFIN_WATCHDOG_BASE 0x7E004000 - -#define WTCON_REG __REG(0x7E004004) -#define WTDAT_REG __REG(0x7E004008) -#define WTCNT_REG __REG(0x7E00400C) - - - -/* - * UART - */ -#define ELFIN_UART_BASE 0x7F005000 - -#define ELFIN_UART0_OFFSET 0x0000 -#define ELFIN_UART1_OFFSET 0x0400 -#define ELFIN_UART2_OFFSET 0x0800 -#define ELFIN_UART3_OFFSET 0x0c00 - -#define ULCON_OFFSET 0x00 -#define UCON_OFFSET 0x04 -#define UFCON_OFFSET 0x08 -#define UMCON_OFFSET 0x0C -#define UTRSTAT_OFFSET 0x10 -#define UERSTAT_OFFSET 0x14 -#define UFSTAT_OFFSET 0x18 -#define UMSTAT_OFFSET 0x1C -#define UTXH_OFFSET 0x20 -#define URXH_OFFSET 0x24 -#define UBRDIV_OFFSET 0x28 -#define UDIVSLOT_OFFSET 0x2C -#define UINTP_OFFSET 0x30 -#define UINTSP_OFFSET 0x34 -#define UINTM_OFFSET 0x38 - -#define ULCON0_REG __REG(0x7F005000) -#define UCON0_REG __REG(0x7F005004) -#define UFCON0_REG __REG(0x7F005008) -#define UMCON0_REG __REG(0x7F00500C) -#define UTRSTAT0_REG __REG(0x7F005010) -#define UERSTAT0_REG __REG(0x7F005014) -#define UFSTAT0_REG __REG(0x7F005018) -#define UMSTAT0_REG __REG(0x7F00501c) -#define UTXH0_REG __REG(0x7F005020) -#define URXH0_REG __REG(0x7F005024) -#define UBRDIV0_REG __REG(0x7F005028) -#define UDIVSLOT0_REG __REG(0x7F00502c) -#define UINTP0_REG __REG(0x7F005030) -#define UINTSP0_REG __REG(0x7F005034) -#define UINTM0_REG __REG(0x7F005038) - -#define ULCON1_REG __REG(0x7F005400) -#define UCON1_REG __REG(0x7F005404) -#define UFCON1_REG __REG(0x7F005408) -#define UMCON1_REG __REG(0x7F00540C) -#define UTRSTAT1_REG __REG(0x7F005410) -#define UERSTAT1_REG __REG(0x7F005414) -#define UFSTAT1_REG __REG(0x7F005418) -#define UMSTAT1_REG __REG(0x7F00541c) -#define UTXH1_REG __REG(0x7F005420) -#define URXH1_REG __REG(0x7F005424) -#define UBRDIV1_REG __REG(0x7F005428) -#define UDIVSLOT1_REG __REG(0x7F00542c) -#define UINTP1_REG __REG(0x7F005430) -#define UINTSP1_REG __REG(0x7F005434) -#define UINTM1_REG __REG(0x7F005438) - -#define UTRSTAT_TX_EMPTY BIT2 -#define UTRSTAT_RX_READY BIT0 -#define UART_ERR_MASK 0xF - - -/* - * PWM timer - */ -#define ELFIN_TIMER_BASE 0x7F006000 - -#define TCFG0_REG __REG(0x7F006000) -#define TCFG1_REG __REG(0x7F006004) -#define TCON_REG __REG(0x7F006008) -#define TCNTB0_REG __REG(0x7F00600c) -#define TCMPB0_REG __REG(0x7F006010) -#define TCNTO0_REG __REG(0x7F006014) -#define TCNTB1_REG __REG(0x7F006018) -#define TCMPB1_REG __REG(0x7F00601c) -#define TCNTO1_REG __REG(0x7F006020) -#define TCNTB2_REG __REG(0x7F006024) -#define TCMPB2_REG __REG(0x7F006028) -#define TCNTO2_REG __REG(0x7F00602c) -#define TCNTB3_REG __REG(0x7F006030) -#define TCMPB3_REG __REG(0x7F006034) -#define TCNTO3_REG __REG(0x7F006038) -#define TCNTB4_REG __REG(0x7F00603c) -#define TCNTO4_REG __REG(0x7F006040) - -/* Fields */ -#define fTCFG0_DZONE Fld(8,16) /* the dead zone length (= timer 0) */ -#define fTCFG0_PRE1 Fld(8,8) /* prescaler value for time 2,3,4 */ -#define fTCFG0_PRE0 Fld(8,0) /* prescaler value for time 0,1 */ -#define fTCFG1_MUX4 Fld(4,16) -/* bits */ -#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) -#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) -#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) -#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ -#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ -#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ -#define COUNT_4_ON (TCON_4_ONOFF*1) -#define COUNT_4_OFF (TCON_4_ONOFF*0) -#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ -#define TIMER3_ATLOAD_ON (TCON_3_AUTO*1) -#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) -#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ -#define TIMER3_IVT_ON (TCON_3_INVERT*1) -#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) -#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ -#define TIMER3_MANUP (TCON_3_MAN*1) -#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) -#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ -#define TIMER3_ON (TCON_3_ONOFF*1) -#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) -/* macros */ -#define GET_PRESCALE_TIMER4(x) FExtr((x), fTCFG0_PRE1) -#define GET_DIVIDER_TIMER4(x) FExtr((x), fTCFG1_MUX4) - -/* - * RTC Controller - */ -#define ELFIN_RTC_BASE 0x7e005000 - -#define RTCCON_REG __REG(0x7e005040) -#define TICNT_REG __REG(0x7e005044) -#define RTCALM_REG __REG(0x7e005050) -#define ALMSEC_REG __REG(0x7e005054) -#define ALMMIN_REG __REG(0x7e005058) -#define ALMHOUR_REG __REG(0x7e00505c) -#define ALMDATE_REG __REG(0x7e005060) -#define ALMMON_REG __REG(0x7e005064) -#define ALMYEAR_REG __REG(0x7e005068) -#define BCDSEC_REG __REG(0x7e005070) -#define BCDMIN_REG __REG(0x7e005074) -#define BCDHOUR_REG __REG(0x7e005078) -#define BCDDATE_REG __REG(0x7e00507c) -#define BCDDAY_REG __REG(0x7e005080) -#define BCDMON_REG __REG(0x7e005084) -#define BCDYEAR_REG __REG(0x7e005088) - -/* - * USB2.0 HS OTG (Chapter 26) - */ -#define USBOTG_LINK_BASE (0x7C000000) -#define USBOTG_PHY_BASE (0x7C100000) - -/* Core Global Registers */ -#define S3C_OTG_GOTGCTL (USBOTG_LINK_BASE + 0x000) /* OTG Control & Status */ -#define S3C_OTG_GOTGINT (USBOTG_LINK_BASE + 0x004) /* OTG Interrupt */ -#define S3C_OTG_GAHBCFG (USBOTG_LINK_BASE + 0x008) /* Core AHB Configuration */ -#define S3C_OTG_GUSBCFG (USBOTG_LINK_BASE + 0x00C) /* Core USB Configuration */ -#define S3C_OTG_GRSTCTL (USBOTG_LINK_BASE + 0x010) /* Core Reset */ -#define S3C_OTG_GINTSTS (USBOTG_LINK_BASE + 0x014) /* Core Interrupt */ -#define S3C_OTG_GINTMSK (USBOTG_LINK_BASE + 0x018) /* Core Interrupt Mask */ -#define S3C_OTG_GRXSTSR (USBOTG_LINK_BASE + 0x01C) /* Receive Status Debug Read/Status Read */ -#define S3C_OTG_GRXSTSP (USBOTG_LINK_BASE + 0x020) /* Receive Status Debug Pop/Status Pop */ -#define S3C_OTG_GRXFSIZ (USBOTG_LINK_BASE + 0x024) /* Receive FIFO Size */ -#define S3C_OTG_GNPTXFSIZ (USBOTG_LINK_BASE + 0x028) /* Non-Periodic Transmit FIFO Size */ -#define S3C_OTG_GNPTXSTS (USBOTG_LINK_BASE + 0x02C) /* Non-Periodic Transmit FIFO/Queue Status */ - -#define S3C_OTG_HPTXFSIZ (USBOTG_LINK_BASE + 0x100) /* Host Periodic Transmit FIFO Size */ -#define S3C_OTG_DPTXFSIZ1 (USBOTG_LINK_BASE + 0x104) /* Device Periodic Transmit FIFO-1 Size */ -#define S3C_OTG_DPTXFSIZ2 (USBOTG_LINK_BASE + 0x108) /* Device Periodic Transmit FIFO-2 Size */ -#define S3C_OTG_DPTXFSIZ3 (USBOTG_LINK_BASE + 0x10C) /* Device Periodic Transmit FIFO-3 Size */ -#define S3C_OTG_DPTXFSIZ4 (USBOTG_LINK_BASE + 0x110) /* Device Periodic Transmit FIFO-4 Size */ -#define S3C_OTG_DPTXFSIZ5 (USBOTG_LINK_BASE + 0x114) /* Device Periodic Transmit FIFO-5 Size */ -#define S3C_OTG_DPTXFSIZ6 (USBOTG_LINK_BASE + 0x118) /* Device Periodic Transmit FIFO-6 Size */ -#define S3C_OTG_DPTXFSIZ7 (USBOTG_LINK_BASE + 0x11C) /* Device Periodic Transmit FIFO-7 Size */ -#define S3C_OTG_DPTXFSIZ8 (USBOTG_LINK_BASE + 0x120) /* Device Periodic Transmit FIFO-8 Size */ -#define S3C_OTG_DPTXFSIZ9 (USBOTG_LINK_BASE + 0x124) /* Device Periodic Transmit FIFO-9 Size */ -#define S3C_OTG_DPTXFSIZ10 (USBOTG_LINK_BASE + 0x128) /* Device Periodic Transmit FIFO-10 Size */ -#define S3C_OTG_DPTXFSIZ11 (USBOTG_LINK_BASE + 0x12C) /* Device Periodic Transmit FIFO-11 Size */ -#define S3C_OTG_DPTXFSIZ12 (USBOTG_LINK_BASE + 0x130) /* Device Periodic Transmit FIFO-12 Size */ -#define S3C_OTG_DPTXFSIZ13 (USBOTG_LINK_BASE + 0x134) /* Device Periodic Transmit FIFO-13 Size */ -#define S3C_OTG_DPTXFSIZ14 (USBOTG_LINK_BASE + 0x138) /* Device Periodic Transmit FIFO-14 Size */ -#define S3C_OTG_DPTXFSIZ15 (USBOTG_LINK_BASE + 0x13C) /* Device Periodic Transmit FIFO-15 Size */ - -/* Host Global Registers */ -#define S3C_OTG_HCFG (USBOTG_LINK_BASE + 0x400) /* Host Configuration */ -#define S3C_OTG_HFIR (USBOTG_LINK_BASE + 0x404) /* Host Frame Interval */ -#define S3C_OTG_HFNUM (USBOTG_LINK_BASE + 0x408) /* Host Frame Number/Frame Time Remaining */ -#define S3C_OTG_HPTXSTS (USBOTG_LINK_BASE + 0x410) /* Host Periodic Transmit FIFO/Queue Status */ -#define S3C_OTG_HAINT (USBOTG_LINK_BASE + 0x414) /* Host All Channels Interrupt */ -#define S3C_OTG_HAINTMSK (USBOTG_LINK_BASE + 0x418) /* Host All Channels Interrupt Mask */ - -/* Host Port Control & Status Registers */ -#define S3C_OTG_HPRT (USBOTG_LINK_BASE + 0x440) /* Host Port Control & Status */ - -/* Host Channel-Specific Registers */ -#define S3C_OTG_HCCHAR0 (USBOTG_LINK_BASE + 0x500) /* Host Channel-0 Characteristics */ -#define S3C_OTG_HCSPLT0 (USBOTG_LINK_BASE + 0x504) /* Host Channel-0 Split Control */ -#define S3C_OTG_HCINT0 (USBOTG_LINK_BASE + 0x508) /* Host Channel-0 Interrupt */ -#define S3C_OTG_HCINTMSK0 (USBOTG_LINK_BASE + 0x50C) /* Host Channel-0 Interrupt Mask */ -#define S3C_OTG_HCTSIZ0 (USBOTG_LINK_BASE + 0x510) /* Host Channel-0 Transfer Size */ -#define S3C_OTG_HCDMA0 (USBOTG_LINK_BASE + 0x514) /* Host Channel-0 DMA Address */ - - -/* Device Global Registers */ -#define S3C_OTG_DCFG (USBOTG_LINK_BASE + 0x800) /* Device Configuration */ -#define S3C_OTG_DCTL (USBOTG_LINK_BASE + 0x804) /* Device Control */ -#define S3C_OTG_DSTS (USBOTG_LINK_BASE + 0x808) /* Device Status */ -#define S3C_OTG_DIEPMSK (USBOTG_LINK_BASE + 0x810) /* Device IN Endpoint Common Interrupt Mask */ -#define S3C_OTG_DOEPMSK (USBOTG_LINK_BASE + 0x814) /* Device OUT Endpoint Common Interrupt Mask */ -#define S3C_OTG_DAINT (USBOTG_LINK_BASE + 0x818) /* Device All Endpoints Interrupt */ -#define S3C_OTG_DAINTMSK (USBOTG_LINK_BASE + 0x81C) /* Device All Endpoints Interrupt Mask */ -#define S3C_OTG_DTKNQR1 (USBOTG_LINK_BASE + 0x820) /* Device IN Token Sequence Learning Queue Read 1 */ -#define S3C_OTG_DTKNQR2 (USBOTG_LINK_BASE + 0x824) /* Device IN Token Sequence Learning Queue Read 2 */ -#define S3C_OTG_DVBUSDIS (USBOTG_LINK_BASE + 0x828) /* Device VBUS Discharge Time */ -#define S3C_OTG_DVBUSPULSE (USBOTG_LINK_BASE + 0x82C) /* Device VBUS Pulsing Time */ -#define S3C_OTG_DTKNQR3 (USBOTG_LINK_BASE + 0x830) /* Device IN Token Sequence Learning Queue Read 3 */ -#define S3C_OTG_DTKNQR4 (USBOTG_LINK_BASE + 0x834) /* Device IN Token Sequence Learning Queue Read 4 */ - -/* Device Logical IN Endpoint-Specific Registers */ -#define S3C_OTG_DIEPCTL0 (USBOTG_LINK_BASE + 0x900) /* Device IN Endpoint 0 Control */ -#define S3C_OTG_DIEPINT0 (USBOTG_LINK_BASE + 0x908) /* Device IN Endpoint 0 Interrupt */ -#define S3C_OTG_DIEPTSIZ0 (USBOTG_LINK_BASE + 0x910) /* Device IN Endpoint 0 Transfer Size */ -#define S3C_OTG_DIEPDMA0 (USBOTG_LINK_BASE + 0x914) /* Device IN Endpoint 0 DMA Address */ - -/* Device Logical OUT Endpoint-Specific Registers */ -#define S3C_OTG_DOEPCTL0 (USBOTG_LINK_BASE + 0xB00) /* Device OUT Endpoint 0 Control */ -#define S3C_OTG_DOEPINT0 (USBOTG_LINK_BASE + 0xB08) /* Device OUT Endpoint 0 Interrupt */ -#define S3C_OTG_DOEPTSIZ0 (USBOTG_LINK_BASE + 0xB10) /* Device OUT Endpoint 0 Transfer Size */ -#define S3C_OTG_DOEPDMA0 (USBOTG_LINK_BASE + 0xB14) /* Device OUT Endpoint 0 DMA Address */ - -/* Power & clock gating registers */ -#define S3C_OTG_PCGCCTRL (USBOTG_LINK_BASE + 0xE00) - -/* Endpoint FIFO address */ -#define S3C_OTG_EP0_FIFO (USBOTG_LINK_BASE + 0x1000) - - - -/* OTG PHY CORE REGISTERS */ -#define S3C_OTG_PHYPWR (USBOTG_PHY_BASE+0x00) -#define S3C_OTG_PHYCTRL (USBOTG_PHY_BASE+0x04) -#define S3C_OTG_RSTCON (USBOTG_PHY_BASE+0x08) - -/* include common stuff */ -#ifndef __ASSEMBLY__ -#if 0 -static inline S3C2410_SDI * S3C2410_GetBase_SDI(void) -{ - return (S3C2410_SDI *)ELFIN_SDI_BASE; -} -#endif -#else /* #ifndef __ASSEMBLY__ */ - -/* watchdog */ -#define WTCON_OFFSET 0x00 - -/* LCD controller */ -#define LCDBGCON_OFFSET 0x5c - -#endif /* #ifndef __ASSEMBLY__ */ - -/* PENDING BIT */ -#define BIT_EINT0 (0x1) -#define BIT_EINT1 (0x1<<1) -#define BIT_EINT2 (0x1<<2) -#define BIT_EINT3 (0x1<<3) -#define BIT_EINT4_7 (0x1<<4) -#define BIT_EINT8_23 (0x1<<5) -#define BIT_BAT_FLT (0x1<<7) -#define BIT_TICK (0x1<<8) -#define BIT_WDT (0x1<<9) -#define BIT_TIMER0 (0x1<<10) -#define BIT_TIMER1 (0x1<<11) -#define BIT_TIMER2 (0x1<<12) -#define BIT_TIMER3 (0x1<<13) -#define BIT_TIMER4 (0x1<<14) -#define BIT_UART2 (0x1<<15) -#define BIT_LCD (0x1<<16) -#define BIT_DMA0 (0x1<<17) -#define BIT_DMA1 (0x1<<18) -#define BIT_DMA2 (0x1<<19) -#define BIT_DMA3 (0x1<<20) -#define BIT_SDI (0x1<<21) -#define BIT_SPI0 (0x1<<22) -#define BIT_UART1 (0x1<<23) -#define BIT_USBH (0x1<<26) -#define BIT_IIC (0x1<<27) -#define BIT_UART0 (0x1<<28) -#define BIT_SPI1 (0x1<<29) -#define BIT_RTC (0x1<<30) -#define BIT_ADC (0x1<<31) -#define BIT_ALLMSK (0xFFFFFFFF) - -#endif /*__S3C6410_H__*/ diff --git a/qiboot/include/serial-s3c24xx.h b/qiboot/include/serial-s3c24xx.h deleted file mode 100644 index 6209401..0000000 --- a/qiboot/include/serial-s3c24xx.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#ifndef __SERIAL_S3C24XX_H__ -#define __SERIAL_S3C24XX_H__ - -#define UART0 0 -#define UART1 1 -#define UART2 2 - -#define rGPHCON (*(volatile unsigned *)0x56000070) /*UART 0 Line control*/ - -#define rULCON0 (*(volatile unsigned *)0x50000000) /*UART 0 Line control*/ -#define rUCON0 (*(volatile unsigned *)0x50000004) /*UART 0 Control*/ -#define rUFCON0 (*(volatile unsigned *)0x50000008) /*UART 0 FIFO control*/ -#define rUMCON0 (*(volatile unsigned *)0x5000000c) /*UART 0 Modem control*/ -#define rUTRSTAT0 (*(volatile unsigned *)0x50000010) /*UART 0 Tx/Rx status*/ -#define rUERSTAT0 (*(volatile unsigned *)0x50000014) /*UART 0 Rx error status*/ -#define rUFSTAT0 (*(volatile unsigned *)0x50000018) /*UART 0 FIFO status*/ -#define rUMSTAT0 (*(volatile unsigned *)0x5000001c) /*UART 0 Modem status*/ -#define rUBRDIV0 (*(volatile unsigned *)0x50000028) /*UART 0 Baud rate divisor*/ - -#define rULCON1 (*(volatile unsigned *)0x50004000) /*UART 1 Line control*/ -#define rUCON1 (*(volatile unsigned *)0x50004004) /*UART 1 Control*/ -#define rUFCON1 (*(volatile unsigned *)0x50004008) /*UART 1 FIFO control*/ -#define rUMCON1 (*(volatile unsigned *)0x5000400c) /*UART 1 Modem control*/ -#define rUTRSTAT1 (*(volatile unsigned *)0x50004010) /*UART 1 Tx/Rx status*/ -#define rUERSTAT1 (*(volatile unsigned *)0x50004014) /*UART 1 Rx error status*/ -#define rUFSTAT1 (*(volatile unsigned *)0x50004018) /*UART 1 FIFO status*/ -#define rUMSTAT1 (*(volatile unsigned *)0x5000401c) /*UART 1 Modem status*/ -#define rUBRDIV1 (*(volatile unsigned *)0x50004028) /*UART 1 Baud rate divisor*/ - -#define rULCON2 (*(volatile unsigned *)0x50008000) /*UART 2 Line control*/ -#define rUCON2 (*(volatile unsigned *)0x50008004) /*UART 2 Control*/ -#define rUFCON2 (*(volatile unsigned *)0x50008008) /*UART 2 FIFO control*/ -#define rUTRSTAT2 (*(volatile unsigned *)0x50008010) /*UART 2 Tx/Rx status*/ -#define rUERSTAT2 (*(volatile unsigned *)0x50008014) /*UART 2 Rx error status*/ -#define rUFSTAT2 (*(volatile unsigned *)0x50008018) /*UART 2 FIFO status*/ -#define rUBRDIV2 (*(volatile unsigned *)0x50008028) /*UART 2 Baud rate divisor*/ - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x50000024) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x50004024) -#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) -#define RdURXH2() (*(volatile unsigned char *)0x50008024) - -extern void serial_init_115200_s3c24xx(const int uart, const int pclk_MHz); -extern void serial_putc_s3c24xx(const int uart, const char c); -extern int puts(const char *string); - -#endif diff --git a/qiboot/include/serial-s3c64xx.h b/qiboot/include/serial-s3c64xx.h deleted file mode 100644 index bab0872..0000000 --- a/qiboot/include/serial-s3c64xx.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#ifndef __SERIAL_S3C64XX_H__ -#define __SERIAL_S3C64XX_H__ - -#define UART0 0 -#define UART1 1 -#define UART2 2 - -#define rGPHCON (*(volatile unsigned *)0x56000070) /*UART 0 Line control*/ - -#define rULCON0 (*(volatile unsigned *)0x50000000) /*UART 0 Line control*/ -#define rUCON0 (*(volatile unsigned *)0x50000004) /*UART 0 Control*/ -#define rUFCON0 (*(volatile unsigned *)0x50000008) /*UART 0 FIFO control*/ -#define rUMCON0 (*(volatile unsigned *)0x5000000c) /*UART 0 Modem control*/ -#define rUTRSTAT0 (*(volatile unsigned *)0x50000010) /*UART 0 Tx/Rx status*/ -#define rUERSTAT0 (*(volatile unsigned *)0x50000014) /*UART 0 Rx error status*/ -#define rUFSTAT0 (*(volatile unsigned *)0x50000018) /*UART 0 FIFO status*/ -#define rUMSTAT0 (*(volatile unsigned *)0x5000001c) /*UART 0 Modem status*/ -#define rUBRDIV0 (*(volatile unsigned *)0x50000028) /*UART 0 Baud rate divisor*/ - -#define rULCON1 (*(volatile unsigned *)0x50004000) /*UART 1 Line control*/ -#define rUCON1 (*(volatile unsigned *)0x50004004) /*UART 1 Control*/ -#define rUFCON1 (*(volatile unsigned *)0x50004008) /*UART 1 FIFO control*/ -#define rUMCON1 (*(volatile unsigned *)0x5000400c) /*UART 1 Modem control*/ -#define rUTRSTAT1 (*(volatile unsigned *)0x50004010) /*UART 1 Tx/Rx status*/ -#define rUERSTAT1 (*(volatile unsigned *)0x50004014) /*UART 1 Rx error status*/ -#define rUFSTAT1 (*(volatile unsigned *)0x50004018) /*UART 1 FIFO status*/ -#define rUMSTAT1 (*(volatile unsigned *)0x5000401c) /*UART 1 Modem status*/ -#define rUBRDIV1 (*(volatile unsigned *)0x50004028) /*UART 1 Baud rate divisor*/ - -#define rULCON2 (*(volatile unsigned *)0x50008000) /*UART 2 Line control*/ -#define rUCON2 (*(volatile unsigned *)0x50008004) /*UART 2 Control*/ -#define rUFCON2 (*(volatile unsigned *)0x50008008) /*UART 2 FIFO control*/ -#define rUTRSTAT2 (*(volatile unsigned *)0x50008010) /*UART 2 Tx/Rx status*/ -#define rUERSTAT2 (*(volatile unsigned *)0x50008014) /*UART 2 Rx error status*/ -#define rUFSTAT2 (*(volatile unsigned *)0x50008018) /*UART 2 FIFO status*/ -#define rUBRDIV2 (*(volatile unsigned *)0x50008028) /*UART 2 Baud rate divisor*/ - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x50000024) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x50004024) -#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) -#define RdURXH2() (*(volatile unsigned char *)0x50008024) - -extern void serial_init_115200_s3c64xx(const int uart, const int pclk_MHz); -extern void serial_putc_s3c64xx(const int uart, const char c); -extern int puts(const char *string); - -#endif diff --git a/qiboot/include/setup.h b/qiboot/include/setup.h deleted file mode 100644 index 89df4dc..0000000 --- a/qiboot/include/setup.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * linux/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See linux/Documentation/arm/Setup - * for more info. - * - * NOTE: - * This file contains two ways to pass information from the boot - * loader to the kernel. The old struct param_struct is deprecated, - * but it will be kept in the kernel for 5 years from now - * (2001). This will allow boot loaders to convert to the new struct - * tag way. - */ -#ifndef __ASMARM_SETUP_H -#define __ASMARM_SETUP_H - -/* - * Usage: - * - do not go blindly adding fields, add them at the end - * - when adding fields, don't rely on the address until - * a patch from me has been released - * - unused fields should be zero (for future expansion) - * - this structure is relatively short-lived - only - * guaranteed to contain useful data in setup_arch() - */ -#define COMMAND_LINE_SIZE 1024 - -/* This is the old deprecated way to pass parameters to the kernel */ -struct param_struct { - union { - struct { - unsigned long page_size; /* 0 */ - unsigned long nr_pages; /* 4 */ - unsigned long ramdisk_size; /* 8 */ - unsigned long flags; /* 12 */ -#define FLAG_READONLY 1 -#define FLAG_RDLOAD 4 -#define FLAG_RDPROMPT 8 - unsigned long rootdev; /* 16 */ - unsigned long video_num_cols; /* 20 */ - unsigned long video_num_rows; /* 24 */ - unsigned long video_x; /* 28 */ - unsigned long video_y; /* 32 */ - unsigned long memc_control_reg; /* 36 */ - unsigned char sounddefault; /* 40 */ - unsigned char adfsdrives; /* 41 */ - unsigned char bytes_per_char_h; /* 42 */ - unsigned char bytes_per_char_v; /* 43 */ - unsigned long pages_in_bank[4]; /* 44 */ - unsigned long pages_in_vram; /* 60 */ - unsigned long initrd_start; /* 64 */ - unsigned long initrd_size; /* 68 */ - unsigned long rd_start; /* 72 */ - unsigned long system_rev; /* 76 */ - unsigned long system_serial_low; /* 80 */ - unsigned long system_serial_high; /* 84 */ - unsigned long mem_fclk_21285; /* 88 */ - } s; - char unused[256]; - } u1; - union { - char paths[8][128]; - struct { - unsigned long magic; - char n[1024 - sizeof(unsigned long)]; - } s; - } u2; - char commandline[COMMAND_LINE_SIZE]; -}; - - -/* - * The new way of passing information: a list of tagged entries - */ - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* describes where the compressed ramdisk image lives (virtual address) */ -/* - * this one accidentally used virtual addresses - as such, - * its depreciated. - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* acorn RiscPC specific information */ -#define ATAG_ACORN 0x41000101 - -struct tag_acorn { - u32 memc_control_reg; - u32 vram_pages; - u8 sounddefault; - u8 adfsdrives; -}; - -/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ -#define ATAG_MEMCLK 0x41000402 - -struct tag_memclk { - u32 fmemclk; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - - /* - * Acorn specific - */ - struct tag_acorn acorn; - - /* - * DC21285 specific - */ - struct tag_memclk memclk; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define __tag __attribute__((unused, __section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - unsigned long end; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -extern struct meminfo meminfo; - -#endif diff --git a/qiboot/include/smdk6410.h b/qiboot/include/smdk6410.h deleted file mode 100644 index a438170..0000000 --- a/qiboot/include/smdk6410.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_MODE__ -#include -extern const struct board_api board_api_smdk6410; -#endif - -#define TEXT_BASE_SMDK6410 0x53000000 diff --git a/qiboot/openocd-openmoko-debug-6410.cfg b/qiboot/openocd-openmoko-debug-6410.cfg deleted file mode 100644 index a8ac051..0000000 --- a/qiboot/openocd-openmoko-debug-6410.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# ARM1176 / s3c6410 OpenOCD config suitable for Openmoko Debug board usage - -telnet_port 4444 -gdb_port 3333 -interface ft2232 -jtag_speed 18 -ft2232_layout oocdlink - -#Info: 446 309386 jtag.c:1410 jtag_examine_chain(): JTAG device found: 0x2b900f0f (Manufacturer: 0x787, Part: 0xb900, Version: 0x2) -#Info: 447 309386 jtag.c:1410 jtag_examine_chain(): JTAG device found: 0x07b76f0f (Manufacturer: 0x787, Part: 0x7b76, Version: 0x0) -jtag_device 4 0x1 0xF 0xE -jtag_device 5 0x1 0x1F 0x1E - -reset_config trst_and_srst -target create target0 arm11 -endian little -chain-position 1 -variant arm11 - diff --git a/qiboot/src/blink_led.c b/qiboot/src/blink_led.c deleted file mode 100644 index 6bac9e7..0000000 --- a/qiboot/src/blink_led.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include "blink_led.h" - -int delay(int time) -{ - int i=0; - for(i=0;i - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __BLINK_LED_H -#define __BLINK_LED_H - -#define GPBCON (*(volatile unsigned *)0x56000010) -#define GPBDAT (*(volatile unsigned *)0x56000014) -#define GPBDW (*(volatile unsigned *)0x56000018) -#define ORANGE_OFF() (GPBDAT &= ~(0x1)) -#define BLUE_OFF() (GPBDAT &= ~(0x2)) -#define ORANGE_ON() (GPBDAT |= (0x1)) -#define BLUE_ON() (GPBDAT |= (0x2)) - -int orange_on(int times); -int blue_on(int times); -int blink_led(void); -int delay(int time); - -#endif /* __BLINK_LED_H */ diff --git a/qiboot/src/common.h b/qiboot/src/common.h deleted file mode 100644 index 055dec2..0000000 --- a/qiboot/src/common.h +++ /dev/null @@ -1,681 +0,0 @@ -/* - * (C) Copyright 2000-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __COMMON_H_ -#define __COMMON_H_ 1 - -#undef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -typedef unsigned char uchar; -typedef volatile unsigned long vu_long; -typedef volatile unsigned short vu_short; -typedef volatile unsigned char vu_char; - -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) -#include -#endif -#if defined(CONFIG_8xx) -#include -#if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \ - defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ - defined(CONFIG_MPC859DSL) || \ - defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \ - defined(CONFIG_MPC866P) -# define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC870) \ - || defined(CONFIG_MPC875) \ - || defined(CONFIG_MPC880) \ - || defined(CONFIG_MPC885) -# define CONFIG_MPC885_FAMILY 1 -#endif -#if defined(CONFIG_MPC860) \ - || defined(CONFIG_MPC860T) \ - || defined(CONFIG_MPC866_FAMILY) \ - || defined(CONFIG_MPC885_FAMILY) -# define CONFIG_MPC86x 1 -#endif -#elif defined(CONFIG_5xx) -#include -#elif defined(CONFIG_MPC5xxx) -#include -#elif defined(CONFIG_MPC512X) -#include -#include -#elif defined(CONFIG_MPC8220) -#include -#elif defined(CONFIG_8260) -#if defined(CONFIG_MPC8247) \ - || defined(CONFIG_MPC8248) \ - || defined(CONFIG_MPC8271) \ - || defined(CONFIG_MPC8272) -#define CONFIG_MPC8272_FAMILY 1 -#endif -#if defined(CONFIG_MPC8272_FAMILY) -#define CONFIG_MPC8260 1 -#endif -#include -#endif -#ifdef CONFIG_MPC86xx -#include -#include -#endif -#ifdef CONFIG_MPC85xx -#include -#include -#endif -#ifdef CONFIG_MPC83XX -#include -#include -#endif -#ifdef CONFIG_4xx -#include -#endif -#ifdef CONFIG_HYMOD -#include -#endif -#ifdef CONFIG_ARM -#define asmlinkage /* nothing */ -#endif -#ifdef CONFIG_BLACKFIN -#include -#endif - -#include -#include -#include - -#ifdef DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#define debugX(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args); -#else -#define debug(fmt,args...) -#define debugX(level,fmt,args...) -#endif /* DEBUG */ - -#define BUG() do { \ - printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ - panic("BUG!"); \ -} while (0) -#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) - -typedef void (interrupt_handler_t)(void *); - -#include /* boot information for Linux kernel */ -#include /* global data used for startup functions */ - -/* - * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards - * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards - * and for the TQM885D board - */ -#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) -# ifndef CONFIG_TQM8xxM -# define CONFIG_TQM8xxM -# endif -#endif -#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \ - defined(CONFIG_TQM885D) -# ifndef CONFIG_TQM8xxL -# define CONFIG_TQM8xxL -# endif -#endif - -#ifndef CONFIG_SERIAL_MULTI - -#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \ - || defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \ - || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) - -#define CONFIG_SERIAL_MULTI 1 - -#endif - -#endif /* CONFIG_SERIAL_MULTI */ - -/* - * General Purpose Utilities - */ -#define min(X, Y) \ - ({ typeof (X) __x = (X), __y = (Y); \ - (__x < __y) ? __x : __y; }) - -#define max(X, Y) \ - ({ typeof (X) __x = (X), __y = (Y); \ - (__x > __y) ? __x : __y; }) - - -/* - * Function Prototypes - */ - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -void serial_buffered_init (void); -void serial_buffered_putc (const char); -void serial_buffered_puts (const char *); -int serial_buffered_getc (void); -int serial_buffered_tstc (void); -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - -void hang (void) __attribute__ ((noreturn)); - -/* */ -long int initdram (int); -int display_options (void); -void print_size (ulong, const char *); -int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen); - -/* common/main.c */ -void main_loop (void); -int run_command (const char *cmd, int flag); -int readline (const char *const prompt); -int readline_into_buffer (const char *const prompt, char * buffer); -int parse_line (char *, char *[]); -void init_cmd_timeout(void); -void reset_cmd_timeout(void); - -/* lib_$(ARCH)/board.c */ -void board_init_f (ulong) __attribute__ ((noreturn)); -void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); -int checkboard (void); -int checkflash (void); -int checkdram (void); -char * strmhz(char *buf, long hz); -int last_stage_init(void); -extern ulong monitor_flash_len; -#ifdef CFG_ID_EEPROM -int mac_read_from_eeprom(void); -#endif - -/* common/flash.c */ -void flash_perror (int); - -/* common/cmd_autoscript.c */ -int autoscript (ulong addr, const char *fit_uname); - -extern ulong load_addr; /* Default Load Address */ - -/* common/cmd_nvedit.c */ -int env_init (void); -void env_relocate (void); -int envmatch (uchar *, int); -char *getenv (char *); -int getenv_r (char *name, char *buf, unsigned len); -int saveenv (void); -#ifdef CONFIG_PPC /* ARM version to be fixed! */ -void inline setenv (char *, char *); -#else -void setenv (char *, char *); -#ifdef CONFIG_HAS_UID -void forceenv (char *, char *); -#endif -#endif /* CONFIG_PPC */ -#ifdef CONFIG_ARM -# include -# include -# include /* ARM version to be fixed! */ -#endif /* CONFIG_ARM */ -#ifdef CONFIG_I386 /* x86 version to be fixed! */ -# include -#endif /* CONFIG_I386 */ - -#ifdef CONFIG_AUTO_COMPLETE -int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); -#endif - -void pci_init (void); -void pci_init_board(void); -void pciinfo (int, int); - -#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) - int pci_pre_init (struct pci_controller * ); -#endif - -#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX)) -# if defined(CFG_PCI_TARGET_INIT) - void pci_target_init (struct pci_controller *); -# endif -# if defined(CFG_PCI_MASTER_INIT) - void pci_master_init (struct pci_controller *); -# endif - int is_pci_host (struct pci_controller *); -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) - void pcie_setup_hoses(int busno); -#endif -#endif - -int misc_init_f (void); -int misc_init_r (void); - -/* common/exports.c */ -void jumptable_init(void); - -/* api/api.c */ -void api_init (void); - -/* common/memsize.c */ -long get_ram_size (volatile long *, long); - -/* $(BOARD)/$(BOARD).c */ -void reset_phy (void); -void fdc_hw_init (void); - -/* $(BOARD)/eeprom.c */ -void eeprom_init (void); -#ifndef CONFIG_SPI -int eeprom_probe (unsigned dev_addr, unsigned offset); -#endif -int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); -int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); -#ifdef CONFIG_LWMON -extern uchar pic_read (uchar reg); -extern void pic_write (uchar reg, uchar val); -#endif - -/* - * Set this up regardless of board - * type, to prevent errors. - */ -#if defined(CONFIG_SPI) || !defined(CFG_I2C_EEPROM_ADDR) -# define CFG_DEF_EEPROM_ADDR 0 -#else -# define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR -#endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */ - -#if defined(CONFIG_SPI) -extern void spi_init_f (void); -extern void spi_init_r (void); -extern ssize_t spi_read (uchar *, int, uchar *, int); -extern ssize_t spi_write (uchar *, int, uchar *, int); -#endif - -#ifdef CONFIG_RPXCLASSIC -void rpxclassic_init (void); -#endif - -void rpxlite_init (void); - -#ifdef CONFIG_MBX -/* $(BOARD)/mbx8xx.c */ -void mbx_init (void); -void board_serial_init (void); -void board_ether_init (void); -#endif - -#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \ - defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \ - defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) || \ - defined(CONFIG_V38B) -void board_get_enetaddr (uchar *addr); -#endif - -#ifdef CONFIG_HERMES -/* $(BOARD)/hermes.c */ -void hermes_start_lxt980 (int speed); -#endif - -#ifdef CONFIG_EVB64260 -void evb64260_init(void); -void debug_led(int, int); -void display_mem_map(void); -void perform_soft_reset(void); -#endif - -void load_sernum_ethaddr (void); - -/* $(BOARD)/$(BOARD).c */ -int board_early_init_f (void); -int board_late_init (void); -int board_postclk_init (void); /* after clocks/timebase, before env/serial */ -int board_early_init_r (void); -void board_poweroff (void); - -#if defined(CFG_DRAM_TEST) -int testdram(void); -#endif /* CFG_DRAM_TEST */ - -/* $(CPU)/start.S */ -#if defined(CONFIG_5xx) || \ - defined(CONFIG_8xx) -uint get_immr (uint); -#endif -uint get_pir (void); -#if defined(CONFIG_MPC5xxx) -uint get_svr (void); -#endif -uint get_pvr (void); -uint get_svr (void); -uint rd_ic_cst (void); -void wr_ic_cst (uint); -void wr_ic_adr (uint); -uint rd_dc_cst (void); -void wr_dc_cst (uint); -void wr_dc_adr (uint); -int icache_status (void); -void icache_enable (void); -void icache_disable(void); -int dcache_status (void); -void dcache_enable (void); -void dcache_disable(void); -void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); -ulong get_endaddr (void); -void trap_init (ulong); -#if defined (CONFIG_4xx) || \ - defined (CONFIG_MPC5xxx) || \ - defined (CONFIG_74xx_7xx) || \ - defined (CONFIG_74x) || \ - defined (CONFIG_75x) || \ - defined (CONFIG_74xx) || \ - defined (CONFIG_MPC8220) || \ - defined (CONFIG_MPC85xx) || \ - defined (CONFIG_MPC86xx) || \ - defined (CONFIG_MPC83XX) -unsigned char in8(unsigned int); -void out8(unsigned int, unsigned char); -unsigned short in16(unsigned int); -unsigned short in16r(unsigned int); -void out16(unsigned int, unsigned short value); -void out16r(unsigned int, unsigned short value); -unsigned long in32(unsigned int); -unsigned long in32r(unsigned int); -void out32(unsigned int, unsigned long value); -void out32r(unsigned int, unsigned long value); -void ppcDcbf(unsigned long value); -void ppcDcbi(unsigned long value); -void ppcSync(void); -void ppcDcbz(unsigned long value); -#endif -#if defined (CONFIG_MICROBLAZE) -unsigned short in16(unsigned int); -void out16(unsigned int, unsigned short value); -#endif - -#if defined (CONFIG_MPC83XX) -void ppcDWload(unsigned int *addr, unsigned int *ret); -void ppcDWstore(unsigned int *addr, unsigned int *value); -#endif - -/* $(CPU)/cpu.c */ -int checkcpu (void); -int checkicache (void); -int checkdcache (void); -void upmconfig (unsigned int, unsigned int *, unsigned int); -ulong get_tbclk (void); -void reset_cpu (ulong addr); -#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) -void ft_cpu_setup(void *blob, bd_t *bd); -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif -#endif - - -/* $(CPU)/serial.c */ -int serial_init (void); -void serial_addr (unsigned int); -void serial_setbrg (void); -void serial_putc (const char); -void serial_putc_raw(const char); -void serial_puts (const char *); -int serial_getc (void); -int serial_tstc (void); - -void _serial_setbrg (const int); -void _serial_putc (const char, const int); -void _serial_putc_raw(const char, const int); -void _serial_puts (const char *, const int); -int _serial_getc (const int); -int _serial_tstc (const int); - -/* $(CPU)/speed.c */ -int get_clocks (void); -int get_clocks_866 (void); -int sdram_adjust_866 (void); -int adjust_sdram_tbs_8xx (void); -#if defined(CONFIG_8260) -int prt_8260_clks (void); -#elif defined(CONFIG_MPC5xxx) -int prt_mpc5xxx_clks (void); -#endif -#if defined(CONFIG_MPC512X) -int prt_mpc512xxx_clks (void); -#endif -#if defined(CONFIG_MPC8220) -int prt_mpc8220_clks (void); -#endif -#ifdef CONFIG_4xx -ulong get_OPB_freq (void); -ulong get_PCI_freq (void); -#endif -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ - defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442) || \ - defined(CONFIG_LH7A40X) -void s3c2410_irq(void); -#define ARM920_IRQ_CALLBACK s3c2410_irq -ulong get_FCLK (void); -ulong get_HCLK (void); -ulong get_PCLK (void); -ulong get_UCLK (void); -#endif -#if defined(CONFIG_LH7A40X) -ulong get_PLLCLK (void); -#endif -#if defined CONFIG_INCA_IP -uint incaip_get_cpuclk (void); -#endif -#if defined(CONFIG_IMX) -ulong get_systemPLLCLK(void); -ulong get_FCLK(void); -ulong get_HCLK(void); -ulong get_BCLK(void); -ulong get_PERCLK1(void); -ulong get_PERCLK2(void); -ulong get_PERCLK3(void); -#endif -ulong get_bus_freq (ulong); - -#if defined(CONFIG_MPC85xx) -typedef MPC85xx_SYS_INFO sys_info_t; -void get_sys_info ( sys_info_t * ); -ulong get_ddr_freq (ulong); -#endif -#if defined(CONFIG_MPC86xx) -typedef MPC86xx_SYS_INFO sys_info_t; -void get_sys_info ( sys_info_t * ); -#endif - -#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) -# if defined(CONFIG_440) -# if defined(CONFIG_440SPE) - unsigned long determine_sysper(void); - unsigned long determine_pci_clock_per(void); -# endif -# endif -typedef PPC4xx_SYS_INFO sys_info_t; -int ppc440spe_revB(void); -void get_sys_info ( sys_info_t * ); -#endif - -/* $(CPU)/cpu_init.c */ -#if defined(CONFIG_8xx) || defined(CONFIG_8260) -void cpu_init_f (volatile immap_t *immr); -#endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) -void cpu_init_f (void); -#endif - -int cpu_init_r (void); -#if defined(CONFIG_8260) -int prt_8260_rsr (void); -#elif defined(CONFIG_MPC83XX) -int prt_83xx_rsr (void); -#endif - -/* $(CPU)/interrupts.c */ -int interrupt_init (void); -void timer_interrupt (struct pt_regs *); -void external_interrupt (struct pt_regs *); -void irq_install_handler(int, interrupt_handler_t *, void *); -void irq_free_handler (int); -void reset_timer (void); -ulong get_timer (ulong base); -void set_timer (ulong t); -void enable_interrupts (void); -int disable_interrupts (void); - -/* $(CPU)/.../commproc.c */ -int dpram_init (void); -uint dpram_base(void); -uint dpram_base_align(uint align); -uint dpram_alloc(uint size); -uint dpram_alloc_align(uint size,uint align); -void post_word_store (ulong); -ulong post_word_load (void); -void bootcount_store (ulong); -ulong bootcount_load (void); -#define BOOTCOUNT_MAGIC 0xB001C041 - -/* $(CPU)/.../ */ -void mii_init (void); - -/* $(CPU)/.../lcd.c */ -ulong lcd_setmem (ulong); - -/* $(CPU)/.../vfd.c */ -ulong vfd_setmem (ulong); - -/* $(CPU)/.../video.c */ -ulong video_setmem (ulong); - -/* lib_$(ARCH)/cache.c */ -void flush_cache (unsigned long, unsigned long); - - -/* lib_$(ARCH)/ticks.S */ -unsigned long long get_ticks(void); -void wait_ticks (unsigned long); - -/* lib_$(ARCH)/time.c */ -void udelay (unsigned long); -ulong usec2ticks (unsigned long usec); -ulong ticks2usec (unsigned long ticks); -int init_timebase (void); - -/* lib_generic/vsprintf.c */ -ulong simple_strtoul(const char *cp,char **endp,unsigned int base); -#ifdef CFG_64BIT_VSPRINTF -unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); -#endif -long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...); -int sprintf(char * buf, const char *fmt, ...); -int vsprintf(char *buf, const char *fmt, va_list args); - -/* lib_generic/crc32.c */ -ulong crc32 (ulong, const unsigned char *, uint); -ulong crc32_no_comp (ulong, const unsigned char *, uint); - -/* common/console.c */ -int console_init_f(void); /* Before relocation; uses the serial stuff */ -int console_init_r(void); /* After relocation; uses the console stuff */ -int console_assign (int file, char *devname); /* Assign the console */ -int ctrlc (void); -int had_ctrlc (void); /* have we had a Control-C since last clear? */ -void clear_ctrlc (void); /* clear the Control-C condition */ -int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ - -/* - * STDIO based functions (can always be used) - */ - -/* serial stuff */ -void serial_printf (const char *fmt, ...); - -/* stdin */ -int getc(void); -int tstc(void); - -/* stdout */ -void putc(const char c); -void puts(const char *s); -void printf(const char *fmt, ...); -void vprintf(const char *fmt, va_list args); - -/* stderr */ -#define eputc(c) fputc(stderr, c) -#define eputs(s) fputs(stderr, s) -#define eprintf(fmt,args...) fprintf(stderr,fmt ,##args) - -/* - * FILE based functions (can only be used AFTER relocation!) - */ - -#define stdin 0 -#define stdout 1 -#define stderr 2 -#define MAX_FILES 3 - -void fprintf(int file, const char *fmt, ...); -void fputs(int file, const char *s); -void fputc(int file, const char c); -int ftstc(int file); -int fgetc(int file); - -int pcmcia_init (void); - -#ifdef CONFIG_STATUS_LED -# include -#endif -/* - * Board-specific Platform code can reimplement show_boot_progress () if needed - */ -void inline show_boot_progress (int val); - -#ifdef CONFIG_INIT_CRITICAL -#error CONFIG_INIT_CRITICAL is deprecated! -#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. -#endif - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -/* Multicore arch functions */ -#ifdef CONFIG_MP -int cpu_status(int nr); -int cpu_reset(int nr); -int cpu_release(int nr, int argc, char *argv[]); -#endif - -#endif /* __COMMON_H_ */ diff --git a/qiboot/src/cpu/s3c2410/gta01.c b/qiboot/src/cpu/s3c2410/gta01.c deleted file mode 100644 index 4686fa2..0000000 --- a/qiboot/src/cpu/s3c2410/gta01.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: Andy Green - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#define GTA01_DEBUG_UART 0 -#define PCF50606_I2C_ADS 0x08 - - -struct pcf50606_init { - u8 index; - u8 value; -}; - -/* initial register set for PCF50606 in Neo1973 devices */ -const struct pcf50606_init pcf50606_initial_regs[] = { - { PCF50606_REG_OOCS, 0x00 }, - { PCF50606_REG_INT1M, 0x00 }, - { PCF50606_REG_INT2M, 0x00 }, - { PCF50606_REG_INT3M, PCF50606_INT3_TSCPRES }, - { PCF50606_REG_OOCC1, PCF50606_OOCC1_RTCWAK | PCF50606_OOCC1_CHGWAK | - PCF50606_OOCC1_EXTONWAK_HIGH }, - { PCF50606_REG_OOCC2, PCF50606_OOCC2_ONKEYDB_14ms | PCF50606_OOCC2_EXTONDB_14ms }, - { PCF50606_REG_PSSC, 0x00 }, - { PCF50606_REG_PWROKM, 0x00 }, - { PCF50606_REG_DCDC1, 0x18 }, /* GL_1V5: off */ - { PCF50606_REG_DCDC2, 0x00 }, - { PCF50606_REG_DCDC3, 0x00 }, - { PCF50606_REG_DCDC4, 0x30 }, /* 1.25A */ - - { PCF50606_REG_DCDEC1, 0xe8 }, /* IO_3V3: on */ - { PCF50606_REG_DCDEC2, 0x00 }, - - { PCF50606_REG_DCUDC1, 0xc4 }, /* CORE_1V8: 2.1V if PWREN2 = HIGH */ - { PCF50606_REG_DCUDC2, 0x30 }, /* 1.25A current limit */ - - { PCF50606_REG_IOREGC, 0xf8 }, /* CODEC_3V3: on */ - { PCF50606_REG_D1REGC1, 0x16 }, /* BT_3V15: off */ - - { PCF50606_REG_D2REGC1, 0x10 }, /* GL_2V5: off */ - - { PCF50606_REG_D3REGC1, 0xec }, /* STBY_1V8: 2.1V */ - - { PCF50606_REG_LPREGC1, 0xf8 }, /* LCM_3V3: on */ - { PCF50606_REG_LPREGC2, 0x00 }, - - { PCF50606_REG_MBCC1, 0x01 }, /* CHGAPE */ - { PCF50606_REG_MBCC2, 0x00 }, /* unlimited charging */ - { PCF50606_REG_MBCC3, 0x1a }, /* 0.2*Ifast, 4.20V */ - { PCF50606_REG_BBCC, 0x1f }, /* 400uA */ - { PCF50606_REG_ADCC1, 0x00 }, - { PCF50606_REG_ADCC2, 0x00 }, - { PCF50606_REG_ACDC1, 0x86 }, /* ACD thresh 1.6V, enabled */ - { PCF50606_REG_BVMC, PCF50606_BVMC_THRSHLD_3V3 }, - { PCF50606_REG_PWMC1, 0x00 }, - { PCF50606_REG_LEDC1, 0x00 }, - { PCF50606_REG_LEDC2, 0x00 }, - { PCF50606_REG_GPOC1, 0x00 }, - { PCF50606_REG_GPOC2, 0x00 }, - { PCF50606_REG_GPOC3, 0x00 }, - { PCF50606_REG_GPOC4, 0x00 }, - { PCF50606_REG_GPOC5, 0x00 }, -}; - - -static const struct board_variant board_variants[] = { - [0] = { - .name = "Bv4", - .machine_revision = 0x240, - } -}; - - -void port_init_gta01(void) -{ - int n; - unsigned int * MPLLCON = (unsigned int *)0x4c000004; - - rGPACON = 0x005E0FFF; - rGPADAT = 0x00010000; /* nNAND_WP set high */ - - rGPBCON = 0x00045455; - rGPBUP = 0x000007FF; - rGPBDAT = 0x00000004; /* SD-card pwr off */ - - rGPCCON = 0xAAAA12A9; - rGPCUP = 0x0000FFFF; - - rGPDCON = 0xAAAAAAAA; - rGPDUP = 0x0000FFFF; - - rGPECON = 0xAAAAAAAA; - rGPEUP = 0x0000FFFF; - - rGPFCON = 0x0000aa99; - rGPFUP = 0x000000FF; - rGPFDAT = 0x00000004; - - rGPGCON = 0xFF14F0F8; - rGPGUP = 0x0000AFEF; - - rGPHCON = 0x0000FAAA; - rGPHUP = 0x000007FF; - - - /* Load PMU with safe values */ - - for (n = 0; n < ARRAY_SIZE(pcf50606_initial_regs); n++) - i2c_write_sync(&bb_s3c24xx, PCF50606_I2C_ADS, - pcf50606_initial_regs[n].index, - pcf50606_initial_regs[n].value); - - /* Give a short vibrate notification */ - rGPBDAT |= (1 << 3); - udelay(1000000); - rGPBDAT &= ~(1 << 3); - - - /* change CPU to 266MHz 1:2:4 */ - *MPLLCON = ((0x7d << 12) + (0x1 << 4) + 0x1); - /* Delay after update of PLL: Page 7-19, seven nops */ - asm __volatile__ ( - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - ); - - - /* set debug UART working at 115kbps */ - serial_init_115200_s3c24xx(GTA01_DEBUG_UART, 66 /* 66.5MHz PCLK */); -} - - -int sd_card_init_gta01(void) -{ - int retval = -1; - - /* Check if AUX is held. Then skip SD-card kernels! - * FIXME: This would be nicer to do with an API. - */ - if (!(rGPFDAT & (1 << 6))) { - return -1; - } - - /* if SD card inserted, power it up and initialize*/ - if (!(rGPFDAT & (1 << 5))) - { - rGPBDAT &= ~(1 << 2); - retval = s3c24xx_mmc_init(1); - } - return retval; -} - -int sd_card_block_read_gta01(unsigned char * buf, unsigned long start512, - int blocks512) -{ - return s3c24xx_mmc_bread(0, start512, blocks512, buf); -} - -int is_this_board_gta01(void) -{ - /* FIXME: How to check for GTA01 ? */ - return 1; -} - -const struct board_variant const * get_board_variant_gta01(void) -{ - return &board_variants[0]; -} - -static __attribute__ (( section (".steppingstone") )) void putc_gta01(char c) -{ - serial_putc_s3c24xx(GTA01_DEBUG_UART, c); -} - -static void close_gta01(void) -{ - /* set I2C GPIO back to peripheral unit */ - (bb_s3c24xx.close)(); -} - -/* Here we will care only about AUX button as polling for PWR button - * through i2c slows down the boot */ - -static u8 get_ui_keys_gta01(void) -{ - u8 keys; - u8 ret = 0; - static u8 old_keys = 0; /* previous state for debounce */ - static u8 older_keys = 0; /* previous debounced output for edge detect */ - - /* GPF6 is AUX on GTA01, map to UI_ACTION_SKIPKERNEL, down = 0 */ - keys = ! (rGPFDAT & (1 << 6)); - - /* edge action */ - if ((old_keys & 1) && !(older_keys & 1)) - ret |= UI_ACTION_SKIPKERNEL; - - older_keys = old_keys; - old_keys = keys; - - return ret; -} - -static u8 get_ui_debug_gta01(void) -{ - /* PWR button state can be seen in OOCS b0, down = 0, map to UI_ACTION_ADD_DEBUG */ - return !(i2c_read_sync(&bb_s3c24xx, PCF50606_I2C_ADS, PCF50606_REG_OOCS) & 1); -} - -/* - * API for bootloader on this machine - */ - -const struct board_api board_api_gta01 = { - .name = "Neo1973 GTA01", - .linux_machine_id = 1182, - .linux_mem_start = 0x30000000, - .linux_mem_size = (128 * 1024 * 1024), - .linux_tag_placement = 0x30000000 + 0x100, - .get_board_variant = get_board_variant_gta01, - .is_this_board = is_this_board_gta01, - .port_init = port_init_gta01, - .putc = putc_gta01, - .close = close_gta01, - .get_ui_keys = get_ui_keys_gta01, - .get_ui_debug = get_ui_debug_gta01, - - .commandline_board = "mtdparts=" - "neo1973-nand:" - "0x00040000(qi)," - "0x00004000(u-boot_env)," - "0x00200000(kernel)," - "0x000a0000(splash)," - "0x03d1c000(rootfs) " - "loglevel=4 " - "console=tty0 " - "console=ttySAC0,115200 " - "init=/sbin/init " - "ro ", - .commandline_board_debug = " loglevel=8 ", - .noboot = "boot/noboot-GTA01", - .append = "boot/append-GTA01", - /* these are the ways we could boot GTA01 in order to try */ - .kernel_source = { - [0] = { - .name = "SD Card EXT2 Kernel p1", - .block_init = sd_card_init_gta01, - .block_read = sd_card_block_read_gta01, - .partition_index = 1, - .filesystem = FS_EXT2, - .filepath = "boot/uImage-GTA01.bin", - .commandline_append = "root=/dev/mmcblk0p1 rootdelay=1 ", - }, - [1] = { - .name = "SD Card EXT2 Kernel p2", - .block_init = sd_card_init_gta01, - .block_read = sd_card_block_read_gta01, - .partition_index = 2, - .filesystem = FS_EXT2, - .filepath = "boot/uImage-GTA01.bin", - .commandline_append = "root=/dev/mmcblk0p2 rootdelay=1 ", - }, - [2] = { - .name = "SD Card EXT2 Kernel p3", - .block_init = sd_card_init_gta01, - .block_read = sd_card_block_read_gta01, - .partition_index = 3, - .filesystem = FS_EXT2, - .filepath = "boot/uImage-GTA01.bin", - .commandline_append = "root=/dev/mmcblk0p3 rootdelay=1 ", - }, - [3] = { - .name = "NAND Kernel", - .block_read = nand_read_ll, - .offset_blocks512_if_no_partition = 0x44000 / 512, - .filesystem = FS_RAW, - .commandline_append = "rootfstype=jffs2 " - "root=/dev/mtdblock4 ", - }, - }, -}; diff --git a/qiboot/src/cpu/s3c2410/i2c-bitbang-s3c24xx.c b/qiboot/src/cpu/s3c2410/i2c-bitbang-s3c24xx.c deleted file mode 100644 index c2d46ed..0000000 --- a/qiboot/src/cpu/s3c2410/i2c-bitbang-s3c24xx.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: Andy Green - * - * s3c24xx-specific i2c shared by, eg, GTA02 and GTA03 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -static char i2c_read_sda_s3c24xx(void) -{ - return (rGPEDAT & 0x8000) != 0; -} - -static void i2c_set_s3c24xx(char clock, char data) -{ - if (clock) /* SCL <- input */ - rGPECON = (rGPECON & ~0x30000000); - else { /* SCL <- output 0 */ - rGPEDAT = (rGPEDAT & ~0x4000); - rGPECON = (rGPECON & ~0x30000000) | 0x10000000; - } - if (data) /* SDA <- input */ - rGPECON = (rGPECON & ~0xc0000000); - else { /* SDA <- output 0 */ - rGPEDAT = (rGPEDAT & ~0x8000); - rGPECON = (rGPECON & ~0xc0000000) | 0x40000000; - } -} - -static void i2c_close_s3c24xx(void) -{ - /* set back to hardware I2C ready for Linux */ - rGPECON = (rGPECON & ~0xf0000000) | 0xa0000000; -} - -static void i2c_spin_s3c24xx(void) -{ - int n; - - for (n = 0; n < 1000; n++) - rGPJDAT |= (1 << 5); -} - -struct i2c_bitbang bb_s3c24xx = { - .read_sda = i2c_read_sda_s3c24xx, - .set = i2c_set_s3c24xx, - .spin = i2c_spin_s3c24xx, - .close = i2c_close_s3c24xx, -}; diff --git a/qiboot/src/cpu/s3c2410/lowlevel_init.S b/qiboot/src/cpu/s3c2410/lowlevel_init.S deleted file mode 100644 index 2b14373..0000000 --- a/qiboot/src/cpu/s3c2410/lowlevel_init.S +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Modified for the FIC Neo1973 GTA01 by Harald Welte - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* NOTE this stuff runs in steppingstone context! */ - - -/* - * #include - * #include - */ -#define __ASM_MODE__ -#include - -/* - * - * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S - * - * Copyright (C) 2002 Samsung Electronics SW.LEE - * - */ - -#define BWSCON 0x48000000 - -/* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW16 + WAIT + UBLB) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* BANK1CON: Smedia Glamo 3362 (on GTA02) */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x3 /* 4clk */ -#define B1_Tacc 0x3 /* 4clk */ -#define B1_Tcoh 0x3 /* 4clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0x0 /* 0clk */ -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 /* 14clk */ -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x0 /* 0clk */ -#define B3_Tacp 0x3 /* 6clk */ -#define B3_PMC 0x0 /* normal */ - -#define B4_Tacs 0x0 /* 0clk */ -#define B4_Tcos 0x0 /* 0clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x0 /* 0clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x0 /* 0clk */ -#define B5_Tacc 0x7 /* 14clk */ -#define B5_Tcoh 0x0 /* 0clk */ -#define B5_Tah 0x0 /* 0clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ - -#define B6_SCAN 0x2 /* 10bit */ -#define B7_SCAN 0x2 /* 10bit */ - - -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ - -/* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x1 /* 3clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -//#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ -#define REFCNT 997 /* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */ -/**************************************/ - -.globl lowlevel_init -lowlevel_init: - - ldr r0, =SMRDATA - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #13*4 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* setup asynchronous bus mode */ - mrc p15, 0, r1 ,c1 ,c0, 0 - orr r1, r1, #0xc0000000 - mcr p15, 0, r1, c1, c0, 0 - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ -SMRDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0xb2 - .word 0x30 - .word 0x30 diff --git a/qiboot/src/cpu/s3c2410/nand_read.c b/qiboot/src/cpu/s3c2410/nand_read.c deleted file mode 100644 index 83b1651..0000000 --- a/qiboot/src/cpu/s3c2410/nand_read.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * nand_read.c: Simple NAND read functions for booting from NAND - * - * This is used by cpu/arm920/start.S assembler code, - * and the board-specific linker script must make sure this - * file is linked within the first 4kB of NAND flash. - * - * Taken from GPLv2 licensed vivi bootloader, - * Copyright (C) 2002 MIZI Research, Inc. - * - * Author: Hwang, Chideok - * Date : $Date: 2004/02/04 10:37:37 $ - * - * u-boot integration and bad-block skipping (C) 2006 by OpenMoko, Inc. - * Author: Harald Welte - */ - -/* NOTE this stuff runs in steppingstone context! */ - -/* the API refers to 512-byte blocks */ - -#include -#include "nand_read.h" - -#define NAND_CMD_READ0 0 -#define NAND_CMD_READOOB 0x50 - -#define __REGb(x) (*(volatile unsigned char *)(x)) -#define __REGw(x) (*(volatile unsigned short *)(x)) -#define __REGi(x) (*(volatile unsigned int *)(x)) -#define NF_BASE 0x4e000000 -#define NFCONF __REGi(NF_BASE + 0x0) -#define NFCMD __REGb(NF_BASE + 0x4) -#define NFADDR __REGb(NF_BASE + 0x8) -#define NFDATA __REGb(NF_BASE + 0xc) -#define NFSTAT __REGb(NF_BASE + 0x10) -#define NFSTAT_BUSY 1 -#define nand_select() (NFCONF &= ~0x800) -#define nand_deselect() (NFCONF |= 0x800) -#define nand_clear_RnB() do {} while (0) - - -static inline void nand_wait(void) -{ - int i; - - while (!(NFSTAT & NFSTAT_BUSY)) - for (i=0; i<10; i++); -} - -/* configuration for 2410 with 512byte sized flash */ -#define NAND_PAGE_SIZE 512 -#define BAD_BLOCK_OFFSET 5 -#define NAND_BLOCK_MASK (NAND_PAGE_SIZE - 1) -#define NAND_BLOCK_SIZE 0x4000 - -static int is_bad_block(unsigned long block_index) -{ - unsigned char data; - - nand_clear_RnB(); - - NFCMD = NAND_CMD_READOOB; /* 0x50 */ - NFADDR = BAD_BLOCK_OFFSET & 0xf; - NFADDR = (block_index ) & 0xff; - NFADDR = (block_index >> 8 ) & 0xff; - NFADDR = (block_index >> 16) & 0xff; - - nand_wait(); - data = (NFDATA & 0xff); - - if (data != 0xff) - return 1; - - return 0; -} - -static int nand_read_page_ll(unsigned char *buf, unsigned long block512) -{ - unsigned int i; - - nand_clear_RnB(); - - NFCMD = NAND_CMD_READ0; - - /* Write Address */ - NFADDR = 0; - NFADDR = (block512 ) & 0xff; - NFADDR = (block512 >> 8 ) & 0xff; - NFADDR = (block512 >> 16) & 0xff; - - nand_wait(); - - for (i = 0; i < NAND_PAGE_SIZE; i++) { - *buf = (NFDATA & 0xff); - buf++; - } - - return 1; -} - -/* low level nand read function */ -int nand_read_ll(unsigned char *buf, unsigned long start_block512, int blocks512) -{ - int i, j; - int bad_count = 0; - - /* chip Enable */ - nand_select(); - nand_clear_RnB(); - - for (i = 0; i < 10; i++) - ; - - while (blocks512 > 0) { - if (is_bad_block(start_block512) || - is_bad_block(start_block512 + 1)) { - start_block512 += 1; - blocks512 += 1; - if (bad_count++ == 4) - return -1; - continue; - } - - j = nand_read_page_ll(buf, start_block512); - start_block512 += j; - buf += j << 9; - blocks512 -= j; - } - - /* chip Disable */ - nand_deselect(); - - return 0; -} - diff --git a/qiboot/src/cpu/s3c2410/nand_read.h b/qiboot/src/cpu/s3c2410/nand_read.h deleted file mode 100644 index 71aeda5..0000000 --- a/qiboot/src/cpu/s3c2410/nand_read.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * nand_read.c: Simple NAND read functions for booting from NAND - * - * This is used by cpu/arm920/start.S assembler code, - * and the board-specific linker script must make sure this - * file is linked within the first 4kB of NAND flash. - * - * Taken from GPLv2 licensed vivi bootloader, - * Copyright (C) 2002 MIZI Research, Inc. - * - * Author: Hwang, Chideok - * Date : $Date: 2004/02/04 10:37:37 $ - * - * u-boot integration and bad-block skipping (C) 2006 by OpenMoko, Inc. - * Author: Harald Welte - */ -#ifndef __NAND_READ_H -#define __NAND_READ_H - -int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size); - -#endif /* __NAND_READ_H */ diff --git a/qiboot/src/cpu/s3c2410/qi.lds b/qiboot/src/cpu/s3c2410/qi.lds deleted file mode 100644 index 27ba2f0..0000000 --- a/qiboot/src/cpu/s3c2410/qi.lds +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - /* this is intended to take the first 4KBytes of stuff initially. - * We have to make sure we have .rodata* in there for everything - * because we do not compile PIC. - */ - - . = ALIGN(4); - .text : - { - src/cpu/s3c2410/start.o (.text .rodata* .data .bss) - src/cpu/s3c2410/lowlevel_init.o (.text .rodata* .data .bss) - src/cpu/s3c2410/start_qi.o (.text .rodata* .data .bss) - src/cpu/s3c2410/nand_read.o (.text .rodata* .data .bss) - src/cpu/s3c2410/serial-s3c24xx.o (.text .rodata* .data .bss) - src/memory-test.o (.text .rodata* .data .bss) - src/utils.o (.text .rodata* .data .bss) - src/ctype.o (.text .rodata* .data .bss) - * (.steppingstone) - } - - . = ALIGN(4); - .everything_else ADDR (.text) + SIZEOF (.text) + 0x33000000 : - AT ( ADDR (.text) + SIZEOF (.text) ) { *(.text .rodata* .data) } - - . = 0x33800000 ; - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss) - } - - _end = .; -} diff --git a/qiboot/src/cpu/s3c2410/s3c24xx-mci.c b/qiboot/src/cpu/s3c2410/s3c24xx-mci.c deleted file mode 100644 index dbef90d..0000000 --- a/qiboot/src/cpu/s3c2410/s3c24xx-mci.c +++ /dev/null @@ -1,579 +0,0 @@ -/* - * qi s3c24xx SD card driver - * Author: Andy Green - * based on ----> - * - * u-boot S3C2410 MMC/SD card driver - * (C) Copyright 2006 by OpenMoko, Inc. - * Author: Harald Welte - * - * based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c - * (C) 2005-2005 Thomas Kleffel - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define SDICON (*(u32 *)0x5a000000) -#define SDIPRE (*(u32 *)0x5a000004) -#define SDICARG (*(u32 *)0x5a000008) -#define SDICCON (*(u32 *)0x5a00000c) -#define SDICSTA (*(u32 *)0x5a000010) -#define SDIRSP0 (*(u32 *)0x5a000014) -#define SDIRSP1 (*(u32 *)0x5a000018) -#define SDIRSP2 (*(u32 *)0x5a00001c) -#define SDIRSP3 (*(u32 *)0x5a000020) -#define SDIDTIMER (*(u32 *)0x5a000024) -#define SDIBSIZE (*(u32 *)0x5a000028) -#define SDIDCON (*(u32 *)0x5a00002c) -#define SDIDCNT (*(u32 *)0x5a000030) -#define SDIDSTA (*(u32 *)0x5a000034) -#define SDIFSTA (*(u32 *)0x5a000038) -/* s3c2410 in GTA01 has these two last ones the other way around!!! */ -#define SDIIMSK (*(u32 *)0x5a00003c) -#define SDIDAT (*(u32 *)0x5a000040) -#define SDIDAT2410 (*(u32 *)0x5a00003c) -#define SDIIMSK2410 (*(u32 *)0x5a000040) - -#define CFG_MMC_BASE 0xff000000 - -int am_i_s3c2410(void) -{ - return 1; -} - -#define CONFIG_MMC_WIDE -#define MMC_BLOCK_SIZE 512 - -/* - * FIXME needs to read cid and csd info to determine block size - * and other parameters - */ -static u8 mmc_buf[MMC_BLOCK_SIZE]; -static mmc_csd_t mmc_csd; -static int mmc_ready = 0; -static int wide = 0; -static int is_sdhc = 0; - - -#define CMD_F_RESP 0x01 -#define CMD_F_RESP_LONG 0x02 - -static u32 *mmc_cmd(u16 cmd, u32 arg, u16 flags) -{ - static u32 resp[5]; - - u32 ccon, csta; - u32 csta_rdy_bit = S3C2410_SDICMDSTAT_CMDSENT; - - memset(resp, 0, sizeof(resp)); - -// debug("mmc_cmd CMD%d arg=0x%08x flags=%x\n", cmd, arg, flags); - - SDICSTA = 0xffffffff; - SDIDSTA = 0xffffffff; - SDIFSTA = 0xffffffff; - - SDICARG = arg; - - ccon = cmd & S3C2410_SDICMDCON_INDEX; - ccon |= S3C2410_SDICMDCON_SENDERHOST|S3C2410_SDICMDCON_CMDSTART; - - if (flags & CMD_F_RESP) { - ccon |= S3C2410_SDICMDCON_WAITRSP; - csta_rdy_bit = S3C2410_SDICMDSTAT_RSPFIN; /* 1 << 9 */ - } - - if (flags & CMD_F_RESP_LONG) - ccon |= S3C2410_SDICMDCON_LONGRSP; - - SDICCON = ccon; - - while (1) { - csta = SDICSTA; - if (csta & csta_rdy_bit) - break; - if (csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { - puts("===============> MMC CMD Timeout\n"); - SDICSTA |= S3C2410_SDICMDSTAT_CMDTIMEOUT; - break; - } - } - -// debug("final MMC CMD status 0x%x\n", csta); - - SDICSTA |= csta_rdy_bit; - - if (flags & CMD_F_RESP) { - resp[0] = SDIRSP0; - resp[1] = SDIRSP1; - resp[2] = SDIRSP2; - resp[3] = SDIRSP3; - } - - return resp; -} - -#define FIFO_FILL() ((SDIFSTA & S3C2410_SDIFSTA_COUNTMASK) >> 2) - -static int mmc_block_read(u8 *dst, u32 src, u32 len) -{ - u32 dcon, fifo; - u32 *dst_u32 = (u32 *)dst; - u32 *resp; - - if (len == 0) - return 0; - -// debug("mmc_block_rd dst %lx src %lx len %d\n", (u32)dst, src, len); - - /* set block len */ - resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, len, CMD_F_RESP); - SDIBSIZE = len; - - //SDIPRE = 0xff; - - /* setup data */ - dcon = (len >> 9) & S3C2410_SDIDCON_BLKNUM; - dcon |= S3C2410_SDIDCON_BLOCKMODE; - dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART; - if (wide) - dcon |= S3C2410_SDIDCON_WIDEBUS; - - if (!am_i_s3c2410()) - dcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART; - - SDIDCON = dcon; - - /* send read command */ - if (!is_sdhc) - resp = mmc_cmd(MMC_CMD_READ_BLOCK, src, CMD_F_RESP); - else - resp = mmc_cmd(MMC_CMD_READ_BLOCK, src / MMC_BLOCK_SIZE, CMD_F_RESP); - - while (len > 0) { - u32 sdidsta = SDIDSTA; - fifo = FIFO_FILL(); - if (sdidsta & (S3C2410_SDIDSTA_FIFOFAIL| - S3C2410_SDIDSTA_CRCFAIL| - S3C2410_SDIDSTA_RXCRCFAIL| - S3C2410_SDIDSTA_DATATIMEOUT)) { - puts("mmc_block_read: err SDIDSTA=0x"); - print32(sdidsta); - puts("\n"); - return -1; - } - - if (am_i_s3c2410()) { - while (fifo--) { - //debug("dst_u32 = 0x%08x\n", dst_u32); - *(dst_u32++) = SDIDAT2410; - if (len >= 4) - len -= 4; - else { - len = 0; - break; - } - } - } else { - while (fifo--) { - //debug("dst_u32 = 0x%08x\n", dst_u32); - *(dst_u32++) = SDIDAT; - if (len >= 4) - len -= 4; - else { - len = 0; - break; - } - } - } - } - -// debug("waiting for SDIDSTA (currently 0x%08x\n", SDIDSTA); - while (!(SDIDSTA & (1 << 4))) {} -// debug("done waiting for SDIDSTA (currently 0x%08x\n", SDIDSTA); - - SDIDCON = 0; - - if (!(SDIDSTA & S3C2410_SDIDSTA_XFERFINISH)) - puts("mmc_block_read; transfer not finished!\n"); - - return 0; -} - -static int mmc_block_write(u32 dst, u8 *src, int len) -{ - puts("MMC block write not yet supported on S3C2410!\n"); - return -1; -} - - -int s3c24xx_mmc_read(u32 src, u8 *dst, int size) -{ - u32 end, part_start, part_end, part_len, aligned_start, aligned_end; - u32 mmc_block_size, mmc_block_address; - - if (size == 0) - return 0; - - if (!mmc_ready) { - puts("Please initialize the MMC first\n"); - return -1; - } - - mmc_block_size = MMC_BLOCK_SIZE; - mmc_block_address = ~(mmc_block_size - 1); - - src -= CFG_MMC_BASE; - end = src + size; - part_start = ~mmc_block_address & src; - part_end = ~mmc_block_address & end; - aligned_start = mmc_block_address & src; - aligned_end = mmc_block_address & end; - - /* all block aligned accesses */ -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_start) { - part_len = mmc_block_size - part_start; -// debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) - return -1; - - memcpy(dst, mmc_buf+part_start, part_len); - dst += part_len; - src += part_len; - } -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { -// debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read((u8 *)(dst), src, mmc_block_size)) < 0) - return -1; - } -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_end && src < end) { -// debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) - return -1; - - memcpy(dst, mmc_buf, part_end); - } - return 0; -} - -int s3c24xx_mmc_write(u8 *src, u32 dst, int size) -{ - u32 end, part_start, part_end, part_len, aligned_start, aligned_end; - u32 mmc_block_size, mmc_block_address; - - if (size == 0) - return 0; - - if (!mmc_ready) { - puts("Please initialize the MMC first\n"); - return -1; - } - - mmc_block_size = MMC_BLOCK_SIZE; - mmc_block_address = ~(mmc_block_size - 1); - - dst -= CFG_MMC_BASE; - end = dst + size; - part_start = ~mmc_block_address & dst; - part_end = ~mmc_block_address & end; - aligned_start = mmc_block_address & dst; - aligned_end = mmc_block_address & end; - - /* all block aligned accesses */ -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_start) { - part_len = mmc_block_size - part_start; -// debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// (u32)src, dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) - return -1; - - memcpy(mmc_buf+part_start, src, part_len); - if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) - return -1; - - dst += part_len; - src += part_len; - } -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { -// debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_write(dst, (u8 *)src, mmc_block_size)) < 0) - return -1; - - } -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_end && dst < end) { -// debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) - return -1; - - memcpy(mmc_buf, src, part_end); - if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) - return -1; - - } - return 0; -} - -u32 s3c24xx_mmc_bread(int dev_num, u32 blknr, u32 blkcnt, void *dst) -{ - int mmc_block_size = MMC_BLOCK_SIZE; - u32 src = blknr * mmc_block_size + CFG_MMC_BASE; - - s3c24xx_mmc_read(src, dst, blkcnt*mmc_block_size); - return blkcnt; -} - -/* MMC_DEFAULT_RCA should probably be just 1, but this may break other code - that expects it to be shifted. */ -static u_int16_t rca = MMC_DEFAULT_RCA >> 16; - -#if 0 -static u32 mmc_size(const struct mmc_csd *csd) -{ - u32 block_len, mult, blocknr; - - block_len = csd->read_bl_len << 12; - mult = csd->c_size_mult1 << 8; - blocknr = (csd->c_size+1) * mult; - - return blocknr * block_len; -} -#endif - -struct sd_cid { - char pnm_0; /* product name */ - char oid_1; /* OEM/application ID */ - char oid_0; - uint8_t mid; /* manufacturer ID */ - char pnm_4; - char pnm_3; - char pnm_2; - char pnm_1; - uint8_t psn_2; /* product serial number */ - uint8_t psn_1; - uint8_t psn_0; /* MSB */ - uint8_t prv; /* product revision */ - uint8_t crc; /* CRC7 checksum, b0 is unused and set to 1 */ - uint8_t mdt_1; /* manufacturing date, LSB, RRRRyyyy yyyymmmm */ - uint8_t mdt_0; /* MSB */ - uint8_t psn_3; /* LSB */ -}; - -static void print_mmc_cid(mmc_cid_t *cid) -{ - puts("MMC found. Card desciption is:\n"); - puts("Manufacturer ID = "); - print8(cid->id[0]); - print8(cid->id[1]); - print8(cid->id[2]); - puts("\nHW/FW Revision = "); - print8(cid->hwrev); - print8(cid->fwrev); - cid->hwrev = cid->fwrev = 0; /* null terminate string */ - puts("Product Name = "); - puts((char *)cid->name); - puts("\nSerial Number = "); - print8(cid->sn[0]); - print8(cid->sn[1]); - print8(cid->sn[2]); - puts("\nMonth = "); - printdec(cid->month); - puts("\nYear = "); - printdec(1997 + cid->year); - puts("\n"); -} - -static void print_sd_cid(const struct sd_cid *cid) -{ - puts("Manufacturer: 0x"); - print8(cid->mid); - puts("OEM \""); - this_board->putc(cid->oid_0); - this_board->putc(cid->oid_1); - puts("\"\nProduct name: \""); - this_board->putc(cid->pnm_0); - this_board->putc(cid->pnm_1); - this_board->putc(cid->pnm_2); - this_board->putc(cid->pnm_3); - this_board->putc(cid->pnm_4); - puts("\", revision "); - printdec(cid->prv >> 4); - puts("."); - printdec(cid->prv & 15); - puts("\nSerial number: "); - printdec(cid->psn_0 << 24 | cid->psn_1 << 16 | cid->psn_2 << 8 | - cid->psn_3); - puts("\nManufacturing date: "); - printdec(cid->mdt_1 & 15); - puts("/"); - printdec(2000+((cid->mdt_0 & 15) << 4)+((cid->mdt_1 & 0xf0) >> 4)); - puts("\nCRC: 0x"); - print8(cid->crc >> 1); - puts(" b0 = "); - print8(cid->crc & 1); - puts("\n"); -} - -int s3c24xx_mmc_init(int verbose) -{ - int retries, rc = -2; - int is_sd = 0; - u32 *resp; - u32 hcs = 0; - - SDICON = S3C2410_SDICON_FIFORESET | S3C2410_SDICON_CLOCKTYPE; - SDIBSIZE = 512; - if (am_i_s3c2410()) { - /* S3C2410 has some bug that prevents reliable operation at higher speed */ - //SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ - SDIPRE = 0x02; /* 2410: SDCLK = PCLK/2 / (SDIPRE+1) = 11MHz */ - SDIDTIMER = 0xffff; - SDIIMSK2410 = 0x0; - } else { - SDIPRE = 0x05; /* 2410: SDCLK = PCLK / (SDIPRE+1) = 11MHz */ - SDIDTIMER = 0x7fffff; - SDIIMSK = 0x0; - } - - udelay(1250000); /* FIXME: 74 SDCLK cycles */ - - mmc_csd.c_size = 0; - - puts("Sending reset...\n"); - - /* reset */ - retries = 10; - resp = mmc_cmd(MMC_CMD_RESET, 0, 0); - - resp = mmc_cmd(8, 0x000001aa, CMD_F_RESP); - if ((resp[0] & 0xff) == 0xaa) { - puts("The card is either SD2.0 or SDHC\n"); - hcs = 0x40000000; - } - - puts("trying to detect SD Card...\n"); - while (retries--) { - udelay(1000000); - resp = mmc_cmd(55, 0x00000000, CMD_F_RESP); - resp = mmc_cmd(41, hcs | 0x00300000, CMD_F_RESP); - - if (resp[0] & (1 << 30)) - is_sdhc = 1; - - if (resp[0] & (1 << 31)) { - is_sd = 1; - break; - } - } - - if (retries < 0 && !is_sd) - return -3; - - /* try to get card id */ - resp = mmc_cmd(MMC_CMD_ALL_SEND_CID, hcs, CMD_F_RESP|CMD_F_RESP_LONG); - if (resp) { - if (!is_sd) { - /* TODO configure mmc driver depending on card - attributes */ - mmc_cid_t *cid = (mmc_cid_t *)resp; - - if (verbose) - print_mmc_cid(cid); -#if 0 - sprintf((char *) mmc_dev.vendor, - "Man %02x%02x%02x Snr %02x%02x%02x", - cid->id[0], cid->id[1], cid->id[2], - cid->sn[0], cid->sn[1], cid->sn[2]); - sprintf((char *) mmc_dev.product,"%s",cid->name); - sprintf((char *) mmc_dev.revision,"%x %x", - cid->hwrev, cid->fwrev); -#endif - } - else { - struct sd_cid *cid = (struct sd_cid *) resp; - - if (verbose) - print_sd_cid(cid); -#if 0 - sprintf((char *) mmc_dev.vendor, - "Man %02 OEM %c%c \"%c%c%c%c%c\"", - cid->mid, cid->oid_0, cid->oid_1, - cid->pnm_0, cid->pnm_1, cid->pnm_2, cid->pnm_3, - cid->pnm_4); - sprintf((char *) mmc_dev.product, "%d", - cid->psn_0 << 24 | cid->psn_1 << 16 | - cid->psn_2 << 8 | cid->psn_3); - sprintf((char *) mmc_dev.revision, "%d.%d", - cid->prv >> 4, cid->prv & 15); -#endif - } - - - /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, CMD_F_RESP); - if (is_sd) - rca = resp[0] >> 16; - - resp = mmc_cmd(MMC_CMD_SEND_CSD, rca<<16, CMD_F_RESP|CMD_F_RESP_LONG); - if (resp) { - mmc_csd_t *csd = (mmc_csd_t *)resp; - memcpy(&mmc_csd, csd, sizeof(csd)); - rc = 0; - mmc_ready = 1; -#if 0 - /* FIXME add verbose printout for csd */ - printf("READ_BL_LEN=%u, C_SIZE_MULT=%u, C_SIZE=%u\n", - csd->read_bl_len, csd->c_size_mult1, csd->c_size); - printf("size = %u\n", mmc_size(csd)); -#endif - } - } - - resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca<<16, CMD_F_RESP); - -#ifdef CONFIG_MMC_WIDE - if (is_sd) { - resp = mmc_cmd(55, rca<<16, CMD_F_RESP); - resp = mmc_cmd(6, 0x02, CMD_F_RESP); - wide = 1; - } -#endif - - return rc; -} - - diff --git a/qiboot/src/cpu/s3c2410/serial-s3c24xx.c b/qiboot/src/cpu/s3c2410/serial-s3c24xx.c deleted file mode 100644 index 0f4ba22..0000000 --- a/qiboot/src/cpu/s3c2410/serial-s3c24xx.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void serial_init_115200_s3c24xx(const int uart, const int pclk_MHz) -{ - int div = (((54 * pclk_MHz) + 26) / 100) -1; - switch(uart) - { - case UART0: - rULCON0 = 0x3; - rUCON0 = 0x245; - rUFCON0 = 0x0; - rUMCON0 = 0x0; - rUBRDIV0 = div; - break; - case UART1: - rULCON1 = 0x3; - rUCON1 = 0x245; - rUFCON1 = 0x0; - rUMCON1 = 0x0; - rUBRDIV1 = div; - break; - case UART2: - rULCON2 = 0x3; - rUCON2 = 0x245; - rUFCON2 = 0x1; - rUBRDIV2 = div; - break; - default: - break; - } -} -/* - * Output a single byte to the serial port. - */ -void serial_putc_s3c24xx(const int uart, const char c) -{ - switch(uart) - { - case UART0: - while ( !( rUTRSTAT0 & 0x2 ) ); - WrUTXH0(c); - break; - case UART1: - while ( !( rUTRSTAT1 & 0x2 ) ); - WrUTXH1(c); - break; - case UART2: - while ( !( rUTRSTAT2 & 0x2 ) ); - WrUTXH2(c); - break; - default: - break; - } -} diff --git a/qiboot/src/cpu/s3c2410/start.S b/qiboot/src/cpu/s3c2410/start.S deleted file mode 100644 index 5c9d3db..0000000 --- a/qiboot/src/cpu/s3c2410/start.S +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define __ASM_MODE__ -#define __ASSEMBLY__ - -#include - -#define S3C2410_MISCCR_nEN_SCLK0 (1 << 17) -#define S3C2410_MISCCR_nEN_SCLK1 (1 << 18) -#define S3C2410_MISCCR_nEN_SCLKE (1 << 19) - - -.globl _start, processor_id, is_jtag - -_start: b start_code -/* if we are injected by JTAG, the script sets _istag content to nonzero */ -is_jtag: - .word 0 - -/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script - * we need to go through this hassle because before this moment, SDRAM is not - * working so we can't prep it from JTAG - */ - -_steppingstone_done: - ldr pc, _start_armboot - -_start_armboot: - .word start_qi - -_TEXT_BASE: - .word TEXT_BASE - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end -/* - * we have a stack in steppingstone because we can want to run full memory - * memory tests - */ - - .fill 128 -.globl _ss_stack -_ss_stack: - - -start_code: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -# define pWTCON 0x53000000 - - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define INTSUBMSK_val 0x000007ff - - mov r1, #0xffffffff - ldr r0, =INTMSK - str r1, [r0] - - ldr r1, =INTSUBMSK_val - ldr r0, =INTSUBMSK - str r1, [r0] - - /* Clock asynchronous mode */ - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, #0xc0000000 - mcr p15, 0, r1, c1, c0, 0 - -#define LOCKTIME 0x4c000000 - - ldr r0, =LOCKTIME - mov r1, #0xffffff - str r1, [r0] - -# define UPLLCON 0x4c000008 -# define MPLLCON_val ((0x90 << 12) + (0x7 << 4) + 0x0) /* 202 MHz */ -# define UPLLCON_val ((0x78 << 12) + (0x2 << 4) + 0x3) - - ldr r0, =UPLLCON - ldr r1, =UPLLCON_val - str r1, [r0] - - /* Page 7-19, seven nops between UPLL and MPLL */ - nop - nop - nop - nop - nop - nop - nop - - ldr r1, =MPLLCON_val - str r1, [r0, #-4] /* MPLLCON */ - -# define CLKDIVN 0x4C000014 /* clock divisor register */ -# define CLKDIVN_val 3 /* FCLK:HCLK:PCLK = 1:2:4 */ - - /* FCLK:HCLK:PCLK = 1:3:6 */ - ldr r0, =CLKDIVN - mov r1, #CLKDIVN_val - str r1, [r0] - - /* enable only CPU peripheral block clocks we actually use */ - ldr r0, =0x4c00000c /* clkcon */ - ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */ - str r1, [r0] - - /* gpio UART0 init */ - ldr r0, =0x56000070 - ldr r1, =0x000000AA - str r1, [r0] - - /* init uart0 */ - ldr r0, =0x50000000 - mov r1, #0x03 - str r1, [r0] - ldr r1, =0x245 - str r1, [r0, #0x04] - mov r1, #0x01 - str r1, [r0, #0x08] - mov r1, #0x00 - str r1, [r0, #0x0c] - mov r1, #0x1a - str r1, [r0, #0x28] - -/* reset nand controller, or it is dead to us */ - -#define oNFCONF 0x00 -#define oNFCMD 0x04 -#define oNFSTAT 0x10 - - mov r1, #0x4E000000 - ldr r2, =0xf842 @ initial value enable tacls=3,rph0=6,rph1=0 - str r2, [r1, #oNFCONF] - ldr r2, [r1, #oNFCONF] - bic r2, r2, #0x800 @ enable chip - str r2, [r1, #oNFCONF] - mov r2, #0xff @ RESET command - strb r2, [r1, #oNFCMD] - mov r3, #0 @ wait -1: add r3, r3, #0x1 - cmp r3, #0xa - blt 1b -2: ldr r2, [r1, #oNFSTAT] @ wait ready - tst r2, #0x1 - beq 2b - ldr r2, [r1, #oNFCONF] - orr r2, r2, #0x800 @ disable chip - str r2, [r1, #oNFCONF] - - /* take sdram out of power down */ - ldr r0, =0x56000080 /* misccr */ - ldr r1, [ r0 ] - bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE) - str r1, [ r0 ] - - /* ensure signals stabalise */ - mov r1, #128 -3: subs r1, r1, #1 - bpl 3b - - bl cpu_init_crit - - /* ensure some refresh has happened */ - ldr r1, =0xfffff -4: subs r1, r1, #1 - bpl 4b - - /* capture full EINT situation into gstatus 4 */ - - ldr r0, =0x4A000000 /* SRCPND */ - ldr r1, [ r0 ] - and r1, r1, #0xf - - ldr r0, =0x560000BC /* gstatus4 */ - str r1, [ r0 ] - - ldr r0, =0x560000A8 /* EINTPEND */ - ldr r1, [ r0 ] - ldr r0, =0xfff0 - and r1, r1, r0 - ldr r0, =0x560000BC /* gstatus4 */ - ldr r0, [ r0 ] - orr r1, r1, r0 - ldr r0, =0x560000BC /* gstatus4 */ - str r1, [ r0 ] - - /* test for resume */ - - ldr r1, =0x560000B4 /* gstatus2 */ - ldr r0, [ r1 ] - tst r0, #0x02 /* is this resume from power down */ - /* well, if it was, we are going to jump to - * whatever address we stashed in gstatus3, - * and gstatus4 will hold the wake interrupt - * source for the OS to look at - */ - ldrne pc, [r1, #4] - - - /* >> CFG_VIDEO_LOGO_MAX_SIZE */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l: - str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - -/* we are going to jump into the C part of the init now */ -spin: - b _steppingstone_done - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -cpu_init_crit: - - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - - bl lowlevel_init - - mov lr, ip - mov pc, lr - diff --git a/qiboot/src/cpu/s3c2410/start_qi.c b/qiboot/src/cpu/s3c2410/start_qi.c deleted file mode 100644 index 4d9b7ae..0000000 --- a/qiboot/src/cpu/s3c2410/start_qi.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * Andy Green - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* NOTE this stuff runs in steppingstone context! */ - - -#include -#include "nand_read.h" -#include - -#define stringify2(s) stringify1(s) -#define stringify1(s) #s - - -extern void bootloader_second_phase(void); - -const struct board_api *boards[] = { - &board_api_gta01, - NULL /* always last */ -}; - - -struct board_api const * this_board; -extern int is_jtag; - -void start_qi(void) -{ - int flag = 0; - int board = 0; - - /* - * well, we can be running on this CPU two different ways. - * - * 1) We were copied into steppingstone and TEXT_BASE already - * by JTAG. We don't have to do anything else. JTAG script - * then sets data at address 0x4 to 0xffffffff as a signal we - * are running by JTAG. - * - * 2) We only got our first 4K into steppingstone, we need to copy - * the rest of ourselves into TEXT_BASE. - * - * So we do the copy out of NAND only if we see we did not come up - * under control of JTAG. - */ - - if (!is_jtag) - /* - * We got the first 4KBytes of the bootloader pulled into the - * steppingstone SRAM for free. Now we pull the whole bootloader - * image into SDRAM. - * - * This code and the .S files are arranged by the linker script - * to expect to run from 0x0. But the linker script has told - * everything else to expect to run from 0x33000000+. That's - * why we are going to be able to copy this code and not have it - * crash when we run it from there. - */ - - /* We randomly pull 32KBytes of bootloader */ - if (nand_read_ll((u8 *)TEXT_BASE, 0, 32 * 1024 / 512) < 0) - goto unhappy; - - /* ask all the boards we support in turn if they recognize this - * hardware we are running on, accept the first positive answer - */ - - this_board = boards[board]; - while (!flag && this_board) { - - /* check if it is the right board... */ - if (this_board->is_this_board()) { - flag = 1; - continue; - } - - this_board = boards[board++]; - } - - /* No valid board found */ - if (!this_board) - goto unhappy; - - this_board->port_init(); - set_putc_func(this_board->putc); - - /* stick some hello messages on debug console */ - - puts("\n\n\nQi Bootloader "stringify2(QI_CPU)" " - stringify2(BUILD_HOST)" " - stringify2(BUILD_VERSION)" " - "\n"); - - puts(stringify2(BUILD_DATE) " Copyright (C) 2008 Openmoko, Inc.\n"); - puts("\n Detected: "); - - puts(this_board->name); - puts(", "); - puts((this_board->get_board_variant)()->name); - puts("\n"); - - - /* - * jump to bootloader_second_phase() running from DRAM copy - */ - bootloader_second_phase(); - -unhappy: - while(1) - ; - -} diff --git a/qiboot/src/cpu/s3c2442/gta02.c b/qiboot/src/cpu/s3c2442/gta02.c deleted file mode 100644 index 13be2ac..0000000 --- a/qiboot/src/cpu/s3c2442/gta02.c +++ /dev/null @@ -1,740 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: Andy Green - * - * (port_init_gta02 came out of Openmoko U-Boot) - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define GTA02_DEBUG_UART 2 -#define PCF50633_I2C_ADS 0x73 -#define BOOST_TO_400MHZ 1 - -static int battery_condition_reasonable = 0; - -extern unsigned long partition_offset_blocks; -extern unsigned long partition_length_blocks; - -const struct board_api board_api_gta02; - -struct nand_dynparts { - const char *name; /* name of this partition for Linux */ - u32 good_length; /* bytes needed from good sectors in this partition */ - u32 true_offset; -}; - -/* - * These are the NAND partitions U-Boot leaves in GTA02 NAND. - * The "dynparts" business means that in the case of bad blocks, all the - * following partitions move up accordingly to have the right amount of - * good blocks. To allow for this, the length of the last, largest - * partition is computed according to the bad blocks that went before. - */ - -static struct nand_dynparts nand_dynparts[] = { - { "qi", 0x40000 }, - { "depr-ub-env", 0x40000 }, - { "kernel", 0x800000 }, - { "depr", 0xa0000 }, - { "identity-ext2", 0x40000 }, - { "rootfs", 0 }, -}; - -static u32 nand_extent_block512 = 256 * 1024 * 1024 / 512; - -const struct pcf50633_init pcf50633_init[] = { - - { PCF50633_REG_OOCWAKE, 0xd3 }, /* wake from ONKEY,EXTON!,RTC,USB,ADP */ - { PCF50633_REG_OOCTIM1, 0xaa }, /* debounce 14ms everything */ - { PCF50633_REG_OOCTIM2, 0x4a }, - { PCF50633_REG_OOCMODE, 0x55 }, - { PCF50633_REG_OOCCTL, 0x47 }, - - { PCF50633_REG_GPIO2CFG, 0x00 }, /* GSM_ON = 0 */ - { PCF50633_REG_GPIOCTL, 0x01 }, /* only GPIO1 is input */ - - { PCF50633_REG_SVMCTL, 0x08 }, /* 3.10V SYS vth, 62ms filter */ - { PCF50633_REG_BVMCTL, 0x02 }, /* 2.80V BAT vth, 62ms filter */ - - { PCF50633_REG_AUTOENA, 0x01 }, /* always on */ - - { PCF50633_REG_DOWN1OUT, 0x1b }, /* 1.3V (0x1b * .025V + 0.625V) */ - { PCF50633_REG_DOWN1ENA, 0x02 }, /* enabled if GPIO1 = HIGH */ - { PCF50633_REG_HCLDOOUT, 21 }, /* 3.0V (21 * 0.1V + 0.9V) */ - { PCF50633_REG_HCLDOENA, 0x01 }, /* ON by default*/ - - { PCF50633_REG_DOWN1OUT, 0x1b }, /* 1.3V (0x1b * .025V + 0.625V) */ - { PCF50633_REG_DOWN1ENA, 0x02 }, /* enabled if GPIO1 = HIGH */ - - { PCF50633_REG_INT1M, 0x00 }, - { PCF50633_REG_INT2M, 0x00 }, - { PCF50633_REG_INT3M, 0x00 }, - { PCF50633_REG_INT4M, 0x00 }, - { PCF50633_REG_INT5M, 0x00 }, - - { PCF50633_REG_MBCC2, 0x28 }, /* Vbatconid=2.7V, Vmax=4.20V */ - { PCF50633_REG_MBCC3, 0x19 }, /* 25/255 == 98mA pre-charge */ - { PCF50633_REG_MBCC4, 0xff }, /* 255/255 == 1A adapter fast */ - { PCF50633_REG_MBCC5, 0xff }, /* 255/255 == 1A usb fast */ - { PCF50633_REG_MBCC6, 0x01 }, /* cutoff current 2/32 * Ichg */ - { PCF50633_REG_MBCC7, 0x00 }, /* 1.6A max bat curr, USB 100mA */ - { PCF50633_REG_MBCC8, 0x00 }, - { PCF50633_REG_MBCC1, 0xff }, /* chgena */ - - { PCF50633_REG_LDO1ENA, 2 }, /* accel enabled if GPIO1 = H */ - { PCF50633_REG_LDO2ENA, 2 }, /* codec enabled if GPIO1 = H */ - { PCF50633_REG_LDO4ENA, 0 }, /* bt off */ - { PCF50633_REG_LDO5ENA, 0 }, /* gps off */ - { PCF50633_REG_LDO6ENA, 2 }, /* lcm enabled if GPIO1 = H */ - - { PCF50633_REG_BBCCTL, 0x19 }, /* 3V, 200uA, on */ - { PCF50633_REG_OOCSHDWN, 0x04 }, /* defeat 8s death from lowsys on A5 */ - -}; - -static const struct board_variant board_variants[] = { - [0] = { - .name = "A5 PCB", - .machine_revision = 0x350, - }, - [1] = { - .name = "A6 PCB", - .machine_revision = 0x360, - }, - [9] = { /* 01001 */ - .name = "A7 PCB", - .machine_revision = 0x360, /* report as A6 */ - }, -}; - - -void port_init_gta02(void) -{ - unsigned int * MPLLCON = (unsigned int *)0x4c000004; - unsigned int * UPLLCON = (unsigned int *)0x4c000008; - unsigned int * CLKDIVN = (unsigned int *)0x4c000014; - int n; - u32 block512 = 0; - u32 start_block512 = 0; - const u32 GTA02_NAND_READBLOCK_SIZE = 2048; - extern int s3c2442_nand_is_bad_block(unsigned long block_index_512); - - //CAUTION:Follow the configuration order for setting the ports. - // 1) setting value(GPnDAT) - // 2) setting control register (GPnCON) - // 3) configure pull-down resistor(GPnUP) - - /* 32bit data bus configuration */ - /* - * === PORT A GROUP - * Ports : GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12 - * Signal : nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 - * Binary : 1 1 1 , 1 1 1 1 , 1 1 1 1 - * Ports : GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 - * Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 - * Binary : 1 1 1 1 , 1 1 1 1 , 1 1 1 1 - */ - rGPACON = 0x007E5FFF; - rGPADAT = 0x00000000; - /* - * ===* PORT B GROUP - * Ports : GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 - * Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard - * Setting: INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT - * Binary : 00 , 01 00 , 01 00 , 01 01 , 01 01 , 01 01 - */ - rGPBCON = 0x00155555; - rGPBUP = 0x000007FF; - rGPBDAT = 0x00000000; - /* - * === PORT C GROUP - * Ports : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0 - * Signal : VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND - * Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 - */ - rGPCCON = 0x55555155; - rGPCUP = 0x0000FFFF & ~(1 << 5); - rGPCDAT = (1 << 13) | (1 << 15); /* index detect -> hi */ - /* - * === PORT D GROUP - * Ports : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 - * Signal : VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 - * Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 ,10 10 - */ - rGPDCON = 0x55555555; - rGPDUP = 0x0000FFFF; - rGPDDAT = (1 << 0) | (1 << 3) | (1 << 4); /* index detect -> hi */ - /* - * === PORT E GROUP - * Ports : GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4 - * Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO - * Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , - * ------------------------------------------------------------------------------------------------------- - * Ports : GPE3 GPE2 GPE1 GPE0 - * Signal : I2SSDI CDCLK I2SSCLK I2SLRCK - * Binary : 10 10 , 10 10 - */ - rGPECON = 0xAAAAAAAA; - rGPEUP = 0x0000FFFF & ~(1 << 11); - rGPEDAT = 0x00000000; - /* - * === PORT F GROUP - * Ports : GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 - * Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0 - * Setting: Output Output Output Output EINT3 EINT2 EINT1 EINT0 - * Binary : 01 01 , 01 01 , 10 10 , 10 10 - */ - /* pulldown on GPF03: TP-4705+debug - debug conn will float */ - rGPFCON = 0x00008AAA; - rGPFUP = 0x000000FF & ~(1 << 3); - rGPFDAT = 0x00000000; - - - /* - * === PORT G GROUP - * Ports : GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6 - * Signal : nYPON YMON nXPON XMON EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI - * Setting: nYPON YMON nXPON XMON EINT19 Output Output Output SPICLK1 SPIMOSI1 - * Binary : 11 11 , 11 11 , 10 01 , 01 01 , 11 11 - * ----------------------------------------------------------------------------------------- - * Ports : GPG5 GPG4 GPG3 GPG2 GPG1 GPG0 - * Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA - * Setting: SPIMISO1 LCD_PWRDN EINT11 nSS0 EINT9 EINT8 - * Binary : 11 11 , 10 11 , 10 10 - */ - rGPGCON = 0x01AAFE79; - rGPGUP = 0x0000FFFF; - rGPGDAT = 0x00000000; - - /* - * === PORT H GROUP - * Ports : GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0 - * Signal : CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0 - * Binary : 10 , 10 10 , 11 11 , 10 10 , 10 10 , 10 10 - */ - -/* - * FIXME the following should be removed eventually and only the first stanza - * kept unconditionally. As it stands it allows TX and RTS to drive high into - * a powered-down GSM unit, which draws considerable fault current. - * - * However kernels earlier than andy-tracking from end Feb 2009 do not enforce - * the mode of these GPIOs, so Qi doing the correct thing here "breaks GSM" - * apparently for those users. - * - * Upgrading to current kernel will solve this, so after most distros are on - * 2.6.29-rc3 and later, we should return here and again disable driving out - * into unpowered GSM. - */ - -#if 0 - rGPHCON = 0x001AAA82; /* H1 and H2 are INPUTs to start with, not UART */ -#else - rGPHCON = 0x001AAAAA; /* Wrong but compatible: H1 and H2 = UART */ -#endif - - /* pulldown on GPH08: UEXTCLK, just floats! - * pulldown GPH1 -- nCTS0 / RTS_MODEM -- floats when GSM off - * pulldown GPH3 -- RXD[0] / RX_MODEM -- floats when GSM off - */ - rGPHUP = 0x000007FF & ~(1 << 8) & ~(1 << 1) & ~(1 << 3); - rGPHDAT = 0x00000000; - - /* pulldown on GPJ00: input, just floats! */ - /* pulldown on GPJ07: WLAN module WLAN_GPIO0, no ext pull */ - rGPJCON = 0x1551544; - rGPJUP = 0x1ffff & ~(1 << 0) & ~(1 << 7); - rGPJDAT = 0x00000100; - - rGPJDAT |= (1 << 4) | (1 << 6); - /* Set GPJ4 to high (nGSM_EN) */ - /* Set GPJ6 to high (nDL_GSM) */ - rGPJDAT &= ~(1 << 5); /* Set GPJ5 to low 3D RST */ - - /* leaving Glamo forced to Reset# active here killed - * U-Boot when you touched the memory region - */ - - rGPJDAT |= (1 << 5); /* Set GPJ5 to high 3D RST */ - - - /* - * We have to talk to the PMU a little bit - */ - - for (n = 0; n < ARRAY_SIZE(pcf50633_init); n++) - i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, - pcf50633_init[n].index, pcf50633_init[n].value); - - /* what does the battery monitoring unit say about the battery? */ - - battery_condition_reasonable = !(i2c_read_sync(&bb_s3c24xx, - PCF50633_I2C_ADS, PCF50633_REG_BVMCTL) & 1); - - if (battery_condition_reasonable) { - /* change CPU clocking to 400MHz 1:4:8 */ - - /* clock divide 1:4:8 - do it first */ - *CLKDIVN = 5; - /* configure UPLL */ - *UPLLCON = ((88 << 12) + (4 << 4) + 2); - /* Magic delay: Page 7-19, seven nops between UPLL and MPLL */ - asm __volatile__ ( - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - ); - /* configure MPLL */ - *MPLLCON = ((42 << 12) + (1 << 4) + 0); - - /* get debug UART working at 115kbps */ - serial_init_115200_s3c24xx(GTA02_DEBUG_UART, 50 /* 50MHz */); - } else { - serial_init_115200_s3c24xx(GTA02_DEBUG_UART, 33 /* 33MHz */); - } - - /* we're going to use Glamo for SD Card access, so we need to init the - * evil beast - */ - glamo_core_init(); - - /* - * dynparts computation - */ - - n = 0; - while (n < ARRAY_SIZE(nand_dynparts)) { - - if (nand_dynparts[n].good_length) - while (nand_dynparts[n].good_length) { - if (!s3c2442_nand_is_bad_block(block512)) - nand_dynparts[n].good_length -= - GTA02_NAND_READBLOCK_SIZE; - block512 += GTA02_NAND_READBLOCK_SIZE / 512; - } - else - /* - * cannot afford to compute real size of last block - * set it to extent - end of last block - */ - block512 = nand_extent_block512; - - /* stash a copy of real offset for each partition */ - nand_dynparts[n].true_offset = start_block512; - - /* and the accurate length */ - nand_dynparts[n].good_length = block512 - start_block512; - - start_block512 = block512; - - n++; - } - - /* fix up the true start of kernel partition */ - - ((struct board_api *)&board_api_gta02)->kernel_source[3]. - offset_blocks512_if_no_partition = nand_dynparts[2].true_offset; - -} - -/** - * returns PCB revision information in b9,b8 and b2,b1,b0 - * Pre-GTA02 A6 returns 0x000 - * GTA02 A6 returns 0x001 - */ - -int gta02_get_pcb_revision(void) -{ - int n; - u32 u; - - /* make C13 and C15 pulled-down inputs */ - rGPCCON &= ~0xcc000000; - rGPCUP &= ~((1 << 13) | (1 << 15)); - /* D0, D3 and D4 pulled-down inputs */ - rGPDCON &= ~0x000003c3; - rGPDUP &= ~((1 << 0) | (1 << 3) | (1 << 4)); - - /* delay after changing pulldowns */ - u = rGPCDAT; - u = rGPDDAT; - - /* read the version info */ - u = rGPCDAT; - n = (u >> (13 - 0)) & 0x001; - n |= (u >> (15 - 1)) & 0x002; - u = rGPDDAT; - n |= (u << (0 + 2)) & 0x004; - - n |= (u << (3 - 3)) & 0x008; - n |= (u << (4 - 4)) & 0x010; - - /* - * when not being interrogated, all of the revision GPIO - * are set to output HIGH without pulldown so no current flows - * if they are NC or pulled up. - */ - /* make C13 and C15 high ouputs with no pulldowns */ - rGPCCON |= 0x44000000; - rGPCUP |= (1 << 13) | (1 << 15); - rGPCDAT |= (1 << 13) | (1 << 15); - /* D0, D3 and D4 high ouputs with no pulldowns */ - rGPDCON |= 0x00000141; - rGPDUP |= (1 << 0) | (1 << 3) | (1 << 4); - rGPDDAT |= (1 << 0) | (1 << 3) | (1 << 4); - - n &= 1; - - return n; -} - -int sd_card_init_gta02(void) -{ - extern int mmc_init(int verbose); - - return mmc_init(1); -} - -int sd_card_block_read_gta02(unsigned char * buf, unsigned long start512, - int blocks512) -{ -unsigned long mmc_bread(int dev_num, unsigned long blknr, unsigned long blkcnt, - void *dst); - - return mmc_bread(0, start512, blocks512, buf); -} - -/* return nonzero if we believe we run on GTA02 */ - -int is_this_board_gta02(void) -{ - /* look for GTA02 NOR */ - - *(volatile unsigned short *)(0x18000000) = 0x98; - - return !!(*(volatile unsigned short *)(0x18000000) == 0x0020); -} - -const struct board_variant const * get_board_variant_gta02(void) -{ - int rev = gta02_get_pcb_revision() & 0x1f; - - if (!board_variants[rev].name) - return &board_variants[1]; /* A6 */ - - return &board_variants[rev]; -} - -static __attribute__ (( section (".steppingstone") )) void putc_gta02(char c) -{ - serial_putc_s3c24xx(GTA02_DEBUG_UART, c); -} - -static void close_gta02(void) -{ - /* explicitly clear any pending 8s timeout */ - - i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_OOCSHDWN, 0x04); - - /* clear any pending timeouts by reading interrupts */ - - i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT1); - i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT2); - i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT3); - i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT4); - i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT5); - - /* set I2C GPIO back to peripheral unit */ - - (bb_s3c24xx.close)(); - - /* aux back to being EINT */ - rGPFCON = 0x0000AAAA; - -} - -/* Here we will care only about AUX button as polling for PWR button - * through i2c slows down the boot */ - -static u8 get_ui_keys_gta02(void) -{ - u8 keys; - u8 ret = 0; - static u8 old_keys = 0; /* previous state for debounce */ - static u8 older_keys = 0; /* previous debounced output for edge detect */ - - /* GPF6 is AUX on GTA02, map to UI_ACTION_SKIPKERNEL, down = 1 */ - keys = !!(rGPFDAT & (1 << 6)); - - /* edge action */ - if ((old_keys & 1) && !(older_keys & 1)) - ret |= UI_ACTION_SKIPKERNEL; - - older_keys = old_keys; - old_keys = keys; - - return ret; -} - -static u8 get_ui_debug_gta02(void) -{ - /* PWR button state can be seen in OOCSTAT b0, down = 0, map to UI_ACTION_ADD_DEBUG */ - return !(i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_OOCSTAT) & 1); -} - -static void set_ui_indication_gta02(enum ui_indication ui_indication) -{ - - switch (ui_indication) { - case UI_IND_UPDATE_ONLY: - break; - - case UI_IND_MOUNT_PART: - case UI_IND_KERNEL_PULL_OK: - case UI_IND_INITRAMFS_PULL_OK: - if (battery_condition_reasonable) - rGPBDAT |= 4; - break; - - case UI_IND_KERNEL_PULL_FAIL: - case UI_IND_SKIPPING: - case UI_IND_INITRAMFS_PULL_FAIL: - case UI_IND_MOUNT_FAIL: - rGPBDAT &= ~4; - if (battery_condition_reasonable) { - rGPBDAT |= 8; - udelay(2000000); - rGPBDAT &= ~8; - udelay(200000); - } - break; - - case UI_IND_KERNEL_START: - case UI_IND_MEM_TEST: - case UI_IND_KERNEL_PULL: - case UI_IND_INITRAMFS_PULL: - rGPBDAT &= ~4; - break; - } -} - - -void post_serial_init_gta02(void) -{ - if (battery_condition_reasonable) - puts("Battery condition reasonable\n"); - else - puts("BATTERY CONDITION LOW\n"); -} - -/* - * Increment a hexadecimal digit represented by a char and - * return 1 if an overflow occured. - */ -static char inc_hexchar(char * p) -{ - if (*p == '9') - *p = 'A'; - else if (*p != 'F') - (*p)++; - else { - *p = '0'; - return 1; - } - return 0; -} - -/* - * create and append device-specific Linux kernel commandline - * - * This takes care of legacy dyanmic partition sizing and USB Ethernet - * MAC address identity information. - */ - -char * append_device_specific_cmdline_gta02(char * cmdline) -{ - int n = 0; - int i; - int len; - static char mac[64]; - struct kernel_source const * real_kernel = this_kernel; - - /* - * dynparts computation - */ - - cmdline += strlen(strcpy(cmdline, - " mtdparts=physmap-flash:-(nor);neo1973-nand:")); - - while (n < ARRAY_SIZE(nand_dynparts)) { - - *cmdline++ = '0'; - *cmdline++ = 'x'; - set32(cmdline, nand_dynparts[n].good_length * 512); - cmdline += 8; - *cmdline++ = '('; - cmdline += strlen(strcpy(cmdline, nand_dynparts[n].name)); - *cmdline++ = ')'; - - if (++n == ARRAY_SIZE(nand_dynparts)) - *cmdline++ = ' '; - else - *cmdline++ = ','; - - } - - *cmdline = '\0'; - - /* - * Identity - */ - - /* position ourselves at true start of GTA02 identity partition */ - partition_offset_blocks = nand_dynparts[4].true_offset; - partition_length_blocks = 0x40000 / 512; - - /* - * lie that we are in NAND context... GTA02 specific - * all filesystem access is completed before we are called - */ - this_kernel = &board_api_gta02.kernel_source[3]; - - if (!ext2fs_mount()) { - puts("Unable to mount ext2 filesystem\n"); - goto bail; - } - - len = ext2fs_open("usb"); - if (len < 0) { - puts(" Open failed\n"); - goto bail; - } - - n = ext2fs_read(mac, sizeof(mac)); - if (n < 0) { - puts(" Read failed\n"); - goto bail; - } - - mac[len] = '\0'; - - cmdline += strlen(strcpy(cmdline, " g_ether.dev_addr=")); - cmdline += strlen(strcpy(cmdline, &mac[2])); - - for (i = 0; i != 10; i++) { - if ((i % 3) == 2) - continue; - if (!inc_hexchar(mac + 18 - i)) - break; /* Carry not needed. */ - } - - cmdline += strlen(strcpy(cmdline, " g_ether.host_addr=")); - cmdline += strlen(strcpy(cmdline, &mac[2])); - *cmdline++ = ' ' ; -bail: - this_kernel = real_kernel; - - *cmdline = '\0'; - - return cmdline; -} - -/* - * our API for bootloader on this machine - */ - -const struct board_api board_api_gta02 = { - .name = "Freerunner / GTA02", - .linux_machine_id = 1304, - .linux_mem_start = 0x30000000, - .linux_mem_size = (128 * 1024 * 1024), - .linux_tag_placement = 0x30000000 + 0x100, - .get_board_variant = get_board_variant_gta02, - .is_this_board = is_this_board_gta02, - .port_init = port_init_gta02, - .post_serial_init = post_serial_init_gta02, - .append_device_specific_cmdline = append_device_specific_cmdline_gta02, - .putc = putc_gta02, - .close = close_gta02, - .get_ui_keys = get_ui_keys_gta02, - .get_ui_debug = get_ui_debug_gta02, - .set_ui_indication = set_ui_indication_gta02, - .commandline_board = "loglevel=4 " - "console=tty0 " - "console=ttySAC2,115200 " - "init=/sbin/init " - "ro ", - .commandline_board_debug = " loglevel=8", - .noboot = "boot/noboot-GTA02", - .append = "boot/append-GTA02", - /* these are the ways we could boot GTA02 in the order to try */ - .kernel_source = { - [0] = { - .name = "SD Card EXT2 P1 Kernel", - .block_init = sd_card_init_gta02, - .block_read = sd_card_block_read_gta02, - .partition_index = 1, - .filesystem = FS_EXT2, - .filepath = "boot/uImage-GTA02.bin", - .commandline_append = " root=/dev/mmcblk0p1 rootdelay=1 ", - }, - [1] = { - .name = "SD Card EXT2 P2 Kernel", - .block_init = sd_card_init_gta02, - .block_read = sd_card_block_read_gta02, - .partition_index = 2, - .filesystem = FS_EXT2, - .filepath = "boot/uImage-GTA02.bin", - .commandline_append = " root=/dev/mmcblk0p2 rootdelay=1 ", - }, - [2] = { - .name = "SD Card EXT2 P3 Kernel", - .block_init = sd_card_init_gta02, - .block_read = sd_card_block_read_gta02, - .partition_index = 3, - .filesystem = FS_EXT2, - .filepath = "boot/uImage-GTA02.bin", - .commandline_append = " root=/dev/mmcblk0p3 rootdelay=1 ", - }, - [3] = { - .name = "NAND Kernel", - .block_read = nand_read_ll, - /* NOTE offset below is replaced at runtime */ - .offset_blocks512_if_no_partition = 0x80000 / 512, - .filesystem = FS_RAW, - .commandline_append = " rootfstype=jffs2 " - "root=/dev/mtdblock6 ", - }, - }, -}; diff --git a/qiboot/src/cpu/s3c2442/i2c-bitbang-s3c24xx.c b/qiboot/src/cpu/s3c2442/i2c-bitbang-s3c24xx.c deleted file mode 100644 index e68b9b9..0000000 --- a/qiboot/src/cpu/s3c2442/i2c-bitbang-s3c24xx.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: Andy Green - * - * s3c24xx-specific i2c used by, eg, GTA02 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -static char i2c_read_sda_s3c24xx(void) -{ - return (rGPEDAT & 0x8000) != 0; -} - -static void i2c_set_s3c24xx(char clock, char data) -{ - if (clock) /* SCL <- input */ - rGPECON = (rGPECON & ~0x30000000); - else { /* SCL <- output 0 */ - rGPEDAT = (rGPEDAT & ~0x4000); - rGPECON = (rGPECON & ~0x30000000) | 0x10000000; - } - if (data) /* SDA <- input */ - rGPECON = (rGPECON & ~0xc0000000); - else { /* SDA <- output 0 */ - rGPEDAT = (rGPEDAT & ~0x8000); - rGPECON = (rGPECON & ~0xc0000000) | 0x40000000; - } -} - -static void i2c_close_s3c24xx(void) -{ - /* set back to hardware I2C ready for Linux */ - rGPECON = (rGPECON & ~0xf0000000) | 0xa0000000; -} - -static void i2c_spin_s3c24xx(void) -{ - int n; - - for (n = 0; n < 1000; n++) - rGPJDAT |= (1 << 5); -} - -struct i2c_bitbang bb_s3c24xx = { - .read_sda = i2c_read_sda_s3c24xx, - .set = i2c_set_s3c24xx, - .spin = i2c_spin_s3c24xx, - .close = i2c_close_s3c24xx, -}; diff --git a/qiboot/src/cpu/s3c2442/lowlevel_init.S b/qiboot/src/cpu/s3c2442/lowlevel_init.S deleted file mode 100644 index 2a1654c..0000000 --- a/qiboot/src/cpu/s3c2442/lowlevel_init.S +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Modified for the FIC Neo1973 GTA01 by Harald Welte - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* NOTE this stuff runs in steppingstone context! */ - - -/* - * #include - * #include - */ -#define __ASM_MODE__ -#include - -/* - * - * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S - * - * Copyright (C) 2002 Samsung Electronics SW.LEE - * - */ - -#define BWSCON 0x48000000 - -/* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW16 + WAIT + UBLB) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* BANK1CON: Smedia Glamo 3362 (on GTA02) */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x3 /* 4clk */ -#define B1_Tacc 0x3 /* 4clk */ -#define B1_Tcoh 0x3 /* 4clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0x0 /* 0clk */ -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 /* 14clk */ -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x0 /* 0clk */ -#define B3_Tacp 0x3 /* 6clk */ -#define B3_PMC 0x0 /* normal */ - -#define B4_Tacs 0x0 /* 0clk */ -#define B4_Tcos 0x0 /* 0clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x0 /* 0clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x0 /* 0clk */ -#define B5_Tacc 0x7 /* 14clk */ -#define B5_Tcoh 0x0 /* 0clk */ -#define B5_Tah 0x0 /* 0clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ - -#define B6_SCAN 0x1 /* 9bit */ -#define B7_SCAN 0x1 /* 9bit */ - - -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ - -/* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x1 /* 3clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -//#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ -#define REFCNT 997 /* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */ -/**************************************/ - -.globl lowlevel_init -lowlevel_init: - - ldr r0, =SMRDATA - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #13*4 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* setup asynchronous bus mode */ - mrc p15, 0, r1 ,c1 ,c0, 0 - orr r1, r1, #0xc0000000 - mcr p15, 0, r1, c1, c0, 0 - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ -SMRDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0xb1 - .word 0x30 - .word 0x30 diff --git a/qiboot/src/cpu/s3c2442/nand_read.c b/qiboot/src/cpu/s3c2442/nand_read.c deleted file mode 100644 index 8206717..0000000 --- a/qiboot/src/cpu/s3c2442/nand_read.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * nand_read.c: Simple NAND read functions for booting from NAND - * - * This is used by cpu/arm920/start.S assembler code, - * and the board-specific linker script must make sure this - * file is linked within the first 4kB of NAND flash. - * - * Taken from GPLv2 licensed vivi bootloader, - * Copyright (C) 2002 MIZI Research, Inc. - * - * Author: Hwang, Chideok - * Date : $Date: 2004/02/04 10:37:37 $ - * - * u-boot integration and bad-block skipping (C) 2006 by OpenMoko, Inc. - * Author: Harald Welte - */ - -/* NOTE this stuff runs in steppingstone context! */ - -/* the API refers to 512-byte blocks */ - -#include -#include "nand_read.h" - -#define NAND_CMD_READ0 0 -#define NAND_CMD_READSTART 0x30 - -#define __REGb(x) (*(volatile unsigned char *)(x)) -#define __REGw(x) (*(volatile unsigned short *)(x)) -#define __REGi(x) (*(volatile unsigned int *)(x)) -#define NF_BASE 0x4e000000 -#define NFCONF __REGi(NF_BASE + 0x0) -#define NFCONT __REGi(NF_BASE + 0x4) -#define NFCMD __REGb(NF_BASE + 0x8) -#define NFADDR __REGb(NF_BASE + 0xc) -#define NFDATA __REGb(NF_BASE + 0x10) -#define NFDATA16 __REGw(NF_BASE + 0x10) -#define NFSTAT __REGb(NF_BASE + 0x20) -#define NFSTAT_BUSY 1 -#define nand_select() (NFCONT &= ~(1 << 1)) -#define nand_deselect() (NFCONT |= (1 << 1)) -#define nand_clear_RnB() (NFSTAT |= (1 << 2)) - -static inline void nand_wait(void) -{ - int i; - - while (!(NFSTAT & NFSTAT_BUSY)) - for (i=0; i<10; i++); -} - -/* configuration for 2440 with 2048byte sized flash */ -#define NAND_5_ADDR_CYCLE -#define NAND_PAGE_SIZE 2048 -#define BAD_BLOCK_OFFSET NAND_PAGE_SIZE -#define NAND_BLOCK_MASK (NAND_PAGE_SIZE - 1) -#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE * 64) - -int s3c2442_nand_is_bad_block(unsigned long block_index) -{ - unsigned char data; - unsigned long page_num; - - nand_select(); - nand_clear_RnB(); - page_num = block_index >> 2; /* addr / 2048 */ - NFCMD = NAND_CMD_READ0; - NFADDR = BAD_BLOCK_OFFSET & 0xff; - NFADDR = (BAD_BLOCK_OFFSET >> 8) & 0xff; - NFADDR = page_num & 0xff; - NFADDR = (page_num >> 8) & 0xff; - NFADDR = (page_num >> 16) & 0xff; - NFCMD = NAND_CMD_READSTART; - nand_wait(); - data = (NFDATA & 0xff); - - if (data != 0xff) - return 1; - - return 0; -} - -static int nand_read_page_ll(unsigned char *buf, unsigned long block512, int blocks512) -{ - unsigned short *ptr16 = (unsigned short *)buf; - unsigned int i, page_num; - unsigned int block_amount; - int blocks_possible = (3 - (block512 & 3)) + 1; - - - if (blocks512 > blocks_possible) - blocks512 = blocks_possible; - - block_amount = (NAND_PAGE_SIZE / 4 / 2) * blocks512; - - nand_clear_RnB(); - - NFCMD = NAND_CMD_READ0; - - page_num = block512 >> 2; /* 512 block -> 2048 block */ - /* Write Address */ - NFADDR = 0; - NFADDR = (block512 & 3) << 1; /* which 512 block in 2048 */ - NFADDR = page_num & 0xff; - NFADDR = (page_num >> 8) & 0xff; - NFADDR = (page_num >> 16) & 0xff; - NFCMD = NAND_CMD_READSTART; - nand_wait(); - - for (i = 0; i < block_amount; i++) - *ptr16++ = NFDATA16; - - return blocks512; -} - - -/* low level nand read function */ -int nand_read_ll(unsigned char *buf, unsigned long start_block512, - int blocks512) -{ - int i, j; - - /* chip Enable */ - nand_select(); - nand_clear_RnB(); - - for (i = 0; i < 10; i++) - ; - - while (blocks512 > 0) { - if (s3c2442_nand_is_bad_block(start_block512)) { - start_block512 += 4; - if (start_block512 >> 2 > BAD_BLOCK_OFFSET) - /* end of NAND */ - return -1; - continue; - } - - j = nand_read_page_ll(buf, start_block512, blocks512); - start_block512 += j; - buf += j << 9; - blocks512 -= j; - - if (this_board->get_ui_keys) - if ((this_board->get_ui_keys)() & UI_ACTION_SKIPKERNEL) { - puts(" ** skipping \n"); - return -3; - } - } - - /* chip Disable */ - nand_deselect(); - - return 0; -} - diff --git a/qiboot/src/cpu/s3c2442/nand_read.h b/qiboot/src/cpu/s3c2442/nand_read.h deleted file mode 100644 index 71aeda5..0000000 --- a/qiboot/src/cpu/s3c2442/nand_read.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * nand_read.c: Simple NAND read functions for booting from NAND - * - * This is used by cpu/arm920/start.S assembler code, - * and the board-specific linker script must make sure this - * file is linked within the first 4kB of NAND flash. - * - * Taken from GPLv2 licensed vivi bootloader, - * Copyright (C) 2002 MIZI Research, Inc. - * - * Author: Hwang, Chideok - * Date : $Date: 2004/02/04 10:37:37 $ - * - * u-boot integration and bad-block skipping (C) 2006 by OpenMoko, Inc. - * Author: Harald Welte - */ -#ifndef __NAND_READ_H -#define __NAND_READ_H - -int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size); - -#endif /* __NAND_READ_H */ diff --git a/qiboot/src/cpu/s3c2442/qi.lds b/qiboot/src/cpu/s3c2442/qi.lds deleted file mode 100644 index 600f950..0000000 --- a/qiboot/src/cpu/s3c2442/qi.lds +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - __steppingstone_always = 0x40000000; - __qi_sdram_copy = 0x33000000; - - . = __steppingstone_always; - - /* this is intended to take the first 4KBytes of stuff initially. - * We have to make sure we have .rodata* in there for everything - * because we do not compile PIC. - */ - - .text __steppingstone_always : AT (0x0) - { - src/cpu/s3c2442/start.o (.text .rodata* .data .bss) - src/cpu/s3c2442/lowlevel_init.o (.text .rodata* .data .bss) - src/cpu/s3c2442/start_qi.o (.text .rodata* .data .bss) - src/cpu/s3c2442/nand_read.o (.text .rodata* .data .bss) - src/cpu/s3c2442/serial-s3c24xx.o (.text .rodata* .data .bss) - src/memory-test.o (.text .rodata* .data .bss) - src/utils.o (.text .rodata* .data .bss) - src/ctype.o (.text .rodata* .data .bss) - * (.steppingstone) - } - - . = ALIGN(4); - .everything_else ADDR (.text) - __steppingstone_always + SIZEOF (.text) + __qi_sdram_copy : - AT ( ADDR (.text) - __steppingstone_always + SIZEOF (.text) ) { *(.text .rodata* .data) } - - . = __qi_sdram_copy + 0x800000 ; - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss) - } - - _end = .; -} diff --git a/qiboot/src/cpu/s3c2442/s3c24xx-mci.c b/qiboot/src/cpu/s3c2442/s3c24xx-mci.c deleted file mode 100644 index 42eecb9..0000000 --- a/qiboot/src/cpu/s3c2442/s3c24xx-mci.c +++ /dev/null @@ -1,569 +0,0 @@ -/* - * qi s3c24xx SD card driver - * Author: Andy Green - * based on ----> - * - * u-boot S3C2410 MMC/SD card driver - * (C) Copyright 2006 by OpenMoko, Inc. - * Author: Harald Welte - * - * based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c - * (C) 2005-2005 Thomas Kleffel - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define SDICON (*(u32 *)0x5a000000) -#define SDIPRE (*(u32 *)0x5a000004) -#define SDICARG (*(u32 *)0x5a000008) -#define SDICCON (*(u32 *)0x5a00000c) -#define SDICSTA (*(u32 *)0x5a000010) -#define SDIRSP0 (*(u32 *)0x5a000014) -#define SDIRSP1 (*(u32 *)0x5a000018) -#define SDIRSP2 (*(u32 *)0x5a00001c) -#define SDIRSP3 (*(u32 *)0x5a000020) -#define SDIDTIMER (*(u32 *)0x5a000024) -#define SDIBSIZE (*(u32 *)0x5a000028) -#define SDIDCON (*(u32 *)0x5a00002c) -#define SDIDCNT (*(u32 *)0x5a000030) -#define SDIDSTA (*(u32 *)0x5a000034) -#define SDIFSTA (*(u32 *)0x5a000038) -/* s3c2410 in GTA01 has these two last ones the other way around!!! */ -#define SDIIMSK (*(u32 *)0x5a00003c) -#define SDIDAT (*(u32 *)0x5a000040) -#define SDIDAT2410 (*(u32 *)0x5a00003c) -#define SDIIMSK2410 (*(u32 *)0x5a000040) - -#define CFG_MMC_BASE 0xff000000 - -/* FIXME: anyone who wants to use this on GTA01 / s3c2410 need to - * have this return 1 on that CPU - */ - -int am_i_s3c2410(void) -{ - return 0; -} - -#define CONFIG_MMC_WIDE -#define MMC_BLOCK_SIZE 512 - -/* - * FIXME needs to read cid and csd info to determine block size - * and other parameters - */ -static u8 mmc_buf[MMC_BLOCK_SIZE]; -static mmc_csd_t mmc_csd; -static int mmc_ready = 0; -static int wide = 0; - - -#define CMD_F_RESP 0x01 -#define CMD_F_RESP_LONG 0x02 - -static u32 *mmc_cmd(u16 cmd, u32 arg, u16 flags) -{ - static u32 resp[5]; - - u32 ccon, csta; - u32 csta_rdy_bit = S3C2410_SDICMDSTAT_CMDSENT; - - memset(resp, 0, sizeof(resp)); - -// debug("mmc_cmd CMD%d arg=0x%08x flags=%x\n", cmd, arg, flags); - - SDICSTA = 0xffffffff; - SDIDSTA = 0xffffffff; - SDIFSTA = 0xffffffff; - - SDICARG = arg; - - ccon = cmd & S3C2410_SDICMDCON_INDEX; - ccon |= S3C2410_SDICMDCON_SENDERHOST|S3C2410_SDICMDCON_CMDSTART; - - if (flags & CMD_F_RESP) { - ccon |= S3C2410_SDICMDCON_WAITRSP; - csta_rdy_bit = S3C2410_SDICMDSTAT_RSPFIN; /* 1 << 9 */ - } - - if (flags & CMD_F_RESP_LONG) - ccon |= S3C2410_SDICMDCON_LONGRSP; - - SDICCON = ccon; - - while (1) { - csta = SDICSTA; - if (csta & csta_rdy_bit) - break; - if (csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { - puts("===============> MMC CMD Timeout\n"); - SDICSTA |= S3C2410_SDICMDSTAT_CMDTIMEOUT; - break; - } - } - -// debug("final MMC CMD status 0x%x\n", csta); - - SDICSTA |= csta_rdy_bit; - - if (flags & CMD_F_RESP) { - resp[0] = SDIRSP0; - resp[1] = SDIRSP1; - resp[2] = SDIRSP2; - resp[3] = SDIRSP3; - } - - return resp; -} - -#define FIFO_FILL() ((SDIFSTA & S3C2410_SDIFSTA_COUNTMASK) >> 2) - -static int mmc_block_read(u8 *dst, u32 src, u32 len) -{ - u32 dcon, fifo; - u32 *dst_u32 = (u32 *)dst; - u32 *resp; - - if (len == 0) - return 0; - -// debug("mmc_block_rd dst %lx src %lx len %d\n", (u32)dst, src, len); - - /* set block len */ - resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, len, CMD_F_RESP); - SDIBSIZE = len; - - //SDIPRE = 0xff; - - /* setup data */ - dcon = (len >> 9) & S3C2410_SDIDCON_BLKNUM; - dcon |= S3C2410_SDIDCON_BLOCKMODE; - dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART; - if (wide) - dcon |= S3C2410_SDIDCON_WIDEBUS; - - if (!am_i_s3c2410()) - dcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART; - - SDIDCON = dcon; - - /* send read command */ - resp = mmc_cmd(MMC_CMD_READ_BLOCK, src, CMD_F_RESP); - - while (len > 0) { - u32 sdidsta = SDIDSTA; - fifo = FIFO_FILL(); - if (sdidsta & (S3C2410_SDIDSTA_FIFOFAIL| - S3C2410_SDIDSTA_CRCFAIL| - S3C2410_SDIDSTA_RXCRCFAIL| - S3C2410_SDIDSTA_DATATIMEOUT)) { - puts("mmc_block_read: err SDIDSTA=0x"); - print32(sdidsta); - puts("\n"); - return -1; - } - - if (am_i_s3c2410()) { - while (fifo--) { - //debug("dst_u32 = 0x%08x\n", dst_u32); - *(dst_u32++) = SDIDAT2410; - if (len >= 4) - len -= 4; - else { - len = 0; - break; - } - } - } else { - while (fifo--) { - //debug("dst_u32 = 0x%08x\n", dst_u32); - *(dst_u32++) = SDIDAT; - if (len >= 4) - len -= 4; - else { - len = 0; - break; - } - } - } - } - -// debug("waiting for SDIDSTA (currently 0x%08x\n", SDIDSTA); - while (!(SDIDSTA & (1 << 4))) {} -// debug("done waiting for SDIDSTA (currently 0x%08x\n", SDIDSTA); - - SDIDCON = 0; - - if (!(SDIDSTA & S3C2410_SDIDSTA_XFERFINISH)) - puts("mmc_block_read; transfer not finished!\n"); - - return 0; -} - -static int mmc_block_write(u32 dst, u8 *src, int len) -{ - puts("MMC block write not yet supported on S3C2410!\n"); - return -1; -} - - -int s3c24xx_mmc_read(u32 src, u8 *dst, int size) -{ - u32 end, part_start, part_end, part_len, aligned_start, aligned_end; - u32 mmc_block_size, mmc_block_address; - - if (size == 0) - return 0; - - if (!mmc_ready) { - puts("Please initialize the MMC first\n"); - return -1; - } - - mmc_block_size = MMC_BLOCK_SIZE; - mmc_block_address = ~(mmc_block_size - 1); - - src -= CFG_MMC_BASE; - end = src + size; - part_start = ~mmc_block_address & src; - part_end = ~mmc_block_address & end; - aligned_start = mmc_block_address & src; - aligned_end = mmc_block_address & end; - - /* all block aligned accesses */ -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_start) { - part_len = mmc_block_size - part_start; -// debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) - return -1; - - memcpy(dst, mmc_buf+part_start, part_len); - dst += part_len; - src += part_len; - } -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { -// debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read((u8 *)(dst), src, mmc_block_size)) < 0) - return -1; - } -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_end && src < end) { -// debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) - return -1; - - memcpy(dst, mmc_buf, part_end); - } - return 0; -} - -int s3c24xx_mmc_write(u8 *src, u32 dst, int size) -{ - u32 end, part_start, part_end, part_len, aligned_start, aligned_end; - u32 mmc_block_size, mmc_block_address; - - if (size == 0) - return 0; - - if (!mmc_ready) { - puts("Please initialize the MMC first\n"); - return -1; - } - - mmc_block_size = MMC_BLOCK_SIZE; - mmc_block_address = ~(mmc_block_size - 1); - - dst -= CFG_MMC_BASE; - end = dst + size; - part_start = ~mmc_block_address & dst; - part_end = ~mmc_block_address & end; - aligned_start = mmc_block_address & dst; - aligned_end = mmc_block_address & end; - - /* all block aligned accesses */ -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_start) { - part_len = mmc_block_size - part_start; -// debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// (u32)src, dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) - return -1; - - memcpy(mmc_buf+part_start, src, part_len); - if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) - return -1; - - dst += part_len; - src += part_len; - } -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { -// debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_write(dst, (u8 *)src, mmc_block_size)) < 0) - return -1; - - } -// debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_end && dst < end) { -// debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", -// src, (u32)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) - return -1; - - memcpy(mmc_buf, src, part_end); - if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) - return -1; - - } - return 0; -} - -u32 s3c24xx_mmc_bread(int dev_num, u32 blknr, u32 blkcnt, void *dst) -{ - int mmc_block_size = MMC_BLOCK_SIZE; - u32 src = blknr * mmc_block_size + CFG_MMC_BASE; - - s3c24xx_mmc_read(src, dst, blkcnt*mmc_block_size); - return blkcnt; -} - -/* MMC_DEFAULT_RCA should probably be just 1, but this may break other code - that expects it to be shifted. */ -static u_int16_t rca = MMC_DEFAULT_RCA >> 16; - -#if 0 -static u32 mmc_size(const struct mmc_csd *csd) -{ - u32 block_len, mult, blocknr; - - block_len = csd->read_bl_len << 12; - mult = csd->c_size_mult1 << 8; - blocknr = (csd->c_size+1) * mult; - - return blocknr * block_len; -} -#endif - -struct sd_cid { - char pnm_0; /* product name */ - char oid_1; /* OEM/application ID */ - char oid_0; - uint8_t mid; /* manufacturer ID */ - char pnm_4; - char pnm_3; - char pnm_2; - char pnm_1; - uint8_t psn_2; /* product serial number */ - uint8_t psn_1; - uint8_t psn_0; /* MSB */ - uint8_t prv; /* product revision */ - uint8_t crc; /* CRC7 checksum, b0 is unused and set to 1 */ - uint8_t mdt_1; /* manufacturing date, LSB, RRRRyyyy yyyymmmm */ - uint8_t mdt_0; /* MSB */ - uint8_t psn_3; /* LSB */ -}; - -static void print_mmc_cid(mmc_cid_t *cid) -{ - puts("MMC found. Card desciption is:\n"); - puts("Manufacturer ID = "); - print8(cid->id[0]); - print8(cid->id[1]); - print8(cid->id[2]); - puts("\nHW/FW Revision = "); - print8(cid->hwrev); - print8(cid->fwrev); - cid->hwrev = cid->fwrev = 0; /* null terminate string */ - puts("Product Name = "); - puts((char *)cid->name); - puts("\nSerial Number = "); - print8(cid->sn[0]); - print8(cid->sn[1]); - print8(cid->sn[2]); - puts("\nMonth = "); - printdec(cid->month); - puts("\nYear = "); - printdec(1997 + cid->year); - puts("\n"); -} - -static void print_sd_cid(const struct sd_cid *cid) -{ - puts("Manufacturer: 0x"); - print8(cid->mid); - puts("OEM \""); - this_board->putc(cid->oid_0); - this_board->putc(cid->oid_1); - puts("\"\nProduct name: \""); - this_board->putc(cid->pnm_0); - this_board->putc(cid->pnm_1); - this_board->putc(cid->pnm_2); - this_board->putc(cid->pnm_3); - this_board->putc(cid->pnm_4); - puts("\", revision "); - printdec(cid->prv >> 4); - puts("."); - printdec(cid->prv & 15); - puts("\nSerial number: "); - printdec(cid->psn_0 << 24 | cid->psn_1 << 16 | cid->psn_2 << 8 | - cid->psn_3); - puts("\nManufacturing date: "); - printdec(cid->mdt_1 & 15); - puts("/"); - printdec(2000+((cid->mdt_0 & 15) << 4)+((cid->mdt_1 & 0xf0) >> 4)); - puts("\nCRC: 0x"); - print8(cid->crc >> 1); - puts(" b0 = "); - print8(cid->crc & 1); - puts("\n"); -} - -int s3c24xx_mmc_init(int verbose) -{ - int retries, rc = -2; - int is_sd = 0; - u32 *resp; - - SDICON = S3C2410_SDICON_FIFORESET | S3C2410_SDICON_CLOCKTYPE; - SDIBSIZE = 512; - if (am_i_s3c2410()) { - /* S3C2410 has some bug that prevents reliable operation at higher speed */ - //SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ - SDIPRE = 0x02; /* 2410: SDCLK = PCLK/2 / (SDIPRE+1) = 11MHz */ - SDIDTIMER = 0xffff; - SDIIMSK2410 = 0x0; - } else { - SDIPRE = 0x05; /* 2410: SDCLK = PCLK / (SDIPRE+1) = 11MHz */ - SDIDTIMER = 0x7fffff; - SDIIMSK = 0x0; - } - - udelay(1250000); /* FIXME: 74 SDCLK cycles */ - - mmc_csd.c_size = 0; - - puts("Sending reset...\n"); - - /* reset */ - retries = 10; - resp = mmc_cmd(MMC_CMD_RESET, 0, 0); - - puts("trying to detect SD Card...\n"); - while (retries--) { - udelay(1000000); - resp = mmc_cmd(55, 0x00000000, CMD_F_RESP); - resp = mmc_cmd(41, 0x00300000, CMD_F_RESP); - - if (resp[0] & (1 << 31)) { - is_sd = 1; - break; - } - } - - if (retries < 0 && !is_sd) - return -3; - - /* try to get card id */ - resp = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, CMD_F_RESP|CMD_F_RESP_LONG); - if (resp) { - if (!is_sd) { - /* TODO configure mmc driver depending on card - attributes */ - mmc_cid_t *cid = (mmc_cid_t *)resp; - - if (verbose) - print_mmc_cid(cid); -#if 0 - sprintf((char *) mmc_dev.vendor, - "Man %02x%02x%02x Snr %02x%02x%02x", - cid->id[0], cid->id[1], cid->id[2], - cid->sn[0], cid->sn[1], cid->sn[2]); - sprintf((char *) mmc_dev.product,"%s",cid->name); - sprintf((char *) mmc_dev.revision,"%x %x", - cid->hwrev, cid->fwrev); -#endif - } - else { - struct sd_cid *cid = (struct sd_cid *) resp; - - if (verbose) - print_sd_cid(cid); -#if 0 - sprintf((char *) mmc_dev.vendor, - "Man %02 OEM %c%c \"%c%c%c%c%c\"", - cid->mid, cid->oid_0, cid->oid_1, - cid->pnm_0, cid->pnm_1, cid->pnm_2, cid->pnm_3, - cid->pnm_4); - sprintf((char *) mmc_dev.product, "%d", - cid->psn_0 << 24 | cid->psn_1 << 16 | - cid->psn_2 << 8 | cid->psn_3); - sprintf((char *) mmc_dev.revision, "%d.%d", - cid->prv >> 4, cid->prv & 15); -#endif - } - - - /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, CMD_F_RESP); - if (is_sd) - rca = resp[0] >> 16; - - resp = mmc_cmd(MMC_CMD_SEND_CSD, rca<<16, CMD_F_RESP|CMD_F_RESP_LONG); - if (resp) { - mmc_csd_t *csd = (mmc_csd_t *)resp; - memcpy(&mmc_csd, csd, sizeof(csd)); - rc = 0; - mmc_ready = 1; -#if 0 - /* FIXME add verbose printout for csd */ - printf("READ_BL_LEN=%u, C_SIZE_MULT=%u, C_SIZE=%u\n", - csd->read_bl_len, csd->c_size_mult1, csd->c_size); - printf("size = %u\n", mmc_size(csd)); -#endif - } - } - - resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca<<16, CMD_F_RESP); - -#ifdef CONFIG_MMC_WIDE - if (is_sd) { - resp = mmc_cmd(55, rca<<16, CMD_F_RESP); - resp = mmc_cmd(6, 0x02, CMD_F_RESP); - wide = 1; - } -#endif - - return rc; -} - - diff --git a/qiboot/src/cpu/s3c2442/serial-s3c24xx.c b/qiboot/src/cpu/s3c2442/serial-s3c24xx.c deleted file mode 100644 index 0f4ba22..0000000 --- a/qiboot/src/cpu/s3c2442/serial-s3c24xx.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void serial_init_115200_s3c24xx(const int uart, const int pclk_MHz) -{ - int div = (((54 * pclk_MHz) + 26) / 100) -1; - switch(uart) - { - case UART0: - rULCON0 = 0x3; - rUCON0 = 0x245; - rUFCON0 = 0x0; - rUMCON0 = 0x0; - rUBRDIV0 = div; - break; - case UART1: - rULCON1 = 0x3; - rUCON1 = 0x245; - rUFCON1 = 0x0; - rUMCON1 = 0x0; - rUBRDIV1 = div; - break; - case UART2: - rULCON2 = 0x3; - rUCON2 = 0x245; - rUFCON2 = 0x1; - rUBRDIV2 = div; - break; - default: - break; - } -} -/* - * Output a single byte to the serial port. - */ -void serial_putc_s3c24xx(const int uart, const char c) -{ - switch(uart) - { - case UART0: - while ( !( rUTRSTAT0 & 0x2 ) ); - WrUTXH0(c); - break; - case UART1: - while ( !( rUTRSTAT1 & 0x2 ) ); - WrUTXH1(c); - break; - case UART2: - while ( !( rUTRSTAT2 & 0x2 ) ); - WrUTXH2(c); - break; - default: - break; - } -} diff --git a/qiboot/src/cpu/s3c2442/start.S b/qiboot/src/cpu/s3c2442/start.S deleted file mode 100644 index 6ff9194..0000000 --- a/qiboot/src/cpu/s3c2442/start.S +++ /dev/null @@ -1,315 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define __ASM_MODE__ -#define __ASSEMBLY__ - -#include - -#define S3C2410_MISCCR_nEN_SCLK0 (1 << 17) -#define S3C2410_MISCCR_nEN_SCLK1 (1 << 18) -#define S3C2410_MISCCR_nEN_SCLKE (1 << 19) - - -.globl _start, processor_id, is_jtag - -_start: b start_code -/* if we are injected by JTAG, the script sets _istag content to nonzero */ -is_jtag: - .word 0 - -/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script - * we need to go through this hassle because before this moment, SDRAM is not - * working so we can't prep it from JTAG - */ - -_steppingstone_done: - ldr pc, _start_armboot - -_start_armboot: - .word start_qi - -_TEXT_BASE: - .word TEXT_BASE - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end -/* - * we have a stack in steppingstone because we can want to run full memory - * memory tests - */ - - .fill 128 -.globl _ss_stack -_ss_stack: - - -start_code: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -# define pWTCON 0x53000000 - - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define INTSUBMSK_val 0x0000ffff - - mov r1, #0xffffffff - ldr r0, =INTMSK - str r1, [r0] - - ldr r1, =INTSUBMSK_val - ldr r0, =INTSUBMSK - str r1, [r0] - - - /* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */ -# define CAMDIVN 0x4C000018 - - ldr r0, =CAMDIVN - mov r1, #0 - str r1, [r0] - - /* Clock asynchronous mode */ - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, #0xc0000000 - mcr p15, 0, r1, c1, c0, 0 - -#define LOCKTIME 0x4c000000 - - ldr r0, =LOCKTIME - mov r1, #0xffffff - str r1, [r0] - -# define UPLLCON 0x4c000008 -# define MPLLCON_val ((142 << 12) + (7 << 4) + 1) -# define UPLLCON_val (( 88 << 12) + (8 << 4) + 2) - - ldr r0, =UPLLCON - ldr r1, =UPLLCON_val - str r1, [r0] - - /* Page 7-19, seven nops between UPLL and MPLL */ - nop - nop - nop - nop - nop - nop - nop - - ldr r1, =MPLLCON_val - str r1, [r0, #-4] /* MPLLCON */ - -# define CLKDIVN 0x4C000014 /* clock divisor register */ -# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */ - - /* FCLK:HCLK:PCLK = 1:3:6 */ - ldr r0, =CLKDIVN - mov r1, #CLKDIVN_val - str r1, [r0] - - /* enable only CPU peripheral block clocks we actually use */ - ldr r0, =0x4c00000c /* clkcon */ - ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */ - str r1, [r0] - - /* gpio UART2 init, H port */ - ldr r0, =0x56000070 - ldr r1, =0x001AAAAA - str r1, [r0] - - /* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */ - ldr r0, =0x56000000 /* GPJ base */ - ldr r1, [r0, #0xd0] /* GPJCON */ - orr r1, r1, #(1 << 16) - str r1, [r0, #0xd0] - - ldr r1, [r0, #0xd4] /* GPJDAT */ - orr r1, r1, #(1 << 8) - str r1, [r0, #0xd4] - - - /* init uart2 */ - ldr r0, =0x50008000 - mov r1, #0x03 - str r1, [r0] - ldr r1, =0x245 - str r1, [r0, #0x04] - mov r1, #0x00 - str r1, [r0, #0x08] - mov r1, #0x00 - str r1, [r0, #0x0c] - mov r1, #0x11 - str r1, [r0, #0x28] - - ldr r0, =0x50008000 - ldr r1, =0x54 - str r1, [r0, #0x20] - -/* reset nand controller, or it is dead to us */ - - mov r1, #0x4E000000 - ldr r2, =0xfff0 @ initial value tacls=3,rph0=7,rph1=7 - ldr r3, [r1, #0] - orr r3, r3, r2 - str r3, [r1, #0] - - ldr r3, [r1, #4] - orr r3, r3, #1 @ enable nand controller - str r3, [r1, #4] - - - /* take sdram out of power down */ - ldr r0, =0x56000080 /* misccr */ - ldr r1, [ r0 ] - bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE) - str r1, [ r0 ] - - /* ensure signals stabalise */ - mov r1, #128 -1: subs r1, r1, #1 - bpl 1b - - bl cpu_init_crit - - /* ensure some refresh has happened */ - ldr r1, =0xfffff -1: subs r1, r1, #1 - bpl 1b - - /* capture full EINT situation into gstatus 4 */ - - ldr r0, =0x4A000000 /* SRCPND */ - ldr r1, [ r0 ] - and r1, r1, #0xf - - ldr r0, =0x560000BC /* gstatus4 */ - str r1, [ r0 ] - - ldr r0, =0x560000A8 /* EINTPEND */ - ldr r1, [ r0 ] - ldr r0, =0xfff0 - and r1, r1, r0 - ldr r0, =0x560000BC /* gstatus4 */ - ldr r0, [ r0 ] - orr r1, r1, r0 - ldr r0, =0x560000BC /* gstatus4 */ - str r1, [ r0 ] - - /* test for resume */ - - ldr r1, =0x560000B4 /* gstatus2 */ - ldr r0, [ r1 ] - tst r0, #0x02 /* is this resume from power down */ - /* well, if it was, we are going to jump to - * whatever address we stashed in gstatus3, - * and gstatus4 will hold the wake interrupt - * source for the OS to look at - */ - ldrne pc, [r1, #4] - - - /* >> CFG_VIDEO_LOGO_MAX_SIZE */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l: - str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - -/* we are going to jump into the C part of the init now */ -spin: - b _steppingstone_done - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -cpu_init_crit: - - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00005000 @ set bits 14, 12 D and I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - - bl lowlevel_init - - mov lr, ip - mov pc, lr - diff --git a/qiboot/src/cpu/s3c2442/start_qi.c b/qiboot/src/cpu/s3c2442/start_qi.c deleted file mode 100644 index d7136fd..0000000 --- a/qiboot/src/cpu/s3c2442/start_qi.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * Andy Green - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* NOTE this stuff runs in steppingstone context! */ - - -#include -#include "nand_read.h" -#include - -#define stringify2(s) stringify1(s) -#define stringify1(s) #s - - -extern void bootloader_second_phase(void); - -const struct board_api *boards[] = { - &board_api_gta02, - NULL /* always last */ -}; - - -struct board_api const * this_board; -extern int is_jtag; - -void start_qi(void) -{ - int flag = 0; - int board = 0; - - /* - * well, we can be running on this CPU two different ways. - * - * 1) We were copied into steppingstone and TEXT_BASE already - * by JTAG. We don't have to do anything else. JTAG script - * then sets data at address 0x4 to 0xffffffff as a signal we - * are running by JTAG. - * - * 2) We only got our first 4K into steppingstone, we need to copy - * the rest of ourselves into TEXT_BASE. - * - * So we do the copy out of NAND only if we see we did not come up - * under control of JTAG. - */ - - if (!is_jtag) - /* - * We got the first 4KBytes of the bootloader pulled into the - * steppingstone SRAM for free. Now we pull the whole bootloader - * image into SDRAM. - * - * This code and the .S files are arranged by the linker script - * to expect to run from 0x0. But the linker script has told - * everything else to expect to run from 0x33000000+. That's - * why we are going to be able to copy this code and not have it - * crash when we run it from there. - */ - - /* We randomly pull 32KBytes of bootloader */ - if (nand_read_ll((u8 *)TEXT_BASE, 0, 32 * 1024 / 512) < 0) - goto unhappy; - - /* ask all the boards we support in turn if they recognize this - * hardware we are running on, accept the first positive answer - */ - - this_board = boards[board]; - while (!flag && this_board) { - - /* check if it is the right board... */ - if (this_board->is_this_board()) { - flag = 1; - continue; - } - - this_board = boards[board++]; - } - - this_board->port_init(); - set_putc_func(this_board->putc); - - /* stick some hello messages on debug console */ - - puts("\n\n\nQi Bootloader "stringify2(QI_CPU)" " - stringify2(BUILD_HOST)" " - stringify2(BUILD_VERSION)" " - "\n"); - - puts(stringify2(BUILD_DATE) " Copyright (C) 2008 Openmoko, Inc.\n"); - puts("\n Detected: "); - - puts(this_board->name); - puts(", "); - puts((this_board->get_board_variant)()->name); - puts("\n"); - - /* - * jump to bootloader_second_phase() running from DRAM copy - */ - bootloader_second_phase(); - -unhappy: - while(1) - ; - -} diff --git a/qiboot/src/cpu/s3c6410/hs_mmc.c b/qiboot/src/cpu/s3c6410/hs_mmc.c deleted file mode 100644 index 485d2a7..0000000 --- a/qiboot/src/cpu/s3c6410/hs_mmc.c +++ /dev/null @@ -1,650 +0,0 @@ -#include -#include "hs_mmc.h" -#include -#include - -#define HCLK_OPERATION -#undef DEBUG_HSMMC -#ifdef DEBUG_HSMMC -#define dbg(x...) printf(x) -#else -#define dbg(x...) do { } while (0) -#endif - -//#include -#include -#include -//#include -//#include -//#include - -#include "hs_mmc.h" -#include - -#define SDI_Tx_buffer_HSMMC (0x51000000) -#define SDI_Rx_buffer_HSMMC (0x51000000+(0x300000)) -#define SDI_Compare_buffer_HSMMC (0x51000000+(0x600000)) - -#define Card_OneBlockSize_ver1 512 - -#define MMC_DEFAULT_RCA (1<<16) - -/* Global variables */ - -static u32 HS_DMA_END = 0; -static u32 rca = 0; - -static ulong HCLK; - -int movi_hc = 1; /* sdhc style block indexing */ -enum card_type card_type; - -/* extern functions */ -extern ulong get_HCLK(void); - - -#define s3c_hsmmc_readl(x) *((unsigned int *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) -#define s3c_hsmmc_readw(x) *((unsigned short *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) -#define s3c_hsmmc_readb(x) *((unsigned char *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) - -#define s3c_hsmmc_writel(v,x) *((unsigned int *) (((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) = v -#define s3c_hsmmc_writew(v,x) *((unsigned short *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) = v -#define s3c_hsmmc_writeb(v,x) *((unsigned char *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) = v - -#define readl(x) *((unsigned int *)(x)) -#define writel(v, x) *((unsigned int *)(x)) = v - -#define UNSTUFF_BITS(resp,start,size) \ - ({ \ - const int __size = size; \ - const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ - const int __off = 3 - ((start) / 32); \ - const int __shft = (start) & 31; \ - u32 __res; \ - \ - __res = resp[__off] >> __shft; \ - if (__size + __shft > 32) \ - __res |= resp[__off-1] << ((32 - __shft) & 31); \ - __res & __mask; \ - }) - -static int wait_for_cmd_done (void) -{ - u32 i; - ushort n_int, e_int; - - dbg("wait_for_cmd_done\n"); - for (i = 0; i < 0x20000000; i++) { - n_int = s3c_hsmmc_readw(HM_NORINTSTS); - dbg(" HM_NORINTSTS: %04x\n", n_int); - if (n_int & 0x8000) - /* any error */ - break; - if (n_int & 0x0001) - /* command complete */ - return 0; - } - - e_int = s3c_hsmmc_readw(HM_ERRINTSTS); - s3c_hsmmc_writew(e_int, HM_ERRINTSTS); - s3c_hsmmc_writew(n_int, HM_NORINTSTS); - puts("cmd error1: 0x"); - print32(e_int); - puts(", HM_NORINTSTS: 0x"); - print32(n_int); - puts("\n"); - - return -1; -} - - -static void ClearCommandCompleteStatus(void) -{ - s3c_hsmmc_writew(1 << 0, HM_NORINTSTS); - while (s3c_hsmmc_readw(HM_NORINTSTS) & 0x1) { - s3c_hsmmc_writew(1 << 0, HM_NORINTSTS); - } -} - -static void card_irq_enable(ushort temp) -{ - s3c_hsmmc_writew((s3c_hsmmc_readw(HM_NORINTSTSEN) & 0xFEFF) | (temp << 8), HM_NORINTSTSEN); -} - -void hsmmc_reset (void) -{ - s3c_hsmmc_writeb(0x3, HM_SWRST); -} - -void hsmmc_set_gpio (void) -{ - u32 reg; - - reg = readl(GPGCON) & 0xf0000000; - writel(reg | 0x02222222, GPGCON); - - reg = readl(GPGPUD) & 0xfffff000; - writel(reg, GPGPUD); -} - -static void set_transfer_mode_register (u32 MultiBlk, u32 DataDirection, u32 AutoCmd12En, u32 BlockCntEn, u32 DmaEn) -{ - s3c_hsmmc_writew((s3c_hsmmc_readw(HM_TRNMOD) & ~(0xffff)) | (MultiBlk << 5) - | (DataDirection << 4) | (AutoCmd12En << 2) - | (BlockCntEn << 1) | (DmaEn << 0), HM_TRNMOD); -// dbg("\nHM_TRNMOD = 0x%04x\n", HM_TRNMOD); -} - -static void set_arg_register (u32 arg) -{ - s3c_hsmmc_writel(arg, HM_ARGUMENT); -} - -static void set_blkcnt_register(ushort uBlkCnt) -{ - s3c_hsmmc_writew(uBlkCnt, HM_BLKCNT); -} - -static void SetSystemAddressReg(u32 SysAddr) -{ - s3c_hsmmc_writel(SysAddr, HM_SYSAD); -} - -static void set_blksize_register(ushort uDmaBufBoundary, ushort uBlkSize) -{ - s3c_hsmmc_writew((uDmaBufBoundary << 12) | (uBlkSize), HM_BLKSIZE); -} - -static void ClearErrInterruptStatus(void) -{ - while (s3c_hsmmc_readw(HM_NORINTSTS) & (0x1 << 15)) { - s3c_hsmmc_writew(s3c_hsmmc_readw(HM_NORINTSTS), HM_NORINTSTS); - s3c_hsmmc_writew(s3c_hsmmc_readw(HM_ERRINTSTS), HM_ERRINTSTS); - } -} - -static void InterruptEnable(ushort NormalIntEn, ushort ErrorIntEn) -{ - ClearErrInterruptStatus(); - s3c_hsmmc_writew(NormalIntEn, HM_NORINTSTSEN); - s3c_hsmmc_writew(ErrorIntEn, HM_ERRINTSTSEN); -} - -static void hsmmc_clock_onoff (int on) -{ - u16 reg16; - - if (on == 0) { - reg16 = s3c_hsmmc_readw(HM_CLKCON) & ~(0x1<<2); - s3c_hsmmc_writew(reg16, HM_CLKCON); - } else { - reg16 = s3c_hsmmc_readw(HM_CLKCON); - s3c_hsmmc_writew(reg16 | (0x1<<2), HM_CLKCON); - - while (1) { - reg16 = s3c_hsmmc_readw(HM_CLKCON); - if (reg16 & (0x1<<3)) /* SD_CLKSRC is Stable */ - break; - } - } -} - -static void set_clock (u32 clksrc, u32 div) -{ - u16 reg16; - u32 i; - - s3c_hsmmc_writel(0xC0004100 | (clksrc << 4), HM_CONTROL2); // rx feedback control - s3c_hsmmc_writel(0x00008080, HM_CONTROL3); // Low clock: 00008080 - s3c_hsmmc_writel(0x3 << 16, HM_CONTROL4); - - s3c_hsmmc_writew(s3c_hsmmc_readw(HM_CLKCON) & ~(0xff << 8), HM_CLKCON); - - /* SDCLK Value Setting + Internal Clock Enable */ - s3c_hsmmc_writew(((div<<8) | 0x1), HM_CLKCON); - - /* CheckInternalClockStable */ - for (i = 0; i < 0x10000; i++) { - reg16 = s3c_hsmmc_readw(HM_CLKCON); - if (reg16 & 0x2) - break; - } - if (i == 0x10000) - puts("internal clock stabilization failed\n"); - - hsmmc_clock_onoff(1); -} - -static void set_cmd_register (ushort cmd, u32 data, u32 flags) -{ - ushort val = (cmd << 8); - - if (cmd == 12) - val |= (3 << 6); - - if (flags & MMC_RSP_136) /* Long RSP */ - val |= 0x01; - else if (flags & MMC_RSP_BUSY) /* R1B */ - val |= 0x03; - else if (flags & MMC_RSP_PRESENT) /* Normal RSP */ - val |= 0x02; - - if (flags & MMC_RSP_OPCODE) - val |= (1<<4); - - if (flags & MMC_RSP_CRC) - val |= (1<<3); - - if (data) - val |= (1<<5); - -// puts("cmdreg = 0x"); -// print32(val); -// puts("\n"); - s3c_hsmmc_writew(val, HM_CMDREG); -} - -static int issue_command (ushort cmd, u32 arg, u32 data, u32 flags) -{ - int i; - -/* puts("### issue_command: "); - printdec(cmd); - puts(" 0x"); - print32(arg); - puts(" "); - printdec(data); - puts(" 0x"); - print32(flags); - puts("\n"); -*/ - /* Check CommandInhibit_CMD */ - for (i = 0; i < 0x1000000; i++) { - if (!(s3c_hsmmc_readl(HM_PRNSTS) & 0x1)) - break; - } - if (i == 0x1000000) { - puts("@@@@@@1 rHM_PRNSTS: "); - printdec(s3c_hsmmc_readl(HM_PRNSTS)); - puts("\n"); - } - - /* Check CommandInhibit_DAT */ - if (flags & MMC_RSP_BUSY) { - for (i = 0; i < 0x1000000; i++) { - if (!(s3c_hsmmc_readl(HM_PRNSTS) & 0x2)) - break; - } - if (i == 0x1000000) { - puts("@@@@@@2 rHM_PRNSTS: "); - print32(s3c_hsmmc_readl(HM_PRNSTS)); - puts("\n"); - } - } - - s3c_hsmmc_writel(arg, HM_ARGUMENT); - - set_cmd_register(cmd, data, flags); - - if (wait_for_cmd_done()) - return 0; - - ClearCommandCompleteStatus(); - - if (!(s3c_hsmmc_readw(HM_NORINTSTS) & 0x8000)) - return 1; - - puts("Command = "); - printdec((s3c_hsmmc_readw(HM_CMDREG) >> 8)); - puts(", Error Stat = 0x"); - print32(s3c_hsmmc_readw(HM_ERRINTSTS)); - return 0; -} - -static int check_card_status(void) -{ - if (!issue_command(MMC_SEND_STATUS, rca<<16, 0, MMC_RSP_R1)) - return 0; - - if (((s3c_hsmmc_readl(HM_RSPREG0) >> 9) & 0xf) == 4) { -// puts("Card is transfer status\n"); - return 1; - } - - return 1; -} - -static void set_hostctl_speed (u8 mode) -{ - u8 reg8; - - reg8 = s3c_hsmmc_readb(HM_HOSTCTL) & ~(0x1<<2); - s3c_hsmmc_writeb(reg8 | (mode<<2), HM_HOSTCTL); -} - -/* return 0: OK - * return -1: error - */ -static int set_bus_width (u32 width) -{ - u8 reg = s3c_hsmmc_readb(HM_HOSTCTL); - u8 bitmode = 0; - - card_irq_enable(0); // Disable sd card interrupt - - - if (!issue_command(MMC_APP_CMD, rca<<16, 0, MMC_RSP_R1)) - return -1; - else { - if (width == 1) { // 1-bits - bitmode = 0; - if (!issue_command(MMC_SWITCH, 0, 0, MMC_RSP_R1B)) - return -1; - } else { // 4-bits - bitmode = 1; - if (!issue_command(MMC_SWITCH, 2, 0, MMC_RSP_R1B)) - return -1; - } - } - - if (bitmode == 2) - reg |= 1 << 5; - else - reg |= bitmode << 1; - - s3c_hsmmc_writeb(reg, HM_HOSTCTL); - card_irq_enable(1); -// puts(" transfer rHM_HOSTCTL(0x28) = 0x"); -// print32(s3c_hsmmc_readb(HM_HOSTCTL)); - - return 0; -} - -static void clock_config (u32 Divisior) -{ - if (100000000 / (Divisior * 2) > 25000000) // Higher than 25MHz, it is necessary to enable high speed mode of the host controller. - set_hostctl_speed(HIGH); - else - set_hostctl_speed(NORMAL); - - hsmmc_clock_onoff(0); // when change the sd clock frequency, need to stop sd clock. - set_clock(SD_EPLL, Divisior); -} - -static void check_dma_int (void) -{ - u32 i; - - for (i = 0; i < 0x10000000; i++) { - if (s3c_hsmmc_readw(HM_NORINTSTS) & 0x0002) { - HS_DMA_END = 1; - s3c_hsmmc_writew(s3c_hsmmc_readw(HM_NORINTSTS) | 0x0002, HM_NORINTSTS); - return; - } - if (s3c_hsmmc_readw(HM_NORINTSTS) & 0x8000) { - puts("error found: "); - print32(s3c_hsmmc_readw(HM_ERRINTSTS)); - return; - } - } - - puts("check_dma_int: timeout\n"); -} - - -static void print_sd_cid(const struct sd_cid *cid) -{ - puts(" Card Type: "); - switch (card_type) { - case CARDTYPE_NONE: - puts("(None) / "); - break; - case CARDTYPE_MMC: - puts("MMC / "); - break; - case CARDTYPE_SD: - puts("SD / "); - break; - case CARDTYPE_SD20: - puts("SD 2.0 / "); - break; - case CARDTYPE_SDHC: - puts("SD 2.0 SDHC / "); - break; - } - - puts("Mfr: 0x"); - print8(cid->mid); - puts(", OEM \""); - this_board->putc(cid->oid_0); - this_board->putc(cid->oid_1); - puts("\" / "); - - this_board->putc(cid->pnm_0); - this_board->putc(cid->pnm_1); - this_board->putc(cid->pnm_2); - this_board->putc(cid->pnm_3); - this_board->putc(cid->pnm_4); - puts("\", rev "); - printdec(cid->prv >> 4); - puts("."); - printdec(cid->prv & 15); - puts(" / s/n: "); - print32(cid->psn_0 << 24 | cid->psn_1 << 16 | cid->psn_2 << 8 | - cid->psn_3); - puts(" / date: "); - printdec(cid->mdt_1 & 15); - puts("/"); - printdec(2000 + ((cid->mdt_0 & 15) << 4)+((cid->mdt_1 & 0xf0) >> 4)); - puts("\n"); -} - -unsigned int s3c6410_mmc_init (int verbose) -{ - u32 reg; - u32 width; - int resp; - int hcs; - int retries = 50; - u8 response[16]; - unsigned int r1[4]; - struct sd_cid *sd_cid = (struct sd_cid *)response; - struct mmc_csd *csd = (struct mmc_csd *)response; - u8 *p8 = (u8 *)&r1[0]; - unsigned int sd_sectors = 0; - /* we need to shift result by 8 bits spread over 4 x 32-bit regs */ - u8 mangle[] = { 7, 0, 1, 2, 11, 4, 5, 6, 15, 8, 9, 10, 0, 12, 13, 14 }; - int n; - - hsmmc_set_gpio(); - - hsmmc_reset(); - - width = 4; - - HCLK = 33000000; /* FIXME */ - hsmmc_clock_onoff(0); - - reg = readl(SCLK_GATE); - writel(reg | (1<<27), SCLK_GATE); - - set_clock(SD_EPLL, 0x80); - s3c_hsmmc_writeb(0xe, HM_TIMEOUTCON); - set_hostctl_speed(NORMAL); - - InterruptEnable(0xff, 0xff); - -// dbg("HM_NORINTSTS = %x\n", s3c_hsmmc_readw(HM_NORINTSTS)); - - /* MMC_GO_IDLE_STATE */ - issue_command(MMC_GO_IDLE_STATE, 0x00, 0, 0); - - udelay(100000); - udelay(100000); - udelay(100000); - udelay(100000); - - /* SDHC card? */ - - resp = issue_command(SD_SEND_IF_COND, 0x000001aa, - 0, MMC_CMD_BCR | MMC_RSP_R7); - if (resp && ((s3c_hsmmc_readl(HM_RSPREG0) & 0xff) == 0xaa)) { - card_type = CARDTYPE_SD20; /* 2.0 SD, may not be SDHC */ - hcs = 0x40000000; - } - - /* Well, either way let's say hello in SD card protocol */ - - while (retries--) { - - udelay(100000); - udelay(100000); - udelay(100000); - - resp = issue_command(MMC_APP_CMD, 0x00000000, 0, - MMC_RSP_R1); - if (!resp) - continue; - resp = issue_command(SD_APP_OP_COND, hcs | 0x00300000, 0, - MMC_RSP_R3); - if (!resp) - continue; - - if ((s3c_hsmmc_readl(HM_RSPREG0) >> 24) & (1 << 6)) { /* asserts block addressing */ - retries = -2; - card_type = CARDTYPE_SDHC; - } - - if ((s3c_hsmmc_readl(HM_RSPREG0) >> 24) & (1 << 7)) { /* not busy */ - retries = -2; - if (card_type == CARDTYPE_NONE) - card_type = CARDTYPE_SD; - break; - } - } - if (retries == -1) { - puts("no response\n"); - return -2; - } - - if (!issue_command(MMC_ALL_SEND_CID, 0, 0, MMC_RSP_R2)) { - puts("CID broken\n"); - return -3; - } - - r1[0] = s3c_hsmmc_readl(HM_RSPREG3); - r1[1] = s3c_hsmmc_readl(HM_RSPREG2); - r1[2] = s3c_hsmmc_readl(HM_RSPREG1); - r1[3] = s3c_hsmmc_readl(HM_RSPREG0); - - for (n = 0; n < 16; n++) - response[n] = p8[mangle[n]]; - - switch (card_type) { - case CARDTYPE_SD: - case CARDTYPE_SD20: - case CARDTYPE_SDHC: - - if (verbose) - print_sd_cid(sd_cid); - resp = issue_command(SD_SEND_RELATIVE_ADDR, MMC_DEFAULT_RCA, - 0, MMC_RSP_R6); - rca = s3c_hsmmc_readl(HM_RSPREG0) >> 16; - break; - - default: - return 1; - } - - /* grab the CSD */ - - resp = issue_command(MMC_SEND_CSD, rca << 16, 0, MMC_RSP_R2); - if (resp) { - - r1[0] = s3c_hsmmc_readl(HM_RSPREG3); - r1[1] = s3c_hsmmc_readl(HM_RSPREG2); - r1[2] = s3c_hsmmc_readl(HM_RSPREG1); - r1[3] = s3c_hsmmc_readl(HM_RSPREG0); - for (n = 0; n < 16; n++) - response[n] = p8[mangle[n]]; - - switch (card_type) { - case CARDTYPE_SDHC: - puts(" SDHC size: "); - sd_sectors = (UNSTUFF_BITS(((u32 *)&response[0]), 48, 22) - + 1) << 10; - break; - default: - puts(" MMC/SD size: "); - sd_sectors = ((((unsigned long)1 << csd->c_size_mult1) * - (unsigned long)(csd->c_size)) >> 9); - } - printdec(sd_sectors / 2048); - puts(" MiB\n"); - } else - puts("CSD grab broken\n"); - - resp = issue_command(MMC_SELECT_CARD, rca<<16, 0, MMC_RSP_R1); - if (!resp) - return 1; - - /* Operating Clock setting */ - clock_config(2); // Divisor 1 = Base clk /2 ,Divisor 2 = Base clk /4, Divisor 4 = Base clk /8 ... - - while (set_bus_width(width)); - while (!check_card_status()); - - /* MMC_SET_BLOCKLEN */ - while (!issue_command(MMC_SET_BLOCKLEN, 512, 0, MMC_RSP_R1)); - - s3c_hsmmc_writew(0xffff, HM_NORINTSTS); - - return sd_sectors; -} - -unsigned long s3c6410_mmc_bread(int dev_num, unsigned long start_blk, unsigned long blknum, - void *dst) -{ - u32 blksize; //j, , Addr_temp = start_blk; - u32 dma = 0, cmd, multi; //, TotalReadByte, read_blk_cnt = 0; - - HS_DMA_END = 0; - - blksize = Card_OneBlockSize_ver1; - - while (!check_card_status()); - - s3c_hsmmc_writew(s3c_hsmmc_readw(HM_NORINTSTSEN) & ~(DMA_STS_INT_EN | BLOCKGAP_EVENT_STS_INT_EN), HM_NORINTSTSEN); - s3c_hsmmc_writew((HM_NORINTSIGEN & ~(0xffff)) | TRANSFERCOMPLETE_SIG_INT_EN, HM_NORINTSIGEN); - - SetSystemAddressReg((unsigned long)dst); // AHB System Address For Write - dma = 1; - - set_blksize_register(7, 512); // Maximum DMA Buffer Size, Block Size - set_blkcnt_register(blknum); // Block Numbers to Write - - if (movi_hc) - set_arg_register(start_blk); // Card Start Block Address to Write - else - set_arg_register(start_blk * 512); // Card Start Block Address to Write - - cmd = (blknum > 1) ? 18 : 17; - multi = (blknum > 1); - - set_transfer_mode_register(multi, 1, multi, 1, dma); - set_cmd_register(cmd, 1, MMC_RSP_R1); - - if (wait_for_cmd_done()) { - puts("Command NOT Complete\n"); - return -1; - } else - ClearCommandCompleteStatus(); - - - check_dma_int(); - while (!HS_DMA_END); - - HS_DMA_END = 0; - - return blknum; -} diff --git a/qiboot/src/cpu/s3c6410/hs_mmc.h b/qiboot/src/cpu/s3c6410/hs_mmc.h deleted file mode 100644 index f1218ce..0000000 --- a/qiboot/src/cpu/s3c6410/hs_mmc.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef __HS_MMC_H__ -#define __HS_MMC_H__ - -///////////////////////////////////////////////////////////////////////////////////////////////// -//#define SDHC_MONITOR (*(volatile unsigned *)0x4800004c) -//#define SDHC_SLOT_INT_STAT (*(volatile unsigned *)0x480000fc) - -///////////////////////////////////////////////////////////////////////////////////////////////// -#define SD_HCLK 1 -#define SD_EPLL 2 -#define SD_EXTCLK 3 - -#define NORMAL 0 -#define HIGH 1 - -//Normal Interrupt Signal Enable -#define READWAIT_SIG_INT_EN (1<<10) -#define CARD_SIG_INT_EN (1<<8) -#define CARD_REMOVAL_SIG_INT_EN (1<<7) -#define CARD_INSERT_SIG_INT_EN (1<<6) -#define BUFFER_READREADY_SIG_INT_EN (1<<5) -#define BUFFER_WRITEREADY_SIG_INT_EN (1<<4) -#define DMA_SIG_INT_EN (1<<3) -#define BLOCKGAP_EVENT_SIG_INT_EN (1<<2) -#define TRANSFERCOMPLETE_SIG_INT_EN (1<<1) -#define COMMANDCOMPLETE_SIG_INT_EN (1<<0) - -//Normal Interrupt Status Enable -#define READWAIT_STS_INT_EN (1<<10) -#define CARD_STS_INT_EN (1<<8) -#define CARD_REMOVAL_STS_INT_EN (1<<7) -#define CARD_INSERT_STS_INT_EN (1<<6) -#define BUFFER_READREADY_STS_INT_EN (1<<5) -#define BUFFER_WRITEREADY_STS_INT_EN (1<<4) -#define DMA_STS_INT_EN (1<<3) -#define BLOCKGAP_EVENT_STS_INT_EN (1<<2) -#define TRANSFERCOMPLETE_STS_INT_EN (1<<1) -#define COMMANDCOMPLETE_STS_INT_EN (1<<0) - -#endif /*__HS_MMC_H__*/ diff --git a/qiboot/src/cpu/s3c6410/i2c-bitbang-s3c6410.c b/qiboot/src/cpu/s3c6410/i2c-bitbang-s3c6410.c deleted file mode 100644 index 0d1236d..0000000 --- a/qiboot/src/cpu/s3c6410/i2c-bitbang-s3c6410.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: Andy Green - * - * s3c6410-specific i2c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -static char i2c_read_sda_s3c6410(void) -{ - return !!(__REG(GPBDAT) & (1 << 6)); -} - -static void i2c_set_s3c6410(char clock, char data) -{ - if (clock) /* SCL <- input */ - __REG(GPBCON) = (__REG(GPBCON) & ~(3 << (5 * 4))); - else { /* SCL <- output 0 */ - __REG(GPBDAT) = (__REG(GPBDAT) & ~(1 << 5)); - __REG(GPBCON) = (__REG(GPBCON) & ~(3 << (5 * 4))) | (1 << (5 * 4)); - } - if (data) /* SDA <- input */ - __REG(GPBCON) = (__REG(GPBCON) & ~(3 << (6 * 4))); - else { /* SDA <- output 0 */ - __REG(GPBDAT) = (__REG(GPBDAT) & ~(1 << 6)); - __REG(GPBCON) = (__REG(GPBCON) & ~(3 << (6 * 4))) | (1 << (6 * 4)); - } -} - -static void i2c_close_s3c6410(void) -{ - /* set back to hardware I2C ready for Linux */ - __REG(GPBCON) = (__REG(GPBCON) & ~(3 << (5 * 4))) | (2 << (5 * 4)); - __REG(GPBCON) = (__REG(GPBCON) & ~(3 << (6 * 4))) | (2 << (6 * 4)); -} - -static void i2c_spin_s3c6410(void) -{ - int n; - - for (n = 0; n < 1000; n++) - __REG(GPBDAT) = __REG(GPBDAT); -} - -struct i2c_bitbang bb_s3c6410 = { - .read_sda = i2c_read_sda_s3c6410, - .set = i2c_set_s3c6410, - .spin = i2c_spin_s3c6410, - .close = i2c_close_s3c6410, -}; diff --git a/qiboot/src/cpu/s3c6410/om_3d7k-steppingstone.c b/qiboot/src/cpu/s3c6410/om_3d7k-steppingstone.c deleted file mode 100644 index 71c57f9..0000000 --- a/qiboot/src/cpu/s3c6410/om_3d7k-steppingstone.c +++ /dev/null @@ -1,114 +0,0 @@ -#include -#include -#include -#include - -#define OM_3D7K_DEBUG_UART 3 - -/* out of steppingstone */ -extern const struct board_variant const * get_board_variant_om_3d7k(void); -extern void port_init_om_3d7k(void); - - -int is_this_board_om_3d7k(void) -{ - /* FIXME: find something om_3d7k specific */ - return 1; -} - -static void putc_om_3d7k(char c) -{ - serial_putc_s3c64xx(OM_3D7K_DEBUG_UART, c); -} - -int sd_card_init_om_3d7k(void) -{ - extern int s3c6410_mmc_init(int verbose); - - return s3c6410_mmc_init(1); -} - -int sd_card_block_read_om_3d7k(unsigned char * buf, unsigned long start512, - int blocks512) -{ -unsigned long s3c6410_mmc_bread(int dev_num, unsigned long blknr, unsigned long blkcnt, - void *dst); - - return s3c6410_mmc_bread(0, start512, blocks512, buf); -} - -/* - * our API for bootloader on this machine - */ - -/* for initrd: - * .initramfs_filepath = "boot/initramfs.gz", - * and - * "root=/dev/ram ramdisk_size=6000000" - */ - -static u8 get_ui_keys_om_3d7k(void) -{ - u8 keys; - u8 ret; - static u8 old_keys = 0; /* previous state for debounce */ - static u8 old_ret = 0; /* previous debounced output for edge detect */ - - /* GPN1 is MINUS on OM_3D7K, map to UI_ACTION_ADD_DEBUG, down = 1 */ - keys = !!(__REG(GPMDAT) & (1 << 1)); - - if (keys == old_keys) - ret = keys; - else - ret = old_keys; - - /* edge action */ - if ((ret & 1) && !(old_ret & 1)) - ret |= UI_ACTION_SKIPKERNEL; - - old_keys = keys; - old_ret = ret; - - return ret; -} - -const struct board_api board_api_om_3d7k = { - .name = "OM_3D7K", - .linux_machine_id = 2120, - .linux_mem_start = 0x50000000, - .linux_mem_size = (128 * 1024 * 1024), - .linux_tag_placement = 0x50000000 + 0x100, - .get_board_variant = get_board_variant_om_3d7k, - .is_this_board = is_this_board_om_3d7k, - .port_init = port_init_om_3d7k, - .putc = putc_om_3d7k, - .noboot = "boot/noboot-OM_3D7K", - .append = "boot/append-OM_3D7K", - .get_ui_keys = get_ui_keys_om_3d7k, - .commandline_board = "console=tty0 " - "console=ttySAC3,115200 " - "init=/sbin/init " - "loglevel=8 " - "rootdelay=1 no_console_suspend " - "ro ", - .commandline_board_debug = " loglevel=8", - .kernel_source = { - [0] = { - .name = "SD Card rootfs", - .block_read = sd_card_block_read_om_3d7k, - .filesystem = FS_EXT2, - .partition_index = 2, - .filepath = "boot/uImage-OM_3D7K.bin", - .commandline_append = "root=/dev/mmcblk0p2 ", - }, - [1] = { - .name = "SD Card backup rootfs", - .block_read = sd_card_block_read_om_3d7k, - .filesystem = FS_EXT2, - .partition_index = 3, - .filepath = "boot/uImage-OM_3D7K.bin", - .commandline_append = "root=/dev/mmcblk0p3 ", - }, - }, -}; - diff --git a/qiboot/src/cpu/s3c6410/om_3d7k.c b/qiboot/src/cpu/s3c6410/om_3d7k.c deleted file mode 100644 index badc595..0000000 --- a/qiboot/src/cpu/s3c6410/om_3d7k.c +++ /dev/null @@ -1,935 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#define PCF50633_I2C_ADS 0x73 - -const struct pcf50633_init om_3d7k_pcf50633_init[] = { - - { PCF50633_REG_OOCWAKE, 0xd3 }, /* wake from ONKEY,EXTON!,RTC,USB,ADP */ - { PCF50633_REG_OOCTIM1, 0xaa }, /* debounce 14ms everything */ - { PCF50633_REG_OOCTIM2, 0x4a }, - { PCF50633_REG_OOCMODE, 0x55 }, - { PCF50633_REG_OOCCTL, 0x47 }, - - { PCF50633_REG_SVMCTL, 0x08 }, /* 3.10V SYS voltage thresh. */ - { PCF50633_REG_BVMCTL, 0x02 }, /* 2.80V BAT voltage thresh. */ - - { PCF50633_REG_AUTOENA, 0x01 }, /* always on */ - - { PCF50633_REG_DOWN1OUT, 0x17 }, /* 1.2V (0x17 * .025V + 0.625V) */ - - /* all of these are down in 3d7k suspend except MEMLDO */ - - { PCF50633_REG_DOWN1ENA, 0x02 }, /* enabled if GPIO1 = HIGH */ - { PCF50633_REG_DOWN2ENA, 0x02 }, /* enabled if GPIO1 = HIGH */ - { PCF50633_REG_HCLDOENA, 0x00 }, /* Camera 2.8V power off */ - { PCF50633_REG_MEMLDOENA, 0x01 }, /* Memory LDO always ON */ - { PCF50633_REG_LDO1ENA, 0x00 }, /* Gsensor power off */ - { PCF50633_REG_LDO2ENA, 0x00 }, /* Camera 1.5V power off */ - { PCF50633_REG_LDO3ENA, 0x02 }, /* Codec power ON */ - { PCF50633_REG_LDO4ENA, 0x02 }, /* SD power ON */ - { PCF50633_REG_LDO5ENA, 0x00 }, /* BT power off */ - { PCF50633_REG_LDO6ENA, 0x00 }, /* LCM power off */ - - { PCF50633_REG_INT1M, 0x00 }, - { PCF50633_REG_INT2M, 0x00 }, - { PCF50633_REG_INT3M, 0x00 }, - { PCF50633_REG_INT4M, 0x00 }, - { PCF50633_REG_INT5M, 0x00 }, - - { PCF50633_REG_MBCC2, 0x28 }, /* Vbatconid=2.7V, Vmax=4.20V */ - { PCF50633_REG_MBCC3, 0x19 }, /* 25/255 == 98mA pre-charge */ - { PCF50633_REG_MBCC4, 0xff }, /* 255/255 == 1A adapter fast */ - { PCF50633_REG_MBCC5, 0xff }, /* 255/255 == 1A USB fast */ - - { PCF50633_REG_MBCC6, 0x00 }, /* cutoff current 1/32 * Ichg */ - - /* current prototype is pulling > 100mA at startup */ - { PCF50633_REG_MBCC7, 0xc1 }, /* 2.2A max bat curr, USB 500mA */ - - { PCF50633_REG_MBCC8, 0x00 }, - { PCF50633_REG_MBCC1, 0xff }, /* chgena */ - - { PCF50633_REG_BBCCTL, 0x19 }, /* 3V, 200uA, on */ - { PCF50633_REG_OOCSHDWN, 0x04 }, /* defeat 8s death from lowsys on A5 */ - -}; - -static const struct board_variant board_variants[] = { - [0] = { - .name = "OM 3D7K unknown", - .machine_revision = 0 - }, - [1] = { - .name = "OM 3D7K A1", - .machine_revision = 1 - }, - [2] = { - .name = "OM 3D7K A2", - .machine_revision = 2 - }, - [3] = { - .name = "OM 3D7K A3", - .machine_revision = 3 - }, - [4] = { - .name = "OM 3D7K A4", - .machine_revision = 4 - }, - [5] = { - .name = "OM 3D7K A5", - .machine_revision = 5 - }, - [6] = { - .name = "OM 3D7K A6", - .machine_revision = 6 - }, - [7] = { - .name = "OM 3D7K A7", - .machine_revision = 7 - } -}; - -#define S0 0 -#define S1 1 -#define SIN 2 -#define SHOLD 3 - -#define SNP 0 -#define SPD 1 -#define SPU 2 - -void port_init_om_3d7k(void) -{ - int n; - -/* - * We leave iROM up for clock and power otherwise resume fails - */ - - __REG(EINT_MASK) = - (0 << 4) /* PMU interrupt */ - ; - - __REG(PWR_CFG) = - (1 << 17) | /* kill OSCotg clock pad */ - (0 << 0) /* 27MHz osc off */ - ; - - __REG(STOP_MEM_CFG) = - (0 << 6) | /* modem */ - (0 << 5) | /* host IF */ - (1 << 4) | /* OTG */ - (1 << 3) | /* HSMMC */ - (1 << 2) | /* iROM */ - (0 << 1) | /* IRDA */ - (1 << 0) /* NFCON / steppingstone */ - ; - - __REG(NOR_CFG) = - (1 << 31) | /* reserved */ - (1 << 30) | /* iROM */ - (0x1fff << 17) | /* reserved */ - (1 << 16) | /* ETM domain */ - (1 << 15) | /* S domain */ - (1 << 14) | /* F domain / LCD */ - (0 << 13) | /* P domain / 2D, scaler, TV encoder */ - (0 << 12) | /* I domain / JPEG / Camera */ - (1 << 11) | /* reserved */ - (0 << 10) | /* G domain / 3D */ - (0 << 9) | /* V domain / MFC */ - (1 << 8) | /* reserved */ - (0x00 << 0) /* reserved */ - ; - - - __REG(HCLK_GATE) = - (0 << 31) | /* 3D unit */ - (1 << 30) | /* reserved */ - (0 << 29) | /* USB host */ - (0 << 28) | /* "security subsystem" */ - (0 << 27) | /* SDMA1 */ - (0 << 26) | /* SDMA0 */ - (1 << 25) | /* iROM */ - (1 << 24) | /* DDR 1 */ - (1 << 23) | /* reserved */ - (1 << 22) | /* DMC1 */ - (1 << 21) | /* SROM / NAND controller / NAND */ - (0 << 20) | /* USB OTG */ - (0 << 19) | /* HSMMC 2 */ - (0 << 18) | /* HSMMC 1 */ - (1 << 17) | /* HSMMC 0 */ - (0 << 16) | /* MDP */ - (0 << 15) | /* direct host */ - (0 << 14) | /* indirect host */ - (1 << 13) | /* DMA1 */ - (1 << 12) | /* DMA0 */ - (0 << 11) | /* JPEG */ - (0 << 10) | /* camera */ - (0 << 9) | /* scaler */ - (0 << 8) | /* 2D */ - (0 << 7) | /* TV */ - (1 << 6) | /* reserved */ - (1 << 5) | /* POST0 */ - (1 << 4) | /* rotator */ - (1 << 3) | /* LCD controller */ - (1 << 2) | /* TZICs */ - (1 << 1) | /* VICs */ - (0 << 0) /* MFC */ - ; - __REG(PCLK_GATE) = - (0x1f << 28) | /* reserved */ - (0 << 27) | /* I2C1 */ - (0 << 26) | /* IIS2 */ - (1 << 25) | /* reserved */ - (0 << 24) | /* security key */ - (1 << 23) | /* chip ID */ - (0 << 22) | /* SPI1 */ - (0 << 21) | /* SPI0 */ - (0 << 20) | /* HSI RX */ - (0 << 19) | /* HSI TX */ - (1 << 18) | /* GPIO */ - (1 << 17) | /* I2C 0 */ - (1 << 16) | /* IIS1 */ - (1 << 15) | /* IIS0 */ - (0 << 14) | /* AC97 */ - (0 << 13) | /* TZPC */ - (0 << 12) | /* TS ADC */ - (0 << 11) | /* keypad */ - (0 << 10) | /* IRDA */ - (0 << 9) | /* PCM1 */ - (0 << 8) | /* PCM0 */ - (1 << 7) | /* PWM */ - (0 << 6) | /* RTC */ - (1 << 5) | /* WDC */ - (1 << 4) | /* UART3 */ - (1 << 3) | /* UART2 */ - (1 << 2) | /* UART1 */ - (1 << 1) | /* UART0 */ - (0 << 0) /* MFC */ - ; - - __REG(SCLK_GATE) = - (1 << 31) | - (0 << 30) | /* USB Host */ - (0 << 29) | /* HSMMC2 48MHz */ - (0 << 28) | /* HSMMC1 48MHz */ - (0 << 27) | /* HSMMC0 48MHz */ - (0 << 26) | /* HSMMC2 */ - (0 << 25) | /* HSMMC1 */ - (1 << 24) | /* HSMMC0 */ - (0 << 23) | /* SPI1 - 48MHz */ - (0 << 22) | /* SPI0 - 48MHz */ - (0 << 21) | /* SPI1 */ - (0 << 20) | /* SPI0 */ - (0 << 19) | /* TV DAC */ - (0 << 18) | /* TV encoder */ - (0 << 17) | /* scaler 27 */ - (0 << 16) | /* scaler */ - (1 << 15) | /* LCD 27MHz */ - (1 << 14) | /* LCD */ - (1 << 13) | /* camera and LCD */ - (1 << 12) | /* POST0 */ - (1 << 11) | /* AUDIO2 */ - (1 << 10) | /* POST0 again */ - (1 << 9) | /* IIS1 */ - (1 << 8) | /* IIS0 */ - (0 << 7) | /* security */ - (0 << 6) | /* IRDA */ - (1 << 5) | /* UART */ - (1 << 4) | /* reserved */ - (0 << 3) | /* MFC */ - (0 << 2) | /* Cam */ - (0 << 1) | /* JPEG */ - (1 << 0) /* reserved */ - ; - - - /* ---------------------------- Port A ---------------------------- */ - - __REG(GPACON) = - (2 << 0) | /* GPA0 - UART_RXD0 */ - (2 << 4) | /* GPA1 - UART_TXD0 */ - (2 << 8) | /* GPA2 - UART_CTS0 */ - (2 << 12) | /* GPA3 - UART_RTS0 */ - (2 << 16) | /* GPA4 - UART_RXD1 */ - (2 << 20) | /* GPA5 - UART_TXD1 */ - (2 << 24) | /* GPA6 - UART_CTS1 */ - (2 << 28) /* GPA7 - UART_RTS1 */ - ; - - __REG(GPAPUD) = /* pullup inputs */ - 0x2222 - ; - __REG(GPADAT) = 0; /* just for determinism */ - - __REG(GPACONSLP) = - (SIN << 0) | /* GPA0 bluetooth down in suspend*/ - (S0 << 2) | /* GPA1 */ - (SIN << 4) | /* GPA2 */ - (S0 << 6) | /* GPA3 */ - (SIN << 8) | /* GPA4 gsm */ - (SHOLD << 10) | /* GPA5 */ - (SIN << 12) | /* GPA6 */ - (SHOLD << 14) /* GPA7 */ - ; - __REG(GPAPUDSLP) = - (SPD << 0) | /* GPA0 */ - (SNP << 2) | /* GPA1 */ - (SPD << 4) | /* GPA2 */ - (SNP << 6) | /* GPA3 */ - (SPU << 8) | /* GPA4 */ - (SNP << 10) | /* GPA5 */ - (SPU << 12) | /* GPA6 */ - (SNP << 14) /* GPA7 */ - ; - - /* ---------------------------- Port B ---------------------------- */ - - __REG(GPBCON) = - (1 << 0) | /* GPB0 - (NC) output low */ - (1 << 4) | /* GPB1 - (NC) output low */ - (2 << 8) | /* GPB2 - UART_RXD3 */ - (2 << 12) | /* GPB3 - UART_TXD3 */ - (1 << 16) | /* GPB4 - (NC) output low */ - (1 << 20) | /* GPB5 - (I2C BB SCL) OUTPUT */ - (1 << 24) /* GPB6 - (I2C BB SDA) OUTPUT */ - ; - - __REG(GPBPUD) = /* all pullup and pulldown disabled */ - (SPU << (2 * 2)) /* pullup console rx */ - ; - - __REG(GPBDAT) = 0; /* just for determinism */ - - __REG(GPBCONSLP) = - (SHOLD << 0) | /* GPB0 */ - (SHOLD << 2) | /* GPB1 */ - (SIN << 4) | /* GPB2 */ - (SHOLD << 6) | /* GPB3 */ - (SHOLD << 8) | /* GPB4 */ - (SIN << 10) | /* GPB5 ext pullup */ - (SIN << 12) /* GPB6 ext pullup */ - ; - - __REG(GPBPUDSLP) = - (SNP << 0) | /* GPB0 */ - (SNP << 2) | /* GPB1 */ - (SPU << 4) | /* GPB2 */ - (SNP << 6) | /* GPB3 */ - (SNP << 8) | /* GPB4 */ - (SNP << 10) | /* GPB5 */ - (SNP << 12) /* GPB6 */ - ; - - /* ---------------------------- Port C ---------------------------- */ - - __REG(GPCCON) = - (0 << 0) | /* GPC0 - SPI_MISO0 INPUT motion sensor spi */ - (1 << 4) | /* GPC1 - SPI_CLK0 OUTPUT */ - (1 << 8) | /* GPC2 - SPI_MOSI0 OUTPUT */ - (1 << 12) | /* GPC3 - SPI_CS0 OUTPUT */ - (1 << 16) | /* GPC4 - (NC) OUTPUT lcm spi*/ - (1 << 20) | /* GPC5 - SPI_CLK1 OUTPUT */ - (1 << 24) | /* GPC6 - SPI_MOSI1 OUTPUT */ - (1 << 28) /* GPC7 - SPI_CS1 OUTPUT */ - ; - - __REG(GPCPUD) = - (SPD << 0) - ; - __REG(GPCDAT) = 0; /* just for determinism */ - - __REG(GPCCONSLP) = /* both peripherals down in suspend */ - (SIN << 0) | /* GPC0 */ - (S0 << 2) | /* GPC1 */ - (S0 << 4) | /* GPC2 */ - (S0 << 6) | /* GPC3 */ - (SIN << 8) | /* GPC4 */ - (S0 << 10) | /* GPC5 */ - (S0 << 12) | /* GPC6 */ - (S0 << 14) /* GPC7 */ - ; - - __REG(GPCPUDSLP) = - (SPD << 0) | /* GPC0 */ - (SNP << 2) | /* GPC1 */ - (SNP << 4) | /* GPC2 */ - (SNP << 6) | /* GPC3 */ - (SPD << 8) | /* GPC4 */ - (SNP << 10) | /* GPC5 */ - (SNP << 12) | /* GPC6 */ - (SNP << 14) /* GPC7 */ - ; - - /* ---------------------------- Port D ---------------------------- */ - - __REG(GPDCON) = - (3 << 0) | /* GPD0 - I2S_CLK0 */ - (3 << 4) | /* GPD1 - I2S_CDCLK0 */ - (3 << 8) | /* GPD2 - I2S_LRCLK0 */ - (3 << 12) | /* GPD3 - I2S_DI */ - (3 << 16) /* GPD4 - I2S_DO */ - ; - - __REG(GPDPUD) = 0; /* all pullup and pulldown disabled */ - - __REG(GPDDAT) = 0; /* just for determinism */ - - __REG(GPDCONSLP) = - (S0 << 0) | /* GPD0 */ - (S0 << 2) | /* GPD1 */ - (S0 << 4) | /* GPD2 */ - (SIN << 6) | /* GPD3 */ - (S0 << 8) /* GPD4 */ - ; - - __REG(GPDPUDSLP) = - (SNP << 0) | /* GPD0 */ - (SNP << 2) | /* GPD1 */ - (SNP << 4) | /* GPD2 */ - (SPD << 6) | /* GPD3 */ - (SNP << 8) /* GPD4 */ - ; - - /* ---------------------------- Port E ---------------------------- */ - - __REG(GPECON) = - (3 << 0) | /* GPE0 - PCM_SCLK1 */ - (3 << 4) | /* GPE1 - PCM_EXTCLK1 */ - (3 << 8) | /* GPE2 - PCM_FSYNC1 */ - (3 << 12) | /* GPE3 - PCM_SIN */ - (3 << 16) /* GPE4 - PCM_SOUT */ - ; - - __REG(GPEPUD) = 0; /* all pullup and pulldown disabled */ - - __REG(GPEDAT) = 0; /* just for determinism */ - - __REG(GPECONSLP) = - (S0 << 0) | /* GPE0 */ - (S0 << 2) | /* GPE1 */ - (S0 << 4) | /* GPE2 */ - (SIN << 6) | /* GPE3 */ - (S0 << 8) /* GPE4 */ - ; - - __REG(GPEPUDSLP) = - (SNP << 0) | /* GPE0 */ - (SNP << 2) | /* GPE1 */ - (SNP << 4) | /* GPE2 */ - (SPD << 6) | /* GPE3 */ - (SNP << 8) /* GPE4 */ - ; - - /* ---------------------------- Port F ---------------------------- */ - - __REG(GPFCON) = - (2 << 0) | /* GPF0 - CAMIF_CLK */ - (2 << 2) | /* GPF1 - CAMIF_HREF */ - (2 << 4) | /* GPF2 - CAMIF_PCLK */ - (2 << 6) | /* GPF3 - CAMIF_RSTn */ - (2 << 8) | /* GPF4 - CAMIF_VSYNC */ - (2 << 10) | /* GPF5 - CAMIF_YDATA0 */ - (2 << 12) | /* GPF6 - CAMIF_YDATA1 */ - (2 << 14) | /* GPF7 - CAMIF_YDATA2 */ - (2 << 16) | /* GPF8 - CAMIF_YDATA3 */ - (2 << 18) | /* GPF9 - CAMIF_YDATA4 */ - (2 << 20) | /* GPF10 - CAMIF_YDATA5 */ - (2 << 22) | /* GPF11 - CAMIF_YDATA6 */ - (2 << 24) | /* GPF12 - CAMIF_YDATA7 */ - (1 << 26) | /* GPF13 - OUTPUT Vibrator */ - (1 << 28) | /* GPF14 - output not CLKOUT0 */ - (1 << 30) /* GPF15 - OUTPUT CAM_PWRDN */ - ; - - __REG(GPFPUD) = - (SPD << (2 * 12)) | - (SPD << (2 * 11)) | - (SPD << (2 * 10)) | - (SPD << (2 * 9)) | - (SPD << (2 * 8)) | - (SPD << (2 * 7)) | - (SPD << (2 * 6)) | - (SPD << (2 * 5)); /* all cam data pulldown */ - - __REG(GPFDAT) = (1 << 15); /* assert CAM_PWRDN */ - - __REG(GPFCONSLP) = - (S0 << 0) | /* GPF0 */ - (S0 << 2) | /* GPF1 */ - (SIN << 4) | /* GPF2 */ - (S0 << 6) | /* GPF3 */ - (S0 << 8) | /* GPF4 */ - (SIN << 10) | /* GPF5 */ - (SIN << 12) | /* GPF6 */ - (SIN << 14) | /* GPF7 */ - (SIN << 16) | /* GPF8 */ - (SIN << 18) | /* GPF9 */ - (SIN << 20) | /* GPF10 */ - (SIN << 22) | /* GPF11 */ - (SIN << 24) | /* GPF12 */ - (S0 << 26) | /* GPF13 */ - (S0 << 28) | /* GPF14 */ - (S0 << 30) /* GPF15 */ - ; - - __REG(GPFPUDSLP) = - (SPD << 4) | /* GPF2 - pull down */ - (SPD << 10) | /* GPF5 - pull down */ - (SPD << 12) | /* GPF6 - pull down */ - (SPD << 14) | /* GPF7 - pull down */ - (SPD << 16) | /* GPF8 - pull down */ - (SPD << 18) | /* GPF9 - pull down */ - (SPD << 20) | /* GPF10 - pull down */ - (SPD << 22) | /* GPF11 - pull down */ - (SPD << 24) /* GPF12 - pull down */ - ; - - /* ---------------------------- Port G ---------------------------- */ - - __REG(GPGCON) = - (2 << 0) | /* GPG0 - MMC_CLK0 */ - (2 << 4) | /* GPG1 - MMC_CMD0 */ - (2 << 8) | /* GPG2 - MMC_DATA00 */ - (2 << 12) | /* GPG3 - MMC_DATA10 */ - (2 << 16) | /* GPG4 - MMC_DATA20 */ - (2 << 20) | /* GPG5 - MMC_DATA30 */ - (2 << 24) /* GPG6 - (NC) MMC CARD DETECT */ - ; - - __REG(GPGPUD) = (1 << (6 * 2)); /* pull down card detect */ - - __REG(GPGDAT) = 0; /* just for determinism */ - - __REG(GPGCONSLP) = - (SIN << 0) | /* GPG0 - it's not powered*/ - (SIN << 2) | /* GPG1 */ - (SIN << 4) | /* GPG2 */ - (SIN << 6) | /* GPG3 */ - (SIN << 8) | /* GPG4 */ - (SIN << 10) | /* GPG5 */ - (SIN << 12) /* GPG6 */ - ; - - __REG(GPGPUDSLP) = - (SPD << 0) | /* GPG0 - it's not powered*/ - (SPD << 2) | /* GPG1 */ - (SPD << 4) | /* GPG2 */ - (SPD << 6) | /* GPG3 */ - (SPD << 8) | /* GPG4 */ - (SPD << 10) | /* GPG5 */ - (SPD << 12) /* GPG6 */ - ; - - /* ---------------------------- Port H ---------------------------- */ - - __REG(GPHCON0) = - (1 << 0) | /* GPH0 - NC OUT 0 */ - (1 << 4) | /* GPH1 - NC OUT 0 */ - (1 << 8) | /* GPH2 - NC OUT 0 */ - (1 << 12) | /* GPH3 - NC OUT 0 */ - (1 << 16) | /* GPH4 - NC OUT 0 */ - (1 << 20) | /* GPH5 - NC OUT 0 */ - (1 << 24) | /* GPH6 - OUTPUT nBT_RESET */ - (0 << 28) /* GPH7 - INPUT HDQ */ - ; - __REG(GPHCON1) = - (1 << 0) | /* GPH8 - OUTPUT BT PIO5 */ - (0 << 4) /* GPH9 - INPUT LED INT */ - ; - - __REG(GPHPUD) = (SPU << (9 * 2)) | (SPU << (7 * 2)); - - __REG(GPHDAT) = 0; - - __REG(GPHCONSLP) = - (S0 << 0) | /* GPH0 */ - (S0 << 2) | /* GPH1 */ - (S0 << 4) | /* GPH2 */ - (S0 << 6) | /* GPH3 */ - (S0 << 8) | /* GPH4 */ - (S0 << 10) | /* GPH5 */ - (S0 << 12) | /* GPH6 */ - (SIN << 14) | /* GPH7 - INPUT (HDQ) */ - (S0 << 16) | /* GPH8 */ - (SIN << 18) /* GPH9 */ - ; - - __REG(GPHPUDSLP) = (SPU << (7 * 2)) | (SPU << (9 * 2)); - - /* ---------------------------- Port I ---------------------------- */ - - __REG(GPICON) = - (0 << 0) | /* GPI0 - INPUT version b0 */ - (0 << 2) | /* GPI1 - INPUT version b1 */ - (2 << 4) | /* GPI2 - LCD_VD2 */ - (2 << 6) | /* GPI3 - LCD_VD3 */ - (2 << 8) | /* GPI4 - LCD_VD4 */ - (2 << 10) | /* GPI5 - LCD_VD5 */ - (2 << 12) | /* GPI6 - LCD_VD6 */ - (2 << 14) | /* GPI7 - LCD_VD7 */ - (0 << 16) | /* GPI8 - INPUT version b2 */ - (2 << 18) | /* GPI9 - LCD_VD9 */ - (2 << 20) | /* GPI10 - LCD_VD10 */ - (2 << 22) | /* GPI11 - LCD_VD11 */ - (2 << 24) | /* GPI12 - LCD_VD12 */ - (2 << 26) | /* GPI13 - LCD_VD13 */ - (2 << 28) | /* GPI14 - LCD_VD14 */ - (2 << 30) /* GPI15 - LCD_VD15 */ - ; - - __REG(GPIPUD) = 0; /* all pullup and pulldown disabled */ - - __REG(GPIDAT) = 0; /* just for determinism */ - - __REG(GPICONSLP) = - (SIN << 0) | /* GPI0 - input */ - (SIN << 2) | /* GPI1 - input */ - (S0 << 4) | /* GPI2 - input */ - (S0 << 6) | /* GPI3 - input */ - (S0 << 8) | /* GPI4 - input */ - (S0 << 10) | /* GPI5 - input */ - (S0 << 12) | /* GPI6 - input */ - (S0 << 14) | /* GPI7 - input */ - (SIN << 16) | /* GPI8 - input */ - (S0 << 18) | /* GPI9 - input */ - (S0 << 20) | /* GPI10 - input */ - (S0 << 22) | /* GPI11 - input */ - (S0 << 24) | /* GPI12 - input */ - (S0 << 26) | /* GPI13 - input */ - (S0 << 28) | /* GPI14 - input */ - (S0 << 30) /* GPI15 - input */ - ; - - __REG(GPIPUDSLP) = - (1 << 0) | /* GPI0 - pull down */ - (1 << 2) | /* GPI1 - pull down */ - (1 << 16) /* GPI8 - pull down */ - ; - - /* ---------------------------- Port J ---------------------------- */ - - __REG(GPJCON) = - (2 << 0) | /* GPJ0 - LCD_VD16 */ - (2 << 2) | /* GPJ1 - LCD_VD17 */ - (2 << 4) | /* GPJ2 - LCD_VD18 */ - (2 << 6) | /* GPJ3 - LCD_VD19 */ - (2 << 8) | /* GPJ4 - LCD_VD20 */ - (2 << 10) | /* GPJ5 - LCD_VD21 */ - (2 << 12) | /* GPJ6 - LCD_VD22 */ - (2 << 14) | /* GPJ7 - LCD_VD23 */ - (2 << 16) | /* GPJ8 - LCD_HSYNC */ - (2 << 18) | /* GPJ9 - LCD_VSYNC */ - (2 << 20) | /* GPJ10 - LCD_VDEN */ - (2 << 22) /* GPJ11 - LCD_VCLK */ - ; - - __REG(GPJPUD) = 0; /* all pullup and pulldown disabled */ - - __REG(GPJDAT) = 0; /* just for determinism */ - - __REG(GPJCONSLP) = - (S0 << 0) | /* GPJ0 */ - (S0 << 2) | /* GPJ1 */ - (S0 << 4) | /* GPJ2 */ - (S0 << 6) | /* GPJ3 */ - (S0 << 8) | /* GPJ4 */ - (S0 << 10) | /* GPJ5 */ - (S0 << 12) | /* GPJ6 */ - (S0 << 14) | /* GPJ7 */ - (S0 << 16) | /* GPJ8 */ - (S0 << 18) | /* GPJ9 */ - (S0 << 20) | /* GPJ10 */ - (S0 << 22) /* GPJ11 */ - ; - - __REG(GPJPUDSLP) = - 0 - ; - - /* ---------------------------- Port K ---------------------------- */ - - __REG(GPKCON0) = - (1 << 0) | /* GPK0 - OUTPUT NC */ - (1 << 4) | /* GPK1 - OUTPUT NC */ - (1 << 8) | /* GPK2 - OUTPUT (nMODEM_ON) */ - - (1 << 12) | /* GPK3 - OUTPUT (LED_TRIG) */ - (1 << 16) | /* GPK4 - OUTPUT (LED_EN) */ - (0 << 20) | /* GPK5 - OUTPUT NC */ - (1 << 24) | /* GPK6 - OUTPUT (LCD_RESET) */ - (0 << 28) /* GPK7 - OUTPUT NC */ - ; - __REG(GPKCON1) = - (1 << 0) | /* GPK8 - OUTPUT NC */ - (1 << 4) | /* GPK9 - OUTPUT NC */ - (1 << 8) | /* GPK10 - OUTPUT NC */ - (1 << 12) | /* GPK11 - OUTPUT NC */ - (1 << 16) | /* GPK12 - OUTPUT NC */ - (1 << 20) | /* GPK13 - OUTPUT NC */ - (1 << 24) | /* GPK14 - OUTPUT NC */ - (1 << 28) /* GPK15 - OUTPUT NC */ - ; - - __REG(GPKPUD) = 0; - - __REG(GPKDAT) = /* rest output 0 */ - (SHOLD << (2 * 2)) | /* nMODEM_ON */ - (SHOLD << (2 * 3)) | /* LED_TRIG */ - (SHOLD << (2 * 4)) | /* LED_EN */ - (S0 << (2 * 6)) /* LCD_RESET */ - ; - - /* ---------------------------- Port L ---------------------------- */ - - __REG(GPLCON0) = - (1 << 0) | /* GPL0 - OUTPUT (NC) */ - (1 << 4) | /* GPL1 - OUTPUT (NC) */ - (1 << 8) | /* GPL2 - OUTPUT (NC) */ - (1 << 12) | /* GPL3 - OUTPUT (NC) */ - (1 << 16) | /* GPL4 - OUTPUT (NC) */ - (1 << 20) | /* GPL5 - OUTPUT (NC) */ - (1 << 24) | /* GPL6 - OUTPUT (NC) */ - (1 << 28) /* GPL7 - OUTPUT (NC) */ - ; - __REG(GPLCON1) = - (1 << 0) | /* GPL8 - OUTPUT (NC) */ - (1 << 4) | /* GPL9 - OUTPUT (NC) */ - (1 << 8) | /* GPL10 - OUTPUT (NC) */ - (1 << 12) | /* GPL11 - OUTPUT (NC) */ - (1 << 16) | /* GPL12 - OUTPUT (NC) */ - (1 << 20) | /* GPL13 - OUTPUT (NC) */ - (1 << 24) /* GPL14 - OUTPUT (NC) */ - ; - - __REG(GPLPUD) = 0; /* all pullup and pulldown disabled */ - - __REG(GPLDAT) = 0; - - - /* ---------------------------- Port M ---------------------------- */ - - __REG(GPMCON) = - (1 << 0) | /* GPM0 - OUTPUT (TP_RESET) */ - (1 << 4) | /* GPM1 - OUTPUT (NC) */ - (1 << 8) | /* GPM2 - OUTPUT (NC) */ - (1 << 12) | /* GPM3 - OUTPUT (NC) */ - (0 << 16) | /* GPM4 - INPUT (nUSB_FLT) */ - (0 << 20) /* GPM5 - INPUT (nUSB_OC) */ - ; - - __REG(GPMPUD) = (2 << (4 * 2)) | (2 << (5 * 2)); /* Pup on inputs */ - - __REG(GPMDAT) = 0; - - /* ---------------------------- Port N ---------------------------- */ - - __REG(GPNCON) = - (2 << 0) | /* GPN0 - EXINT0 nG1INT1 */ - (2 << 2) | /* GPN1 - EXINT1 KEY_MINUS */ - (2 << 4) | /* GPN2 - EXINT2 KEY_PLUS */ - (2 << 6) | /* GPN3 - EXINT3 PWR_IND */ - (2 << 8) | /* GPN4 - EXINT4 PWR_IRQ */ - (2 << 10) | /* GPN5 - EXINT5 nTOUCH */ - (2 << 12) | /* GPN6 - EXINT6 nJACK_INSERT */ - (1 << 14) | /* GPN7 - EXINT7 NC OUTPUT */ - (2 << 16) | /* GPN8 - EXINT8 nHOLD */ - (2 << 18) | /* GPN9 - EXINT9 WLAN_WAKEUP */ - (2 << 20) | /* GPN10 - EXINT10 nG1INT2 */ - (2 << 22) | /* GPN11 - EXINT11 nIO1 */ - (2 << 24) | /* GPN12 - EXINT12 nONKEYWAKE */ - (0 << 26) | /* GPN13 - INPUT (iROM CFG0) */ - (0 << 28) | /* GPN14 - INPUT (iROM CFG1) */ - (0 << 30) /* GPN15 - INPUT (iROM CFG2) */ - ; - - __REG(GPNPUD) = - (SPD << 0) | /* GPN0 - EXINT0 nG1INT1 */ - (SPU << 2) | /* GPN1 - EXINT1 KEY_MINUS */ - (SPU << 4) | /* GPN2 - EXINT2 KEY_PLUS */ - (SPU << 6) | /* GPN3 - EXINT3 PWR_IND */ - (SNP << 8) | /* GPN4 - EXINT4 PWR_IRQ */ - (SPU << 10) | /* GPN5 - EXINT5 nTOUCH */ - (SNP << 12) | /* GPN6 - EXINT6 nJACK_INSERT */ - (SNP << 14) | /* GPN7 - EXINT7 NC OP */ - (SPU << 16) | /* GPN8 - EXINT8 nHOLD */ - (SPU << 18) | /* GPN9 - EXINT9 BT_WAKEUP */ - (SPD << 20) | /* GPN10 - EXINT10 nG1INT2 */ - (SPD << 22) | /* GPN11 - EXINT11 nIO1 */ - (SPU << 24) | /* GPN12 - EXINT12 nONKEYWAKE */ - (SPD << 26) | /* GPN13 - INPUT (iROM CFG0) */ - (SPD << 28) | /* GPN14 - INPUT (iROM CFG1) */ - (SPD << 30) /* GPN15 - INPUT (iROM CFG2) */ - ; - - __REG(GPNDAT) = 0; - - - /* ---------------------------- Port O ---------------------------- */ - - __REG(GPOCON) = - (2 << 0) | /* GPO0 - XM0CS2 (nNANDCS0) */ - (1 << 2) | /* GPO1 - OUTPUT (nMODEM_RESET) */ - (1 << 4) | /* GPO2 - OUTPUT (NC) */ - (1 << 6) | /* GPO3 - OUTPUT (NC) */ - (1 << 8) | /* GPO4 - OUTPUT (NC) */ - (1 << 10) | /* GPO5 - OUTPUT (NC) */ - (1 << 12) | /* GPO6 - OUTPUT (NC) */ - (1 << 14) | /* GPO7 - OUTPUT (NC) */ - (1 << 16) | /* GPO8 - OUTPUT (NC) */ - (1 << 18) | /* GPO9 - OUTPUT (NC) */ - (1 << 20) | /* GPO10 - OUTPUT (NC) */ - (1 << 22) | /* GPO11 - OUTPUT (NC) */ - (1 << 24) | /* GPO12 - OUTPUT (NC) */ - (1 << 26) | /* GPO13 - OUTPUT (NC) */ - (1 << 28) | /* GPO14 - OUTPUT (NC) */ - (1 << 30) /* GPO15 - OUTPUT (NC) */ - ; - - __REG(GPOPUD) = 0; /* no pulling */ - - __REG(GPODAT) = (1 << 15); /* assert CAM_PWRDN */ - - __REG(GPOCONSLP) = - (SHOLD << 0) | /* GPO0 - hold state */ - (SHOLD << 2) | /* GPO1 - OUTPUT 1 (do not reset modem) */ - (S0 << 4) | /* GPO2 - OUTPUT 0 */ - (S0 << 6) | /* GPO3 - OUTPUT 0 */ - (S0 << 8) | /* GPO4 - OUTPUT 0 */ - (S0 << 10) | /* GPO5 - OUTPUT 0 */ - (S0 << 12) | /* GPO6 - OUTPUT 0 */ - (S0 << 14) | /* GPO7 - OUTPUT 0 */ - (S0 << 16) | /* GPO8 - OUTPUT 0 */ - (S0 << 18) | /* GPO9 - OUTPUT 0 */ - (S0 << 20) | /* GPO10 - OUTPUT 0 */ - (S0 << 22) | /* GPO11 - OUTPUT 0 */ - (S0 << 24) | /* GPO12 - OUTPUT 0 */ - (S0 << 26) | /* GPO13 - OUTPUT 0 */ - (S0 << 28) | /* GPO14 - OUTPUT 0 */ - (S0 << 30) /* GPO15 - OUTPUT 0 */ - ; - - __REG(GPOPUDSLP) = - 0 - ; - - /* ---------------------------- Port P ---------------------------- */ - - __REG(GPPCON) = - (1 << 0) | /* GPP0 - input (NC) */ - (1 << 2) | /* GPP1 - input (NC) */ - (1 << 4) | /* GPP2 - input (NC) */ - (1 << 6) | /* GPP3 - input (NC) */ - (1 << 8) | /* GPP4 - input (NC) */ - (1 << 10) | /* GPP5 - input (NC) */ - (1 << 12) | /* GPP6 - input (NC) */ - (1 << 14) | /* GPP7 - input (NC) */ - (1 << 16) | /* GPP8 - input (NC) */ - (1 << 18) | /* GPP9 - input (NC) */ - (1 << 20) | /* GPP10 - input (NC) */ - (1 << 22) | /* GPP11 - input (NC) */ - (1 << 24) | /* GPP12 - input (NC) */ - (1 << 26) | /* GPP13 - input (NC) */ - (1 << 28) /* GPP14 - input (NC) */ - ; - - __REG(GPPPUD) = 0; /* no pull */ - - __REG(GPPDAT) = 0; - - __REG(GPPCONSLP) = - (S0 << 0) | /* GPP0 - OUTPUT 0 */ - (S0 << 2) | /* GPP1 - OUTPUT 0 */ - (S0 << 4) | /* GPP2 - OUTPUT 0 */ - (S0 << 6) | /* GPP3 - OUTPUT 0 */ - (S0 << 8) | /* GPP4 - OUTPUT 0 */ - (S0 << 10) | /* GPP5 - OUTPUT 0 */ - (S0 << 12) | /* GPP6 - OUTPUT 0 */ - (S0 << 14) | /* GPP7 - OUTPUT 0 */ - (S0 << 16) | /* GPP8 - OUTPUT 0 */ - (S0 << 18) | /* GPP9 - OUTPUT 0 */ - (S0 << 20) | /* GPP10 - OUTPUT 0 */ - (S0 << 22) | /* GPP11 - OUTPUT 0 */ - (S0 << 24) | /* GPP12 - OUTPUT 0 */ - (S0 << 26) | /* GPP13 - OUTPUT 0 */ - (S0 << 28) /* GPP14 - OUTPUT 0 */ - ; - - __REG(GPPPUDSLP) = 0; - - /* ---------------------------- Port Q ---------------------------- */ - - __REG(GPQCON) = - (1 << 0) | /* GPQ0 - OUTPUT (NC) */ - (1 << 2) | /* GPQ1 - OUTPUT (NC) */ - (1 << 4) | /* GPQ2 - OUTPUT (NC) */ - (1 << 6) | /* GPQ3 - OUTPUT (NC) */ - (1 << 8) | /* GPQ4 - OUTPUT (NC) */ - (1 << 10) | /* GPQ5 - OUTPUT (NC) */ - (1 << 12) | /* GPQ6 - OUTPUT (NC) */ - (1 << 14) | /* GPQ7 - OUTPUT (NC) */ - (1 << 16) /* GPQ8 - OUTPUT (NC) */ - ; - - __REG(GPQPUD) = 0; /* no pull */ - - __REG(GPQDAT) = 0; - - __REG(GPQCONSLP) = - (S0 << 0) | /* GPQ0 - OUTPUT 0 */ - (S0 << 2) | /* GPQ1 - OUTPUT 0 */ - (S0 << 4) | /* GPQ2 - OUTPUT 0 */ - (S0 << 6) | /* GPQ3 - OUTPUT 0 */ - (S0 << 8) | /* GPQ4 - OUTPUT 0 */ - (S0 << 10) | /* GPQ5 - OUTPUT 0 */ - (S0 << 12) | /* GPQ6 - OUTPUT 0 */ - (S0 << 14) | /* GPQ7 - OUTPUT 0 */ - (S0 << 16) /* GPQ8 - OUTPUT 0 */ - ; - - __REG(GPQPUDSLP) = 0; - - /* LCD Controller enable */ - - __REG(0x7410800c) = 0; - __REG(0x7f0081a0) = 0xbfc115c1; - - /* - * We have to talk to the PMU a little bit - */ - for (n = 0; n < ARRAY_SIZE(om_3d7k_pcf50633_init); n++) - i2c_write_sync(&bb_s3c6410, PCF50633_I2C_ADS, - om_3d7k_pcf50633_init[n].index, - om_3d7k_pcf50633_init[n].value); - -} - -int om_3d7k_get_pcb_revision(void) -{ - u32 v = __REG(GPIDAT); - /* - * PCB rev is 3 bit code (info from Dkay) - * (b2, b1, b0) = (0,0,1) => pcb rev A1 - * maximum rev = A7 - * bit0 = GPI8 - * bit1 = GPI1 - * bit2 = GPI0 - */ - - return ( - ((v & (1 << 8)) ? 1 : 0) | - ((v & (1 << 1)) ? 2 : 0) | - ((v & (1 << 0)) ? 4 : 0) - ); -} - -const struct board_variant const * get_board_variant_om_3d7k(void) -{ - return &board_variants[om_3d7k_get_pcb_revision()]; -} - diff --git a/qiboot/src/cpu/s3c6410/qi.lds b/qiboot/src/cpu/s3c6410/qi.lds deleted file mode 100644 index 22d8546..0000000 --- a/qiboot/src/cpu/s3c6410/qi.lds +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - __system_ram_start = 0x50000000; - __steppingstone = 0x0c000000; - - /* this text section is magically pulled from the SD Card - * and stored by the iRom at 0x0c000000, then it is jumped into - * by the iRom. So we arrange our early parts needed at 0 in the - * output file, but set to run at 0x0c000000+ - */ - - .text - __steppingstone : - AT (0) - { - src/cpu/s3c6410/start.o (.text .rodata* .data .bss) - src/cpu/s3c6410/start_qi.o (.text .rodata* .data .bss) - src/cpu/s3c6410/serial-s3c64xx.o (.text .rodata* .data .bss) - src/cpu/s3c6410/om_3d7k-steppingstone.o (.text .rodata* .data .bss) - src/cpu/s3c6410/smdk6410-steppingstone.o (.text .rodata* .data .bss) - src/cpu/s3c6410/hs_mmc.o (.text .rodata* .data .bss) - src/utils.o (.text .rodata* .data .bss) - src/memory-test.o (.text .rodata* .data .bss) -/* src/ctype.o (.text .rodata* .data .bss) */ - * (.steppingstone) - } - - . = ALIGN(4); - .everything_else - __system_ram_start + 0x3000000 + SIZEOF(.text) : - AT (SIZEOF(.text)) - { - *(.text .rodata* .data) - } - - - __bss_start = __system_ram_start + 0x03800000; - .bss_6410 - __bss_start (NOLOAD) : - AT (SIZEOF(.text) + SIZEOF(.everything_else)) - { - * (.bss) - } - - _end = .; -} diff --git a/qiboot/src/cpu/s3c6410/serial-s3c64xx.c b/qiboot/src/cpu/s3c6410/serial-s3c64xx.c deleted file mode 100644 index 256419b..0000000 --- a/qiboot/src/cpu/s3c6410/serial-s3c64xx.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: Andy Green - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * Output a single byte to the serial port. - */ -void serial_putc_s3c64xx(const int uart, const char c) -{ - if (uart >= 4) - return; - - while (!(__REG(0x7F005000 + UTRSTAT_OFFSET + (uart << 10)) & 0x2)) - ; - - __REG(0x7F005000 + UTXH_OFFSET + (uart << 10)) = c; -} diff --git a/qiboot/src/cpu/s3c6410/smdk6410-steppingstone.c b/qiboot/src/cpu/s3c6410/smdk6410-steppingstone.c deleted file mode 100644 index c1d991f..0000000 --- a/qiboot/src/cpu/s3c6410/smdk6410-steppingstone.c +++ /dev/null @@ -1,73 +0,0 @@ -#include -#include -#include - -#define SMDK6410_DEBUG_UART 0 - -extern const struct board_variant const * get_board_variant_smdk6410(void); - -int is_this_board_smdk6410(void) -{ - /* FIXME: find something smdk6410 specific */ - return 1; -} - -static void putc_smdk6410(char c) -{ - serial_putc_s3c64xx(SMDK6410_DEBUG_UART, c); -} - -int sd_card_init_smdk6410(void) -{ - extern int s3c6410_mmc_init(int verbose); - - return s3c6410_mmc_init(1); -} - -int sd_card_block_read_smdk6410(unsigned char * buf, unsigned long start512, - int blocks512) -{ -unsigned long s3c6410_mmc_bread(int dev_num, unsigned long blknr, - unsigned long blkcnt, void *dst); - - return s3c6410_mmc_bread(0, start512, blocks512, buf); -} - -/* - * our API for bootloader on this machine - */ -const struct board_api board_api_smdk6410 = { - .name = "SMDK6410", - .linux_machine_id = 1866 /* 1626 */, - .linux_mem_start = 0x50000000, - .linux_mem_size = (128 * 1024 * 1024), - .linux_tag_placement = 0x50000000 + 0x100, - .get_board_variant = get_board_variant_smdk6410, - .is_this_board = is_this_board_smdk6410, - .putc = putc_smdk6410, - .commandline_board = "console=ttySAC0,115200 " - "loglevel=3 " - "init=/bin/sh ", - .commandline_board_debug = " loglevel=8", - .noboot = "boot/noboot-SDMK6410", - .append = "boot/append-SMDK6410", - .kernel_source = { - [0] = { - .name = "SD Card rootfs", - .block_read = sd_card_block_read_smdk6410, - .filesystem = FS_EXT2, - .partition_index = 2, - .filepath = "boot/uImage-SMDK6410.bin", - .commandline_append = "root=/dev/mmcblk0p2 " - }, - [1] = { - .name = "SD Card backup rootfs", - .block_read = sd_card_block_read_smdk6410, - .filesystem = FS_EXT2, - .partition_index = 3, - .filepath = "boot/uImage-SMDK6410.bin", - .commandline_append = "root=/dev/mmcblk0p3 " - }, - }, -}; - diff --git a/qiboot/src/cpu/s3c6410/smdk6410.c b/qiboot/src/cpu/s3c6410/smdk6410.c deleted file mode 100644 index 63dc3b6..0000000 --- a/qiboot/src/cpu/s3c6410/smdk6410.c +++ /dev/null @@ -1,27 +0,0 @@ -#include -#include -#include - -static const struct board_variant board_variants[] = { - [0] = { - .name = "SMDK", - .machine_revision = 0, - }, -}; - -/** - * returns PCB revision information in b0, d8, d9 - * SMDK6410 EVB returns 0x000 - * SMDK6410 returns 0x001 - */ - -int smdk6410_get_pcb_revision(void) -{ - return 0; -} - -const struct board_variant const * get_board_variant_smdk6410(void) -{ - return &board_variants[smdk6410_get_pcb_revision()]; -} - diff --git a/qiboot/src/cpu/s3c6410/start.S b/qiboot/src/cpu/s3c6410/start.S deleted file mode 100644 index be90d57..0000000 --- a/qiboot/src/cpu/s3c6410/start.S +++ /dev/null @@ -1,487 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define __ASM_MODE__ -#define __ASSEMBLY__ - -#include - -#define TEXT_BASE 0x53000000 - - -#define S3C6410_POP_A 1 - -#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) - -/* fixed MPLL 533MHz */ -#define MPLL_MDIV 266 -#define MPLL_PDIV 3 -#define MPLL_SDIV 1 - -#define Startup_APLLdiv 0 -#define APLL_MDIV 266 -#define APLL_PDIV 3 -#define APLL_SDIV 1 -#define Startup_PCLKdiv 3 -#define Startup_HCLKdiv 1 -#define Startup_MPLLdiv 1 -#define Startup_HCLKx2div 1 -#define Startup_APLL (12000000/(APLL_PDIV< EXT_UCLK1*/ - - str r1, [r0, #UCON_OFFSET] - - ldr r1, =0x22 - str r1, [r0, #UBRDIV_OFFSET] - - ldr r1, =0x1FFF - str r1, [r0, #UDIVSLOT_OFFSET] - - /* resuming? */ - - ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset - - /* no, cold boot */ - - ldr r0, =ELFIN_UART_BASE + ELFIN_UART3_OFFSET - ldr r1, =0x55 - str r1, [r0, #UTXH_OFFSET] @'U' - /* >> CFG_VIDEO_LOGO_MAX_SIZE */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - - - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ - sub sp, r0, #12 /* leave 3 words for abort-stack */ -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l: - str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - - b _steppingstone_done - - /* resume */ - -wakeup_reset: - - ldr r0, =ELFIN_UART_BASE + ELFIN_UART3_OFFSET - ldr r1, =0x4b4b4b4b - str r1, [r0, #UTXH_OFFSET] - - /*Clear wakeup status register*/ - ldr r0, =(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET) - ldr r1, [r0] - str r1, [r0] - -#if 0 - /*LED test*/ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x3000 - str r1, [r0, #GPNDAT_OFFSET] -#endif - - /*Load return address and jump to kernel*/ - ldr r0, =(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) - ldr r1, [r0] /* r1 = physical address of s3c6400_cpu_resume function*/ - mov pc, r1 /*Jump to kernel (sleep-s3c6400.S)*/ - nop - nop - -4: - b 4b diff --git a/qiboot/src/cpu/s3c6410/start_qi.c b/qiboot/src/cpu/s3c6410/start_qi.c deleted file mode 100644 index e85d63b..0000000 --- a/qiboot/src/cpu/s3c6410/start_qi.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * Andy Green - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* NOTE this stuff runs in steppingstone context! */ - - -#include -#include -#include - -#define stringify2(s) stringify1(s) -#define stringify1(s) #s - -extern void bootloader_second_phase(void); - -const struct board_api *boards[] = { - &board_api_om_3d7k, - &board_api_smdk6410, - NULL /* always last */ -}; - -struct board_api const * this_board; -extern int is_jtag; - -#include - -void start_qi(void) -{ - int flag = 0; - int board = 0; - unsigned int sd_sectors = 0; - - /* - * well, we can be running on this CPU two different ways. - * - * 1) We were copied into steppingstone and TEXT_BASE already - * by JTAG. We don't have to do anything else. JTAG script - * then sets data at address 0x4 to 0xffffffff as a signal we - * are running by JTAG. - * - * 2) We only got our first 4K into steppingstone, we need to copy - * the rest of ourselves into TEXT_BASE. - * - * So we do the copy out of NAND only if we see we did not come up - * under control of JTAG. - */ - - - /* ask all the boards we support in turn if they recognize this - * hardware we are running on, accept the first positive answer - */ - - this_board = boards[board]; - while (!flag && this_board) - /* check if it is the right board... */ - if (this_board->is_this_board()) - flag = 1; - else - this_board = boards[board++]; - - /* okay, do the critical port and serial init for our board */ - - if (this_board->early_port_init) - this_board->early_port_init(); - - set_putc_func(this_board->putc); - - /* stick some hello messages on debug console */ - - puts("\n\n\nQi Bootloader "stringify2(QI_CPU)" " - stringify2(BUILD_HOST)" " - stringify2(BUILD_VERSION)" " - "\n"); - - puts(stringify2(BUILD_DATE) " Copyright (C) 2008 Openmoko, Inc.\n\n"); - - if (!is_jtag) { - /* - * We got the first 8KBytes of the bootloader pulled into the - * steppingstone SRAM for free. Now we pull the whole bootloader - * image into SDRAM. - * - * This code and the .S files are arranged by the linker script - * to expect to run from 0x0. But the linker script has told - * everything else to expect to run from 0x53000000+. That's - * why we are going to be able to copy this code and not have it - * crash when we run it from there. - */ - - /* We randomly pull 32KBytes of bootloader */ - - extern unsigned int s3c6410_mmc_init(int verbose); - unsigned long s3c6410_mmc_bread(int dev_num, - unsigned long start_blk, unsigned long blknum, - void *dst); - sd_sectors = s3c6410_mmc_init(1); - s3c6410_mmc_bread(0, sd_sectors - 1026 - 16 - (256 * 2), - 32 * 2, (u8 *)0x53000000); - } - - /* all of Qi is in memory now, stuff outside steppingstone too */ - - if (this_board->port_init) - this_board->port_init(); - - puts("\n Detected: "); - puts(this_board->name); - puts(", "); - puts((this_board->get_board_variant)()->name); - puts("\n"); - - /* - * jump to bootloader_second_phase() running from DRAM copy - */ - bootloader_second_phase(); -} diff --git a/qiboot/src/crc32.c b/qiboot/src/crc32.c deleted file mode 100644 index 81f1792..0000000 --- a/qiboot/src/crc32.c +++ /dev/null @@ -1,90 +0,0 @@ -#include -#include - - -/* original copyright notice for this crc code (it is from U-Boot) --> */ -/* - * This file is derived from crc32.c from the zlib-1.1.3 distribution - * by Jean-loup Gailly and Mark Adler. - */ - -/* crc32.c -- compute the CRC-32 of a data stream - * Copyright (C) 1995-1998 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h - */ - -const unsigned long crc_table[256] = { - 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, - 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L, - 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, - 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, - 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L, - 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, - 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, - 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL, - 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, - 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL, - 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, - 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, - 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L, - 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, - 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, - 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L, - 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, - 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L, - 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, - 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, - 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL, - 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, - 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L, - 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL, - 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, - 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L, - 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, - 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, - 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L, - 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, - 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, - 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L, - 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, - 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL, - 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, - 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, - 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL, - 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, - 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, - 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L, - 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, - 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L, - 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, - 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, - 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L, - 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, - 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, - 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L, - 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, - 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L, - 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, - 0x2d02ef8dL -}; - -#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8); -#define DO2(buf) DO1(buf); DO1(buf); -#define DO4(buf) DO2(buf); DO2(buf); -#define DO8(buf) DO4(buf); DO4(buf); - -unsigned long crc32(unsigned long crc, const unsigned char *buf, - unsigned int len) -{ - crc = crc ^ 0xffffffffL; - while (len >= 8) { - DO8(buf); - len -= 8; - } - if (len) - do { - DO1(buf); - } while (--len); - - return crc ^ 0xffffffffL; -} diff --git a/qiboot/src/ctype.c b/qiboot/src/ctype.c deleted file mode 100644 index cf5a5a6..0000000 --- a/qiboot/src/ctype.c +++ /dev/null @@ -1,27 +0,0 @@ -#include - -unsigned char _ctype[] = { -_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ -_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ -_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ -_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ -_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ -_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ -_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ -_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ -_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ -_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ -_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ -_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */ -_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */ -_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ diff --git a/qiboot/src/drivers/glamo-init.c b/qiboot/src/drivers/glamo-init.c deleted file mode 100644 index cf96794..0000000 --- a/qiboot/src/drivers/glamo-init.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2007 by OpenMoko, Inc. - * Author: Harald Welte - * Andy Green - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define GLAMO_REG(x) (*(volatile unsigned short *)(0x08000000 + x)) - -static void glamo_reg_write(u16 reg, u16 val) -{ - GLAMO_REG(reg) = val; -} - -static u16 glamo_reg_read(u16 reg) -{ - return GLAMO_REG(reg); -} - - -static u16 u16a_gen_init_0x0000[] = { - 0x2020, 0x3650, 0x0002, 0x01FF, 0x0000, 0x0000, 0x0000, 0x0000, - 0x000D, 0x000B, 0x00EE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x1801 /*0x1839*/, 0x0000, 0x2000, 0x0001, 0x0100, 0x0000, 0x0000, 0x0000, - 0x05DB, 0x5231, 0x09C3, 0x8261, 0x0003, 0x0000, 0x0000, 0x0000, - 0x000F, 0x101E, 0xC0C3, 0x101E, 0x000F, 0x0001, 0x030F, 0x020F, - 0x080F, 0x0F0F -}; - -static u16 u16a_gen_init_0x0200[] = { - 0x0EF0, 0x07FF, 0x0000, 0x0080, 0x0344, 0x0600, 0x0000, 0x0000, - 0x0000, 0x0000, 0x4000, 0xF00E, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x0873, 0xAFAF, 0x0108, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x1002, 0x6006, 0x00FF, 0x0001, 0x0020, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x3210, 0x5432, 0xE100, 0x01D6 -}; - - -void glamo_core_init(void) -{ - int bp; - - /* power up PLL1 and PLL2 */ - glamo_reg_write(GLAMO_REG_PLL_GEN7, 0x0000); - glamo_reg_write(GLAMO_REG_PLL_GEN3, 0x0400); - - /* enable memory clock and get it out of deep pwrdown */ - glamo_reg_write(GLAMO_REG_CLOCK_MEMORY, - glamo_reg_read(GLAMO_REG_CLOCK_MEMORY) | 8); - glamo_reg_write(GLAMO_REG_MEM_DRAM2, - glamo_reg_read(GLAMO_REG_MEM_DRAM2) & (~(1 << 12))); - glamo_reg_write(GLAMO_REG_MEM_DRAM1, - glamo_reg_read(GLAMO_REG_MEM_DRAM1) & (~(1 << 12))); - /* - * we just fill up the general hostbus and LCD register sets - * with magic values taken from the Linux framebuffer init action - */ - for (bp = 0; bp < ARRAY_SIZE(u16a_gen_init_0x0000); bp++) - glamo_reg_write(0x0 | (bp << 1), - u16a_gen_init_0x0000[bp]); - - for (bp = 0; bp < ARRAY_SIZE(u16a_gen_init_0x0200); bp++) - glamo_reg_write(0x200 | (bp << 1), - u16a_gen_init_0x0200[bp]); - - /* spin until PLL1 lock */ - while (!(glamo_reg_read(GLAMO_REG_PLL_GEN5) & 1)) - ; -} - diff --git a/qiboot/src/drivers/glamo-mmc.c b/qiboot/src/drivers/glamo-mmc.c deleted file mode 100644 index c3b92c3..0000000 --- a/qiboot/src/drivers/glamo-mmc.c +++ /dev/null @@ -1,851 +0,0 @@ -/* - * linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver - * - * Copyright (C) 2007 OpenMoko, Inc, Andy Green - * Based on the Glamo MCI driver that was --> - * - * Copyright (C) 2007 OpenMoko, Inc, Andy Green - * Based on S3C MMC driver that was: - * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel - * - * and - * - * Based on S3C MMC driver that was (original copyright notice ---->) - * - * (C) Copyright 2006 by OpenMoko, Inc. - * Author: Harald Welte - * - * based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c - * (C) 2005-2005 Thomas Kleffel - * - * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - -#include -#include - -#define CONFIG_GLAMO_BASE 0x08000000 - -#define MMC_BLOCK_SIZE_BITS 9 - -#define GLAMO_REG(x) (*(volatile u16 *)(CONFIG_GLAMO_BASE + x)) -#define GLAMO_INTRAM_OFFSET (8 * 1024 * 1024) -#define GLAMO_FB_SIZE ((8 * 1024 * 1024) - 0x10000) -#define GLAMO_START_OF_MMC_INTMEM ((volatile u16 *)(CONFIG_GLAMO_BASE + \ - GLAMO_INTRAM_OFFSET + GLAMO_FB_SIZE)) - -static int ccnt; -//static mmc_csd_t mmc_csd; -static int mmc_ready = 0; -//static int wide = 0; -static enum card_type card_type = CARDTYPE_NONE; - - -#define MULTI_READ_BLOCKS_PER_COMMAND 64 - -int mmc_read(unsigned long src, u8 *dst, int size); - -#define UNSTUFF_BITS(resp,start,size) \ - ({ \ - const int __size = size; \ - const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ - const int __off = 3 - ((start) / 32); \ - const int __shft = (start) & 31; \ - u32 __res; \ - \ - __res = resp[__off] >> __shft; \ - if (__size + __shft > 32) \ - __res |= resp[__off-1] << ((32 - __shft) & 31); \ - __res & __mask; \ - }) - - -static void -glamo_reg_write(u16 val, u16 reg) -{ - GLAMO_REG(reg) = val; -} - -static u16 -glamo_reg_read(u16 reg) -{ - return GLAMO_REG(reg); -} - -unsigned char CRC7(u8 * pu8, int cnt) -{ - u8 crc = 0; - - while (cnt--) { - int n; - u8 d = *pu8++; - for (n = 0; n < 8; n++) { - crc <<= 1; - if ((d & 0x80) ^ (crc & 0x80)) - crc ^= 0x09; - d <<= 1; - } - } - return (crc << 1) | 1; -} - -unsigned long mmc_bread(int dev_num, unsigned long blknr, unsigned long blkcnt, - void *dst) -{ - int ret; - - if (!blkcnt) - return 0; - -/* printf("mmc_bread(%d, %ld, %ld, %p)\n", dev_num, blknr, blkcnt, dst); */ - ret = mmc_read(blknr, dst, blkcnt); - if (ret) - return ret; - - return blkcnt; -} - -/* MMC_DEFAULT_RCA should probably be just 1, but this may break other code - that expects it to be shifted. */ -static u16 rca = MMC_DEFAULT_RCA >> 16; - -static void do_pio_read(u16 *buf, int count_words) -{ - volatile u16 *from_ptr = GLAMO_START_OF_MMC_INTMEM; - - while (count_words--) - *buf++ = *from_ptr++; -} - -static void do_pio_write(u16 *buf, int count_words) -{ - volatile u16 *to_ptr = GLAMO_START_OF_MMC_INTMEM; - - while (count_words--) - *to_ptr++ = *buf++; -} - - -static int mmc_cmd(int opcode, int arg, int flags, - int data_size, int data_blocks, - int will_stop, u16 *resp) -{ - u16 * pu16 = (u16 *)&resp[0]; - u16 * reg_resp = (u16 *)(CONFIG_GLAMO_BASE + GLAMO_REGOFS_MMC + - GLAMO_REG_MMC_CMD_RSP1); - u16 status; - int n; - u8 u8a[6]; - u16 fire = 0; - int cmd_is_stop = 0; - int error = 0; - -#if 0 - printf("mmc_cmd(opcode=%d, arg=0x%08X, flags=0x%x, " - "data_size=%d, data_blocks=%d, will_stop=%d, resp=%p)\n", - opcode, arg, flags, data_size, data_blocks, will_stop, resp); -#endif - switch (opcode) { - case MMC_STOP_TRANSMISSION: - cmd_is_stop = 1; - break; - default: - break; - } - - ccnt++; - - /* this guy has data to read/write? */ - if ((!cmd_is_stop) && (flags & (MMC_DATA_WRITE | MMC_DATA_READ))) { - /* - * the S-Media-internal RAM offset for our MMC buffer - */ - glamo_reg_write((u16)GLAMO_FB_SIZE, - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_WDATADS1); - glamo_reg_write((u16)(GLAMO_FB_SIZE >> 16), - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_WDATADS2); - glamo_reg_write((u16)GLAMO_FB_SIZE, - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_RDATADS1); - glamo_reg_write((u16)(GLAMO_FB_SIZE >> 16), - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_RDATADS2); - - /* set up the block info */ - glamo_reg_write(data_size, GLAMO_REGOFS_MMC + - GLAMO_REG_MMC_DATBLKLEN); - glamo_reg_write(data_blocks, GLAMO_REGOFS_MMC + - GLAMO_REG_MMC_DATBLKCNT); - } - - /* if we can't do it, reject as busy */ - if (!glamo_reg_read(GLAMO_REGOFS_MMC + GLAMO_REG_MMC_RB_STAT1) & - GLAMO_STAT1_MMC_IDLE) - return -1; - - /* create an array in wire order for CRC computation */ - u8a[0] = 0x40 | (opcode & 0x3f); - u8a[1] = (arg >> 24); - u8a[2] = (arg >> 16); - u8a[3] = (arg >> 8); - u8a[4] = arg; - u8a[5] = CRC7(&u8a[0], 5); /* CRC7 on first 5 bytes of packet */ - - /* issue the wire-order array including CRC in register order */ - glamo_reg_write((u8a[4] << 8) | u8a[5], - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_CMD_REG1); - glamo_reg_write((u8a[2] << 8) | u8a[3], - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_CMD_REG2); - glamo_reg_write((u8a[0] << 8) | u8a[1], - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_CMD_REG3); - - /* command index toggle */ - fire |= (ccnt & 1) << 12; - - /* set type of command */ - switch (mmc_cmd_type(flags)) { - case MMC_CMD_BC: - fire |= GLAMO_FIRE_MMC_CMDT_BNR; - break; - case MMC_CMD_BCR: - fire |= GLAMO_FIRE_MMC_CMDT_BR; - break; - case MMC_CMD_AC: - fire |= GLAMO_FIRE_MMC_CMDT_AND; - break; - case MMC_CMD_ADTC: - fire |= GLAMO_FIRE_MMC_CMDT_AD; - break; - } - /* - * if it expects a response, set the type expected - * - * R1, Length : 48bit, Normal response - * R1b, Length : 48bit, same R1, but added card busy status - * R2, Length : 136bit (really 128 bits with CRC snipped) - * R3, Length : 48bit (OCR register value) - * R4, Length : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card - * R5, Length : 48bit, IO_RW_DIRECTION, Reverse SDIO Card - * R6, Length : 48bit (RCA register) - * R7, Length : 48bit (interface condition, VHS(voltage supplied), - * check pattern, CRC7) - */ - switch (mmc_resp_type(flags)) { - case MMC_RSP_R6: /* same index as R7 and R1 */ - fire |= GLAMO_FIRE_MMC_RSPT_R1; - break; - case MMC_RSP_R1B: - fire |= GLAMO_FIRE_MMC_RSPT_R1b; - break; - case MMC_RSP_R2: - fire |= GLAMO_FIRE_MMC_RSPT_R2; - break; - case MMC_RSP_R3: - fire |= GLAMO_FIRE_MMC_RSPT_R3; - break; - /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */ - } - /* - * From the command index, set up the command class in the host ctrllr - * - * missing guys present on chip but couldn't figure out how to use yet: - * 0x0 "stream read" - * 0x9 "cancel running command" - */ - switch (opcode) { - case MMC_READ_SINGLE_BLOCK: - fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */ - break; - case MMC_SWITCH: /* 64 byte payload */ - case 0x33: /* observed issued by MCI */ - case MMC_READ_MULTIPLE_BLOCK: - /* we will get an interrupt off this */ - if (!will_stop) - /* multiblock no stop */ - fire |= GLAMO_FIRE_MMC_CC_MBRNS; - else - /* multiblock with stop */ - fire |= GLAMO_FIRE_MMC_CC_MBRS; - break; - case MMC_WRITE_BLOCK: - fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */ - break; - case MMC_WRITE_MULTIPLE_BLOCK: - if (will_stop) - /* multiblock with stop */ - fire |= GLAMO_FIRE_MMC_CC_MBWS; - else - /* multiblock NO stop-- 'RESERVED'? */ - fire |= GLAMO_FIRE_MMC_CC_MBWNS; - break; - case MMC_STOP_TRANSMISSION: - fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */ - break; - default: - fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */ - break; - } - /* enforce timeout */ - glamo_reg_write(0xfff, GLAMO_REGOFS_MMC + GLAMO_REG_MMC_TIMEOUT); - - /* Generate interrupt on txfer; drive strength max */ - glamo_reg_write((glamo_reg_read(GLAMO_REGOFS_MMC + - GLAMO_REG_MMC_BASIC) & 0xfe) | - 0x0800 | GLAMO_BASIC_MMC_NO_CLK_RD_WAIT | - GLAMO_BASIC_MMC_EN_COMPL_INT | - GLAMO_BASIC_MMC_EN_DR_STR0 | - GLAMO_BASIC_MMC_EN_DR_STR1, - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_BASIC); - - /* send the command out on the wire */ - /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */ - glamo_reg_write(fire, GLAMO_REGOFS_MMC + GLAMO_REG_MMC_CMD_FIRE); - - /* - * we must spin until response is ready or timed out - * -- we don't get interrupts unless there is a bulk rx - */ - do - status = glamo_reg_read(GLAMO_REGOFS_MMC + - GLAMO_REG_MMC_RB_STAT1); - while ((((status >> 15) & 1) != (ccnt & 1)) || - (!(status & (GLAMO_STAT1_MMC_RB_RRDY | - GLAMO_STAT1_MMC_RTOUT | - GLAMO_STAT1_MMC_DTOUT | - GLAMO_STAT1_MMC_BWERR | - GLAMO_STAT1_MMC_BRERR)))); - - if (status & (GLAMO_STAT1_MMC_RTOUT | GLAMO_STAT1_MMC_DTOUT)) - error = -4; - if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR)) - error = -5; - - if (cmd_is_stop) - return 0; - - if (error) { -#if 0 - puts("cmd 0x"); - print8(opcode); - puts(", arg 0x"); - print8(arg); - puts(", flags 0x"); - print32(flags); - puts("\n"); - puts("Error after cmd: 0x"); - print32(error); - puts("\n"); -#endif - goto done; - } - /* - * mangle the response registers in two different exciting - * undocumented ways discovered by trial and error - */ - if (mmc_resp_type(flags) == MMC_RSP_R2) - /* grab the response */ - for (n = 0; n < 8; n++) /* super mangle power 1 */ - pu16[n ^ 6] = reg_resp[n]; - else - for (n = 0; n < 3; n++) /* super mangle power 2 */ - pu16[n] = (reg_resp[n] >> 8) | - (reg_resp[n + 1] << 8); - /* - * if we don't have bulk data to take care of, we're done - */ - if (!(flags & (MMC_DATA_READ | MMC_DATA_WRITE))) - goto done; - - /* enforce timeout */ - glamo_reg_write(0xfff, GLAMO_REGOFS_MMC + GLAMO_REG_MMC_TIMEOUT); - /* - * spin - */ - while (!(glamo_reg_read(GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) - ; - /* ack this interrupt source */ - glamo_reg_write(GLAMO_IRQ_MMC, GLAMO_REG_IRQ_CLEAR); - - if (status & GLAMO_STAT1_MMC_DTOUT) - error = -1; - if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR)) - error = -2; - if (status & GLAMO_STAT1_MMC_RTOUT) - error = -5; - if (error) { -// printf("cmd 0x%x, arg 0x%x flags 0x%x\n", opcode, arg, flags); -#if 0 - puts("Error after resp: 0x"); - print32(status); - puts("\n"); -#endif - goto done; - } -#if 0 - if (flags & MMC_DATA_READ) { - volatile u8 * pu8 = (volatile u8 *)GLAMO_START_OF_MMC_INTMEM; - for (n = 0; n < 512; n += 16) { - int n1; - for (n1 = 0; n1 < 16; n1++) { - printf("%02X ", pu8[n + n1]); - } - printf("\n"); - } - } -#endif - return 0; - -done: - return error; -} - -static void glamo_mci_reset(void) -{ - /* reset MMC controller */ - glamo_reg_write(GLAMO_CLOCK_MMC_RESET | GLAMO_CLOCK_MMC_DG_TCLK | - GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK | - GLAMO_CLOCK_MMC_EN_M9CLK, - GLAMO_REG_CLOCK_MMC); - /* and disable reset */ - glamo_reg_write(GLAMO_CLOCK_MMC_DG_TCLK | - GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK | - GLAMO_CLOCK_MMC_EN_M9CLK, - GLAMO_REG_CLOCK_MMC); -} - - - -int mmc_read(unsigned long src, u8 *dst, int size) -{ - int resp; - u8 response[16]; - int size_original = size; - int lump; - - if (((int)dst) & 1) { - puts("Bad align on dst\n"); - return 0; - } - - resp = mmc_cmd(MMC_SET_BLOCKLEN, MMC_BLOCK_SIZE, - MMC_CMD_AC | MMC_RSP_R1, 0, 0, 0, - (u16 *)&response[0]); - if (resp) - return resp; - - while (size) { - /* glamo mmc times out as this increases too much */ - lump = MULTI_READ_BLOCKS_PER_COMMAND; - if (lump > size) - lump = size; - - switch (card_type) { - case CARDTYPE_SDHC: /* block addressing */ - resp = mmc_cmd(MMC_READ_MULTIPLE_BLOCK, - src, - MMC_CMD_ADTC | MMC_RSP_R1 | - MMC_DATA_READ, MMC_BLOCK_SIZE, lump, 1, - (u16 *)&response[0]); - break; - default: /* byte addressing */ - resp = mmc_cmd(MMC_READ_MULTIPLE_BLOCK, src * MMC_BLOCK_SIZE, - MMC_CMD_ADTC | MMC_RSP_R1 | MMC_DATA_READ, - MMC_BLOCK_SIZE, lump, 1, - (u16 *)&response[0]); - break; - } - - if (resp) - return resp; - - /* final speed 16MHz */ - glamo_reg_write((glamo_reg_read(GLAMO_REG_CLOCK_GEN8) & - 0xff00) | 2, GLAMO_REG_CLOCK_GEN8); - - - do_pio_read((u16 *)dst, lump * MMC_BLOCK_SIZE >> 1); - - if (size) - size -= lump; - - dst += lump * MMC_BLOCK_SIZE; - src += lump; - - resp = mmc_cmd(MMC_STOP_TRANSMISSION, 0, - MMC_CMD_AC | MMC_RSP_R1B, 0, 0, 0, - (u16 *)&response[0]); - if (resp) - return resp; - - } - - return size_original; -} - -int mmc_write(u8 *src, unsigned long dst, int size) -{ - int resp; - u8 response[16]; - int size_original = size; - - if ((!size) || (size & (MMC_BLOCK_SIZE - 1))) { - puts("Bad size 0x"); - print32(size); - return 0; - } - - if (((int)dst) & 1) { - puts("Bad align on dst\n"); - return 0; - } - - resp = mmc_cmd(MMC_SET_BLOCKLEN, MMC_BLOCK_SIZE, - MMC_CMD_AC | MMC_RSP_R1, 0, 0, 0, - (u16 *)&response[0]); - - while (size) { - do_pio_write((u16 *)src, MMC_BLOCK_SIZE >> 1); - switch (card_type) { - case CARDTYPE_SDHC: /* block addressing */ - resp = mmc_cmd(MMC_WRITE_BLOCK, - dst >> MMC_BLOCK_SIZE_BITS, - MMC_CMD_ADTC | MMC_RSP_R1 | - MMC_DATA_WRITE, - MMC_BLOCK_SIZE, 1, 0, - (u16 *)&response[0]); - break; - default: /* byte addressing */ - resp = mmc_cmd(MMC_WRITE_BLOCK, dst, - MMC_CMD_ADTC | MMC_RSP_R1 | - MMC_DATA_WRITE, - MMC_BLOCK_SIZE, 1, 0, - (u16 *)&response[0]); - break; - } - if (size >= MMC_BLOCK_SIZE) - size -= MMC_BLOCK_SIZE; - else - size = 0; - dst += MMC_BLOCK_SIZE; - src += MMC_BLOCK_SIZE; - } - return size_original; -} - -#if 0 -static void print_mmc_cid(mmc_cid_t *cid) -{ - puts("MMC found. Card desciption is:\n"); - puts("Manufacturer ID = "); - print8(cid->id[0]); - print8(cid->id[1]); - print8(cid->id[2]); -/* - puts("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); - cid->hwrev = cid->fwrev = 0; - puts("Product Name = %s\n",cid->name); - printf("Serial Number = %02x%02x%02x\n", - cid->sn[0], cid->sn[1], cid->sn[2]); - printf("Month = %d\n",cid->month); - printf("Year = %d\n",1997 + cid->year); -*/ -} -#endif -static void print_sd_cid(const struct sd_cid *cid) -{ - puts(" Card Type: "); - switch (card_type) { - case CARDTYPE_NONE: - puts("(None) / "); - break; - case CARDTYPE_MMC: - puts("MMC / "); - break; - case CARDTYPE_SD: - puts("SD / "); - break; - case CARDTYPE_SD20: - puts("SD 2.0 / "); - break; - case CARDTYPE_SDHC: - puts("SD 2.0 SDHC / "); - break; - } - - puts("Mfr: 0x"); - print8(cid->mid); - puts(", OEM \""); - this_board->putc(cid->oid_0); - this_board->putc(cid->oid_1); - puts("\" / "); - - this_board->putc(cid->pnm_0); - this_board->putc(cid->pnm_1); - this_board->putc(cid->pnm_2); - this_board->putc(cid->pnm_3); - this_board->putc(cid->pnm_4); - puts("\", rev "); - printdec(cid->prv >> 4); - puts("."); - printdec(cid->prv & 15); - puts(" / s/n: "); - printdec(cid->psn_0 << 24 | cid->psn_1 << 16 | cid->psn_2 << 8 | - cid->psn_3); - puts(" / date: "); - printdec(cid->mdt_1 & 15); - puts("/"); - printdec(2000 + ((cid->mdt_0 & 15) << 4)+((cid->mdt_1 & 0xf0) >> 4)); - puts("\n"); - -/* printf("CRC: 0x%02x, b0 = %d\n", - cid->crc >> 1, cid->crc & 1); */ -} - - -int mmc_init(int verbose) -{ - int retries = 1000, rc = -1; - int resp; - u8 response[16]; -// mmc_cid_t *mmc_cid = (mmc_cid_t *)response; - struct sd_cid *sd_cid = (struct sd_cid *)response; - u32 hcs = 0; - - card_type = CARDTYPE_NONE; - - /* enable engine */ - - glamo_reg_write(GLAMO_CLOCK_MMC_EN_M9CLK | - GLAMO_CLOCK_MMC_EN_TCLK | - GLAMO_CLOCK_MMC_DG_M9CLK | - GLAMO_CLOCK_MMC_DG_TCLK, GLAMO_REG_CLOCK_MMC); - glamo_reg_write(glamo_reg_read(GLAMO_REG_HOSTBUS(2)) | - GLAMO_HOSTBUS2_MMIO_EN_MMC, GLAMO_REG_HOSTBUS(2)); - - /* controller reset */ - - glamo_mci_reset(); - - /* start the clock -- slowly (50MHz / 250 == 195kHz */ - - glamo_reg_write((glamo_reg_read(GLAMO_REG_CLOCK_GEN8) & 0xff00) | 250, - GLAMO_REG_CLOCK_GEN8); - - /* enable clock to divider input */ - - glamo_reg_write(glamo_reg_read( - GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK, - GLAMO_REG_CLOCK_GEN5_1); - - udelay(100000); - - /* set bus width to 1 */ - - glamo_reg_write((glamo_reg_read(GLAMO_REGOFS_MMC + - GLAMO_REG_MMC_BASIC) & - (~GLAMO_BASIC_MMC_EN_4BIT_DATA)), - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_BASIC); - - /* reset */ - - resp = mmc_cmd(MMC_GO_IDLE_STATE, 0, MMC_CMD_BCR, 0, 0, 0, - (u16 *)&response[0]); - - udelay(100000); - udelay(100000); - udelay(100000); - udelay(100000); - - /* SDHC card? */ - - resp = mmc_cmd(SD_SEND_IF_COND, 0x000001aa, - MMC_CMD_BCR | MMC_RSP_R7, 0, 0, 0, - (u16 *)&response[0]); - if (!resp && (response[0] == 0xaa)) { - card_type = CARDTYPE_SD20; /* 2.0 SD, may not be SDHC */ - hcs = 0x40000000; - } - - /* Well, either way let's say hello in SD card protocol */ - - while (retries--) { - - udelay(10000); - - resp = mmc_cmd(MMC_APP_CMD, 0x00000000, - MMC_CMD_AC | MMC_RSP_R1, 0, 0, 0, - (u16 *)&response[0]); - if (resp) - continue; - resp = mmc_cmd(SD_APP_OP_COND, hcs | 0x00300000, - MMC_CMD_BCR | MMC_RSP_R3, 0, 0, 0, - (u16 *)&response[0]); - if (resp) - continue; - - if (response[3] & (1 << 6)) { /* asserts block addressing */ - retries = -2; - card_type = CARDTYPE_SDHC; - } - if (response[3] & (1 << 7)) { /* not busy */ - if (card_type == CARDTYPE_NONE) - card_type = CARDTYPE_SD; - retries = -2; - break; - } - } - if (retries == -1) { - puts("no response\n"); - return 1; - } - - if (card_type == CARDTYPE_NONE) { - retries = 10; - puts("failed to detect SD Card, trying MMC\n"); - do { - resp = mmc_cmd(MMC_SEND_OP_COND, 0x00ffc000, - MMC_CMD_BCR | MMC_RSP_R3, 0, 0, 0, - (u16 *)&response[0]); - udelay(50); - } while (retries-- && !(response[3] & 0x80)); - if (retries >= 0) - card_type = CARDTYPE_MMC; - else - return 1; - } - - /* fill in device description */ -#if 0 - mmc_dev.if_type = IF_TYPE_MMC; - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = 0; - mmc_dev.removable = 0; - mmc_dev.block_read = mmc_bread; - mmc_dev.blksz = 512; - mmc_dev.lba = 1 << 16; /* 64K x 512 blocks = 32MB default */ -#endif - /* try to get card id */ - resp = mmc_cmd(MMC_ALL_SEND_CID, hcs, - MMC_CMD_BCR | MMC_RSP_R2, 0, 0, 0, - (u16 *)&response[0]); - if (resp) - return 1; - - switch (card_type) { - case CARDTYPE_MMC: - /* TODO configure mmc driver depending on card - attributes */ -#if 0 - if (verbose) - print_mmc_cid(mmc_cid); - sprintf((char *) mmc_dev.vendor, - "Man %02x%02x%02x Snr %02x%02x%02x", - mmc_cid->id[0], mmc_cid->id[1], mmc_cid->id[2], - mmc_cid->sn[0], mmc_cid->sn[1], mmc_cid->sn[2]); - sprintf((char *) mmc_dev.product, "%s", mmc_cid->name); - sprintf((char *) mmc_dev.revision, "%x %x", - mmc_cid->hwrev, mmc_cid->fwrev); -#endif - /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_SET_RELATIVE_ADDR, MMC_DEFAULT_RCA, - MMC_CMD_AC | MMC_RSP_R1, 0, 0, 0, - (u16 *)&response[0]); - break; - - case CARDTYPE_SD: - case CARDTYPE_SD20: - case CARDTYPE_SDHC: - - if (verbose) - print_sd_cid(sd_cid); -#if 0 - sprintf((char *) mmc_dev.vendor, - "Man %02 OEM %c%c \"%c%c%c%c%c\"", - sd_cid->mid, sd_cid->oid_0, sd_cid->oid_1, - sd_cid->pnm_0, sd_cid->pnm_1, sd_cid->pnm_2, - sd_cid->pnm_3, sd_cid->pnm_4); - sprintf((char *) mmc_dev.product, "%d", - sd_cid->psn_0 << 24 | sd_cid->psn_1 << 16 | - sd_cid->psn_2 << 8 | sd_cid->psn_3); - sprintf((char *) mmc_dev.revision, "%d.%d", - sd_cid->prv >> 4, sd_cid->prv & 15); -#endif - resp = mmc_cmd(SD_SEND_RELATIVE_ADDR, MMC_DEFAULT_RCA, - MMC_CMD_BCR | MMC_RSP_R6, 0, 0, 0, - (u16 *)&response[0]); - rca = response[2] | (response[3] << 8); - break; - - default: - return 1; - } - - /* grab the CSD */ - - resp = mmc_cmd(MMC_SEND_CSD, rca << 16, - MMC_CMD_AC | MMC_RSP_R2, 0, 0, 0, - (u16 *)&response[0]); - if (!resp) { - mmc_csd_t *csd = (mmc_csd_t *)response; - -// memcpy(&mmc_csd, csd, sizeof(csd)); - rc = 0; - mmc_ready = 1; - /* FIXME add verbose printout for csd */ - /* printf("READ_BL_LEN=%u, C_SIZE_MULT=%u, C_SIZE=%u\n", - csd->read_bl_len, csd->c_size_mult1, - csd->c_size); */ -// mmc_dev.blksz = 512; -// mmc_dev.lba = (((unsigned long)1 << csd->c_size_mult1) * -// (unsigned long)csd->c_size) >> 9; - - switch (card_type) { - case CARDTYPE_SDHC: - puts(" SDHC size: "); - printdec((UNSTUFF_BITS(((u32 *)&response[0]), 48, 22) - + 1) / 2); - break; - default: - puts(" MMC/SD size: "); - printdec((((unsigned long)1 << csd->c_size_mult1) * - (unsigned long)(csd->c_size)) >> 10); - } - puts(" MiB\n"); - } - - resp = mmc_cmd(MMC_SELECT_CARD, rca<<16, MMC_CMD_AC | MMC_RSP_R1, - 0, 0, 0, (u16 *)&response[0]); - if (resp) - return 1; - -#ifdef CONFIG_MMC_WIDE - /* yay 4-bit! */ - if (card_type == CARDTYPE_SD || card_type == CARDTYPE_SDHC) { - resp = mmc_cmd(MMC_APP_CMD, rca<<16, MMC_CMD_AC | MMC_RSP_R1, - 0, 0, 0, (u16 *)&response[0]); - resp = mmc_cmd(MMC_SWITCH, 0x02, MMC_CMD_AC | MMC_RSP_R1B, - 0, 0, 0, (u16 *)&response[0]); - wide = 1; - glamo_reg_write(glamo_reg_read(GLAMO_REGOFS_MMC + - GLAMO_REG_MMC_BASIC) | GLAMO_BASIC_MMC_EN_4BIT_DATA, - GLAMO_REGOFS_MMC + GLAMO_REG_MMC_BASIC); - } -#endif - - /* set the clock to slow until first bulk completes (for slow SDHC) */ - - glamo_reg_write((glamo_reg_read(GLAMO_REG_CLOCK_GEN8) & 0xff00) | 32, - GLAMO_REG_CLOCK_GEN8); - - return rc; -} - - - diff --git a/qiboot/src/drivers/i2c-bitbang.c b/qiboot/src/drivers/i2c-bitbang.c deleted file mode 100644 index 436003e..0000000 --- a/qiboot/src/drivers/i2c-bitbang.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: Andy Green - * - * Generic i2c bitbang state machine - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include - -void i2c_read(struct i2c_bitbang * bb, unsigned char ads7, unsigned char reg) -{ - bb->data[0] = (ads7 << 1); /* write the register address */ - bb->data[1] = reg; - bb->data[2] = IBCONTROL_DO_START; - bb->data[3] = (ads7 << 1) | 1; /* then issue read cycle to device */ - bb->data[4] = IBCONTROL_DO_READ; - bb->data[5] = IBCONTROL_DO_STOP; - bb->data[6] = IBCONTROL_COMPLETE; - bb->state = IBS_INIT; -} - -void i2c_write(struct i2c_bitbang * bb, unsigned char ads7, unsigned char reg, - unsigned char b) -{ - bb->data[0] = (ads7 << 1); - bb->data[1] = reg; - bb->data[2] = b; - bb->data[3] = IBCONTROL_DO_STOP; - bb->data[4] = IBCONTROL_COMPLETE; - bb->state = IBS_INIT; -} - -int i2c_next_state(struct i2c_bitbang * bb) -{ - switch (bb->state) { - case IBS_INIT: - bb->index = 0; - bb->index_read = 0; - (bb->set)(1, 1); - bb->state = IBS_START1; - break; - - case IBS_START1: - (bb->set)(1, 0); - bb->state = IBS_START2; - break; - - case IBS_START2: - (bb->set)(0, 0); /* start */ - bb->count = 8; - bb->state = IBS_ADS_TX_S; - break; - - /* transmit address or data */ - case IBS_ADS_TX_S: - (bb->set)(0, !!(bb->data[bb->index] & 0x80)); - bb->state = IBS_ADS_TX_H; - break; - case IBS_ADS_TX_H: - (bb->set)(1, !!(bb->data[bb->index] & 0x80)); - bb->state = IBS_ADS_TX_L; - break; - case IBS_ADS_TX_L: - (bb->set)(0, !!(bb->data[bb->index] & 0x80)); - bb->data[bb->index] <<= 1; - bb->count--; - if (bb->count) { - bb->state = IBS_ADS_TX_S; - break; - } - - (bb->set)(0, 1); - bb->state = IBS_ADS_TX_ACK_H; - break; - - case IBS_ADS_TX_ACK_H: - /* we finished... we expect an ack now */ - if ((bb->read_sda)()) - return -1; - - (bb->set)(1, 1); - bb->state = IBS_ADS_TX_ACK_L; - break; - - case IBS_ADS_TX_ACK_L: - (bb->set)(0, 1); - - bb->count = 8; - bb->index++; - switch (bb->data[bb->index]) { - case IBCONTROL_DO_START: - bb->state = IBS_START1; - bb->index++; - break; - case IBCONTROL_DO_STOP: - bb->state = IBS_STOP1; - bb->index++; - break; - case IBCONTROL_DO_READ: - bb->data[bb->index_read] = 0; - bb->state = IBS_DATA_RX_S; - break; - case IBCONTROL_COMPLETE: - return 1; - default: - bb->state = IBS_ADS_TX_S; /* write it out */ - break; - } - break; - - - /* receive data */ - case IBS_DATA_RX_S: - (bb->set)(0, 1); - bb->state = IBS_DATA_RX_H; - break; - - case IBS_DATA_RX_H: - (bb->set)(1, 1); - bb->state = IBS_DATA_RX_L; - break; - - case IBS_DATA_RX_L: - bb->data[bb->index_read] <<= 1; - bb->data[bb->index_read] |= !!(bb->read_sda)(); - bb->count--; - if (bb->count) { - (bb->set)(0, 1); - bb->state = IBS_DATA_RX_S; - break; - } - - /* slave has released SDA now, bang down ACK */ - if (bb->data[bb->index + 1] != IBCONTROL_DO_READ) - (bb->set)(0, 1); - else - (bb->set)(0, 0); - bb->state = IBS_DATA_RX_ACK_H; - break; - - case IBS_DATA_RX_ACK_H: - if (bb->data[bb->index + 1] != IBCONTROL_DO_READ) - (bb->set)(1, 1); /* NAK */ - else - (bb->set)(1, 0); /* ACK */ - bb->state = IBS_DATA_RX_ACK_L; - break; - - case IBS_DATA_RX_ACK_L: - if (bb->data[bb->index + 1] != IBCONTROL_DO_READ) - (bb->set)(0, 1); /* NAK */ - else - (bb->set)(0, 0); /* ACK */ - bb->index_read++; - bb->index++; - switch (bb->data[bb->index]) { - case IBCONTROL_DO_START: - bb->state = IBS_START1; - bb->index++; - break; - case IBCONTROL_DO_STOP: - bb->state = IBS_STOP1; - bb->index++; - break; - case IBCONTROL_DO_READ: - bb->state = IBS_DATA_RX_S; - bb->data[bb->index_read] = 0; - break; - case IBCONTROL_COMPLETE: - return 1; - default: - bb->state = IBS_ADS_TX_S; /* write it out */ - break; - } - break; - - break; - - - case IBS_STOP1: - (bb->set)(0, 0); - bb->state = IBS_STOP2; - break; - - case IBS_STOP2: - (bb->set)(1, 0); - bb->state = IBS_STOP3; - break; - - case IBS_STOP3: - (bb->set)(1, 1); - bb->state = IBS_STOP4; - break; - - case IBS_STOP4: - (bb->set)(1, 1); - return 1; /* done */ - } - - return 0; /* keep going */ -} - -static int i2c_complete_synchronously(struct i2c_bitbang * bb) -{ - int ret = 0; - - while (!ret) { - ret = i2c_next_state(bb); - (bb->spin)(); - } - - if (ret < 0) { - puts("i2c transaction failed "); - printdec(ret); - puts("\n"); - } - return ret; -} - -int i2c_read_sync(struct i2c_bitbang * bb, unsigned char ads7, - unsigned char reg) -{ - i2c_read(bb, ads7, reg); - if (i2c_complete_synchronously(bb) < 0) - return -1; - - return bb->data[0]; -} - -void i2c_write_sync(struct i2c_bitbang * bb, unsigned char ads7, - unsigned char reg, unsigned char b) -{ - i2c_write(bb, ads7, reg, b); - i2c_complete_synchronously(bb); -} diff --git a/qiboot/src/fs/dev.c b/qiboot/src/fs/dev.c deleted file mode 100644 index 9d4fba3..0000000 --- a/qiboot/src/fs/dev.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2004 - * esd gmbh - * Reinhard Arlt - * - * based on code of fs/reiserfs/dev.c by - * - * (C) Copyright 2003 - 2004 - * Sysgo AG, , Pavel Bartusek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - - -#include -#include -#include - -extern unsigned long partition_offset_blocks; -extern unsigned long partition_length_blocks; - - -int ext2fs_devread(int sector, int filesystem_block_log2, int byte_offset, int byte_len, u8 *buf) -{ - unsigned char sec_buf[SECTOR_SIZE]; - unsigned block_len; - - sector = sector << filesystem_block_log2; - - -/* - * Check partition boundaries - */ - if ((sector < 0) - || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >= - partition_length_blocks)) { - /* errnum = ERR_OUTSIDE_PART; */ - puts(" ** ext2fs_devread() read outside partition sector "); - printdec(sector); - puts("\n"); - return 0; - } - - if (this_board->get_ui_keys) - if ((this_board->get_ui_keys)() & UI_ACTION_SKIPKERNEL) { - puts(" ** skipping \n"); - return 0; - } - -/* - * Get the read to the beginning of a partition. - */ - sector += byte_offset >> SECTOR_BITS; - byte_offset &= SECTOR_SIZE - 1; - - if (byte_offset) { - int minimum = SECTOR_SIZE - byte_offset; - - if (byte_len < minimum) - minimum = byte_len; - - /* read first part which isn't aligned with start of sector */ - if ((this_kernel->block_read)(sec_buf, - partition_offset_blocks + sector, 1) < 0) { - puts(" ** ext2fs_devread() read error **\n"); - return 0; - } - memcpy(buf, sec_buf + byte_offset, - minimum); - buf += minimum; - byte_len -= minimum; - sector++; - } - - if (!byte_len) - return 1; - - /* read sector aligned part */ - block_len = byte_len & ~(SECTOR_SIZE - 1); - - if (block_len == 0) { - u8 p[SECTOR_SIZE]; - - block_len = SECTOR_SIZE; - this_kernel->block_read(p,partition_offset_blocks + sector, 1); - memcpy(buf, p, byte_len); - return 1; - } - - if (this_kernel->block_read(buf, partition_offset_blocks + sector, - block_len / SECTOR_SIZE) < 0) { - puts(" ** ext2fs_devread() read error - block\n"); - printdec(partition_offset_blocks + sector); - puts(" "); - print32(block_len); - puts(" "); - print32(sector); - return 0; - } - block_len = byte_len & ~(SECTOR_SIZE - 1); - buf += block_len; - byte_len -= block_len; - sector += block_len / SECTOR_SIZE; - - if (byte_len) { - /* read rest of data which are not in whole sector */ - if (this_kernel->block_read(sec_buf, - partition_offset_blocks + sector, 1) != 1) { - puts(" ** ext2fs_devread() read error - last part\n"); - printdec(partition_offset_blocks + sector); - puts(" "); - print32(block_len); - puts(" "); - print32(sector); - return 0; - } - memcpy (buf, sec_buf, byte_len); - } - return 1; -} - diff --git a/qiboot/src/fs/ext2.c b/qiboot/src/fs/ext2.c deleted file mode 100644 index 2709806..0000000 --- a/qiboot/src/fs/ext2.c +++ /dev/null @@ -1,940 +0,0 @@ -/* - *(C) Copyright 2004 - * esd gmbh - * Reinhard Arlt - * - * based on code from grub2 fs/ext2.c and fs/fshelp.c by - * - * GRUB -- GRand Unified Bootloader - * Copyright(C) 2003, 2004 Free Software Foundation, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -#include -#include -#include - -extern int ext2fs_devread(int sector, int log2blksize, int byte_offset, int byte_len, - char *buf); - -/* Magic value used to identify an ext2 filesystem. */ -#define EXT2_MAGIC 0xEF53 -/* Amount of indirect blocks in an inode. */ -#define INDIRECT_BLOCKS 12 -/* Maximum lenght of a pathname. */ -#define EXT2_PATH_MAX 4096 -/* Maximum nesting of symlinks, used to prevent a loop. */ -#define EXT2_MAX_SYMLINKCNT 8 - -/* Filetype used in directory entry. */ -#define FILETYPE_UNKNOWN 0 -#define FILETYPE_REG 1 -#define FILETYPE_DIRECTORY 2 -#define FILETYPE_SYMLINK 7 - -/* Filetype information as used in inodes. */ -#define FILETYPE_INO_MASK 0170000 -#define FILETYPE_INO_REG 0100000 -#define FILETYPE_INO_DIRECTORY 0040000 -#define FILETYPE_INO_SYMLINK 0120000 - -/* Bits used as offset in sector */ -#define DISK_SECTOR_BITS 9 - -/* Log2 size of ext2 block in 512 blocks. */ -#define LOG2_EXT2_BLOCK_SIZE(data)(__le32_to_cpu(data->sblock.log2_block_size) + 1) - -/* Log2 size of ext2 block in bytes. */ -#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu(data->sblock.log2_block_size) + 10) - -/* The size of an ext2 block in bytes. */ -#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data)) - -#define EXT2_GOOD_OLD_REV 0 /* The good old (original) format */ -#define EXT2_DYNAMIC_REV 1 /* V2 format w/ dynamic inode sizes */ - -#define EXT2_GOOD_OLD_INODE_SIZE 128 -uint32_t ext2_inode_size = EXT2_GOOD_OLD_INODE_SIZE; - -/* The ext2 superblock. */ -struct ext2_sblock { - uint32_t total_inodes; - uint32_t total_blocks; - uint32_t reserved_blocks; - uint32_t free_blocks; - uint32_t free_inodes; - uint32_t first_data_block; - uint32_t log2_block_size; - uint32_t log2_fragment_size; - uint32_t blocks_per_group; - uint32_t fragments_per_group; - uint32_t inodes_per_group; - uint32_t mtime; - uint32_t utime; - uint16_t mnt_count; - uint16_t max_mnt_count; - uint16_t magic; - uint16_t fs_state; - uint16_t error_handling; - uint16_t minor_revision_level; - uint32_t lastcheck; - uint32_t checkinterval; - uint32_t creator_os; - uint32_t revision_level; - uint16_t uid_reserved; - uint16_t gid_reserved; - uint32_t first_inode; - uint16_t inode_size; - uint16_t block_group_number; - uint32_t feature_compatibility; - uint32_t feature_incompat; - uint32_t feature_ro_compat; - uint32_t unique_id[4]; - char volume_name[16]; - char last_mounted_on[64]; - uint32_t compression_info; -}; - -/* The ext2 blockgroup. */ -struct ext2_block_group { - uint32_t block_id; - uint32_t inode_id; - uint32_t inode_table_id; - uint16_t free_blocks; - uint16_t free_inodes; - uint16_t pad; - uint32_t reserved[3]; -}; - -/* The ext2 inode. */ -struct ext2_inode { - uint16_t mode; - uint16_t uid; - uint32_t size; - uint32_t atime; - uint32_t ctime; - uint32_t mtime; - uint32_t dtime; - uint16_t gid; - uint16_t nlinks; - uint32_t blockcnt; /* Blocks of 512 bytes!! */ - uint32_t flags; - uint32_t osd1; - union { - struct datablocks { - uint32_t dir_blocks[INDIRECT_BLOCKS]; - uint32_t indir_block; - uint32_t double_indir_block; - uint32_t tripple_indir_block; - } blocks; - char symlink[60]; - } b; - uint32_t version; - uint32_t acl; - uint32_t dir_acl; - uint32_t fragment_addr; - uint32_t osd2[3]; -}; - -/* The header of an ext2 directory entry. */ -struct ext2_dirent { - uint32_t inode; - uint16_t direntlen; - uint8_t namelen; - uint8_t filetype; -}; - -struct ext2fs_node { - struct ext2_data *data; - struct ext2_inode inode; - int ino; - int inode_read; -}; - -/* Information about a "mounted" ext2 filesystem. */ -struct ext2_data { - struct ext2_sblock sblock; - struct ext2_inode *inode; - struct ext2fs_node diropen; -}; - - -typedef struct ext2fs_node *ext2fs_node_t; - -struct ext2_data *ext2fs_root = NULL; -ext2fs_node_t ext2fs_file = NULL; -int symlinknest = 0; -uint32_t *indir1_block = NULL; -int indir1_size = 0; -int indir1_blkno = -1; -uint32_t *indir2_block = NULL; -int indir2_size = 0; -int indir2_blkno = -1; - - -static int ext2fs_blockgroup - (struct ext2_data *data, int group, struct ext2_block_group *blkgrp) { - return ext2fs_devread - ((__le32_to_cpu(data->sblock.first_data_block) + - 1), LOG2_EXT2_BLOCK_SIZE(data), - group * sizeof(struct ext2_block_group), - sizeof(struct ext2_block_group),(char *) blkgrp); -} - - -static int ext2fs_read_inode - (struct ext2_data *data, int ino, struct ext2_inode *inode) { - struct ext2_block_group blkgrp; - struct ext2_sblock *sblock = &data->sblock; - int inodes_per_block; - int status; - - unsigned int blkno; - unsigned int blkoff; - - /* It is easier to calculate if the first inode is 0. */ - ino--; - status = ext2fs_blockgroup(data, - ino / - __le32_to_cpu(sblock->inodes_per_group), - &blkgrp); - if (status == 0) - return 0; - - inodes_per_block = EXT2_BLOCK_SIZE(data) / ext2_inode_size; - blkno =(ino % __le32_to_cpu(sblock->inodes_per_group)) / - inodes_per_block; - blkoff =(ino % __le32_to_cpu(sblock->inodes_per_group)) % - inodes_per_block; -#ifdef DEBUG - puts("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff); -#endif - /* Read the inode. */ - - status = ext2fs_devread(__le32_to_cpu(blkgrp.inode_table_id) + blkno, - LOG2_EXT2_BLOCK_SIZE(data), - ext2_inode_size * blkoff, - sizeof(struct ext2_inode), (char *)inode); - - return !!status; -} - - -void ext2fs_free_node(ext2fs_node_t node, ext2fs_node_t currroot) { - if ((node != &ext2fs_root->diropen) &&(node != currroot)) { - free(node); - } -} - - -static int ext2fs_read_block(ext2fs_node_t node, int fileblock) { - struct ext2_data *data = node->data; - struct ext2_inode *inode = &node->inode; - int blknr; - int blksz = EXT2_BLOCK_SIZE(data); - int log2_blksz = LOG2_EXT2_BLOCK_SIZE(data); - int status; - - /* Direct blocks. */ - if (fileblock < INDIRECT_BLOCKS) { - blknr = __le32_to_cpu(inode->b.blocks.dir_blocks[fileblock]); - } - /* Indirect. */ - else if (fileblock <(INDIRECT_BLOCKS +(blksz / 4))) { - if (indir1_block == NULL) { - indir1_block =(uint32_t *) malloc(blksz); - if (indir1_block == NULL) { - puts("** ext2fs read block(indir 1) malloc failed. **\n"); - return -1; - } - indir1_size = blksz; - indir1_blkno = -1; - } - if (blksz != indir1_size) { - free(indir1_block); - indir1_block = NULL; - indir1_size = 0; - indir1_blkno = -1; - indir1_block =(uint32_t *) malloc(blksz); - if (indir1_block == NULL) { - puts("** ext2fs read block(indir 1) malloc failed. **\n"); - return -1; - } - indir1_size = blksz; - } - if ((__le32_to_cpu(inode->b.blocks.indir_block) << - log2_blksz) != indir1_blkno) { - status = ext2fs_devread(__le32_to_cpu(inode->b.blocks.indir_block), log2_blksz, - 0, blksz, - (char *) indir1_block); - if (status == 0) { - puts("** ext2fs read block(indir 1) failed. **\n"); - return 0; - } - indir1_blkno = - __le32_to_cpu(inode->b.blocks. - indir_block) << log2_blksz; - } - blknr = __le32_to_cpu(indir1_block - [fileblock - INDIRECT_BLOCKS]); - } - /* Double indirect. */ - else if (fileblock < - (INDIRECT_BLOCKS +(blksz / 4 *(blksz / 4 + 1)))) { - unsigned int perblock = blksz / 4; - unsigned int rblock = fileblock -(INDIRECT_BLOCKS - + blksz / 4); - - if (indir1_block == NULL) { - indir1_block =(uint32_t *) malloc(blksz); - if (indir1_block == NULL) { - puts("** ext2fs read block(indir 2 1) malloc failed. **\n"); - return -1; - } - indir1_size = blksz; - indir1_blkno = -1; - } - if (blksz != indir1_size) { - free(indir1_block); - indir1_block = NULL; - indir1_size = 0; - indir1_blkno = -1; - indir1_block =(uint32_t *) malloc(blksz); - if (indir1_block == NULL) { - puts("** ext2fs read block(indir 2 1) malloc failed. **\n"); - return -1; - } - indir1_size = blksz; - } - if ((__le32_to_cpu(inode->b.blocks.double_indir_block) << - log2_blksz) != indir1_blkno) { - status = ext2fs_devread(__le32_to_cpu(inode->b.blocks.double_indir_block), log2_blksz, - 0, blksz, - (char *) indir1_block); - if (status == 0) { - puts("** ext2fs read block(indir 2 1) failed. **\n"); - return -1; - } - indir1_blkno = - __le32_to_cpu(inode->b.blocks.double_indir_block) << log2_blksz; - } - - if (indir2_block == NULL) { - indir2_block =(uint32_t *) malloc(blksz); - if (indir2_block == NULL) { - puts("** ext2fs read block(indir 2 2) malloc failed. **\n"); - return -1; - } - indir2_size = blksz; - indir2_blkno = -1; - } - if (blksz != indir2_size) { - free(indir2_block); - indir2_block = NULL; - indir2_size = 0; - indir2_blkno = -1; - indir2_block =(uint32_t *) malloc(blksz); - if (indir2_block == NULL) { - puts("** ext2fs read block(indir 2 2) malloc failed. **\n"); - return -1; - } - indir2_size = blksz; - } - if ((__le32_to_cpu(indir1_block[rblock / perblock]) << - log2_blksz) != indir2_blkno) { - status = ext2fs_devread(__le32_to_cpu(indir1_block[rblock / perblock]), log2_blksz, - 0, blksz, - (char *) indir2_block); - if (status == 0) { - puts("** ext2fs read block(indir 2 2) failed. **\n"); - return -1; - } - indir2_blkno = - __le32_to_cpu(indir1_block[rblock / perblock]) << log2_blksz; - } - blknr = __le32_to_cpu(indir2_block[rblock % perblock]); - } - /* Triple indirect. */ - else { - puts("** ext2fs doesn't support triple indirect blocks. **\n"); - return -1; - } -#ifdef DEBUG - printf("ext2fs_read_block %08x\n", blknr); -#endif - return blknr; -} - - -int ext2fs_read_file(ext2fs_node_t node, int pos, unsigned int len, char *buf) { - int i; - int blockcnt; - int log2blocksize = LOG2_EXT2_BLOCK_SIZE(node->data); - int blocksize = 1 <<(log2blocksize + DISK_SECTOR_BITS); - unsigned int filesize = __le32_to_cpu(node->inode.size); - int previous_block_number = -1; - int delayed_start = 0; - int delayed_extent = 0; - int delayed_skipfirst = 0; - int delayed_next = 0; - char * delayed_buf = NULL; - int status; - - /* Adjust len so it we can't read past the end of the file. */ - if (len > filesize) { - len = filesize; - } - blockcnt = ((len + pos) + blocksize - 1) / blocksize; - - for(i = pos / blocksize; i < blockcnt; i++) { - int blknr; - int blockoff = pos % blocksize; - int blockend = blocksize; - - int skipfirst = 0; - - blknr = ext2fs_read_block(node, i); - if (blknr < 0) - return -1; - - blknr = blknr << log2blocksize; - - /* Last block. */ - if (i == blockcnt - 1) { - blockend =(len + pos) % blocksize; - - /* The last portion is exactly blocksize. */ - if (!blockend) { - blockend = blocksize; - } - } - - /* First block. */ - if (i == pos / blocksize) { - skipfirst = blockoff; - blockend -= skipfirst; - } - - /* If the block number is 0 this block is not stored on disk but - is zero filled instead. */ - if (blknr) { - int status; - - if (previous_block_number != -1) { - if (delayed_next == blknr) { - delayed_extent += blockend; - delayed_next += blockend >> SECTOR_BITS; - } else { /* spill */ - status = ext2fs_devread(delayed_start, - 0, delayed_skipfirst, - delayed_extent, delayed_buf); - if (status == 0) - return -1; - previous_block_number = blknr; - delayed_start = blknr; - delayed_extent = blockend; - delayed_skipfirst = skipfirst; - delayed_buf = buf; - delayed_next = blknr + (blockend >> SECTOR_BITS); - } - } else { - previous_block_number = blknr; - delayed_start = blknr; - delayed_extent = blockend; - delayed_skipfirst = skipfirst; - delayed_buf = buf; - delayed_next = blknr + (blockend >> SECTOR_BITS); - } - - } else { - if (previous_block_number != -1) { - /* spill */ - status = ext2fs_devread(delayed_start, - 0, delayed_skipfirst, - delayed_extent, delayed_buf); - if (status == 0) - return -1; - previous_block_number = -1; - } - memset(buf, 0, blocksize - skipfirst); - } - buf += blocksize - skipfirst; - } - - if (previous_block_number != -1) { - /* spill */ - status = ext2fs_devread(delayed_start, - 0, delayed_skipfirst, - delayed_extent, delayed_buf); - if (status == 0) - return -1; - previous_block_number = -1; - } - - return(len); -} - - -static int ext2fs_iterate_dir(ext2fs_node_t dir, char *name, ext2fs_node_t * fnode, int *ftype) -{ - unsigned int fpos = 0; - int status; - struct ext2fs_node *diro =(struct ext2fs_node *) dir; - -#ifdef DEBUG - if (name != NULL) - printf("Iterate dir %s\n", name); -#endif /* of DEBUG */ - if (!diro->inode_read) { - status = ext2fs_read_inode(diro->data, diro->ino, - &diro->inode); - if (status == 0) { - printdec(diro->ino); - puts("failed to read inode\n"); - return(0); - } - } - - /* Search the file. */ - while (fpos < __le32_to_cpu(diro->inode.size)) { - struct ext2_dirent dirent; - - status = ext2fs_read_file(diro, fpos, - sizeof(struct ext2_dirent), - (char *) &dirent); - if (status < 1) { - puts("ext2fs_read_file ret < 1\n"); - return 0; - } - - if (dirent.namelen != 0) { - char filename[256]; - ext2fs_node_t fdiro; - int type = FILETYPE_UNKNOWN; - - status = ext2fs_read_file(diro, - fpos + sizeof(struct ext2_dirent), - dirent.namelen, filename); - if (status < 1) { - puts("ext2fs_read_file fail 2\n"); - return(0); - } - - fdiro = malloc(sizeof(struct ext2fs_node)); - if (!fdiro) { - puts("malloc fail\n"); - return(0); - } - - - fdiro->data = diro->data; - fdiro->ino = __le32_to_cpu(dirent.inode); - - filename[dirent.namelen] = '\0'; - - if (dirent.filetype != FILETYPE_UNKNOWN) { - fdiro->inode_read = 0; - - if (dirent.filetype == FILETYPE_DIRECTORY) { - type = FILETYPE_DIRECTORY; - } else if (dirent.filetype == - FILETYPE_SYMLINK) { - type = FILETYPE_SYMLINK; - } else if (dirent.filetype == FILETYPE_REG) { - type = FILETYPE_REG; - } - } else { - /* The filetype can not be read from the dirent, get it from inode */ - - status = ext2fs_read_inode(diro->data, - __le32_to_cpu(dirent.inode), - &fdiro->inode); - if (status == 0) { - puts("inner ext2fs_read_inode fail\n"); - free(fdiro); - return(0); - } - fdiro->inode_read = 1; - - if ((__le16_to_cpu(fdiro->inode.mode) & - FILETYPE_INO_MASK) == - FILETYPE_INO_DIRECTORY) { - type = FILETYPE_DIRECTORY; - } else if ((__le16_to_cpu(fdiro->inode.mode) - & FILETYPE_INO_MASK) == - FILETYPE_INO_SYMLINK) { - type = FILETYPE_SYMLINK; - } else if ((__le16_to_cpu(fdiro->inode.mode) - & FILETYPE_INO_MASK) == - FILETYPE_INO_REG) { - type = FILETYPE_REG; - } - } -#ifdef DEBUG - printf("iterate >%s<\n", filename); -#endif /* of DEBUG */ - if ((name != NULL) &&(fnode != NULL) - &&(ftype != NULL)) { - if (strcmp(filename, name) == 0) { - *ftype = type; - *fnode = fdiro; - return 1; - } - } else { - if (fdiro->inode_read == 0) { - status = ext2fs_read_inode(diro->data, - __le32_to_cpu(dirent.inode), - &fdiro->inode); - if (status == 0) { - puts("ext2fs_read_inode 3 fail\n"); - free(fdiro); - return(0); - } - fdiro->inode_read = 1; - } - switch(type) { - case FILETYPE_DIRECTORY: - puts(" "); - break; - case FILETYPE_SYMLINK: - puts(" "); - break; - case FILETYPE_REG: - puts(" "); - break; - default: - puts("< ? > "); - break; - } - printdec(__le32_to_cpu(fdiro->inode.size)); - puts(" "); - puts(filename); - puts("\n"); - } - free(fdiro); - } - fpos += __le16_to_cpu(dirent.direntlen); - } - return 0; -} - - -static char *ext2fs_read_symlink(ext2fs_node_t node) { - char *symlink; - struct ext2fs_node *diro = node; - int status; - - if (!diro->inode_read) { - status = ext2fs_read_inode(diro->data, diro->ino, - &diro->inode); - if (status == 0) { - return(0); - } - } - symlink = malloc(__le32_to_cpu(diro->inode.size) + 1); - if (!symlink) - return(0); - - /* If the filesize of the symlink is bigger than - 60 the symlink is stored in a separate block, - otherwise it is stored in the inode. */ - if (__le32_to_cpu(diro->inode.size) < 60) { - strncpy(symlink, diro->inode.b.symlink, - __le32_to_cpu(diro->inode.size)); - } else { - status = ext2fs_read_file(diro, 0, - __le32_to_cpu(diro->inode.size), - symlink); - if (status == 0) { - free(symlink); - return(0); - } - } - symlink[__le32_to_cpu(diro->inode.size)] = '\0'; - return(symlink); -} - - -int ext2fs_find_file1 - (const char *currpath, - ext2fs_node_t currroot, ext2fs_node_t * currfound, int *foundtype) { - char fpath[strlen(currpath) + 1]; - char *name = fpath; - char *next; - int status; - int type = FILETYPE_DIRECTORY; - ext2fs_node_t currnode = currroot; - ext2fs_node_t oldnode = currroot; - - strncpy(fpath, currpath, strlen(currpath) + 1); - - /* Remove all leading slashes. */ - while (*name == '/') - name++; - - if (!*name) { - *currfound = currnode; - return 1; - } - - for(;;) { - int found; - - /* Extract the actual part from the pathname. */ - next = strchr(name, '/'); - if (next) { - /* Remove all leading slashes. */ - while (*next == '/') { - *(next++) = '\0'; - } - } - - /* At this point it is expected that the current node is a directory, check if this is true. */ - if (type != FILETYPE_DIRECTORY) { - ext2fs_free_node(currnode, currroot); - return(0); - } - - oldnode = currnode; - - /* Iterate over the directory. */ - found = ext2fs_iterate_dir(currnode, name, &currnode, &type); - if (found == 0) - return(0); - - if (found == -1) - break; - - /* Read in the symlink and follow it. */ - if (type == FILETYPE_SYMLINK) { - char *symlink; - - /* Test if the symlink does not loop. */ - if (++symlinknest == 8) { - ext2fs_free_node(currnode, currroot); - ext2fs_free_node(oldnode, currroot); - return(0); - } - - symlink = ext2fs_read_symlink(currnode); - ext2fs_free_node(currnode, currroot); - - if (!symlink) { - ext2fs_free_node(oldnode, currroot); - return(0); - } -#ifdef DEBUG - printf("Got symlink >%s<\n", symlink); -#endif /* of DEBUG */ - /* The symlink is an absolute path, go back to the root inode. */ - if (symlink[0] == '/') { - ext2fs_free_node(oldnode, currroot); - oldnode = &ext2fs_root->diropen; - } - - /* Lookup the node the symlink points to. */ - status = ext2fs_find_file1(symlink, oldnode, - &currnode, &type); - - free(symlink); - - if (status == 0) { - ext2fs_free_node(oldnode, currroot); - return(0); - } - } - - ext2fs_free_node(oldnode, currroot); - - /* Found the node! */ - if (!next || *next == '\0') { - *currfound = currnode; - *foundtype = type; - return(1); - } - name = next; - } - return -1; -} - - -int ext2fs_find_file - (const char *path, - ext2fs_node_t rootnode, ext2fs_node_t * foundnode, int expecttype) { - int status; - int foundtype = FILETYPE_DIRECTORY; - - - symlinknest = 0; - if (!path) - return 0; - - status = ext2fs_find_file1(path, rootnode, foundnode, &foundtype); - if (status == 0) - return 0; - - /* Check if the node that was found was of the expected type. */ - if ((expecttype == FILETYPE_REG) &&(foundtype != expecttype)) { - return 0; - } else if ((expecttype == FILETYPE_DIRECTORY) - &&(foundtype != expecttype)) { - return 0; - } - return 1; -} - - -int ext2fs_ls(char *dirname) { - ext2fs_node_t dirnode; - int status; - - if (ext2fs_root == NULL) - return 0; - - status = ext2fs_find_file(dirname, &ext2fs_root->diropen, &dirnode, - FILETYPE_DIRECTORY); - if (status != 1) { - puts("** Can not find directory. **\n"); - return 1; - } - ext2fs_iterate_dir(dirnode, NULL, NULL, NULL); - ext2fs_free_node(dirnode, &ext2fs_root->diropen); - return 0; -} - - -int ext2fs_open(const char *filename) { - ext2fs_node_t fdiro = NULL; - int status; - int len; - int ret = -1; - - if (ext2fs_root == NULL) - goto fail; - - ext2fs_file = NULL; - status = ext2fs_find_file(filename, &ext2fs_root->diropen, &fdiro, - FILETYPE_REG); - if (status == 0) { - ret = -2; - goto fail; - } - - if (!fdiro->inode_read) { - status = ext2fs_read_inode(fdiro->data, fdiro->ino, - &fdiro->inode); - if (status == 0) { - ret = -3; - goto fail; - } - } - len = __le32_to_cpu(fdiro->inode.size); - ext2fs_file = fdiro; - - return(len); - -fail: - ext2fs_free_node(fdiro, &ext2fs_root->diropen); - return ret; -} - - -int ext2fs_close(void - ) { - if ((ext2fs_file != NULL) &&(ext2fs_root != NULL)) { - ext2fs_free_node(ext2fs_file, &ext2fs_root->diropen); - ext2fs_file = NULL; - } - if (ext2fs_root != NULL) { - free(ext2fs_root); - ext2fs_root = NULL; - } - if (indir1_block != NULL) { - free(indir1_block); - indir1_block = NULL; - indir1_size = 0; - indir1_blkno = -1; - } - if (indir2_block != NULL) { - free(indir2_block); - indir2_block = NULL; - indir2_size = 0; - indir2_blkno = -1; - } - return(0); -} - - -int ext2fs_read(char *buf, unsigned len) { - int status; - - if (ext2fs_root == NULL) - return 0; - - if (ext2fs_file == NULL) - return 0; - - status = ext2fs_read_file(ext2fs_file, 0, len, buf); - return status; -} - - -int ext2fs_mount(void) { - struct ext2_data *data; - int status; - - data = malloc(sizeof(struct ext2_data)); - if (!data) - return 0; - - /* Read the superblock. */ - status = ext2fs_devread(1 * 2, 0, 0, sizeof(struct ext2_sblock), - (char *) &data->sblock); - if (!status) - goto fail; - - /* Make sure this is an ext2 filesystem. */ - if (__le16_to_cpu(data->sblock.magic) != EXT2_MAGIC) - goto fail; - - if (__le32_to_cpu(data->sblock.revision_level) == EXT2_GOOD_OLD_REV) - ext2_inode_size = EXT2_GOOD_OLD_INODE_SIZE; - else - ext2_inode_size = __le16_to_cpu (data->sblock.inode_size); - - data->diropen.data = data; - data->diropen.ino = 2; - data->diropen.inode_read = 1; - data->inode = &data->diropen.inode; - - status = ext2fs_read_inode(data, 2, data->inode); - if (status == 0) - goto fail; - - ext2fs_root = data; - - return 1; - -fail: - puts("Failed to mount ext2 filesystem...\n"); - free(data); - ext2fs_root = NULL; - - return 0; -} - diff --git a/qiboot/src/io.h b/qiboot/src/io.h deleted file mode 100644 index 029b7f9..0000000 --- a/qiboot/src/io.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * linux/include/asm-arm/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ -#ifndef __ASM_ARM_IO_H -#define __ASM_ARM_IO_H - -#ifdef __KERNEL__ - -#include -#include -#include -#if 0 /* XXX###XXX */ -#include -#endif /* XXX###XXX */ - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -typedef unsigned long phys_addr_t; - -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -#define writeb(v,a) __arch_putb(v,a) -#define writew(v,a) __arch_putw(v,a) -#define writel(v,a) __arch_putl(v,a) - -#define readb(a) __arch_getb(a) -#define readw(a) __arch_getw(a) -#define readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) - -/* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include -#endif /* XXX###XXX */ - -/* - * IO port access primitives - * ------------------------- - * - * The ARM doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerious - * ARM documents: - * - * PCI: D0-D7 D8-D15 D16-D23 D24-D31 - * ARM: D24-D31 D16-D23 D8-D15 D0-D7 - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif - -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define outl_p(val,port) outl((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -extern void __readwrite_bug(const char *fn); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) - -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) - -#define eth_io_copy_and_sum(s,c,l,b) \ - eth_copy_and_sum((s),__mem_pci(c),(l),(b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ -#endif /* __ASM_ARM_IO_H */ diff --git a/qiboot/src/memory-test.c b/qiboot/src/memory-test.c deleted file mode 100644 index 4cdc8cc..0000000 --- a/qiboot/src/memory-test.c +++ /dev/null @@ -1,145 +0,0 @@ -#include -#include - -int memory_test_const32(void * start, unsigned int length, u32 value) -{ - int errors = 0; - u32 * p = (u32 *)start; - u32 * pend = (u32 *)(start + length); - int count = length >> 2; - - puts("."); - - while (p < pend) - *p++ = value; - - p = (u32 *)start; - count = length >> 2; - - while (count--) - if (*p++ != value) { - puts("*** Error "); - print32((long)p - 4); - errors++; - } - - return errors; -} - -int memory_test_ads(void * start, unsigned int length, u32 mask) -{ - int errors = 0; - u32 * p = (u32 *)start; - u32 * pend = (u32 *)(start + length); - - puts("."); - - while (p < pend) - if ((u32)p & mask) - *p++ = 0xffffffff; - else - *p++ = 0; - - p = (u32 *)start; - - while (p < pend) { - if ((u32)p & mask) { - if (*p++ != 0xffffffff) { - puts("*** Error "); - print32((long)p - 4); - errors++; - } - } else { - if (*p++) { - puts("*** Error "); - print32((long)p - 4); - errors++; - } - } - } - return errors; -} - -int memory_test_walking1(void * start, unsigned int length) -{ - int errors = 0; - u32 value = 1; - - while (value) { - errors += memory_test_const32(start, length, value); - value <<= 1; - } - - return errors; -} - -/* negative runs == run forever */ - -void __memory_test(void * start, unsigned int length) -{ - int errors = 0; - int series = 0; - int mask; - - puts("\nMemory Testing 0x"); - print32((u32)start); - puts(" length "); - printdec(length >> 20); - puts(" MB\n"); - - while (1) { - puts(" Test series "); - printdec(series + 1); - puts(" "); - - /* these are looking at data issues, they flood the whole - * array with the same data - */ - - errors += memory_test_const32(start, length, 0x55555555); - errors += memory_test_const32(start, length, 0xaaaaaaaa); - errors += memory_test_const32(start, length, 0x55aa55aa); - errors += memory_test_const32(start, length, 0xaa55aa55); - errors += memory_test_const32(start, length, 0x00ff00ff); - errors += memory_test_const32(start, length, 0xff00ff00); - errors += memory_test_walking1(start, length); - - /* this is looking at addressing issues, it floods only - * addresses meeting a walking mask with 0xffffffff (the rest - * is zeroed), and makes sure all the bits are only seen where - * they were placed - */ - - mask = 1; - while (! (length & mask)) { - errors += memory_test_ads(start, length, mask); - mask = mask << 1; - } - - puts(" Total errors: "); - printdec(errors); - puts("\n"); - - series++; - } -} - - -void memory_test(void * start, unsigned int length) -{ - /* it's a small steppingstone stack from start.S */ - extern int _ss_stack; - - /* - * we won't be coming back from this, so just force our local stack to - * steppingstone out of the way of main memory test action - * - * then jump into the actual test - */ - asm volatile ( - "mov sp, %0\n" - : : "r" (&_ss_stack) - ); - - __memory_test(start, length); -} diff --git a/qiboot/src/part.h b/qiboot/src/part.h deleted file mode 100644 index b22a637..0000000 --- a/qiboot/src/part.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _PART_H -#define _PART_H - -#include - -typedef struct block_dev_desc { - int if_type; /* type of the interface */ - int dev; /* device number */ - unsigned char part_type; /* partition type */ - unsigned char target; /* target SCSI ID */ - unsigned char lun; /* target LUN */ - unsigned char type; /* device type */ - unsigned char removable; /* removable device */ -#ifdef CONFIG_LBA48 - unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */ -#endif - lbaint_t lba; /* number of blocks */ - unsigned long blksz; /* block size */ - char vendor [40+1]; /* IDE model, SCSI Vendor */ - char product[20+1]; /* IDE Serial no, SCSI product */ - char revision[8+1]; /* firmware revision */ - unsigned long (*block_read)(int dev, - unsigned long start, - lbaint_t blkcnt, - void *buffer); - unsigned long (*block_write)(int dev, - unsigned long start, - lbaint_t blkcnt, - const void *buffer); - void *priv; /* driver private struct pointer */ -}block_dev_desc_t; - -/* Interface types: */ -#define IF_TYPE_UNKNOWN 0 -#define IF_TYPE_IDE 1 -#define IF_TYPE_SCSI 2 -#define IF_TYPE_ATAPI 3 -#define IF_TYPE_USB 4 -#define IF_TYPE_DOC 5 -#define IF_TYPE_MMC 6 -#define IF_TYPE_SD 7 -#define IF_TYPE_SATA 8 - -/* Part types */ -#define PART_TYPE_UNKNOWN 0x00 -#define PART_TYPE_MAC 0x01 -#define PART_TYPE_DOS 0x02 -#define PART_TYPE_ISO 0x03 -#define PART_TYPE_AMIGA 0x04 - -/* - * Type string for U-Boot bootable partitions - */ -#define BOOT_PART_TYPE "U-Boot" /* primary boot partition type */ -#define BOOT_PART_COMP "PPCBoot" /* PPCBoot compatibility type */ - -/* device types */ -#define DEV_TYPE_UNKNOWN 0xff /* not connected */ -#define DEV_TYPE_HARDDISK 0x00 /* harddisk */ -#define DEV_TYPE_TAPE 0x01 /* Tape */ -#define DEV_TYPE_CDROM 0x05 /* CD-ROM */ -#define DEV_TYPE_OPDISK 0x07 /* optical disk */ - -typedef struct disk_partition { - ulong start; /* # of first block in partition */ - ulong size; /* number of blocks in partition */ - ulong blksz; /* block size in bytes */ - uchar name[32]; /* partition name */ - uchar type[32]; /* string type description */ -} disk_partition_t; - -/* Misc _get_dev functions */ -block_dev_desc_t* get_dev(char* ifname, int dev); -block_dev_desc_t* ide_get_dev(int dev); -block_dev_desc_t* sata_get_dev(int dev); -block_dev_desc_t* scsi_get_dev(int dev); -block_dev_desc_t* usb_stor_get_dev(int dev); -block_dev_desc_t* mmc_get_dev(int dev); -block_dev_desc_t* systemace_get_dev(int dev); - -/* disk/part.c */ -int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part (block_dev_desc_t *dev_desc); -void init_part (block_dev_desc_t *dev_desc); -void dev_print(block_dev_desc_t *dev_desc); - - -#ifdef CONFIG_MAC_PARTITION -/* disk/part_mac.c */ -int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part_mac (block_dev_desc_t *dev_desc); -int test_part_mac (block_dev_desc_t *dev_desc); -#endif - -#ifdef CONFIG_DOS_PARTITION -/* disk/part_dos.c */ -int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part_dos (block_dev_desc_t *dev_desc); -int test_part_dos (block_dev_desc_t *dev_desc); -#endif - -#ifdef CONFIG_ISO_PARTITION -/* disk/part_iso.c */ -int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part_iso (block_dev_desc_t *dev_desc); -int test_part_iso (block_dev_desc_t *dev_desc); -#endif - -#ifdef CONFIG_AMIGA_PARTITION -/* disk/part_amiga.c */ -int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part_amiga (block_dev_desc_t *dev_desc); -int test_part_amiga (block_dev_desc_t *dev_desc); -#endif - -#endif /* _PART_H */ diff --git a/qiboot/src/phase2.c b/qiboot/src/phase2.c deleted file mode 100644 index 4a7ff18..0000000 --- a/qiboot/src/phase2.c +++ /dev/null @@ -1,495 +0,0 @@ -/* - * (C) Copyright 2008 Openmoko, Inc. - * Author: Andy Green - * - * Parse the U-Boot header and Boot Linux - * based on various code from U-Boot - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "blink_led.h" -#include -#define __ARM__ -#include -#include -#include - - -typedef void (*the_kernel_fn)(int zero, int arch, uint params); - -unsigned long partition_offset_blocks = 0; -unsigned long partition_length_blocks = 0; - -struct kernel_source const * this_kernel = 0; - -static const int INITRD_OFFSET = (8 * 1024 * 1024); - - -int raise(int n) -{ - return 0; -} - -static void indicate(enum ui_indication ui_indication) -{ - if (this_board->set_ui_indication) - (this_board->set_ui_indication)(ui_indication); -} - -static int read_file(const char * filepath, u8 * destination, int size) -{ - int len = size; - int ret; - - switch (this_kernel->filesystem) { - case FS_EXT2: - if (!ext2fs_mount()) { - puts("Unable to mount ext2 filesystem\n"); - indicate(UI_IND_MOUNT_FAIL); - return -2; /* death */ - } - puts(" EXT2 open: "); - puts(filepath); - len = ext2fs_open(filepath); - if (len < 0) { - puts(" Open failed\n"); - return -1; - } - puts(" OK\n"); - ret = ext2fs_read((char *)destination, size); - if (ret < 0) { - puts(" Read failed\n"); - return -1; - } - break; - - case FS_FAT: - /* FIXME */ - case FS_RAW: - /* any filename-related request in raw filesystem will fail */ - if (filepath) - return -1; - puts(" RAW open: +"); - printdec(partition_offset_blocks); - puts(" 512-byte blocks\n"); - if (this_kernel->block_read(destination, - partition_offset_blocks, size >> 9) < 0) { - puts("Bad kernel header\n"); - return -1; - } - break; - } - - return len; -} - -static int do_block_init(void) -{ - static void * last_block_init = NULL; - static int last_block_init_result = 0; - int fresh = 0; - - /* if this device needs initializing, try to init it */ - if (!this_kernel->block_init) - return 1; /* happy */ - - /* - * cache result to limit attempts for same - * block device to one time - */ - if (this_kernel->block_init != last_block_init) { - last_block_init = this_kernel->block_init; - last_block_init_result = (this_kernel->block_init)(); - fresh = 1; - } - - if (last_block_init_result) { - puts("block device init failed\n"); - if (fresh) - indicate(UI_IND_MOUNT_FAIL); - - return 0; /* failed */ - } - last_block_init = this_kernel->block_init; - - return 1; /* happy */ -} - -static int do_partitions(void *kernel_dram) -{ - unsigned char *p = kernel_dram; - - /* if there's a partition table implied, parse it, otherwise - * just use a fixed offset - */ - if (!this_kernel->partition_index) { - partition_offset_blocks = - this_kernel->offset_blocks512_if_no_partition; - return 1; - } - - if ((int)this_kernel->block_read(kernel_dram, 0, 4) < 0) { - puts("Bad partition read\n"); - indicate(UI_IND_MOUNT_FAIL); - return 0; - } - - if ((p[0x1fe] != 0x55) || (p[0x1ff] != 0xaa)) { - puts("partition signature missing\n"); - indicate(UI_IND_MOUNT_FAIL); - return 0; - } - - p += 0x1be + 8 + (0x10 * (this_kernel->partition_index - 1)); - - partition_offset_blocks = (((u32)p[3]) << 24) | - (((u32)p[2]) << 16) | - (((u32)p[1]) << 8) | - p[0]; - partition_length_blocks = (((u32)p[7]) << 24) | - (((u32)p[6]) << 16) | - (((u32)p[5]) << 8) | - p[4]; - - puts(" Partition: "); - printdec(this_kernel->partition_index); - puts(" start +"); - printdec(partition_offset_blocks); - puts(" 512-byte blocks, size "); - printdec(partition_length_blocks / 2048); - puts(" MiB\n"); - - return 1; -} - -static void do_params(unsigned initramfs_len, - const char *commandline_rootfs_append) -{ - const struct board_variant * board_variant = - (this_board->get_board_variant)(); - const char *p; - char * cmdline; - struct tag *params = (struct tag *)this_board->linux_tag_placement; - - /* eat leading white space */ - for (p = this_board->commandline_board; *p == ' '; p++); - - /* first tag */ - params->hdr.tag = ATAG_CORE; - params->hdr.size = tag_size(tag_core); - params->u.core.flags = 0; - params->u.core.pagesize = 0; - params->u.core.rootdev = 0; - params = tag_next(params); - - /* revision tag */ - params->hdr.tag = ATAG_REVISION; - params->hdr.size = tag_size(tag_revision); - params->u.revision.rev = board_variant->machine_revision; - params = tag_next(params); - - /* memory tags */ - params->hdr.tag = ATAG_MEM; - params->hdr.size = tag_size(tag_mem32); - params->u.mem.start = this_board->linux_mem_start; - params->u.mem.size = this_board->linux_mem_size; - params = tag_next(params); - - if (this_kernel->initramfs_filepath) { - /* INITRD2 tag */ - params->hdr.tag = ATAG_INITRD2; - params->hdr.size = tag_size(tag_initrd); - params->u.initrd.start = this_board->linux_mem_start + - INITRD_OFFSET; - params->u.initrd.size = initramfs_len; - params = tag_next(params); - } - - /* kernel commandline */ - - cmdline = params->u.cmdline.cmdline; - - /* start with the fixed device part of the commandline */ - - cmdline += strlen(strcpy(cmdline, p)); - - /* if the board itself needs a computed commandline, add it now */ - - if (this_board->append_device_specific_cmdline) - cmdline = (this_board->append_device_specific_cmdline)(cmdline); - - /* If he is giving an append commandline for this rootfs, apply that */ - - if (this_kernel->commandline_append) - cmdline += strlen(strcpy(cmdline, - this_kernel->commandline_append)); - if (commandline_rootfs_append[0]) - cmdline += strlen(strcpy(cmdline, - commandline_rootfs_append)); - - /* deal with any trailing newlines that hitched a ride */ - - while (*(cmdline - 1) == '\n') - cmdline--; - - *cmdline = '\0'; - - /* - * if he's still holding down the UI_ACTION_SKIPKERNEL key - * now we finished loading the kernel, take it to mean he wants - * to have the debugging options added to the commandline - */ - - if (this_board->commandline_board_debug && this_board->get_ui_debug) - if ((this_board->get_ui_debug)()) - cmdline += strlen(strcpy(cmdline, this_board-> - commandline_board_debug)); - - params->hdr.tag = ATAG_CMDLINE; - params->hdr.size = (sizeof(struct tag_header) + - strlen(params->u.cmdline.cmdline) + 1 + 4) >> 2; - - puts(" Cmdline: "); - puts(params->u.cmdline.cmdline); - puts("\n"); - - params = tag_next(params); - - /* needs to always be the last tag */ - params->hdr.tag = ATAG_NONE; - params->hdr.size = 0; -} - -static int do_crc(const image_header_t *hdr, const void *kernel_dram) -{ - unsigned long crc; - - /* - * It's good for now to know that our kernel is intact from - * the storage before we jump into it and maybe crash silently - * even though it costs us some time - */ - crc = crc32(0, kernel_dram + sizeof(image_header_t), - __be32_to_cpu(hdr->ih_size)); - if (crc == __be32_to_cpu(hdr->ih_dcrc)) - return 1; - - puts("\nKernel CRC ERROR: read 0x"); - print32(crc); - puts(" vs hdr CRC 0x"); - print32(__be32_to_cpu(hdr->ih_dcrc)); - puts("\n"); - - return 0; -} - -static the_kernel_fn load_uimage(void *kernel_dram) -{ - image_header_t *hdr; - u32 kernel_size; - - hdr = (image_header_t *)kernel_dram; - - if (__be32_to_cpu(hdr->ih_magic) != IH_MAGIC) { - puts("bad magic "); - print32(hdr->ih_magic); - puts("\n"); - return NULL; - } - - puts(" Found: \""); - puts((const char *)hdr->ih_name); - puts("\"\n Size: "); - printdec(__be32_to_cpu(hdr->ih_size) >> 10); - puts(" KiB\n"); - - kernel_size = ((__be32_to_cpu(hdr->ih_size) + - sizeof(image_header_t) + 2048) & ~(2048 - 1)); - - if (read_file(this_kernel->filepath, kernel_dram, kernel_size) < 0) { - indicate(UI_IND_KERNEL_PULL_FAIL); - return NULL; - } - - indicate(UI_IND_KERNEL_PULL_OK); - - if (!do_crc(hdr, kernel_dram)) - return NULL; - - return (the_kernel_fn) (((char *)hdr) + sizeof(image_header_t)); -} - -static the_kernel_fn load_zimage(void *kernel_dram) -{ - u32 magic = *(u32 *) (kernel_dram + 0x24); - u32 size = *(u32 *) (kernel_dram + 0x2c); - int got; - - if (magic != 0x016f2818) { - puts("bad magic "); - print32(magic); - puts("\n"); - return NULL; - } - - puts(" Size: "); - printdec(size >> 10); - puts(" KiB\n"); - - got = read_file(this_kernel->filepath, kernel_dram, size); - if (got < 0) { - indicate(UI_IND_KERNEL_PULL_FAIL); - return NULL; - } - - if (got != size) { - puts("short kernel\n"); - return NULL; - } - - indicate(UI_IND_KERNEL_PULL_OK); - - return (the_kernel_fn) kernel_dram; -} - -static void try_this_kernel(void) -{ - the_kernel_fn the_kernel; - unsigned int initramfs_len = 0; - static char commandline_rootfs_append[512] = ""; - int ret; - void * kernel_dram = (void *)this_board->linux_mem_start + 0x8000; - - partition_offset_blocks = 0; - partition_length_blocks = 0; - - puts("\nTrying kernel: "); - puts(this_kernel->name); - puts("\n"); - - indicate(UI_IND_MOUNT_PART); - - if (!do_block_init()) - return; - - if (!do_partitions(kernel_dram)) - return; - - /* does he want us to skip this? */ - - ret = read_file(this_board->noboot, kernel_dram, 512); - if (ret != -1) { - /* -2 (mount fail) should make us give up too */ - if (ret >= 0) { - puts(" (Skipping on finding "); - puts(this_board->noboot); - puts(")\n"); - indicate(UI_IND_SKIPPING); - } - return; - } - - /* is there a commandline append file? */ - - commandline_rootfs_append[0] = '\0'; - read_file(this_board->append, (u8 *)commandline_rootfs_append, 512); - - indicate(UI_IND_KERNEL_PULL); - - /* pull the kernel image */ - - if (read_file(this_kernel->filepath, kernel_dram, 4096) < 0) - return; - - the_kernel = load_uimage(kernel_dram); - if (!the_kernel) - the_kernel = load_zimage(kernel_dram); - if (!the_kernel) - return; - - /* initramfs if needed */ - - if (this_kernel->initramfs_filepath) { - indicate(UI_IND_INITRAMFS_PULL); - initramfs_len = read_file(this_kernel->initramfs_filepath, - (u8 *)this_board->linux_mem_start + INITRD_OFFSET, - 16 * 1024 * 1024); - if (initramfs_len < 0) { - puts("initramfs load failed\n"); - indicate(UI_IND_INITRAMFS_PULL_FAIL); - return; - } - indicate(UI_IND_INITRAMFS_PULL_OK); - } - - do_params(initramfs_len, commandline_rootfs_append); - - /* give board implementation a chance to shut down - * anything it may have going on, leave GPIO set for Linux - */ - if (this_board->close) - (this_board->close)(); - - puts("Starting --->\n\n"); - indicate(UI_IND_KERNEL_START); - - /* - * ooh that's it, we're gonna try boot this image! - * never mind the cache, Linux will take care of it - */ - the_kernel(0, this_board->linux_machine_id, - this_board->linux_tag_placement); - - /* we won't come back here no matter what */ -} - -void bootloader_second_phase(void) -{ - /* give device a chance to print device-specific things */ - - if (this_board->post_serial_init) - (this_board->post_serial_init)(); - - /* we try the possible kernels for this board in order */ - - for (this_kernel = this_board->kernel_source; this_kernel->name; - this_kernel++) - try_this_kernel(); - - /* none of the kernels worked out */ - - puts("\nNo usable kernel image found\n"); - - /* - * sit there doing a memory test in this case. - * - * This phase 2 code will get destroyed but it's OK, we won't be - * coming back and the whole memory test and dependency functions are - * in phase 1 / steppingstone, so we can test entire memory range. - * - * It means we just boot with SD Card with kernel(s) renamed or removed - * to provoke memory test. - */ - - indicate(UI_IND_MEM_TEST); - - memory_test((void *)this_board->linux_mem_start, - this_board->linux_mem_size); - -} diff --git a/qiboot/src/serial.h b/qiboot/src/serial.h deleted file mode 100644 index c10a386..0000000 --- a/qiboot/src/serial.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * Author: xiangfu liu - * - * Configuation settings for the FIC Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#define UART0 0 -#define UART1 1 -#define UART2 2 - -#define rGPHCON (*(volatile unsigned *)0x56000070) /*UART 0 Line control*/ - -#define rULCON0 (*(volatile unsigned *)0x50000000) /*UART 0 Line control*/ -#define rUCON0 (*(volatile unsigned *)0x50000004) /*UART 0 Control*/ -#define rUFCON0 (*(volatile unsigned *)0x50000008) /*UART 0 FIFO control*/ -#define rUMCON0 (*(volatile unsigned *)0x5000000c) /*UART 0 Modem control*/ -#define rUTRSTAT0 (*(volatile unsigned *)0x50000010) /*UART 0 Tx/Rx status*/ -#define rUERSTAT0 (*(volatile unsigned *)0x50000014) /*UART 0 Rx error status*/ -#define rUFSTAT0 (*(volatile unsigned *)0x50000018) /*UART 0 FIFO status*/ -#define rUMSTAT0 (*(volatile unsigned *)0x5000001c) /*UART 0 Modem status*/ -#define rUBRDIV0 (*(volatile unsigned *)0x50000028) /*UART 0 Baud rate divisor*/ - -#define rULCON1 (*(volatile unsigned *)0x50004000) /*UART 1 Line control*/ -#define rUCON1 (*(volatile unsigned *)0x50004004) /*UART 1 Control*/ -#define rUFCON1 (*(volatile unsigned *)0x50004008) /*UART 1 FIFO control*/ -#define rUMCON1 (*(volatile unsigned *)0x5000400c) /*UART 1 Modem control*/ -#define rUTRSTAT1 (*(volatile unsigned *)0x50004010) /*UART 1 Tx/Rx status*/ -#define rUERSTAT1 (*(volatile unsigned *)0x50004014) /*UART 1 Rx error status*/ -#define rUFSTAT1 (*(volatile unsigned *)0x50004018) /*UART 1 FIFO status*/ -#define rUMSTAT1 (*(volatile unsigned *)0x5000401c) /*UART 1 Modem status*/ -#define rUBRDIV1 (*(volatile unsigned *)0x50004028) /*UART 1 Baud rate divisor*/ - -#define rULCON2 (*(volatile unsigned *)0x50008000) /*UART 2 Line control*/ -#define rUCON2 (*(volatile unsigned *)0x50008004) /*UART 2 Control*/ -#define rUFCON2 (*(volatile unsigned *)0x50008008) /*UART 2 FIFO control*/ -#define rUTRSTAT2 (*(volatile unsigned *)0x50008010) /*UART 2 Tx/Rx status*/ -#define rUERSTAT2 (*(volatile unsigned *)0x50008014) /*UART 2 Rx error status*/ -#define rUFSTAT2 (*(volatile unsigned *)0x50008018) /*UART 2 FIFO status*/ -#define rUBRDIV2 (*(volatile unsigned *)0x50008028) /*UART 2 Baud rate divisor*/ - -#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) -#define RdURXH0() (*(volatile unsigned char *)0x50000024) -#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) -#define RdURXH1() (*(volatile unsigned char *)0x50004024) -#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) -#define RdURXH2() (*(volatile unsigned char *)0x50008024) - - - -// I/O PORT -#define rGPACON (*(volatile unsigned *)0x56000000) -#define rGPADAT (*(volatile unsigned *)0x56000004) - -#define rGPBCON (*(volatile unsigned *)0x56000010) -#define rGPBDAT (*(volatile unsigned *)0x56000014) -#define rGPBUP (*(volatile unsigned *)0x56000018) - -#define rGPCCON (*(volatile unsigned *)0x56000020) -#define rGPCDAT (*(volatile unsigned *)0x56000024) -#define rGPCUP (*(volatile unsigned *)0x56000028) - -#define rGPDCON (*(volatile unsigned *)0x56000030) -#define rGPDDAT (*(volatile unsigned *)0x56000034) -#define rGPDUP (*(volatile unsigned *)0x56000038) - -#define rGPECON (*(volatile unsigned *)0x56000040) -#define rGPEDAT (*(volatile unsigned *)0x56000044) -#define rGPEUP (*(volatile unsigned *)0x56000048) - -#define rGPFCON (*(volatile unsigned *)0x56000050) -#define rGPFDAT (*(volatile unsigned *)0x56000054) -#define rGPFUP (*(volatile unsigned *)0x56000058) - -#define rGPGCON (*(volatile unsigned *)0x56000060) -#define rGPGDAT (*(volatile unsigned *)0x56000064) -#define rGPGUP (*(volatile unsigned *)0x56000068) - -#define rGPHCON (*(volatile unsigned *)0x56000070) -#define rGPHDAT (*(volatile unsigned *)0x56000074) -#define rGPHUP (*(volatile unsigned *)0x56000078) - -#define rGPJCON (*(volatile unsigned *)0x560000d0) //Port J control -#define rGPJDAT (*(volatile unsigned *)0x560000d4) //Port J data -#define rGPJUP (*(volatile unsigned *)0x560000d8) //Port J data - -void port_init(void); -void serial_init (const int uart); -void serial_putc (const int uart,const char c); -int printk(const char *fmt, ...); -int puts(const char *string); - -#endif diff --git a/qiboot/src/start.S b/qiboot/src/start.S deleted file mode 100644 index bbc8186..0000000 --- a/qiboot/src/start.S +++ /dev/null @@ -1,332 +0,0 @@ -/* - * (C) Copyright 2007 OpenMoko, Inc. - * - * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define __ASM_MODE__ -#include - -#define S3C2410_MISCCR_nEN_SCLK0 (1 << 17) -#define S3C2410_MISCCR_nEN_SCLK1 (1 << 18) -#define S3C2410_MISCCR_nEN_SCLKE (1 << 19) - - - -.globl _start, processor_id, is_jtag - -_start: b start_code -/* if we are injected by JTAG, the script sets _istag content to nonzero */ -is_jtag: - .word 0 - -/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script - * we need to go through this hassle because before this moment, SDRAM is not - * working so we can't prep it from JTAG - */ - -_steppingstone_done: - ldr pc, _start_armboot - -_start_armboot: - .word start_qi - -_TEXT_BASE: - .word TEXT_BASE - -processor_id: - .word 0 - .word 0x41129200 /* s3c2442 ID */ - .word 0x410fb760 /* s3c6410 ID */ - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -start_code: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * detect processor we are running on - * s3c2442: 0x4112920x - * s3c6410: 0x410fb76x - */ - MRC p15, 0 ,r0, c0, c0, 0 - ldr r1, =processor_id - str r0, [r1] - ldr r2, [r1, #4] - - and r0, #0xfffffff0 - cmp r0, r2 - beq startup_2442 - - /* 6410 startup */ -startup_6410: - - mov r0, #0 - str r0, [r1] - - /* 2442 startup */ -startup_2442: -# define pWTCON 0x53000000 - - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define INTSUBMSK_val 0x0000ffff - - mov r1, #0xffffffff - ldr r0, =INTMSK - str r1, [r0] - - ldr r1, =INTSUBMSK_val - ldr r0, =INTSUBMSK - str r1, [r0] - - - /* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */ -# define CAMDIVN 0x4C000018 - - ldr r0, =CAMDIVN - mov r1, #0 - str r1, [r0] - - /* Clock asynchronous mode */ - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, #0xc0000000 - mcr p15, 0, r1, c1, c0, 0 - -#define LOCKTIME 0x4c000000 - - ldr r0, =LOCKTIME - mov r1, #0xffffff - str r1, [r0] - -# define UPLLCON 0x4c000008 -# define MPLLCON_val ((142 << 12) + (7 << 4) + 1) -# define UPLLCON_val (( 88 << 12) + (8 << 4) + 2) - - ldr r0, =UPLLCON - ldr r1, =UPLLCON_val - str r1, [r0] - - /* Page 7-19, seven nops between UPLL and MPLL */ - nop - nop - nop - nop - nop - nop - nop - - ldr r1, =MPLLCON_val - str r1, [r0, #-4] /* MPLLCON */ - -# define CLKDIVN 0x4C000014 /* clock divisor register */ -# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */ - - /* FCLK:HCLK:PCLK = 1:3:6 */ - ldr r0, =CLKDIVN - mov r1, #CLKDIVN_val - str r1, [r0] - - /* enable only CPU peripheral block clocks we actually use */ - ldr r0, =0x4c00000c /* clkcon */ - ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */ - str r1, [r0] - - /* gpio UART2 init, H port */ - ldr r0, =0x56000070 - ldr r1, =0x001AAAAA - str r1, [r0] - - /* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */ - ldr r0, =0x56000000 /* GPJ base */ - ldr r1, [r0, #0xd0] /* GPJCON */ - orr r1, r1, #(1 << 16) - str r1, [r0, #0xd0] - - ldr r1, [r0, #0xd4] /* GPJDAT */ - orr r1, r1, #(1 << 8) - str r1, [r0, #0xd4] - - - /* init uart2 */ - ldr r0, =0x50008000 - mov r1, #0x03 - str r1, [r0] - ldr r1, =0x245 - str r1, [r0, #0x04] - mov r1, #0x00 - str r1, [r0, #0x08] - mov r1, #0x00 - str r1, [r0, #0x0c] - mov r1, #0x11 - str r1, [r0, #0x28] - - ldr r0, =0x50008000 - ldr r1, =0x54 - str r1, [r0, #0x20] - -/* reset nand controller, or it is dead to us */ - - mov r1, #0x4E000000 - ldr r2, =0xfff0 @ initial value tacls=3,rph0=7,rph1=7 - ldr r3, [r1, #0] - orr r3, r3, r2 - str r3, [r1, #0] - - ldr r3, [r1, #4] - orr r3, r3, #1 @ enable nand controller - str r3, [r1, #4] - - - /* take sdram out of power down */ - ldr r0, =0x56000080 /* misccr */ - ldr r1, [ r0 ] - bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE) - str r1, [ r0 ] - - /* ensure signals stabalise */ - mov r1, #128 -1: subs r1, r1, #1 - bpl 1b - - bl cpu_init_crit - - /* ensure some refresh has happened */ - ldr r1, =0xfffff -1: subs r1, r1, #1 - bpl 1b - - /* capture full EINT situation into gstatus 4 */ - - ldr r0, =0x4A000000 /* SRCPND */ - ldr r1, [ r0 ] - and r1, r1, #0xf - - ldr r0, =0x560000BC /* gstatus4 */ - str r1, [ r0 ] - - ldr r0, =0x560000A8 /* EINTPEND */ - ldr r1, [ r0 ] - ldr r0, =0xfff0 - and r1, r1, r0 - ldr r0, =0x560000BC /* gstatus4 */ - ldr r0, [ r0 ] - orr r1, r1, r0 - ldr r0, =0x560000BC /* gstatus4 */ - str r1, [ r0 ] - - /* test for resume */ - - ldr r1, =0x560000B4 /* gstatus2 */ - ldr r0, [ r1 ] - tst r0, #0x02 /* is this resume from power down */ - /* well, if it was, we are going to jump to - * whatever address we stashed in gstatus3, - * and gstatus4 will hold the wake interrupt - * source for the OS to look at - */ - ldrne pc, [r1, #4] - - - /* >> CFG_VIDEO_LOGO_MAX_SIZE */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l: - str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - -/* we are going to jump into the C part of the init now */ -spin: - b _steppingstone_done - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -cpu_init_crit: - - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - - bl lowlevel_init - - mov lr, ip - mov pc, lr - diff --git a/qiboot/src/utils-phase2.c b/qiboot/src/utils-phase2.c deleted file mode 100644 index bbbd672..0000000 --- a/qiboot/src/utils-phase2.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2008 Openmoko, Inc. - * Author: Andy Green - * - * Little utils for print and strings - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -extern void (*putc_func)(char); - -/* - * malloc pool needs to be in phase 2 bss section, we have phase 1 bss in - * steppingstone to allow full memory range testing in C - */ -u8 malloc_pool[MALLOC_POOL_EXTENT]; -void * malloc_pointer = &malloc_pool[0]; - - -/* improbably simple malloc and free for small and non-intense allocation - * just moves the allocation ptr forward each time and ignores free - */ - -void *malloc(size_t size) -{ - void *p = malloc_pointer; - - malloc_pointer += (size & ~3) + 4; - - if (((u8 *)malloc_pointer - &malloc_pool[0]) > sizeof(malloc_pool)) { - puts("Ran out of malloc pool\n"); - while (1) - ; - } - - return p; -} - -void free(void *ptr) -{ -} - -char *strncpy(char *dest, const char *src, size_t n) -{ - char * dest_orig = dest; - - while (*src && n--) - *dest++ = *src++; - - if (n) - *dest = '\0'; - - return dest_orig; -} - - -int strcmp(const char *s1, const char *s2) -{ - while (1) { - if (*s1 != *s2) - return *s1 - *s2; - if (!*s1) - return 0; - s1++; - s2++; - } -} - -char *strchr(const char *s, int c) -{ - while ((*s) && (*s != c)) - s++; - - if (*s == c) - return (char *)s; - - return NULL; -} - -void hexdump(unsigned char *start, int len) -{ - int n; - - while (len > 0) { - print32((int)start); - (putc_func)(':'); - (putc_func)(' '); - for (n = 0; n < 16; n++) { - print8(*start++); - (putc_func)(' '); - } - (putc_func)('\n'); - len -= 16; - } -} - -void setnybble(char *p, unsigned char n) -{ - if (n < 10) - *p = '0' + n; - else - *p = 'a' + n - 10; -} - -void set8(char *p, unsigned char n) -{ - setnybble(p, (n >> 4) & 15); - setnybble(p + 1, n & 15); -} - -void set32(char *p, unsigned int u) -{ - set8(p, u >> 24); - set8(p + 2, u >> 16); - set8(p + 4, u >> 8); - set8(p + 6, u); -} - diff --git a/qiboot/src/utils.c b/qiboot/src/utils.c deleted file mode 100644 index 82f3e4a..0000000 --- a/qiboot/src/utils.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2008 Openmoko, Inc. - * Author: Andy Green - * - * Little utils for print and strings - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void (*putc_func)(char) = NULL; - - -void set_putc_func(void (*p)(char)) -{ - putc_func = p; -} - -size_t strlen(const char *s) -{ - size_t n = 0; - - while (*s++) - n++; - - return n; -} - -char *strcpy(char *dest, const char *src) -{ - char * dest_orig = dest; - - while (*src) - *dest++ = *src++; - *dest = '\0'; - - return dest_orig; -} - -int puts(const char *string) -{ - while (*string) - (putc_func)(*string++); - - return 1; -} - -/* done like this to avoid needing statics in steppingstone */ -void printnybble(unsigned char n) -{ - if (n < 10) - (putc_func)('0' + n); - else - (putc_func)('a' + n - 10); -} - -void print8(unsigned char n) -{ - printnybble((n >> 4) & 15); - printnybble(n & 15); -} - -void print32(unsigned int u) -{ - print8(u >> 24); - print8(u >> 16); - print8(u >> 8); - print8(u); -} - -void printdec(int n) -{ - int d[] = { - 1 * 1000 * 1000 * 1000, - 100 * 1000 * 1000, - 10 * 1000 * 1000, - 1 * 1000 * 1000, - 100 * 1000, - 10 * 1000, - 1 * 1000, - 100, - 10, - 1, - 0 - }; - int flag = 0; - int div = 0; - - if (n < 0) { - (putc_func)('-'); - n = -n; - } - - while (d[div]) { - int r = 0; - while (n >= d[div]) { - r++; - n -= d[div]; - } - if (r || flag || (d[div] == 1)) { - (putc_func)('0' + r); - flag = 1; - } - div++; - } -} - -void *memcpy(void *dest, const void *src, size_t n) -{ - u8 const * ps = src; - u8 * pd = dest; - - while (n--) - *pd++ = *ps++; - - return dest; -} - -void *memset(void *s, int c, size_t n) -{ - u8 * p = s; - - while (n--) - *p++ = c; - - return s; -} - -int q; - -void udelay(int n) -{ - while (n--) - q+=n * q; -} diff --git a/qiboot/tools/Makefile b/qiboot/tools/Makefile deleted file mode 100644 index e2a5409..0000000 --- a/qiboot/tools/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -#(C) Copyright 2007 OpenMoko, Inc. -# Author: xiangfu liu -# -# Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -include ../config.mk - -CC = ${HOSTCC} -CFLAGS = -Wall -C_SRCS = $(wildcard *.c) -C_OBJS = $(patsubst %.c,%.o, $(C_SRCS)) -SRCS = ${C_SRCS} -OBJS = ${C_OBJS} -TARGET = mkudfu - -%.o: %.c - CC $(CFLAGS) -o $@ $< - -all:${TARGET} - -${TARGET}:${SRCS} - -clean: - @rm -f *.o *~ ${TARGET} diff --git a/qiboot/tools/mkudfu.c b/qiboot/tools/mkudfu.c deleted file mode 100644 index 57ac294..0000000 --- a/qiboot/tools/mkudfu.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * USB DFU file trailer tool - * (C) Copyright by OpenMoko, Inc. - * Author: Harald Welte - * - * based on mkimage.c, copyright information as follows: - * - * (C) Copyright 2000-2004 - * DENX Software Engineering - * Wolfgang Denk, wd@denx.de - * All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#ifndef __WIN32__ -#include /* for host / network byte order conversions */ -#endif -#include -#include -#include -#include - -#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__) -#include -#endif - -#ifdef __WIN32__ -typedef unsigned int __u32; - -#define SWAP_LONG(x) \ - ((__u32)( \ - (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ - (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ - (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ - (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; - -#define ntohl(a) SWAP_LONG(a) -#define htonl(a) SWAP_LONG(a) -#endif /* __WIN32__ */ - -#ifndef O_BINARY /* should be define'd on __WIN32__ */ -#define O_BINARY 0 -#endif - -#include "usb_dfu_trailer.h" - -extern int errno; - -#ifndef MAP_FAILED -#define MAP_FAILED (-1) -#endif - -static char *cmdname; - -static char *datafile; -static char *imagefile; - - -static void usage() -{ - fprintf (stderr, "%s - create / display u-boot DFU trailer\n", cmdname); - fprintf (stderr, "Usage: %s -l image\n" - " -l ==> list image header information\n" - " %s -v VID -p PID -r REV -d data_file image\n", - cmdname, cmdname); - fprintf (stderr, " -v ==> set vendor ID to 'VID'\n" - " -p ==> set product ID system to 'PID'\n" - " -r ==> set hardware revision to 'REV'\n" - " -d ==> use 'data_file' as input file\n" - ); - exit (EXIT_FAILURE); -} - -static void print_trailer(struct uboot_dfu_trailer *trailer) -{ - printf("===> DFU Trailer information:\n"); - printf("Trailer Vers.: %d\n", trailer->version); - printf("Trailer Length: %d\n", trailer->length); - printf("VendorID: 0x%04x\n", trailer->vendor); - printf("ProductID: 0x%04x\n", trailer->product); - printf("HW Revision: 0x%04x\n", trailer->revision); -} - -static void copy_file (int ifd, const char *datafile, int pad) -{ - int dfd; - struct stat sbuf; - unsigned char *ptr; - int tail; - int zero = 0; - int offset = 0; - int size; - - if ((dfd = open(datafile, O_RDONLY|O_BINARY)) < 0) { - fprintf (stderr, "%s: Can't open %s: %s\n", - cmdname, datafile, strerror(errno)); - exit (EXIT_FAILURE); - } - - if (fstat(dfd, &sbuf) < 0) { - fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, datafile, strerror(errno)); - exit (EXIT_FAILURE); - } - - ptr = (unsigned char *)mmap(0, sbuf.st_size, - PROT_READ, MAP_SHARED, dfd, 0); - if (ptr == (unsigned char *)MAP_FAILED) { - fprintf (stderr, "%s: Can't read %s: %s\n", - cmdname, datafile, strerror(errno)); - exit (EXIT_FAILURE); - } - - size = sbuf.st_size - offset; - if (write(ifd, ptr + offset, size) != size) { - fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - if (pad && ((tail = size % 4) != 0)) { - - if (write(ifd, (char *)&zero, 4-tail) != 4-tail) { - fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - } - - (void) munmap((void *)ptr, sbuf.st_size); - (void) close (dfd); -} - - -int main(int argc, char **argv) -{ - int ifd; - int lflag = 0; - struct stat sbuf; - u_int16_t opt_vendor, opt_product, opt_revision; - struct uboot_dfu_trailer _hdr, _mirror, *hdr = &_hdr; - - opt_vendor = opt_product = opt_revision = 0; - - cmdname = *argv; - - while (--argc > 0 && **++argv == '-') { - while (*++*argv) { - switch (**argv) { - case 'l': - lflag = 1; - break; - case 'v': - if (--argc <= 0) - usage (); - opt_vendor = strtoul(*++argv, NULL, 16); - goto NXTARG; - case 'p': - if (--argc <= 0) - usage (); - opt_product = strtoul(*++argv, NULL, 16); - goto NXTARG; - case 'r': - if (--argc <= 0) - usage (); - opt_revision = strtoul(*++argv, NULL, 16); - goto NXTARG; - case 'd': - if (--argc <= 0) - usage (); - datafile = *++argv; - goto NXTARG; - case 'h': - usage(); - break; - default: - usage(); - } - } -NXTARG: ; - } - - if (argc != 1) - usage(); - - imagefile = *argv; - - if (lflag) - ifd = open(imagefile, O_RDONLY|O_BINARY); - else - ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666); - - if (ifd < 0) { - fprintf (stderr, "%s: Can't open %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - if (lflag) { - unsigned char *ptr; - /* list header information of existing image */ - if (fstat(ifd, &sbuf) < 0) { - fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - if ((unsigned)sbuf.st_size < sizeof(struct uboot_dfu_trailer)) { - fprintf (stderr, - "%s: Bad size: \"%s\" is no valid image\n", - cmdname, imagefile); - exit (EXIT_FAILURE); - } - - ptr = (unsigned char *)mmap(0, sbuf.st_size, - PROT_READ, MAP_SHARED, ifd, 0); - if ((caddr_t)ptr == (caddr_t)-1) { - fprintf (stderr, "%s: Can't read %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - dfu_trailer_mirror(hdr, ptr+sbuf.st_size); - - if (hdr->magic != UBOOT_DFU_TRAILER_MAGIC) { - fprintf (stderr, - "%s: Bad Magic Number: \"%s\" is no valid image\n", - cmdname, imagefile); - exit (EXIT_FAILURE); - } - - /* for multi-file images we need the data part, too */ - print_trailer(hdr); - - (void) munmap((void *)ptr, sbuf.st_size); - (void) close (ifd); - - exit (EXIT_SUCCESS); - } - - /* if we're not listing: */ - - copy_file (ifd, datafile, 0); - - memset (hdr, 0, sizeof(struct uboot_dfu_trailer)); - - /* Build new header */ - hdr->version = UBOOT_DFU_TRAILER_V1; - hdr->magic = UBOOT_DFU_TRAILER_MAGIC; - hdr->length = sizeof(struct uboot_dfu_trailer); - hdr->vendor = opt_vendor; - hdr->product = opt_product; - hdr->revision = opt_revision; - - print_trailer(hdr); - dfu_trailer_mirror(&_mirror, (unsigned char *)hdr+sizeof(*hdr)); - - if (write(ifd, &_mirror, sizeof(struct uboot_dfu_trailer)) - != sizeof(struct uboot_dfu_trailer)) { - fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - /* We're a bit of paranoid */ -#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) - (void) fdatasync (ifd); -#else - (void) fsync (ifd); -#endif - - if (fstat(ifd, &sbuf) < 0) { - fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - /* We're a bit of paranoid */ -#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) - (void) fdatasync (ifd); -#else - (void) fsync (ifd); -#endif - - if (close(ifd)) { - fprintf (stderr, "%s: Write error on %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - exit (EXIT_SUCCESS); -} diff --git a/qiboot/tools/usb_dfu_trailer.h b/qiboot/tools/usb_dfu_trailer.h deleted file mode 100644 index 3903b85..0000000 --- a/qiboot/tools/usb_dfu_trailer.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _USB_DFU_TRAILER_H -#define _USB_DFU_TRAILER_H - -/* trailer handling for DFU files */ - -#define UBOOT_DFU_TRAILER_V1 1 -#define UBOOT_DFU_TRAILER_MAGIC 0x19731978 -struct uboot_dfu_trailer { - u_int32_t magic; - u_int16_t version; - u_int16_t length; - u_int16_t vendor; - u_int16_t product; - u_int32_t revision; -} __attribute__((packed)); - -/* we mirror the trailer because we want it to be longer in later versions - * while keeping backwards compatibility */ -static inline void dfu_trailer_mirror(struct uboot_dfu_trailer *trailer, - unsigned char *eof) -{ - int i; - int len = sizeof(struct uboot_dfu_trailer); - unsigned char *src = eof - len; - unsigned char *dst = (unsigned char *) trailer; - - for (i = 0; i < len; i++) - dst[len-1-i] = src[i]; -} - -#endif /* _USB_DFU_TRAILER_H */