From 82d2e255c33ec8bfcf5aa2aa6eb56edd58c7324b Mon Sep 17 00:00:00 2001 From: Andy Green Date: Fri, 28 Nov 2008 10:16:40 +0000 Subject: [PATCH] qi-add-sc36410-mci.patch This heavily adapts the Samsung U-Boot hs_mmc code and combines it with the SD / SDHC startup code written for glamo-mci stuff that is known to work OK with common SD and SDHC. tla01 is changed to use the implementation. Signed-off-by: Andy Green --- qiboot/Makefile | 2 - qiboot/include/linux-mmc-protocol.h | 382 ++++++++++++++++ qiboot/include/linux-mmc.h | 120 +++++ qiboot/include/s3c6410.h | 64 ++- qiboot/src/cpu/s3c2442/start_qi.c | 20 + qiboot/src/cpu/s3c6410/hs_mmc.c | 683 ++++++++++++++++++++++++++++ qiboot/src/cpu/s3c6410/hs_mmc.h | 40 ++ qiboot/src/cpu/s3c6410/qi.lds | 37 +- qiboot/src/cpu/s3c6410/start_qi.c | 70 ++- qiboot/src/cpu/s3c6410/tla01.c | 41 +- qiboot/src/phase2.c | 36 +- 11 files changed, 1416 insertions(+), 79 deletions(-) create mode 100644 qiboot/include/linux-mmc-protocol.h create mode 100644 qiboot/include/linux-mmc.h create mode 100644 qiboot/src/cpu/s3c6410/hs_mmc.c create mode 100644 qiboot/src/cpu/s3c6410/hs_mmc.h diff --git a/qiboot/Makefile b/qiboot/Makefile index cd4f3e3..374d83e 100644 --- a/qiboot/Makefile +++ b/qiboot/Makefile @@ -44,8 +44,6 @@ SRCS = ${S_SRCS} ${C_SRCS} OBJS = ${S_OBJS} ${C_OBJS} LIBS = -L${COMPILER_LIB_PATH} -lgcc -OBJS = src/cpu/s3c6410/start.o src/cpu/s3c6410/start_qi.o src/cpu/s3c6410/serial-s3c64xx.o src/ctype.o src/utils.o src/cpu/s3c6410/tla01.o src/phase2.o - # GTA02 A5 and A6 U-Boot will eat these for DFU action UDFU_VID = 0x1d50 UDFU_PID = 0x5119 diff --git a/qiboot/include/linux-mmc-protocol.h b/qiboot/include/linux-mmc-protocol.h new file mode 100644 index 0000000..2d90273 --- /dev/null +++ b/qiboot/include/linux-mmc-protocol.h @@ -0,0 +1,382 @@ +/* + * Header for MultiMediaCard (MMC) + * + * Copyright 2002 Hewlett-Packard Company + * + * Use consistent with the GNU GPL is permitted, + * provided that this copyright notice is + * preserved in its entirety in all copies and derived works. + * + * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Many thanks to Alessandro Rubini and Jonathan Corbet! + * + * Based strongly on code by: + * + * Author: Yong-iL Joh + * Date : $Date: 2006/12/06 02:50:52 $ + * + * Author: Andrew Christian + * 15 May 2002 + */ + +#ifndef MMC_MMC_PROTOCOL_H +#define MMC_MMC_PROTOCOL_H + +#ifdef CONFIG_SUPPORT_MMC_PLUS +/* Standard MMC commands (4.2) type argument response */ +#else +/* Standard MMC commands (3.1) type argument response */ +#endif + /* class 1 */ +#define MMC_GO_IDLE_STATE 0 /* bc */ +#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ +#define MMC_ALL_SEND_CID 2 /* bcr R2 */ +#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ +#define MMC_SET_DSR 4 /* bc [31:16] RCA */ +#define MMC_SWITCH 6 /* ac R1b */ +#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ +#define MMC_SEND_EXT_CSD 8 /* adtc R1 */ +#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ +#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ +#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ +#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ +#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ +#define MMC_BUSTEST_R 14 /* adtc R1 */ +#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ +#define MMC_BUSTEST_W 19 /* adtc R1 */ + + /* class 2 */ +#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ +#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ +#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ + + /* class 3 */ +#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ + + /* class 4 */ +#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ +#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ +#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ +#define MMC_PROGRAM_CID 26 /* adtc R1 */ +#define MMC_PROGRAM_CSD 27 /* adtc R1 */ + + /* class 6 */ +#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ +#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ +#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ + + /* class 5 */ +#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ +#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ +#define MMC_ERASE 38 /* ac R1b */ + + /* class 9 */ +#define MMC_FAST_IO 39 /* ac R4 */ +#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ + + /* class 7 */ +#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ + + /* class 8 */ +#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ +#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ + +/* SD commands type argument response */ + /* class 8 */ +/* This is basically the same command as for MMC with some quirks. */ +#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */ + + /* Application commands */ +#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ +#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ +#define SD_APP_SEND_SCR 51 /* adtc R1 */ + +/* + MMC status in R1 + Type + e : error bit + s : status bit + r : detected and set for the actual command response + x : detected and set during command execution. the host must poll + the card by sending status command in order to read these bits. + Clear condition + a : according to the card state + b : always related to the previous command. Reception of + a valid command will clear it (with a delay of one command) + c : clear by read + */ + +#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ +#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ +#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ +#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ +#define R1_ERASE_PARAM (1 << 27) /* ex, c */ +#define R1_WP_VIOLATION (1 << 26) /* erx, c */ +#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ +#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ +#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ +#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ +#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ +#define R1_CC_ERROR (1 << 20) /* erx, c */ +#define R1_ERROR (1 << 19) /* erx, c */ +#define R1_UNDERRUN (1 << 18) /* ex, c */ +#define R1_OVERRUN (1 << 17) /* ex, c */ +#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ +#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ +#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ +#define R1_ERASE_RESET (1 << 13) /* sr, c */ +#define R1_STATUS(x) (x & 0xFFFFE000) +#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ +#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ +#define R1_APP_CMD (1 << 5) /* sr, c */ + +/* + MMC CURRENT_STATE in R1 [12:9] + */ +#define STATE_IDLE (0x0 << 9) /* 0 */ +#define STATE_READY (0x1 << 9) /* 1 */ +#define STATE_IDENT (0x2 << 9) /* 2 */ +#define STATE_STBY (0x3 << 9) /* 3 */ +#define STATE_TRAN (0x4 << 9) /* 4 */ +#define STATE_DATA (0x5 << 9) /* 5 */ +#define STATE_RCV (0x6 << 9) /* 6 */ +#define STATE_PRG (0x7 << 9) /* 7 */ +#define STATE_DIS (0x8 << 9) /* 8 */ +#define STATE_BTST (0x9 << 9) /* 9 */ + +/* These are unpacked versions of the actual responses */ + +struct _mmc_csd { + u8 csd_structure; + u8 spec_vers; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc; + u8 read_bl_len; + u8 read_bl_partial; + u8 write_blk_misalign; + u8 read_blk_misalign; + u8 dsr_imp; + u16 c_size; + u8 vdd_r_curr_min; + u8 vdd_r_curr_max; + u8 vdd_w_curr_min; + u8 vdd_w_curr_max; + u8 c_size_mult; + union { + struct { /* MMC system specification version 3.1 */ + u8 erase_grp_size; + u8 erase_grp_mult; + } v31; + struct { /* MMC system specification version 2.2 */ + u8 sector_size; + u8 erase_grp_size; + } v22; + } erase; + u8 wp_grp_size; + u8 wp_grp_enable; + u8 default_ecc; + u8 r2w_factor; + u8 write_bl_len; + u8 write_bl_partial; + u8 file_format_grp; + u8 copy; + u8 perm_write_protect; + u8 tmp_write_protect; + u8 file_format; + u8 ecc; +}; + +struct _mmc_ext_csd { + u8 s_cmd_set; + u32 sec_count; + u8 MIN_PERF_W_8_52; + u8 MIN_PERF_R_8_52; + u8 MIN_PERF_W_8_26_4_52; + u8 MIN_PERF_R_8_26_4_52; + u8 MIN_PERF_W_4_26; + u8 MIN_PERF_R_4_26; + u8 PWR_CL_26_360; + u8 PWR_CL_52_360; + u8 PWR_CL_26_195; + u8 PWR_CL_52_195; + u8 card_type; + u8 csd_structure; + u8 ext_csd_rev; + u8 cmd_set; + u8 cmd_set_rev; + u8 power_class; + u8 hs_timing; + u8 bus_width; +}; + +#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */ +#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */ +#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */ +#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */ +#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */ +#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */ +#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */ +#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ +#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ + +/* + * Card Command Classes (CCC) + */ +#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ + /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ +#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ + /* (CMD11) */ +#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ + /* (CMD16,17,18) */ +#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ + /* (CMD20) */ +#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ + /* (CMD16,24,25,26,27) */ +#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ + /* (CMD32,33,34,35,36,37,38,39) */ +#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ + /* (CMD28,29,30) */ +#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ + /* (CMD16,CMD42) */ +#define CCC_APP_SPEC (1<<8) /* (8) Application specific */ + /* (CMD55,56,57,ACMD*) */ +#define CCC_IO_MODE (1<<9) /* (9) I/O mode */ + /* (CMD5,39,40,52,53) */ +#define CCC_SWITCH (1<<10) /* (10) High speed switch */ + /* (CMD6,34,35,36,37,50) */ + /* (11) Reserved */ + /* (CMD?) */ + +/* + * CSD field definitions + */ + +#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ +#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ +#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */ + +#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ +#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ +#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ +#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */ +#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 ~ 4.2 */ + +/* + * SD bus widths + */ +#define SD_BUS_WIDTH_1 0 +#define SD_BUS_WIDTH_4 2 + +/* + * EXT_CSD field definitions + */ + +/* + * S_CMD_SET + */ + +#define STANDARD_MMC 0 /* Standard MMC */ +#define SECURE_MMC 1 /* Secure MMC */ +#define CPS_MMC 2 /* Content Protection Secure MMC */ +#define SECURE_MMC_2 3 /* Secure MMC 2.0 */ +#define ATA_MMC 4 /* ATA on MMC */ + +/* + * MIN_PERF_a_b_ff + */ +#define NO_CLASS 0x0 /* For cards not reaching the 2.4MB/s minimum value */ +#define CLASS_A 0x08 /* Class A */ +#define CLASS_B 0x0A /* Class B */ +#define CLASS_C 0x0F /* Class C */ +#define CLASS_D 0x14 /* Class D */ +#define CLASS_E 0x1E /* Class E */ +#define CLASS_F 0x28 /* Class F */ +#define CLASS_G 0x32 /* Class G */ +#define CLASS_H 0x3c /* Class H */ +#define CLASS_J 0x46 /* Class J */ +#define CLASS_K 0x50 /* Class E */ +#define CLASS_M 0x64 /* Class M */ +#define CLASS_O 0x78 /* Class O */ +#define CLASS_R 0x8c /* Class R */ +#define CLASS_T 0xa0 /* Class T */ + +/* + * CARD_TYPE + */ + +#define MMCPLUS_26MHZ (1<<0) +#define MMCPLUS_52MHZ (1<<1) + +/* + * EXT_CSD_REV + */ + +#define EXT_CSD_REV_1_0 0 +#define EXT_CSD_REV_1_1 1 +#define EXT_CSD_REV_1_2 2 + +/* + * HS_TIMING + */ +#define HS_TIMING_LOW 0 +#define HS_TIMING_HIGH 1 + +/* + * BUS_WIDTH + */ +#define MMCPLUS_BUS_WIDTH_1 0 +#define MMCPLUS_BUS_WIDTH_4 1 +#define MMCPLUS_BUS_WIDTH_8 2 + + +/* + * ERASED_MEM_CONT + */ + +#define ERASED_MEM_CONT_0 0 +#define ERASED_MEM_CONT_1 1 + +/* + * Argument for CMD6 + */ + +/* + * EXT_CSD Access Modes + */ + +#define EXT_CSD_COMMAND_SET 0 +#define EXT_CSD_SET_BITS 1 +#define EXT_CSD_CLEAR_BITS 2 +#define EXT_CSD_WRITE_BYTE 3 + +/* + * EXT_CSD Argument Byte + */ + +#define EXT_CSD_POWER_CLASS 187 +#define EXT_CSD_BUS_WIDTH 183 +#define EXT_CSD_HS_TIMING 185 + +#endif /* MMC_MMC_PROTOCOL_H */ + diff --git a/qiboot/include/linux-mmc.h b/qiboot/include/linux-mmc.h new file mode 100644 index 0000000..2750a51 --- /dev/null +++ b/qiboot/include/linux-mmc.h @@ -0,0 +1,120 @@ +/* + * linux/include/linux/mmc/mmc.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef MMC_H +#define MMC_H + +/* removed by scsuh */ +#if 0 +#include +#include +#include + +struct request; +struct mmc_data; +struct mmc_request; +#endif + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ +#define MMC_CMD_MASK (3 << 5) /* command type */ +#define MMC_CMD_AC (0 << 5) +#define MMC_CMD_ADTC (1 << 5) +#define MMC_CMD_BC (2 << 5) +#define MMC_CMD_BCR (3 << 5) + +/* + * These are the response types, and correspond to valid bit + * patterns of the above flags. One additional valid pattern + * is all zeros, which means we don't expect a response. + */ +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC) + +#define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE)) + +/* + * These are the command types. + */ +#define mmc_cmd_type(cmd) ((cmd)->flags & MMC_CMD_MASK) + +#define MMC_ERR_NONE 0 +#define MMC_ERR_TIMEOUT 1 +#define MMC_ERR_BADCRC 2 +#define MMC_ERR_FIFO 3 +#define MMC_ERR_FAILED 4 +#define MMC_ERR_INVALID 5 + +struct mmc_command { + u32 opcode; + u32 arg; + u32 resp[4]; + unsigned int flags; /* expected response type */ + struct mmc_data *data; /* data segment associated with cmd */ + struct mmc_request *mrq; /* associated request */ + unsigned int retries; /* max number of retries */ + unsigned int error; /* command error */ + +}; + +struct mmc_data { + unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */ + unsigned int timeout_clks; /* data timeout (in clocks) */ + unsigned int blksz_bits; /* data block size */ + unsigned int blksz; /* data block size */ + unsigned int blocks; /* number of blocks */ + unsigned int error; /* data error */ + unsigned int flags; + +#define MMC_DATA_WRITE (1 << 8) +#define MMC_DATA_READ (1 << 9) +#define MMC_DATA_STREAM (1 << 10) +#define MMC_DATA_MULTI (1 << 11) + + unsigned int bytes_xfered; + + struct mmc_command *stop; /* stop command */ + struct mmc_request *mrq; /* associated request */ + + unsigned int sg_len; /* size of scatter list */ + struct scatterlist *sg; /* I/O scatter list */ +}; + +struct mmc_request { + struct mmc_command *cmd; + struct mmc_data *data; + struct mmc_command *stop; + + void *done_data; /* completion data */ + void (*done)(struct mmc_request *);/* completion function */ +}; + +struct mmc_host; +struct mmc_card; + +extern int mmc_wait_for_req(struct mmc_host *, struct mmc_request *); +extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int); +extern int mmc_wait_for_app_cmd(struct mmc_host *, unsigned int, + struct mmc_command *, int); + +extern int __mmc_claim_host(struct mmc_host *host, struct mmc_card *card); + +static inline void mmc_claim_host(struct mmc_host *host) +{ + __mmc_claim_host(host, (struct mmc_card *)-1); +} + +extern void mmc_release_host(struct mmc_host *host); + +#endif diff --git a/qiboot/include/s3c6410.h b/qiboot/include/s3c6410.h index 926c38d..960c493 100644 --- a/qiboot/include/s3c6410.h +++ b/qiboot/include/s3c6410.h @@ -36,9 +36,71 @@ #define S3C64XX_UART_CHANNELS 3 #define S3C64XX_SPI_CHANNELS 2 +#define HSMMC_CHANNEL 0 +#define MOVI_INIT_REQUIRED 0 +#define TCM_BASE 0x0C004000 +#define BL2_BASE 0x57E00000 +#define CopyMovitoMem(a,b,c,d,e) (((int(*)(int, uint, ushort, uint *, int))(*((uint *)(TCM_BASE + 0x8))))(a,b,c,d,e)) +#define SS_SIZE (8 * 1024) +#define eFUSE_SIZE (1 * 1024) // 0.5k eFuse, 0.5k reserved` +#define PART_UBOOT_OFFSET 0x0 +#define PART_ZIMAGE_OFFSET 0x40000 +#define PART_ROOTFS_OFFSET 0x200000 +#define PART_EXTRA_OFFSET 0x3200000 + +/* movinand definitions */ +#define MOVI_BLKSIZE 512 + +#define MOVI_TOTAL_BLKCNT 7864320 // 7864320 // 3995648 // 1003520 /* static movinand total block count: for writing to movinand when nand boot */ +#define MOVI_HIGH_CAPACITY 0 + +#define MOVI_LAST_BLKPOS (MOVI_TOTAL_BLKCNT - (eFUSE_SIZE / MOVI_BLKSIZE)) +#define MOVI_BL1_BLKCNT (SS_SIZE / MOVI_BLKSIZE) +#define MOVI_ENV_BLKCNT (CFG_ENV_SIZE / MOVI_BLKSIZE) +#define MOVI_BL2_BLKCNT (((PART_ZIMAGE_OFFSET - PART_UBOOT_OFFSET) / MOVI_BLKSIZE) - MOVI_ENV_BLKCNT) +#define MOVI_ZIMAGE_BLKCNT ((PART_ROOTFS_OFFSET - PART_ZIMAGE_OFFSET) / MOVI_BLKSIZE) +#define MOVI_BL2_POS (MOVI_LAST_BLKPOS - MOVI_BL1_BLKCNT - MOVI_BL2_BLKCNT - MOVI_ENV_BLKCNT) +#ifndef __ASSEMBLY__ + +struct movi_offset_t { + uint last; + uint bl1; + uint env; + uint bl2; + uint zimage; +}; + +/* external functions */ +extern void hsmmc_set_gpio(void); +extern void hsmmc_reset (void); +extern int hsmmc_init (void); +extern int movi_init(void); +extern void movi_set_capacity(void); +extern int movi_set_ofs(uint last); +extern void movi_write (uint addr, uint start_blk, uint blknum); +extern void movi_read (uint addr, uint start_blk, uint blknum); +extern void movi_write_env(ulong addr); +extern void movi_read_env(ulong addr); + +#if defined(CONFIG_S3C2450) +extern ulong virt_to_phy_smdk2450(ulong addr); +#elif defined(CONFIG_S3C6400) +extern ulong virt_to_phy_smdk6400(ulong addr); +#elif defined(CONFIG_S3C6410) +extern ulong virt_to_phy_smdk6410(ulong addr); +#elif defined(CONFIG_S3C6430) +extern ulong virt_to_phy_smdk6430(ulong addr); +#elif defined(CONFIG_S3C2416) +extern ulong virt_to_phy_smdk2416(ulong addr); +#endif + +extern void test_hsmmc (uint width, uint test, uint start_blk, uint blknum); + +/* external variables */ +extern struct movi_offset_t ofsinfo; + //#include -#ifndef __ASSEMBLY__ typedef enum { S3C64XX_UART0, S3C64XX_UART1, diff --git a/qiboot/src/cpu/s3c2442/start_qi.c b/qiboot/src/cpu/s3c2442/start_qi.c index ff479b6..cfb5c61 100644 --- a/qiboot/src/cpu/s3c2442/start_qi.c +++ b/qiboot/src/cpu/s3c2442/start_qi.c @@ -29,6 +29,10 @@ #include #include +#define stringify2(s) stringify1(s) +#define stringify1(s) #s + + extern void bootloader_second_phase(void); const struct board_api *boards[] = { @@ -94,6 +98,22 @@ void start_qi(void) this_board = boards[board++]; } + this_board->port_init(); + + /* stick some hello messages on debug console */ + + puts("\n\n\nQi Bootloader "stringify2(QI_CPU)" " + stringify2(BUILD_HOST)" " + stringify2(BUILD_VERSION)" " + "\n"); + + puts(stringify2(BUILD_DATE) " Copyright (C) 2008 Openmoko, Inc.\n"); + puts("\n Detected: "); + + puts(this_board->name); + puts(", "); + puts((this_board->get_board_variant)()->name); + /* * jump to bootloader_second_phase() running from DRAM copy */ diff --git a/qiboot/src/cpu/s3c6410/hs_mmc.c b/qiboot/src/cpu/s3c6410/hs_mmc.c new file mode 100644 index 0000000..def5046 --- /dev/null +++ b/qiboot/src/cpu/s3c6410/hs_mmc.c @@ -0,0 +1,683 @@ +#include +#include "hs_mmc.h" +#include +#include + +#define HCLK_OPERATION +#undef DEBUG_HSMMC +#ifdef DEBUG_HSMMC +#define dbg(x...) printf(x) +#else +#define dbg(x...) do { } while (0) +#endif + +//#include +#include +#include +//#include +//#include +//#include + +#include "hs_mmc.h" +#include + +#define SDI_Tx_buffer_HSMMC (0x51000000) +#define SDI_Rx_buffer_HSMMC (0x51000000+(0x300000)) +#define SDI_Compare_buffer_HSMMC (0x51000000+(0x600000)) + +#define Card_OneBlockSize_ver1 512 + +#define MMC_DEFAULT_RCA (1<<16) + +/* Global variables */ + +static u32 rd_cnt_HSMMC; +//static u32 wt_cnt_HSMMC; +static u32 BlockNum_HSMMC = 0; + +//static u32 WriteBlockCnt_INT = 0; +static u32 ReadBlockCnt_INT = 0; +//static u32 WRITEINT_DONE = 0; +//static u32 READINT_DONE = 0; +//static u32 COMPARE_INT_DONE = 0; +//static u32 CompareCnt_INT = 0; +//static u32 BufferBoundary_INT_Cnt = 0; + +static u32 HS_DMA_END = 0; +//static u32 HS_CARD_DETECT = 0; + +//static u32 ocr_check = 0; +//static u32 mmc_card = 0; +static u32 rca = 0; + +static ulong HCLK; +//static u32 card_mid = 0; + +int movi_hc = 1; /* sdhc style block indexing */ +enum card_type card_type; + +/* extern functions */ +extern ulong get_HCLK(void); + + +#define s3c_hsmmc_readl(x) *((unsigned int *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) +#define s3c_hsmmc_readw(x) *((unsigned short *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) +#define s3c_hsmmc_readb(x) *((unsigned char *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) + +#define s3c_hsmmc_writel(v,x) *((unsigned int *) (((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) = v +#define s3c_hsmmc_writew(v,x) *((unsigned short *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) = v +#define s3c_hsmmc_writeb(v,x) *((unsigned char *)(((ELFIN_HSMMC_BASE + (HSMMC_CHANNEL * 0x100000)) + (x)))) = v + +#define readl(x) *((unsigned int *)(x)) +#define writel(v, x) *((unsigned int *)(x)) = v + +#define UNSTUFF_BITS(resp,start,size) \ + ({ \ + const int __size = size; \ + const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ + const int __off = 3 - ((start) / 32); \ + const int __shft = (start) & 31; \ + u32 __res; \ + \ + __res = resp[__off] >> __shft; \ + if (__size + __shft > 32) \ + __res |= resp[__off-1] << ((32 - __shft) & 31); \ + __res & __mask; \ + }) + +static int wait_for_cmd_done (void) +{ + u32 i; + ushort n_int, e_int; + + dbg("wait_for_cmd_done\n"); + for (i = 0; i < 0x20000000; i++) { + n_int = s3c_hsmmc_readw(HM_NORINTSTS); + dbg(" HM_NORINTSTS: %04x\n", n_int); + if (n_int & 0x8000) + /* any error */ + break; + if (n_int & 0x0001) + /* command complete */ + return 0; + } + + e_int = s3c_hsmmc_readw(HM_ERRINTSTS); + s3c_hsmmc_writew(e_int, HM_ERRINTSTS); + s3c_hsmmc_writew(n_int, HM_NORINTSTS); + puts("cmd error1: 0x"); + print32(e_int); + puts(", HM_NORINTSTS: 0x"); + print32(n_int); + puts("\n"); + + return -1; +} + + +static void ClearCommandCompleteStatus(void) +{ + s3c_hsmmc_writew(1 << 0, HM_NORINTSTS); + while (s3c_hsmmc_readw(HM_NORINTSTS) & 0x1) { + s3c_hsmmc_writew(1 << 0, HM_NORINTSTS); + } +} + +static void card_irq_enable(ushort temp) +{ + s3c_hsmmc_writew((s3c_hsmmc_readw(HM_NORINTSTSEN) & 0xFEFF) | (temp << 8), HM_NORINTSTSEN); +} + +void hsmmc_reset (void) +{ + s3c_hsmmc_writeb(0x3, HM_SWRST); +} + +void hsmmc_set_gpio (void) +{ + u32 reg; + + reg = readl(GPGCON) & 0xf0000000; + writel(reg | 0x02222222, GPGCON); + + reg = readl(GPGPUD) & 0xfffff000; + writel(reg, GPGPUD); +} + +static void set_transfer_mode_register (u32 MultiBlk, u32 DataDirection, u32 AutoCmd12En, u32 BlockCntEn, u32 DmaEn) +{ + s3c_hsmmc_writew((s3c_hsmmc_readw(HM_TRNMOD) & ~(0xffff)) | (MultiBlk << 5) + | (DataDirection << 4) | (AutoCmd12En << 2) + | (BlockCntEn << 1) | (DmaEn << 0), HM_TRNMOD); +// dbg("\nHM_TRNMOD = 0x%04x\n", HM_TRNMOD); +} + +static void set_arg_register (u32 arg) +{ + s3c_hsmmc_writel(arg, HM_ARGUMENT); +} + +static void set_blkcnt_register(ushort uBlkCnt) +{ + s3c_hsmmc_writew(uBlkCnt, HM_BLKCNT); +} + +static void SetSystemAddressReg(u32 SysAddr) +{ + s3c_hsmmc_writel(SysAddr, HM_SYSAD); +} + +static void set_blksize_register(ushort uDmaBufBoundary, ushort uBlkSize) +{ + s3c_hsmmc_writew((uDmaBufBoundary << 12) | (uBlkSize), HM_BLKSIZE); +} + +static void ClearErrInterruptStatus(void) +{ + while (s3c_hsmmc_readw(HM_NORINTSTS) & (0x1 << 15)) { + s3c_hsmmc_writew(s3c_hsmmc_readw(HM_NORINTSTS), HM_NORINTSTS); + s3c_hsmmc_writew(s3c_hsmmc_readw(HM_ERRINTSTS), HM_ERRINTSTS); + } +} + +static void InterruptEnable(ushort NormalIntEn, ushort ErrorIntEn) +{ + ClearErrInterruptStatus(); + s3c_hsmmc_writew(NormalIntEn, HM_NORINTSTSEN); + s3c_hsmmc_writew(ErrorIntEn, HM_ERRINTSTSEN); +} + +static void hsmmc_clock_onoff (int on) +{ + u16 reg16; + + if (on == 0) { + reg16 = s3c_hsmmc_readw(HM_CLKCON) & ~(0x1<<2); + s3c_hsmmc_writew(reg16, HM_CLKCON); + } else { + reg16 = s3c_hsmmc_readw(HM_CLKCON); + s3c_hsmmc_writew(reg16 | (0x1<<2), HM_CLKCON); + + while (1) { + reg16 = s3c_hsmmc_readw(HM_CLKCON); + if (reg16 & (0x1<<3)) /* SD_CLKSRC is Stable */ + break; + } + } +} + +static void set_clock (u32 clksrc, u32 div) +{ + u16 reg16; + u32 i; + + s3c_hsmmc_writel(0xC0004100 | (clksrc << 4), HM_CONTROL2); // rx feedback control + s3c_hsmmc_writel(0x00008080, HM_CONTROL3); // Low clock: 00008080 + s3c_hsmmc_writel(0x3 << 16, HM_CONTROL4); + + s3c_hsmmc_writew(s3c_hsmmc_readw(HM_CLKCON) & ~(0xff << 8), HM_CLKCON); + + /* SDCLK Value Setting + Internal Clock Enable */ + s3c_hsmmc_writew(((div<<8) | 0x1), HM_CLKCON); + + /* CheckInternalClockStable */ + for (i = 0; i < 0x10000; i++) { + reg16 = s3c_hsmmc_readw(HM_CLKCON); + if (reg16 & 0x2) + break; + } + if (i == 0x10000) + puts("internal clock stabilization failed\n"); + + hsmmc_clock_onoff(1); +} + +static void set_cmd_register (ushort cmd, u32 data, u32 flags) +{ + ushort val = (cmd << 8); + + if (cmd == 12) + val |= (3 << 6); + + if (flags & MMC_RSP_136) /* Long RSP */ + val |= 0x01; + else if (flags & MMC_RSP_BUSY) /* R1B */ + val |= 0x03; + else if (flags & MMC_RSP_PRESENT) /* Normal RSP */ + val |= 0x02; + + if (flags & MMC_RSP_OPCODE) + val |= (1<<4); + + if (flags & MMC_RSP_CRC) + val |= (1<<3); + + if (data) + val |= (1<<5); + +// puts("cmdreg = 0x"); +// print32(val); +// puts("\n"); + s3c_hsmmc_writew(val, HM_CMDREG); +} + +static int issue_command (ushort cmd, u32 arg, u32 data, u32 flags) +{ + int i; + +/* puts("### issue_command: "); + printdec(cmd); + puts(" 0x"); + print32(arg); + puts(" "); + printdec(data); + puts(" 0x"); + print32(flags); + puts("\n"); +*/ + /* Check CommandInhibit_CMD */ + for (i = 0; i < 0x1000000; i++) { + if (!(s3c_hsmmc_readl(HM_PRNSTS) & 0x1)) + break; + } + if (i == 0x1000000) { + puts("@@@@@@1 rHM_PRNSTS: "); + printdec(s3c_hsmmc_readl(HM_PRNSTS)); + puts("\n"); + } + + /* Check CommandInhibit_DAT */ + if (flags & MMC_RSP_BUSY) { + for (i = 0; i < 0x1000000; i++) { + if (!(s3c_hsmmc_readl(HM_PRNSTS) & 0x2)) + break; + } + if (i == 0x1000000) { + puts("@@@@@@2 rHM_PRNSTS: "); + print32(s3c_hsmmc_readl(HM_PRNSTS)); + puts("\n"); + } + } + + s3c_hsmmc_writel(arg, HM_ARGUMENT); + + set_cmd_register(cmd, data, flags); + + if (wait_for_cmd_done()) + return 0; + + ClearCommandCompleteStatus(); + + if (!(s3c_hsmmc_readw(HM_NORINTSTS) & 0x8000)) + return 1; + + puts("Command = "); + printdec((s3c_hsmmc_readw(HM_CMDREG) >> 8)); + puts(", Error Stat = 0x"); + print32(s3c_hsmmc_readw(HM_ERRINTSTS)); + return 0; +} + +static int check_card_status(void) +{ + if (!issue_command(MMC_SEND_STATUS, rca<<16, 0, MMC_RSP_R1)) + return 0; + + if (((s3c_hsmmc_readl(HM_RSPREG0) >> 9) & 0xf) == 4) { +// puts("Card is transfer status\n"); + return 1; + } + + return 1; +} + +static void set_hostctl_speed (u8 mode) +{ + u8 reg8; + + reg8 = s3c_hsmmc_readb(HM_HOSTCTL) & ~(0x1<<2); + s3c_hsmmc_writeb(reg8 | (mode<<2), HM_HOSTCTL); +} + +/* return 0: OK + * return -1: error + */ +static int set_bus_width (u32 width) +{ + u8 reg = s3c_hsmmc_readb(HM_HOSTCTL); + u8 bitmode = 0; + + card_irq_enable(0); // Disable sd card interrupt + + + if (!issue_command(MMC_APP_CMD, rca<<16, 0, MMC_RSP_R1)) + return -1; + else { + if (width == 1) { // 1-bits + bitmode = 0; + if (!issue_command(MMC_SWITCH, 0, 0, MMC_RSP_R1B)) + return -1; + } else { // 4-bits + bitmode = 1; + if (!issue_command(MMC_SWITCH, 2, 0, MMC_RSP_R1B)) + return -1; + } + } + + if (bitmode == 2) + reg |= 1 << 5; + else + reg |= bitmode << 1; + + s3c_hsmmc_writeb(reg, HM_HOSTCTL); + card_irq_enable(1); +// puts(" transfer rHM_HOSTCTL(0x28) = 0x"); +// print32(s3c_hsmmc_readb(HM_HOSTCTL)); + + return 0; +} + +static void clock_config (u32 Divisior) +{ + if (100000000 / (Divisior * 2) > 25000000) // Higher than 25MHz, it is necessary to enable high speed mode of the host controller. + set_hostctl_speed(HIGH); + else + set_hostctl_speed(NORMAL); + + hsmmc_clock_onoff(0); // when change the sd clock frequency, need to stop sd clock. + set_clock(SD_EPLL, Divisior); +} + +static void check_dma_int (void) +{ + u32 i; + + for (i = 0; i < 0x1000000; i++) { + if (s3c_hsmmc_readw(HM_NORINTSTS) & 0x0002) { + HS_DMA_END = 1; + s3c_hsmmc_writew(s3c_hsmmc_readw(HM_NORINTSTS) | 0x0002, HM_NORINTSTS); + break; + } + if (s3c_hsmmc_readw(HM_NORINTSTS) & 0x8000) { + puts("error found: "); + print32(s3c_hsmmc_readw(HM_ERRINTSTS)); + break; + } + } +} + + +static void print_sd_cid(const struct sd_cid *cid) +{ + puts(" Card Type: "); + switch (card_type) { + case CARDTYPE_NONE: + puts("(None) / "); + break; + case CARDTYPE_MMC: + puts("MMC / "); + break; + case CARDTYPE_SD: + puts("SD / "); + break; + case CARDTYPE_SD20: + puts("SD 2.0 / "); + break; + case CARDTYPE_SDHC: + puts("SD 2.0 SDHC / "); + break; + } + + puts("Mfr: 0x"); + print8(cid->mid); + puts(", OEM \""); + this_board->putc(cid->oid_0); + this_board->putc(cid->oid_1); + puts("\" / "); + + this_board->putc(cid->pnm_0); + this_board->putc(cid->pnm_1); + this_board->putc(cid->pnm_2); + this_board->putc(cid->pnm_3); + this_board->putc(cid->pnm_4); + puts("\", rev "); + printdec(cid->prv >> 4); + puts("."); + printdec(cid->prv & 15); + puts(" / s/n: "); + print32(cid->psn_0 << 24 | cid->psn_1 << 16 | cid->psn_2 << 8 | + cid->psn_3); + puts(" / date: "); + printdec(cid->mdt_1 & 15); + puts("/"); + printdec(2000 + ((cid->mdt_0 & 15) << 4)+((cid->mdt_1 & 0xf0) >> 4)); + puts("\n"); +} + +unsigned int s3c6410_mmc_init (int verbose) +{ + u32 reg; + u32 width; + int resp; + int hcs; + int retries = 50; + u8 response[16]; + unsigned int r1[4]; + struct sd_cid *sd_cid = (struct sd_cid *)response; + struct mmc_csd *csd = (struct mmc_csd *)response; + u8 *p8 = (u8 *)&r1[0]; + unsigned int sd_sectors = 0; + /* we need to shift result by 8 bits spread over 4 x 32-bit regs */ + u8 mangle[] = { 7, 0, 1, 2, 11, 4, 5, 6, 15, 8, 9, 10, 0, 12, 13, 14 }; + int n; + + hsmmc_set_gpio(); + + hsmmc_reset(); + + width = 4; + + HCLK = 33000000; /* FIXME */ + hsmmc_clock_onoff(0); + + reg = readl(SCLK_GATE); + writel(reg | (1<<27), SCLK_GATE); + + set_clock(SD_EPLL, 0x80); + s3c_hsmmc_writeb(0xe, HM_TIMEOUTCON); + set_hostctl_speed(NORMAL); + + InterruptEnable(0xff, 0xff); + +// dbg("HM_NORINTSTS = %x\n", s3c_hsmmc_readw(HM_NORINTSTS)); + + /* MMC_GO_IDLE_STATE */ + issue_command(MMC_GO_IDLE_STATE, 0x00, 0, 0); + + udelay(100000); + udelay(100000); + udelay(100000); + udelay(100000); + + /* SDHC card? */ + + resp = issue_command(SD_SEND_IF_COND, 0x000001aa, + 0, MMC_CMD_BCR | MMC_RSP_R7); + if (resp && ((s3c_hsmmc_readl(HM_RSPREG0) & 0xff) == 0xaa)) { + puts("SD 2.0\n"); + card_type = CARDTYPE_SD20; /* 2.0 SD, may not be SDHC */ + hcs = 0x40000000; + } + + /* Well, either way let's say hello in SD card protocol */ + + while (retries--) { + + udelay(100000); + udelay(100000); + udelay(100000); + + resp = issue_command(MMC_APP_CMD, 0x00000000, 0, + MMC_RSP_R1); + if (!resp) + continue; + resp = issue_command(SD_APP_OP_COND, hcs | 0x00300000, 0, + MMC_RSP_R3); + if (!resp) + continue; + + if ((s3c_hsmmc_readl(HM_RSPREG0) >> 24) & (1 << 6)) { /* asserts block addressing */ + retries = -2; + card_type = CARDTYPE_SDHC; + } + + if ((s3c_hsmmc_readl(HM_RSPREG0) >> 24) & (1 << 7)) { /* not busy */ + retries = -2; + if (card_type == CARDTYPE_NONE) + card_type = CARDTYPE_SD; + break; + } + } + if (retries == -1) { + puts("no response\n"); + return -2; + } + + if (!issue_command(MMC_ALL_SEND_CID, 0, 0, MMC_RSP_R2)) { + puts("CID broken\n"); + return -3; + } + + r1[0] = s3c_hsmmc_readl(HM_RSPREG3); + r1[1] = s3c_hsmmc_readl(HM_RSPREG2); + r1[2] = s3c_hsmmc_readl(HM_RSPREG1); + r1[3] = s3c_hsmmc_readl(HM_RSPREG0); + + for (n = 0; n < 16; n++) + response[n] = p8[mangle[n]]; + + switch (card_type) { + case CARDTYPE_SD: + case CARDTYPE_SD20: + case CARDTYPE_SDHC: + + if (verbose) + print_sd_cid(sd_cid); + resp = issue_command(SD_SEND_RELATIVE_ADDR, MMC_DEFAULT_RCA, + 0, MMC_RSP_R6); + rca = s3c_hsmmc_readl(HM_RSPREG0) >> 16; + break; + + default: + return 1; + } + + /* grab the CSD */ + + resp = issue_command(MMC_SEND_CSD, rca << 16, 0, MMC_RSP_R2); + if (resp) { + + r1[0] = s3c_hsmmc_readl(HM_RSPREG3); + r1[1] = s3c_hsmmc_readl(HM_RSPREG2); + r1[2] = s3c_hsmmc_readl(HM_RSPREG1); + r1[3] = s3c_hsmmc_readl(HM_RSPREG0); + for (n = 0; n < 16; n++) + response[n] = p8[mangle[n]]; + + switch (card_type) { + case CARDTYPE_SDHC: + puts(" SDHC size: "); + sd_sectors = (UNSTUFF_BITS(((u32 *)&response[0]), 48, 22) + + 1) << 10; + break; + default: + puts(" MMC/SD size: "); + sd_sectors = ((((unsigned long)1 << csd->c_size_mult1) * + (unsigned long)(csd->c_size)) >> 9); + } + printdec(sd_sectors / 2048); + puts(" MiB\n"); + } else + puts("CSD grab broken\n"); + + resp = issue_command(MMC_SELECT_CARD, rca<<16, 0, MMC_RSP_R1); + if (!resp) + return 1; + + /* Operating Clock setting */ + clock_config(2); // Divisor 1 = Base clk /2 ,Divisor 2 = Base clk /4, Divisor 4 = Base clk /8 ... + + while (set_bus_width(width)); + while (!check_card_status()); + + /* MMC_SET_BLOCKLEN */ + while (!issue_command(MMC_SET_BLOCKLEN, 512, 0, MMC_RSP_R1)); + + s3c_hsmmc_writew(0xffff, HM_NORINTSTS); + + return sd_sectors; +} + +unsigned long s3c6410_mmc_bread(int dev_num, unsigned long start_blk, unsigned long blknum, + void *dst) +{ + u32 blksize; //j, , Addr_temp = start_blk; + u32 dma = 0, cmd, multi; //, TotalReadByte, read_blk_cnt = 0; + + rd_cnt_HSMMC = 0; + HS_DMA_END = 0; + BlockNum_HSMMC = 0; + rd_cnt_HSMMC = 0; + ReadBlockCnt_INT = 0; + +// printf("\nHS-MMC block Read test: %d, 0x%x 0x%x\n", test, start_blk, blknum); + + BlockNum_HSMMC = blknum; + + blksize = Card_OneBlockSize_ver1; + +#if 0 + Rx_buffer_HSMMC = (u32 *) SDI_Rx_buffer_HSMMC; + for (i = 0; i < (blksize * BlockNum_HSMMC) / 4; i++) + *(Rx_buffer_HSMMC + i) = 0x0; +#endif + while (!check_card_status()); + + s3c_hsmmc_writew(s3c_hsmmc_readw(HM_NORINTSTSEN) & ~(DMA_STS_INT_EN | BLOCKGAP_EVENT_STS_INT_EN), HM_NORINTSTSEN); + s3c_hsmmc_writew((HM_NORINTSIGEN & ~(0xffff)) | TRANSFERCOMPLETE_SIG_INT_EN, HM_NORINTSIGEN); + + SetSystemAddressReg((unsigned long)dst); // AHB System Address For Write + dma = 1; + + set_blksize_register(7, 512); // Maximum DMA Buffer Size, Block Size + set_blkcnt_register(BlockNum_HSMMC); // Block Numbers to Write + + if (movi_hc) + set_arg_register(start_blk); // Card Start Block Address to Write + else + set_arg_register(start_blk * 512); // Card Start Block Address to Write + + cmd = (blknum > 1) ? 18 : 17; + multi = (blknum > 1); + + set_transfer_mode_register(multi, 1, multi, 1, dma); + set_cmd_register(cmd, 1, MMC_RSP_R1); + + if (wait_for_cmd_done()) { + puts("Command NOT Complete\n"); + return -1; + } else + ClearCommandCompleteStatus(); + + + check_dma_int(); + while (!HS_DMA_END); +// puts("\nDMA Read End\n"); + + HS_DMA_END = 0; + BlockNum_HSMMC = 0; + rd_cnt_HSMMC = 0; + ReadBlockCnt_INT = 0; + + return 0; +} diff --git a/qiboot/src/cpu/s3c6410/hs_mmc.h b/qiboot/src/cpu/s3c6410/hs_mmc.h new file mode 100644 index 0000000..f1218ce --- /dev/null +++ b/qiboot/src/cpu/s3c6410/hs_mmc.h @@ -0,0 +1,40 @@ +#ifndef __HS_MMC_H__ +#define __HS_MMC_H__ + +///////////////////////////////////////////////////////////////////////////////////////////////// +//#define SDHC_MONITOR (*(volatile unsigned *)0x4800004c) +//#define SDHC_SLOT_INT_STAT (*(volatile unsigned *)0x480000fc) + +///////////////////////////////////////////////////////////////////////////////////////////////// +#define SD_HCLK 1 +#define SD_EPLL 2 +#define SD_EXTCLK 3 + +#define NORMAL 0 +#define HIGH 1 + +//Normal Interrupt Signal Enable +#define READWAIT_SIG_INT_EN (1<<10) +#define CARD_SIG_INT_EN (1<<8) +#define CARD_REMOVAL_SIG_INT_EN (1<<7) +#define CARD_INSERT_SIG_INT_EN (1<<6) +#define BUFFER_READREADY_SIG_INT_EN (1<<5) +#define BUFFER_WRITEREADY_SIG_INT_EN (1<<4) +#define DMA_SIG_INT_EN (1<<3) +#define BLOCKGAP_EVENT_SIG_INT_EN (1<<2) +#define TRANSFERCOMPLETE_SIG_INT_EN (1<<1) +#define COMMANDCOMPLETE_SIG_INT_EN (1<<0) + +//Normal Interrupt Status Enable +#define READWAIT_STS_INT_EN (1<<10) +#define CARD_STS_INT_EN (1<<8) +#define CARD_REMOVAL_STS_INT_EN (1<<7) +#define CARD_INSERT_STS_INT_EN (1<<6) +#define BUFFER_READREADY_STS_INT_EN (1<<5) +#define BUFFER_WRITEREADY_STS_INT_EN (1<<4) +#define DMA_STS_INT_EN (1<<3) +#define BLOCKGAP_EVENT_STS_INT_EN (1<<2) +#define TRANSFERCOMPLETE_STS_INT_EN (1<<1) +#define COMMANDCOMPLETE_STS_INT_EN (1<<0) + +#endif /*__HS_MMC_H__*/ diff --git a/qiboot/src/cpu/s3c6410/qi.lds b/qiboot/src/cpu/s3c6410/qi.lds index 888972a..dbc9aa8 100644 --- a/qiboot/src/cpu/s3c6410/qi.lds +++ b/qiboot/src/cpu/s3c6410/qi.lds @@ -29,35 +29,44 @@ SECTIONS { . = 0x00000000; + __system_ram_start = 0x50000000; + __steppingstone = 0x0c000000; + /* this text section is magically pulled from the SD Card * and stored by the iRom at 0x0c000000, then it is jumped into * by the iRom. So we arrange our early parts needed at 0 in the * output file, but set to run at 0x0c000000+ */ - .text 0x0c000000 : AT ( 0 ) + .text + __steppingstone : + AT (0) { src/cpu/s3c6410/start.o (.text .rodata* .data) src/cpu/s3c6410/start_qi.o (.text .rodata* .data) src/cpu/s3c6410/serial-s3c64xx.o (.text .rodata* .data) src/cpu/s3c6410/tla01.o (.text .rodata* .data) - src/ctype.o (.text .rodata* .data) - src/phase2.o (.text .rodata* .data) + src/cpu/s3c6410/hs_mmc.o (.text .rodata* .data) src/utils.o (.text .rodata* .data) + src/ctype.o (.text .rodata* .data) } -/* . = ALIGN(4); - .everything_else ADDR (.text) + SIZEOF (.text) + 0x53000000 : - AT ( ADDR (.text) + SIZEOF (.text) ) { *(.text .rodata* .data) } + . = ALIGN(4); + .everything_else + __system_ram_start + 0x3000000 + SIZEOF(.text) : + AT (SIZEOF(.text)) + { + *(.text .rodata* .data) + } -*/ - . = 0x53800000 ; -/* . = 0x0c001900 ; */ - __bss_start = .; - .bss_6410 (NOLOAD) : - { - * (.bss) - } + + __bss_start = __system_ram_start + 0x03800000; + .bss_6410 + __bss_start (NOLOAD) : + AT (SIZEOF(.text) + SIZEOF(.everything_else)) + { + * (.bss) + } _end = .; } diff --git a/qiboot/src/cpu/s3c6410/start_qi.c b/qiboot/src/cpu/s3c6410/start_qi.c index a39abc5..f29d994 100644 --- a/qiboot/src/cpu/s3c6410/start_qi.c +++ b/qiboot/src/cpu/s3c6410/start_qi.c @@ -27,6 +27,9 @@ #include #include +#define stringify2(s) stringify1(s) +#define stringify1(s) #s + extern void bootloader_second_phase(void); const struct board_api *boards[] = { @@ -43,6 +46,7 @@ void start_qi(void) { int flag = 0; int board = 0; + unsigned int sd_sectors = 0; /* * well, we can be running on this CPU two different ways. @@ -59,7 +63,38 @@ void start_qi(void) * under control of JTAG. */ - if (!is_jtag) + + /* ask all the boards we support in turn if they recognize this + * hardware we are running on, accept the first positive answer + */ + + this_board = boards[board]; + while (!flag && this_board) + /* check if it is the right board... */ + if (this_board->is_this_board()) + flag = 1; + else + this_board = boards[board++]; + + /* okay, do the critical port and serial init for our board */ + + this_board->port_init(); + + /* stick some hello messages on debug console */ + + puts("\n\n\nQi Bootloader "stringify2(QI_CPU)" " + stringify2(BUILD_HOST)" " + stringify2(BUILD_VERSION)" " + "\n"); + + puts(stringify2(BUILD_DATE) " Copyright (C) 2008 Openmoko, Inc.\n"); + puts("\n Detected: "); + + puts(this_board->name); + puts(", "); + puts((this_board->get_board_variant)()->name); + + if (!is_jtag) { /* * We got the first 4KBytes of the bootloader pulled into the * steppingstone SRAM for free. Now we pull the whole bootloader @@ -67,40 +102,25 @@ void start_qi(void) * * This code and the .S files are arranged by the linker script * to expect to run from 0x0. But the linker script has told - * everything else to expect to run from 0x33000000+. That's + * everything else to expect to run from 0x53000000+. That's * why we are going to be able to copy this code and not have it * crash when we run it from there. */ /* We randomly pull 32KBytes of bootloader */ - /* FIXME this ain't right for s3c6410 */ -#if 0 - if (nand_read_ll((u8 *)TEXT_BASE, 0, 32 * 1024 / 512) < 0) - goto unhappy; -#endif - /* ask all the boards we support in turn if they recognize this - * hardware we are running on, accept the first positive answer - */ - - this_board = boards[board]; - while (!flag && this_board) { - - /* check if it is the right board... */ - if (this_board->is_this_board()) { - flag = 1; - continue; - } - - this_board = boards[board++]; + extern unsigned int s3c6410_mmc_init(int verbose); + unsigned long s3c6410_mmc_bread(int dev_num, + unsigned long start_blk, unsigned long blknum, + void *dst); + sd_sectors = s3c6410_mmc_init(1); + s3c6410_mmc_bread(0, sd_sectors - 1026 - 16 - (256 * 2), + 256 * 2, (u8 *)0x53000000); } + /* * jump to bootloader_second_phase() running from DRAM copy */ bootloader_second_phase(); - - while(1) - ; - } diff --git a/qiboot/src/cpu/s3c6410/tla01.c b/qiboot/src/cpu/s3c6410/tla01.c index f4b9714..09422dc 100644 --- a/qiboot/src/cpu/s3c6410/tla01.c +++ b/qiboot/src/cpu/s3c6410/tla01.c @@ -137,6 +137,7 @@ void port_init_tla01(void) i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_DOWN1OUT, 0x2b); #endif + } /** @@ -166,13 +167,28 @@ static void putc_tla01(char c) serial_putc_s3c64xx(GTA03_DEBUG_UART, c); } +int sd_card_init_tla01(void) +{ + extern int s3c6410_mmc_init(int verbose); + + return s3c6410_mmc_init(1); +} + +int sd_card_block_read_tla01(unsigned char * buf, unsigned long start512, + int blocks512) +{ +unsigned long s3c6410_mmc_bread(int dev_num, unsigned long blknr, unsigned long blkcnt, + void *dst); + + return s3c6410_mmc_bread(0, start512, blocks512, buf); +} /* * our API for bootloader on this machine */ const struct board_api board_api_tla01 = { .name = "TLA01", - .linux_machine_id = 1866, + .linux_machine_id = 1304 /*1866*/, .linux_mem_start = 0x50000000, .linux_mem_size = (128 * 1024 * 1024), .linux_tag_placement = 0x50000000 + 0x100, @@ -182,10 +198,11 @@ const struct board_api board_api_tla01 = { .putc = putc_tla01, .kernel_source = { [0] = { - .name = "SD Card", - .block_read = NULL, /* FIXME It's s3c6400 sd card*/ - .offset_blocks512_if_no_partition = 0x80000 / 512, - .filesystem = FS_RAW, + .name = "SD Card rootfs", + .block_read = sd_card_block_read_tla01, + .filesystem = FS_EXT2, + .partition_index = 2, + .filepath = "boot/uImage.bin", .commandline = "rootfstype=ext3 " \ "root=/dev/mmcblk0p1 " \ "console=ttySAC2,115200 " \ @@ -193,5 +210,17 @@ const struct board_api board_api_tla01 = { "init=/sbin/init "\ "ro" }, - }, + [1] = { + .name = "SD Card backup rootfs", + .block_read = sd_card_block_read_tla01, + .filesystem = FS_EXT2, + .partition_index = 3, + .filepath = "boot/uImage.bin", + .commandline = "rootfstype=ext3 " \ + "root=/dev/mmcblk0p1 " \ + "console=ttySAC2,115200 " \ + "loglevel=4 " \ + "init=/sbin/init "\ + "ro" + }, }, }; diff --git a/qiboot/src/phase2.c b/qiboot/src/phase2.c index 679f206..29137a5 100644 --- a/qiboot/src/phase2.c +++ b/qiboot/src/phase2.c @@ -30,10 +30,6 @@ #include #include -#define stringify2(s) stringify1(s) -#define stringify1(s) #s - - unsigned long partition_offset_blocks = 0; unsigned long partition_length_blocks = 0; @@ -49,28 +45,8 @@ void bootloader_second_phase(void) { void (*the_kernel)(int zero, int arch, uint params); int kernel = 0; - const struct board_variant * board_variant; - - /* okay, do the critical port and serial init for our board */ - - this_board->port_init(); - - /* stick some hello messages on debug console */ - - puts("\n\n\nQi Bootloader "stringify2(QI_CPU)" " - stringify2(BUILD_HOST)" " - stringify2(BUILD_VERSION)" " - stringify2(BUILD_DATE)"\n"); - - puts("Copyright (C) 2008 Openmoko, Inc.\n"); - puts("This is free software; see the source for copying conditions.\n" - "There is NO warranty; not even for MERCHANTABILITY or " - "FITNESS FOR A PARTICULAR PURPOSE.\n\n Detected: "); - - puts(this_board->name); - puts(", "); - board_variant = (this_board->get_board_variant)(); - puts(board_variant->name); + const struct board_variant * board_variant = + (this_board->get_board_variant)(); /* we try the possible kernels for this board in order */ @@ -79,7 +55,7 @@ void bootloader_second_phase(void) while (this_kernel->name) { const char *p; struct tag *params = (struct tag *)this_board->linux_tag_placement; - void * kernel_dram = (void *)(TEXT_BASE - (8 * 1024 * 1024)); + void * kernel_dram = (void *)this_board->linux_mem_start + 0x8000; unsigned long crc; image_header_t *hdr; u32 kernel_size; @@ -150,7 +126,6 @@ void bootloader_second_phase(void) switch (this_kernel->filesystem) { case FS_EXT2: -#if 0 if (!ext2fs_mount()) { puts("Unable to mount ext2 filesystem\n"); this_kernel = &this_board-> @@ -168,7 +143,7 @@ void bootloader_second_phase(void) } ext2fs_read(kernel_dram, 4096); break; -#endif + case FS_FAT: /* FIXME */ case FS_RAW: @@ -206,11 +181,10 @@ void bootloader_second_phase(void) switch (this_kernel->filesystem) { case FS_EXT2: -#if 0 /* This read API always restarts from beginning */ ext2fs_read(kernel_dram, kernel_size); break; -#endif + case FS_FAT: /* FIXME */ case FS_RAW: