From b43ca37f46d070b6ef2bfbb382ee93fe9a2aed4c Mon Sep 17 00:00:00 2001 From: Xiangfu Liu Date: Wed, 9 Jun 2010 17:28:00 +0800 Subject: [PATCH] [xbboot] rename cpm_start_all to cpm_start_all_4760 fix typo of cpu speed, remove useless define(NAND) in board-jz4760.h --- xbboot/target-stage1/board-jz4760.c | 26 ++++++------- xbboot/target-stage1/board-jz4760.h | 59 +++-------------------------- xbboot/target-stage1/stage1.c | 6 +-- 3 files changed, 21 insertions(+), 70 deletions(-) diff --git a/xbboot/target-stage1/board-jz4760.c b/xbboot/target-stage1/board-jz4760.c index 8820682..68b3bea 100644 --- a/xbboot/target-stage1/board-jz4760.c +++ b/xbboot/target-stage1/board-jz4760.c @@ -10,9 +10,7 @@ #include "jz4760.h" #include "board-jz4760.h" -#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/ - -void cpm_start_all() +void cpm_start_all_4760() { __cpm_start_all(); } @@ -136,7 +134,7 @@ void pll_init_4760() (n2FR[div[4]] << CPM_CPCCR_MDIV_BIT) | (n2FR[div[5]] << CPM_CPCCR_SDIV_BIT); - if (CFG_EXTAL > 16000000) + if (ARG_EXTAL > 16000000) cfcr |= CPM_CPCCR_ECS; else cfcr &= ~CPM_CPCCR_ECS; @@ -149,9 +147,9 @@ void pll_init_4760() #endif cfcr |= CPM_CPCCR_CE; - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); + pllout2 = (cfcr & CPM_CPCCR_PCS) ? ARG_CPU_SPEED : (ARG_CPU_SPEED / 2); - plcr1 = pll_calc_m_n_od(CFG_CPU_SPEED, CFG_EXTAL); + plcr1 = pll_calc_m_n_od(ARG_CPU_SPEED, ARG_EXTAL); plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT) /* PLL stable time */ | CPM_CPPCR_PLLEN; /* enable PLL */ @@ -361,7 +359,7 @@ for(times = 0; times < banks; times++) { DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3; #endif - cpu_clk = CFG_CPU_SPEED; + cpu_clk = ARG_CPU_SPEED; #ifdef DMA_CHANNEL0_EN addr = DDR_DMA0_SRC; @@ -468,7 +466,7 @@ void ddr_mem_init(int msel, int hl, int tsel, int arg) register unsigned int cpu_clk, ddr_twr; register unsigned int ddrc_cfg_reg=0, init_ddrc_mdelay=0; - cpu_clk = CFG_CPU_SPEED; + cpu_clk = ARG_CPU_SPEED; #if defined(CONFIG_SDRAM_DDR2) // ddr2 serial_puts("\nddr2-\n"); @@ -768,7 +766,7 @@ static int dma_memcpy_test(int channle_0, int channle_1) { DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2; DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3; - cpu_clk = CFG_CPU_SPEED; + cpu_clk = ARG_CPU_SPEED; // for(channel = 0; channel < MAX_DMA_NUM; channel++) { @@ -883,10 +881,10 @@ void sdram_init_4760(void) ddrc_regs_print(); #endif - cpu_clk = CFG_CPU_SPEED; + cpu_clk = ARG_CPU_SPEED; #if defined(CONFIG_FPGA) - mem_clk = CFG_EXTAL / CFG_DIV; + mem_clk = ARG_EXTAL / CFG_DIV; #else mem_clk = __cpm_get_mclk(); #endif @@ -1174,7 +1172,7 @@ void sdram_init_4760(void) int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - cpu_clk = CFG_CPU_SPEED; + cpu_clk = ARG_CPU_SPEED; mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; REG_EMC_BCR = 0; /* Disable bus release */ @@ -1266,9 +1264,9 @@ static void serial_setbrg(void) u32 baud_div, tmp; // baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ? -// (CFG_EXTAL / 32 / CONFIG_BAUDRATE) : (CFG_EXTAL / 16 / CONFIG_BAUDRATE); +// (ARG_EXTAL / 32 / CONFIG_BAUDRATE) : (ARG_EXTAL / 16 / CONFIG_BAUDRATE); - baud_div = (CFG_EXTAL / 16 / 57600); + baud_div = (ARG_EXTAL / 16 / 57600); tmp = *uart_lcr; tmp |= UART_LCR_DLAB; *uart_lcr = tmp; diff --git a/xbboot/target-stage1/board-jz4760.h b/xbboot/target-stage1/board-jz4760.h index 76ff76c..25d845c 100644 --- a/xbboot/target-stage1/board-jz4760.h +++ b/xbboot/target-stage1/board-jz4760.h @@ -1,66 +1,19 @@ /* - * jz4760_board.h - * * JZ4760 board definitions. * * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. - * */ #ifndef __BOARD_JZ4760_H__ #define __BOARD_JZ4760_H__ -//#define CONFIG_FPGA //#define DEBUG +//#define CONFIG_FPGA +//#define CFG_DIV 2 /* for FPGA */ -#define CONFIG_SDRAM_MDDR +//#define CONFIG_SDRAM_MDDR //#define CONFIG_SDRAM_DDR1 //#define CONFIG_SDRAM_DDR2 - -//#define CONFIG_LOAD_UBOOT /* if not defined, load zImage */ - -/*------------------------------------------------------------------- - * Frequency of the external OSC in Hz. - */ -#define CFG_EXTAL 12000000 -#define CFG_DIV 2 /* for FPGA */ -/*------------------------------------------------------------------- - * CPU speed. - */ -#define CFG_CPU_SPEED 144000000 /* CPU clock */ - -/*------------------------------------------------------------------- - * Serial console. - */ -#define CFG_UART_BASE UART1_BASE -//CONFIG_BAUDRATE = 115200 - -/*----------------------------------------------------------------------- - * NAND FLASH configuration - */ -#define CFG_NAND_BW8 1 /* Data bus width: 0-16bit, 1-8bit */ -#define CFG_NAND_PAGE_SIZE 2048 -#define CFG_NAND_ROW_CYCLE 3 -#define CFG_NAND_BLOCK_SIZE (256 << 10) /* NAND chip block size */ -#define CFG_NAND_BADBLOCK_PAGE 127 /* NAND bad block was marked at this page in a block, starting from 0 */ -#define CFG_NAND_BCH_BIT 4 /* Specify the hardware BCH algorithm for 4760 (4|8) */ -#define CFG_NAND_ECC_POS 24 /* Ecc offset position in oob area, its default value is 3 if it isn't defined. */ -#define CFG_NAND_BASE 0xBA000000 -#define CFG_NAND_SMCR1 0x0D555500 /* 0x0fff7700 is slowest */ - -#define CFG_NAND_USE_PN 1 /* Use PN in jz4760 for TLC NAND */ - -#ifdef CONFIG_LOAD_UBOOT -#define CFG_NAND_U_BOOT_OFFS (CFG_NAND_BLOCK_SIZE*2) /* Offset to RAM U-Boot image */ -#define CFG_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ -#define CFG_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */ -#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ -#else // load zImage -#define PARAM_BASE 0x80004000 -#define CFG_KERNEL_OFFS (CFG_NAND_BLOCK_SIZE*2) /* NAND offset of kernel image being loaded */ -#define CFG_KERNEL_SIZE (2 << 20) /* Size of kernel image */ -#define CFG_KERNEL_DST 0x80100000 /* Load kernel to this addr */ -#define CFG_KERNEL_START CFG_KERNEL_DST /* Start kernel from this addr */ -#endif +//#define CONFIG_MOBILE_SDRAM #if (!defined(CONFIG_SDRAM_MDDR) && !defined(CONFIG_SDRAM_DDR1) && !defined(CONFIG_SDRAM_DDR2)) /*----------------------------------------------------------------------- @@ -203,8 +156,8 @@ #endif #define DDR_CLK_DIV 1 /* Clock Divider. auto refresh - * cnt_clk = memclk/(16*(2^DDR_CLK_DIV)) - */ + * cnt_clk = memclk/(16*(2^DDR_CLK_DIV)) + */ #endif /* CONFIG_DDRC */ #endif /* __BOARD_JZ4760_H__ */ diff --git a/xbboot/target-stage1/stage1.c b/xbboot/target-stage1/stage1.c index 7e86694..f56c0ef 100644 --- a/xbboot/target-stage1/stage1.c +++ b/xbboot/target-stage1/stage1.c @@ -18,7 +18,7 @@ extern void nand_init_4740(); extern void gpio_init_4760(); extern void pll_init_4760(); -extern void cpm_start_all(); +extern void cpm_start_all_4760(); extern void serial_init_4760(int uart); extern void sdram_init_4760(); @@ -39,7 +39,7 @@ void load_args_4760() { ARG_CPU_ID = 0x4760; ARG_EXTAL = 12 * 1000000; - ARG_CPU_SPEED = 2 * ARG_EXTAL; + ARG_CPU_SPEED = 12 * ARG_EXTAL; ARG_PHM_DIV = 3; ARG_UART_BAUD = 57600; ARG_BUS_WIDTH_16 = * (int *)0x80002014; @@ -63,7 +63,7 @@ void c_main(void) break; case 0x4760: gpio_init_4760(); - cpm_start_all(); + cpm_start_all_4760(); serial_init_4760(1); pll_init_4760(); sdram_init_4760();