mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2024-11-01 12:09:40 +02:00
[xbboot] rename cpm_start_all to cpm_start_all_4760
fix typo of cpu speed, remove useless define(NAND) in board-jz4760.h
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@ -10,9 +10,7 @@
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#include "jz4760.h"
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#include "jz4760.h"
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#include "board-jz4760.h"
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#include "board-jz4760.h"
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#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
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void cpm_start_all_4760()
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void cpm_start_all()
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{
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{
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__cpm_start_all();
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__cpm_start_all();
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}
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}
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@ -136,7 +134,7 @@ void pll_init_4760()
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(n2FR[div[4]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[4]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[5]] << CPM_CPCCR_SDIV_BIT);
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(n2FR[div[5]] << CPM_CPCCR_SDIV_BIT);
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if (CFG_EXTAL > 16000000)
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if (ARG_EXTAL > 16000000)
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cfcr |= CPM_CPCCR_ECS;
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cfcr |= CPM_CPCCR_ECS;
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else
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else
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cfcr &= ~CPM_CPCCR_ECS;
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cfcr &= ~CPM_CPCCR_ECS;
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@ -149,9 +147,9 @@ void pll_init_4760()
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#endif
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#endif
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cfcr |= CPM_CPCCR_CE;
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cfcr |= CPM_CPCCR_CE;
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? ARG_CPU_SPEED : (ARG_CPU_SPEED / 2);
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plcr1 = pll_calc_m_n_od(CFG_CPU_SPEED, CFG_EXTAL);
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plcr1 = pll_calc_m_n_od(ARG_CPU_SPEED, ARG_EXTAL);
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plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT) /* PLL stable time */
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plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT) /* PLL stable time */
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| CPM_CPPCR_PLLEN; /* enable PLL */
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| CPM_CPPCR_PLLEN; /* enable PLL */
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@ -361,7 +359,7 @@ for(times = 0; times < banks; times++) {
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DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3;
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DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3;
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#endif
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#endif
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cpu_clk = CFG_CPU_SPEED;
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cpu_clk = ARG_CPU_SPEED;
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#ifdef DMA_CHANNEL0_EN
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#ifdef DMA_CHANNEL0_EN
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addr = DDR_DMA0_SRC;
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addr = DDR_DMA0_SRC;
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@ -468,7 +466,7 @@ void ddr_mem_init(int msel, int hl, int tsel, int arg)
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register unsigned int cpu_clk, ddr_twr;
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register unsigned int cpu_clk, ddr_twr;
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register unsigned int ddrc_cfg_reg=0, init_ddrc_mdelay=0;
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register unsigned int ddrc_cfg_reg=0, init_ddrc_mdelay=0;
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cpu_clk = CFG_CPU_SPEED;
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cpu_clk = ARG_CPU_SPEED;
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#if defined(CONFIG_SDRAM_DDR2) // ddr2
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#if defined(CONFIG_SDRAM_DDR2) // ddr2
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serial_puts("\nddr2-\n");
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serial_puts("\nddr2-\n");
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@ -768,7 +766,7 @@ static int dma_memcpy_test(int channle_0, int channle_1) {
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DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2;
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DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2;
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DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3;
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DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3;
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cpu_clk = CFG_CPU_SPEED;
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cpu_clk = ARG_CPU_SPEED;
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// for(channel = 0; channel < MAX_DMA_NUM; channel++) {
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// for(channel = 0; channel < MAX_DMA_NUM; channel++) {
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@ -883,10 +881,10 @@ void sdram_init_4760(void)
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ddrc_regs_print();
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ddrc_regs_print();
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#endif
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#endif
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cpu_clk = CFG_CPU_SPEED;
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cpu_clk = ARG_CPU_SPEED;
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#if defined(CONFIG_FPGA)
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#if defined(CONFIG_FPGA)
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mem_clk = CFG_EXTAL / CFG_DIV;
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mem_clk = ARG_EXTAL / CFG_DIV;
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#else
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#else
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mem_clk = __cpm_get_mclk();
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mem_clk = __cpm_get_mclk();
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#endif
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#endif
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@ -1174,7 +1172,7 @@ void sdram_init_4760(void)
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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cpu_clk = CFG_CPU_SPEED;
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cpu_clk = ARG_CPU_SPEED;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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REG_EMC_BCR = 0; /* Disable bus release */
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REG_EMC_BCR = 0; /* Disable bus release */
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@ -1266,9 +1264,9 @@ static void serial_setbrg(void)
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u32 baud_div, tmp;
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u32 baud_div, tmp;
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// baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ?
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// baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ?
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// (CFG_EXTAL / 32 / CONFIG_BAUDRATE) : (CFG_EXTAL / 16 / CONFIG_BAUDRATE);
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// (ARG_EXTAL / 32 / CONFIG_BAUDRATE) : (ARG_EXTAL / 16 / CONFIG_BAUDRATE);
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baud_div = (CFG_EXTAL / 16 / 57600);
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baud_div = (ARG_EXTAL / 16 / 57600);
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tmp = *uart_lcr;
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tmp = *uart_lcr;
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tmp |= UART_LCR_DLAB;
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tmp |= UART_LCR_DLAB;
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*uart_lcr = tmp;
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*uart_lcr = tmp;
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@ -1,66 +1,19 @@
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/*
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/*
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* jz4760_board.h
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*
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* JZ4760 board definitions.
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* JZ4760 board definitions.
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*
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*
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* Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
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* Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
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*
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*/
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*/
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#ifndef __BOARD_JZ4760_H__
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#ifndef __BOARD_JZ4760_H__
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#define __BOARD_JZ4760_H__
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#define __BOARD_JZ4760_H__
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//#define CONFIG_FPGA
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//#define DEBUG
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//#define DEBUG
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//#define CONFIG_FPGA
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//#define CFG_DIV 2 /* for FPGA */
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#define CONFIG_SDRAM_MDDR
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//#define CONFIG_SDRAM_MDDR
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//#define CONFIG_SDRAM_DDR1
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//#define CONFIG_SDRAM_DDR1
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//#define CONFIG_SDRAM_DDR2
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//#define CONFIG_SDRAM_DDR2
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//#define CONFIG_MOBILE_SDRAM
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//#define CONFIG_LOAD_UBOOT /* if not defined, load zImage */
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/*-------------------------------------------------------------------
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* Frequency of the external OSC in Hz.
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*/
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#define CFG_EXTAL 12000000
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#define CFG_DIV 2 /* for FPGA */
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/*-------------------------------------------------------------------
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* CPU speed.
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*/
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#define CFG_CPU_SPEED 144000000 /* CPU clock */
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/*-------------------------------------------------------------------
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* Serial console.
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*/
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#define CFG_UART_BASE UART1_BASE
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//CONFIG_BAUDRATE = 115200
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/*-----------------------------------------------------------------------
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* NAND FLASH configuration
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*/
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#define CFG_NAND_BW8 1 /* Data bus width: 0-16bit, 1-8bit */
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#define CFG_NAND_PAGE_SIZE 2048
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#define CFG_NAND_ROW_CYCLE 3
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#define CFG_NAND_BLOCK_SIZE (256 << 10) /* NAND chip block size */
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#define CFG_NAND_BADBLOCK_PAGE 127 /* NAND bad block was marked at this page in a block, starting from 0 */
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#define CFG_NAND_BCH_BIT 4 /* Specify the hardware BCH algorithm for 4760 (4|8) */
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#define CFG_NAND_ECC_POS 24 /* Ecc offset position in oob area, its default value is 3 if it isn't defined. */
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#define CFG_NAND_BASE 0xBA000000
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#define CFG_NAND_SMCR1 0x0D555500 /* 0x0fff7700 is slowest */
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#define CFG_NAND_USE_PN 1 /* Use PN in jz4760 for TLC NAND */
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#ifdef CONFIG_LOAD_UBOOT
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#define CFG_NAND_U_BOOT_OFFS (CFG_NAND_BLOCK_SIZE*2) /* Offset to RAM U-Boot image */
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#define CFG_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
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#define CFG_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#else // load zImage
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#define PARAM_BASE 0x80004000
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#define CFG_KERNEL_OFFS (CFG_NAND_BLOCK_SIZE*2) /* NAND offset of kernel image being loaded */
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#define CFG_KERNEL_SIZE (2 << 20) /* Size of kernel image */
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#define CFG_KERNEL_DST 0x80100000 /* Load kernel to this addr */
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#define CFG_KERNEL_START CFG_KERNEL_DST /* Start kernel from this addr */
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#endif
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#if (!defined(CONFIG_SDRAM_MDDR) && !defined(CONFIG_SDRAM_DDR1) && !defined(CONFIG_SDRAM_DDR2))
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#if (!defined(CONFIG_SDRAM_MDDR) && !defined(CONFIG_SDRAM_DDR1) && !defined(CONFIG_SDRAM_DDR2))
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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@ -18,7 +18,7 @@ extern void nand_init_4740();
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extern void gpio_init_4760();
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extern void gpio_init_4760();
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extern void pll_init_4760();
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extern void pll_init_4760();
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extern void cpm_start_all();
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extern void cpm_start_all_4760();
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extern void serial_init_4760(int uart);
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extern void serial_init_4760(int uart);
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extern void sdram_init_4760();
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extern void sdram_init_4760();
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@ -39,7 +39,7 @@ void load_args_4760()
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{
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{
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ARG_CPU_ID = 0x4760;
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ARG_CPU_ID = 0x4760;
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ARG_EXTAL = 12 * 1000000;
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ARG_EXTAL = 12 * 1000000;
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ARG_CPU_SPEED = 2 * ARG_EXTAL;
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ARG_CPU_SPEED = 12 * ARG_EXTAL;
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ARG_PHM_DIV = 3;
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ARG_PHM_DIV = 3;
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ARG_UART_BAUD = 57600;
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ARG_UART_BAUD = 57600;
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ARG_BUS_WIDTH_16 = * (int *)0x80002014;
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ARG_BUS_WIDTH_16 = * (int *)0x80002014;
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@ -63,7 +63,7 @@ void c_main(void)
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break;
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break;
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case 0x4760:
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case 0x4760:
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gpio_init_4760();
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gpio_init_4760();
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cpm_start_all();
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cpm_start_all_4760();
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serial_init_4760(1);
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serial_init_4760(1);
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pll_init_4760();
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pll_init_4760();
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sdram_init_4760();
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sdram_init_4760();
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