diff --git a/usbboot/xburst_include/target/configs.h b/usbboot/xburst_include/target/configs.h index a8d96f5..e897c72 100644 --- a/usbboot/xburst_include/target/configs.h +++ b/usbboot/xburst_include/target/configs.h @@ -25,6 +25,7 @@ /* Once your system configration change, just modify the file */ #include "target/xburst_types.h" + #define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/ #define SDRAM_CASL 3 /* CAS latency: 2 or 3 */ /* SDRAM Timings, unit: ns */ @@ -34,7 +35,6 @@ #define SDRAM_TRWL 7 /* Write Latency Time */ #define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */ - extern volatile u32 CPU_ID; extern volatile u8 SDRAM_BW16; extern volatile u8 SDRAM_BANK4; @@ -48,13 +48,4 @@ extern volatile u32 CONFIG_BAUDRATE; extern volatile u32 UART_BASE; extern volatile u8 CONFIG_MOBILE_SDRAM; extern volatile u8 IS_SHARE; - -extern void gpio_init_4740(void); -extern void sdram_init_4740(void); -extern void pll_init_4740(void); - -extern void gpio_init_4760(void); -extern void sdram_init_4760(void); -extern void pll_init_4760(void); - #endif diff --git a/usbboot/xburst_include/target/jz4750.h b/usbboot/xburst_include/target/jz4760.h similarity index 67% rename from usbboot/xburst_include/target/jz4750.h rename to usbboot/xburst_include/target/jz4760.h index f9cee96..9cf3922 100644 --- a/usbboot/xburst_include/target/jz4750.h +++ b/usbboot/xburst_include/target/jz4760.h @@ -1,33 +1,14 @@ /* - * Include file for Ingenic Semiconductor's JZ4750 CPU. - * - * Copyright 2009 (C) Qi Hardware Inc., - * Author: Xiangfu Liu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 3 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA + * Include file for Ingenic Semiconductor's JZ4760 CPU. */ +#ifndef __JZ4760_H__ +#define __JZ4760_H__ -#ifndef __JZ4750_H__ -#define __JZ4750_H__ +#include "target/xburst_types.h" -#include "xburst_types.h" - -#ifndef __ASSEMBLY__ +#if 0 /* if 0, for spl program */ #define UCOS_CSP 0 -#if 0 #if UCOS_CSP #define __KERNEL__ #include @@ -40,7 +21,7 @@ #include #include #endif -#endif + #define cache_unroll(base,op) \ __asm__ __volatile__(" \ .set noreorder; \ @@ -51,7 +32,7 @@ : \ : "r" (base), \ "i" (op)); -#if 0 + static inline void jz_flush_dcache(void) { unsigned long start; @@ -78,7 +59,6 @@ static inline void jz_flush_icache(void) } } -#endif /* cpu pipeline flush */ static inline void jz_sync(void) { @@ -114,118 +94,158 @@ static inline u32 jz_readl(u32 address) { return *((volatile u32 *)address); } - -#define REG8(addr) *((volatile u8 *)(addr)) -#define REG16(addr) *((volatile u16 *)(addr)) -#define REG32(addr) *((volatile u32 *)(addr)) - -#else - -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) - -#endif /* !ASSEMBLY */ +#endif //---------------------------------------------------------------------- // Boot ROM Specification // /* NOR Boot config */ -#define JZ4750_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ -#define JZ4750_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ -#define JZ4750_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ +#define JZ4760_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ +#define JZ4760_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ +#define JZ4760_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ /* NAND Boot config */ -#define JZ4750_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ -#define JZ4750_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ -#define JZ4750_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ -#define JZ4750_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ +#define JZ4760_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ +#define JZ4760_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ +#define JZ4760_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ +#define JZ4760_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ //---------------------------------------------------------------------- // Register Definitions // +/* AHB0 BUS Devices Base */ +#define HARB0_BASE 0xB3000000 +#define EMC_BASE 0xB3010000 +#define DDRC_BASE 0xB3020000 +#define MDMAC_BASE 0xB3030000 +#define LCD_BASE 0xB3050000 +#define TVE_BASE 0xB3050000 +#define SLCD_BASE 0xB3050000 +#define CIM_BASE 0xB3060000 +#define IPU_BASE 0xB3080000 +/* AHB1 BUS Devices Base */ +#define HARB1_BASE 0xB3200000 +#define DMAGP0_BASE 0xB3210000 +#define DMAGP1_BASE 0xB3220000 +#define DMAGP2_BASE 0xB3230000 +#define MC_BASE 0xB3250000 +#define ME_BASE 0xB3260000 +#define DEBLK_BASE 0xB3270000 +#define IDCT_BASE 0xB3280000 +#define CABAC_BASE 0xB3290000 +#define TCSM0_BASE 0xB32B0000 +#define TCSM1_BASE 0xB32C0000 +#define SRAM_BASE 0xB32D0000 +/* AHB2 BUS Devices Base */ +#define HARB2_BASE 0xB3400000 +#define NEMC_BASE 0xB3410000 +#define DMAC_BASE 0xB3420000 +#define UHC_BASE 0xB3430000 +#define UDC_BASE 0xB3440000 +#define GPS_BASE 0xB3480000 +#define ETHC_BASE 0xB34B0000 +#define BCH_BASE 0xB34D0000 +/* APB BUS Devices Base */ #define CPM_BASE 0xB0000000 #define INTC_BASE 0xB0001000 #define TCU_BASE 0xB0002000 +#define OST_BASE 0xB0002000 #define WDT_BASE 0xB0002000 #define RTC_BASE 0xB0003000 #define GPIO_BASE 0xB0010000 #define AIC_BASE 0xB0020000 #define ICDC_BASE 0xB0020000 -#define MSC_BASE 0xB0021000 +#define MSC0_BASE 0xB0021000 +#define MSC1_BASE 0xB0022000 +#define MSC2_BASE 0xB0023000 #define UART0_BASE 0xB0030000 #define UART1_BASE 0xB0031000 #define UART2_BASE 0xB0032000 #define UART3_BASE 0xB0033000 -#define I2C_BASE 0xB0042000 -#define SSI_BASE 0xB0043000 +#define SCC_BASE 0xB0040000 +#define SSI0_BASE 0xB0043000 +#define SSI1_BASE 0xB0044000 +#define SSI2_BASE 0xB0045000 +#define I2C0_BASE 0xB0050000 +#define I2C1_BASE 0xB0051000 +#define PS2_BASE 0xB0060000 #define SADC_BASE 0xB0070000 -#define EMC_BASE 0xB3010000 -#define DMAC_BASE 0xB3020000 -#define UHC_BASE 0xB3030000 -#define UDC_BASE 0xB3040000 -#define LCD_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define BCH_BASE 0xB30D0000 -#define ETH_BASE 0xB3100000 - +#define OWI_BASE 0xB0072000 +#define TSSI_BASE 0xB0073000 /************************************************************************* * INTC (Interrupt Controller) *************************************************************************/ -#define INTC_ISR (INTC_BASE + 0x00) -#define INTC_IMR (INTC_BASE + 0x04) -#define INTC_IMSR (INTC_BASE + 0x08) -#define INTC_IMCR (INTC_BASE + 0x0c) -#define INTC_IPR (INTC_BASE + 0x10) +#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20) +#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20) +#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20) +#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20) +#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20) + +#define REG_INTC_ISR(n) REG32(INTC_ISR((n))) +#define REG_INTC_IMR(n) REG32(INTC_IMR((n))) +#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n))) +#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n))) +#define REG_INTC_IPR(n) REG32(INTC_IPR((n))) -#define REG_INTC_ISR REG32(INTC_ISR) -#define REG_INTC_IMR REG32(INTC_IMR) -#define REG_INTC_IMSR REG32(INTC_IMSR) -#define REG_INTC_IMCR REG32(INTC_IMCR) -#define REG_INTC_IPR REG32(INTC_IPR) // 1st-level interrupts -#define IRQ_OWI 0 -#define IRQ_I2C 1 -#define IRQ_TSSI 2 -#define IRQ_UART3 3 -#define IRQ_UART2 4 -#define IRQ_UART1 5 -#define IRQ_UART0 6 -#define IRQ_PCM 7 -#define IRQ_AIC 8 -#define IRQ_RTC 9 -#define IRQ_SADC 10 -#define IRQ_SSI1 11 -#define IRQ_SSI0 12 -#define IRQ_MSC1 13 -#define IRQ_MSC0 14 -#define IRQ_ETH 15 -#define IRQ_BCH 16 -#define IRQ_UHC 17 -#define IRQ_CIM 18 -#define IRQ_UDC 19 -#define IRQ_DMAC 20 -#define IRQ_TCU2 21 -#define IRQ_TCU1 22 -#define IRQ_TCU0 23 -#define IRQ_GPIO5 24 -#define IRQ_GPIO4 25 -#define IRQ_GPIO3 26 -#define IRQ_GPIO2 27 -#define IRQ_GPIO1 28 -#define IRQ_GPIO0 29 -#define IRQ_IPU 30 +#define IRQ_I2C1 0 +#define IRQ_I2C0 1 +#define IRQ_UART3 2 +#define IRQ_UART2 3 +#define IRQ_UART1 4 +#define IRQ_UART0 5 +#define IRQ_SSI2 6 +#define IRQ_SSI1 7 +#define IRQ_SSI0 8 +#define IRQ_TSSI 9 +#define IRQ_BDMA 10 +#define IRQ_KBC 11 +#define IRQ_GPIO5 12 +#define IRQ_GPIO4 13 +#define IRQ_GPIO3 14 +#define IRQ_GPIO2 15 +#define IRQ_GPIO1 16 +#define IRQ_GPIO0 17 +#define IRQ_SADC 18 +#define IRQ_ETH 19 +#define IRQ_UHC 20 +#define IRQ_OTG 21 +#define IRQ_MDMA 22 +#define IRQ_DMAC1 23 +#define IRQ_DMAC0 24 +#define IRQ_TCU2 25 +#define IRQ_TCU1 26 +#define IRQ_TCU0 27 +#define IRQ_GPS 28 +#define IRQ_IPU 29 +#define IRQ_CIM 30 #define IRQ_LCD 31 -// 2nd-level interrupts -#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ -#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ +#define IRQ_RTC 32 +#define IRQ_OWI 33 +#define IRQ_AIC 34 +#define IRQ_MSC2 35 +#define IRQ_MSC1 36 +#define IRQ_MSC0 37 +#define IRQ_SCC 38 +#define IRQ_BCH 39 +#define IRQ_PCM 40 +// 2nd-level interrupts +#define IRQ_DMA_0 64 /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */ +#define IRQ_DMA_1 (IRQ_DMA_0 + HALF_DMA_NUM) /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */ +#define IRQ_MDMA_0 (IRQ_DMA_0 + MAX_DMA_NUM) /* 64 ~ 66 for MDMAC channel 0 ~ 2 */ + +#define IRQ_GPIO_0 96 /* 96 to 287 for GPIO pin 0 to 127 */ + +#define NUM_INTC 41 +#define NUM_DMA MAX_DMA_NUM /* 12 */ +#define NUM_MDMA MAX_MDMA_NUM /* 3 */ +#define NUM_GPIO MAX_GPIO_NUM /* GPIO NUM: 192, Jz4760 real num GPIO 178 */ /************************************************************************* * RTC @@ -241,6 +261,7 @@ static inline u32 jz_readl(u32 address) #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ +#define RTC_WENR (RTC_BASE + 0x3c) /* Write enable pattern register */ #define REG_RTC_RCR REG32(RTC_RCR) #define REG_RTC_RSR REG32(RTC_RSR) @@ -252,6 +273,7 @@ static inline u32 jz_readl(u32 address) #define REG_RTC_HWCR REG32(RTC_HWCR) #define REG_RTC_HWRSR REG32(RTC_HWRSR) #define REG_RTC_HSPR REG32(RTC_HSPR) +#define REG_RTC_WENR REG32(RTC_WENR) /* RTC Control Register */ #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ @@ -289,113 +311,230 @@ static inline u32 jz_readl(u32 address) #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ +/* Write enable pattern register */ +#define RTC_WENR_WEN (1 << 31) /* write has been enabled */ +#define RTC_WENR_WENPAT_BIT 0 +#define RTC_WENR_WENPAT_MASK (0xffff << RTC_WENR_WENPAT_BIT) /* The write enable pattern. */ + /************************************************************************* * CPM (Clock reset and Power control Management) *************************************************************************/ -#define CPM_CPCCR (CPM_BASE+0x00) -#define CPM_CPPCR (CPM_BASE+0x10) -#define CPM_CPPSR (CPM_BASE+0x14) /* PLL Switch and Status Register */ -#define CPM_I2SCDR (CPM_BASE+0x60) -#define CPM_LPCDR (CPM_BASE+0x64) -#define CPM_MSCCDR(n) (CPM_BASE+0x10*(n)+0x68) /* MSC0(n=0) or MSC1(n=1) device clock divider Register */ -#define CPM_UHCCDR (CPM_BASE+0x6C) -#define CPM_SSICDR (CPM_BASE+0x74) -#define CPM_PCMCDR (CPM_BASE+0x7C) /* PCM device clock divider Register */ +#define CPM_CPCCR (CPM_BASE+0x00) /* Clock control register */ +#define CPM_CPPCR (CPM_BASE+0x10) /* PLL control register 0 */ +#define CPM_CPPSR (CPM_BASE+0x14) /* PLL switch and status Register */ +#define CPM_CPPCR1 (CPM_BASE+0x30) /* PLL control register 1 */ +#define CPM_CPSPR (CPM_BASE+0x34) /* CPM scratch pad register */ +#define CPM_CPSPPR (CPM_BASE+0x38) /* CPM scratch protected register */ +#define CPM_USBPCR (CPM_BASE+0x3c) /* USB parameter control register */ +#define CPM_USBRDT (CPM_BASE+0x40) /* USB reset detect timer register */ +#define CPM_USBVBFIL (CPM_BASE+0x44) /* USB jitter filter register */ +#define CPM_USBCDR (CPM_BASE+0x50) /* USB OTG PHY clock divider register */ +#define CPM_I2SCDR (CPM_BASE+0x60) /* I2S device clock divider register */ +#define CPM_LPCDR (CPM_BASE+0x64) /* LCD pix clock divider register */ +#define CPM_MSCCDR (CPM_BASE+0x68) /* MSC clock divider register */ +#define CPM_UHCCDR (CPM_BASE+0x6C) /* UHC 48M clock divider register */ +#define CPM_SSICDR (CPM_BASE+0x74) /* SSI clock divider register */ +#define CPM_CIMCDR (CPM_BASE+0x7c) /* CIM MCLK clock divider register */ +#define CPM_GPSCDR (CPM_BASE+0x80) /* GPS clock divider register */ +#define CPM_PCMCDR (CPM_BASE+0x84) /* PCM device clock divider register */ +#define CPM_GPUCDR (CPM_BASE+0x88) /* GPU clock divider register */ -#define CPM_LCR (CPM_BASE+0x04) -#define CPM_CLKGR (CPM_BASE+0x20) -#define CPM_OPCR (CPM_BASE+0x24) /* Oscillator and Power Control Register */ +#define CPM_LCR (CPM_BASE+0x04) +#define CPM_PSWCST(n) (CPM_BASE+0x4*(n)+0x90) +#define CPM_CLKGR0 (CPM_BASE+0x20) /* Clock Gate Register0 */ +#define CPM_CLKGR1 (CPM_BASE+0x28) /* Clock Gate Register1 */ +#define CPM_OPCR (CPM_BASE+0x24) /* Oscillator and Power Control Register */ -#define CPM_RSR (CPM_BASE+0x08) +#define CPM_RSR (CPM_BASE+0x08) -#define REG_CPM_CPCCR REG32(CPM_CPCCR) -#define REG_CPM_CPPCR REG32(CPM_CPPCR) -#define REG_CPM_CPPSR REG32(CPM_CPPSR) -#define REG_CPM_I2SCDR REG32(CPM_I2SCDR) -#define REG_CPM_LPCDR REG32(CPM_LPCDR) -#define REG_CPM_MSCCDR(n) REG32(CPM_MSCCDR(n)) -#define REG_CPM_UHCCDR REG32(CPM_UHCCDR) -#define REG_CPM_SSICDR REG32(CPM_SSICDR) -#define REG_CPM_PCMCDR REG32(CPM_PCMCDR) + +#define REG_CPM_CPCCR REG32(CPM_CPCCR) +#define REG_CPM_CPPCR REG32(CPM_CPPCR) +#define REG_CPM_CPPSR REG32(CPM_CPPSR) +#define REG_CPM_CPPCR1 REG32(CPM_CPPCR1) +#define REG_CPM_CPSPR REG32(CPM_CPSPR) +#define REG_CPM_CPSPPR REG32(CPM_CPSPPR) +#define REG_CPM_USBPCR REG32(CPM_USBPCR) +#define REG_CPM_USBRDT REG32(CPM_USBRDT) +#define REG_CPM_USBVBFIL REG32(CPM_USBVBFIL) +#define REG_CPM_USBCDR REG32(CPM_USBCDR) +#define REG_CPM_I2SCDR REG32(CPM_I2SCDR) +#define REG_CPM_LPCDR REG32(CPM_LPCDR) +#define REG_CPM_MSCCDR REG32(CPM_MSCCDR) +#define REG_CPM_UHCCDR REG32(CPM_UHCCDR) +#define REG_CPM_SSICDR REG32(CPM_SSICDR) +#define REG_CPM_CIMCDR REG32(CPM_CIMCDR) +#define REG_CPM_GPSCDR REG32(CPM_GPSCDR) +#define REG_CPM_PCMCDR REG32(CPM_PCMCDR) +#define REG_CPM_GPUCDR REG32(CPM_GPUCDR) #define REG_CPM_LCR REG32(CPM_LCR) -#define REG_CPM_CLKGR REG32(CPM_CLKGR) +#define REG_CPM_CLKGR0 REG32(CPM_CLKGR0) +#define REG_CPM_CLKGR1 REG32(CPM_CLKGR1) #define REG_CPM_OPCR REG32(CPM_OPCR) #define REG_CPM_RSR REG32(CPM_RSR) +/* Clock control register */ +#define CPM_CPCCR_ECS (0x01 << 31) +#define CPM_CPCCR_MEM (0x01 << 30) +#define CPM_CPCCR_SDIV_BIT 24 +#define CPM_CPCCR_SDIV_MASK (0x0f << CPM_CPCCR_SDIV_BIT) +#define CPM_CPCCR_CE (0x01 << 22) +#define CPM_CPCCR_PCS (0x01 << 21) +#define CPM_CPCCR_H2DIV_BIT 16 +#define CPM_CPCCR_H2DIV_MASK (0x0f << CPM_CPCCR_H2DIV_BIT) +#define CPM_CPCCR_MDIV_BIT 12 +#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) +#define CPM_CPCCR_PDIV_BIT 8 +#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) +#define CPM_CPCCR_HDIV_BIT 4 +#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) +#define CPM_CPCCR_CDIV_BIT 0 +#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) -/* Clock Control Register */ -#define CPM_CPCCR_I2CS (1 << 31) -#define CPM_CPCCR_ECS (1 << 30) /* Select the between EXCLK and EXCLK/2 output */ -#define CPM_CPCCR_UCS (1 << 29) -#define CPM_CPCCR_UDIV_BIT 23 -#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) -#define CPM_CPCCR_CE (1 << 22) -#define CPM_CPCCR_PCS (1 << 21) -#define CPM_CPCCR_LDIV_BIT 16 -#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) -#define CPM_CPCCR_MDIV_BIT 12 -#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) -#define CPM_CPCCR_PDIV_BIT 8 -#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) -#define CPM_CPCCR_HDIV_BIT 4 -#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) -#define CPM_CPCCR_CDIV_BIT 0 -#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) +/* PLL control register 0 */ +#define CPM_CPPCR_PLLM_BIT 24 +#define CPM_CPPCR_PLLM_MASK (0x7f << CPM_CPPCR_PLLM_BIT) +#define CPM_CPPCR_PLLN_BIT 18 +#define CPM_CPPCR_PLLN_MASK (0x0f << CPM_CPPCR_PLLN_BIT) +#define CPM_CPPCR_PLLOD_BIT 16 +#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) +#define CPM_CPPCR_LOCK0 (1 << 15) +#define CPM_CPPCR_ENLOCK (1 << 14) +#define CPM_CPPCR_PLLS (1 << 10) +#define CPM_CPPCR_PLLBP (1 << 9) +#define CPM_CPPCR_PLLEN (1 << 8) +#define CPM_CPPCR_PLLST_BIT 0 +#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) -/* PLL Switch and Status Register */ -#define CPM_CPPSR_PLLOFF 31 -#define CPM_CPPSR_PLLBP 30 -#define CPM_CPPSR_PLLON 29 -#define CPM_CPPSR_PS 28 /* Indicate whether the PLL parameters' change has finished */ -#define CPM_CPPSR_FS 27 /* Indicate whether the main clock's change has finished */ -#define CPM_CPPSR_CS 26 /* Indicate whether the clock switch has finished */ -#define CPM_CPPSR_PM 1 /* Clock switch mode */ -#define CPM_CPPSR_FM 0 /* Clock frequency change mode */ +/* PLL control register 1 */ +#define CPM_CPPCR1_PLL1M_BIT 24 +#define CPM_CPPCR1_PLL1M_MASK (0x7f << CPM_CPPCR1_PLL1M_BIT) +#define CPM_CPPCR1_PLL1N_BIT 18 +#define CPM_CPPCR1_PLL1N_MASK (0x0f << CPM_CPPCR1_PLL1N_BIT) +#define CPM_CPPCR1_PLL1OD_BIT 16 +#define CPM_CPPCR1_PLL1OD_MASK (0x03 << CPM_CPPCR1_PLL1OD_BIT) +#define CPM_CPPCR1_P1SCS (1 << 15) +#define CPM_CPPCR1_P1SDIV_BIT 9 +#define CPM_CPPCR1_P1SDIV_MASK (0x3f << CPM_CPPCR1_P1SDIV_BIT) +#define CPM_CPPCR1_PLL1EN (1 << 7) +#define CPM_CPPCR1_PLL1S (1 << 6) +#define CPM_CPPCR1_LOCK1 (1 << 2) +#define CPM_CPPCR1_PLL1OFF (1 << 1) +#define CPM_CPPCR1_PLL1ON (1 << 0) -/* I2S Clock Divider Register */ -#define CPM_I2SCDR_I2SDIV_BIT 0 -#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) +/* PLL switch and status Register */ +#define CPM_CPPSR_PLLOFF (1 << 31) +#define CPM_CPPSR_PLLBP (1 << 30) +#define CPM_CPPSR_PLLON (1 << 29) +#define CPM_CPPSR_PS (1 << 28) +#define CPM_CPPSR_FS (1 << 27) +#define CPM_CPPSR_CS (1 << 26) +#define CPM_CPPSR_SM (1 << 2) +#define CPM_CPPSR_PM (1 << 1) +#define CPM_CPPSR_FM (1 << 0) -/* LCD Pixel Clock Divider Register */ -#define CPM_LPCDR_LSCS 31 /* TV encoder Source Pixel Clock Selection */ -#define CPM_LPCDR_LPCS 30 /* LCD Panel pix clock Selection */ -#define CPM_LPCDR_LTCS 29 /* LCD TV Encoder or Panel pix clock Selection */ -#define CPM_LPCDR_PIXDIV_BIT 0 -#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT) +/* CPM scratch protected register */ +#define CPM_CPSPPR_BIT 0 +#define CPM_CPSPPR_MASK (0xffff << CPM_CPSPPR_BIT) -/* MSC Clock Divider Register */ -#define CPM_MSCCDR_MSCDIV_BIT 0 -#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) +/* USB parameter control register */ +#define CPM_USBPCR_USB_MODE (1 << 31) /* 1: OTG, 0: UDC*/ +#define CPM_USBPCR_AVLD_REG (1 << 30) +#define CPM_USBPCR_IDPULLUP_MASK_BIT 28 +#define CPM_USBPCR_IDPULLUP_MASK_MASK (0x02 << IDPULLUP_MASK_BIT) +#define CPM_USBPCR_INCR_MASK (1 << 27) +#define CPM_USBPCR_CLK12_EN (1 << 26) +#define CPM_USBPCR_COMMONONN (1 << 25) +#define CPM_USBPCR_VBUSVLDEXT (1 << 24) +#define CPM_USBPCR_VBUSVLDEXTSEL (1 << 23) +#define CPM_USBPCR_POR (1 << 22) +#define CPM_USBPCR_SIDDQ (1 << 21) +#define CPM_USBPCR_OTG_DISABLE (1 << 20) +#define CPM_USBPCR_COMPDISTUNE_BIT 17 +#define CPM_USBPCR_COMPDISTUNE_MASK (0x07 << COMPDISTUNE_BIT) +#define CPM_USBPCR_OTGTUNE_BIT 14 +#define CPM_USBPCR_OTGTUNE_MASK (0x07 << OTGTUNE_BIT) +#define CPM_USBPCR_SQRXTUNE_BIT 11 +#define CPM_USBPCR_SQRXTUNE_MASK (0x7x << SQRXTUNE_BIT) +#define CPM_USBPCR_TXFSLSTUNE_BIT 7 +#define CPM_USBPCR_TXFSLSTUNE_MASK (0x0f << TXFSLSTUNE_BIT) +#define CPM_USBPCR_TXPREEMPHTUNE (1 << 6) +#define CPM_USBPCR_TXRISETUNE_BIT 4 +#define CPM_USBPCR_TXRISETUNE_MASK (0x03 << TXRISETUNE_BIT) +#define CPM_USBPCR_TXVREFTUNE_BIT 0 +#define CPM_USBPCR_TXVREFTUNE_MASK (0x0f << TXVREFTUNE_BIT) -/* UHC Clock Divider Register */ -#define CPM_UHCCDR_UHCDIV_BIT 0 -#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT) +/* USB reset detect timer register */ +#define CPM_USBRDT_VBFIL_LD_EN (1 << 25) +#define CPM_USBRDT_IDDIG_EN (1 << 24) +#define CPM_USBRDT_IDDIG_REG (1 << 23) +#define CPM_USBRDT_USBRDT_BIT 0 +#define CPM_USBRDT_USBRDT_MASK (0x7fffff << CPM_USBRDT_USBRDT_BIT) -/* SSI Clock Divider Register */ -#define CPM_SSICDR_SSIDIV_BIT 0 -#define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT) +/* USB OTG PHY clock divider register */ +#define CPM_USBCDR_UCS (1 << 31) +#define CPM_USBCDR_UPCS (1 << 30) +#define CPM_USBCDR_OTGDIV_BIT 0 +#define CPM_USBCDR_OTGDIV_MASK (0x3f << CPM_USBCDR_OTGDIV_BIT) -/* PCM device clock divider Register */ -#define CPM_PCMCDR_PCMS 31 /* PCM source clock Selection */ -#define CPM_PCMCDR_PCMCD_BIT 0 -#define CPM_PCMCDR_PCMCD_MASK (0x1ff << CPM_PCMCDR_PCMCD_BIT) +/* I2S device clock divider register */ +#define CPM_I2SCDR_I2CS (1 << 31) +#define CPM_I2SCDR_I2PCS (1 << 30) +#define CPM_I2SCDR_I2SDIV_BIT 0 +#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) -/* PLL Control Register */ -#define CPM_CPPCR_PLLM_BIT 23 -#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) -#define CPM_CPPCR_PLLN_BIT 18 -#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) -#define CPM_CPPCR_PLLOD_BIT 16 -#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) -#define CPM_CPPCR_PLLS (1 << 10) /* obsolete, replaced by CPM_CPPSR_PLLON */ -#define CPM_CPPCR_PLLBP (1 << 9) -#define CPM_CPPCR_PLLEN (1 << 8) -#define CPM_CPPCR_PLLST_BIT 0 -#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) +/* LCD pix clock divider register */ +#define CPM_LPCDR_LSCS (1 << 31) +#define CPM_LPCDR_LTCS (1 << 30) +#define CPM_LPCDR_LPCS (1 << 29) +#define CPM_LPCDR_PIXDIV_BIT 0 +#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT) + +/* MSC clock divider register */ +#define CPM_MSCCDR_MCS (1 << 31) +#define CPM_MSCCDR_MSCDIV_BIT 0 +#define CPM_MSCCDR_MSCDIV_MASK (0x3f << CPM_MSCCDR_PIXDIV_BIT) + +/* UHC 48M clock divider register */ +#define CPM_UHCCDR_UHPCS (1 << 31) +#define CPM_UHCCDR_UHCDIV_BIT 0 +#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT) + +/* SSI clock divider register */ +#define CPM_SSICDR_SCS (1 << 31) +#define CPM_SSICDR_SSIDIV_BIT 0 +#define CPM_SSICDR_SSIDIV_MASK (0x3f << CPM_SSICDR_SSIDIV_BIT) + +/* CIM MCLK clock divider register */ +#define CPM_CIMCDR_CIMDIV_BIT 0 +#define CPM_CIMCDR_CIMDIV_MASK (0xff << CPM_CIMCDR_CIMDIV_BIT) + +/* GPS clock divider register */ +#define CPM_GPSCDR_GPCS (1 << 31) +#define CPM_GPSCDR_GPSDIV_BIT 0 +#define CPM_GSPCDR_GPSDIV_MASK (0xf << CPM_GPSCDR_GPSDIV_BIT) + +/* PCM device clock divider register */ +#define CPM_PCMCDR_PCMS (1 << 31) +#define CPM_PCMCDR_PCMPCS (1 << 30) +#define CPM_PCMCDR_PCMDIV_BIT 0 +#define CPM_PCMCDR_PCMDIV_MASK (0x1ff << CPM_PCMCDR_PCMDIV_BIT) + +/* GPU clock divider register */ +#define CPM_GPUCDR_GPCS (1 << 31) +#define CPM_GPUCDR_GPUDIV_BIT 0 +#define CPM_GPUCDR_GPUDIV_MASK (0x7 << CPM_GPUCDR_GPUDIV_BIT) /* Low Power Control Register */ +#define CPM_LCR_PD_AHB1 (1 << 30) +#define CPM_LCR_VBAT_IR (1 << 29) +#define CPM_LCR_PD_GPS (1 << 28) +#define CPM_LCR_PD_AHB1S (1 << 26) +#define CPM_LCR_PD_GPSS (1 << 24) +#define CPM_LCR_PST_BIT 8 +#define CPM_LCR_PST_MASK (0xfff << CPM_LCR_PST_BIT) #define CPM_LCR_DOZE_DUTY_BIT 3 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) #define CPM_LCR_DOZE_ON (1 << 2) @@ -404,49 +543,65 @@ static inline u32 jz_readl(u32 address) #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) -/* Clock Gate Register */ -#define CPM_CLKGR_CIMRAM (1 << 28) -#define CPM_CLKGR_IDCT (1 << 27) -#define CPM_CLKGR_DB (1 << 26) -#define CPM_CLKGR_ME (1 << 25) -#define CPM_CLKGR_MC (1 << 24) -#define CPM_CLKGR_TVE (1 << 23) -#define CPM_CLKGR_TSSI (1 << 22) -#define CPM_CLKGR_OWI (1 << 21) -#define CPM_CLKGR_PCM (1 << 20) -#define CPM_CLKGR_MSC1 (1 << 19) -#define CPM_CLKGR_SSI0 (1 << 18) -#define CPM_CLKGR_UART3 (1 << 17) -#define CPM_CLKGR_UART2 (1 << 16) -#define CPM_CLKGR_UART1 (1 << 15) -#define CPM_CLKGR_UHC (1 << 14) -#define CPM_CLKGR_IPU (1 << 13) -#define CPM_CLKGR_DMAC (1 << 12) -#define CPM_CLKGR_UDC (1 << 11) -#define CPM_CLKGR_LCD (1 << 10) -#define CPM_CLKGR_CIM (1 << 9) -#define CPM_CLKGR_SADC (1 << 8) -#define CPM_CLKGR_MSC0 (1 << 7) -#define CPM_CLKGR_AIC1 (1 << 6) -#define CPM_CLKGR_AIC2 (1 << 5) -#define CPM_CLKGR_SSI1 (1 << 4) -#define CPM_CLKGR_I2C (1 << 3) -#define CPM_CLKGR_RTC (1 << 2) -#define CPM_CLKGR_TCU (1 << 1) -#define CPM_CLKGR_UART0 (1 << 0) +/* Clock Gate Register0 */ +#define CPM_CLKGR0_EMC (1 << 31) +#define CPM_CLKGR0_DDR (1 << 30) +#define CPM_CLKGR0_IPU (1 << 29) +#define CPM_CLKGR0_LCD (1 << 28) +#define CPM_CLKGR0_TVE (1 << 27) +#define CPM_CLKGR0_CIM (1 << 26) +#define CPM_CLKGR0_MDMA (1 << 25) +#define CPM_CLKGR0_UHC (1 << 24) +#define CPM_CLKGR0_MAC (1 << 23) +#define CPM_CLKGR0_GPS (1 << 22) +#define CPM_CLKGR0_DMAC (1 << 21) +#define CPM_CLKGR0_SSI2 (1 << 20) +#define CPM_CLKGR0_SSI1 (1 << 19) +#define CPM_CLKGR0_UART3 (1 << 18) +#define CPM_CLKGR0_UART2 (1 << 17) +#define CPM_CLKGR0_UART1 (1 << 16) +#define CPM_CLKGR0_UART0 (1 << 15) +#define CPM_CLKGR0_SADC (1 << 14) +#define CPM_CLKGR0_KBC (1 << 13) +#define CPM_CLKGR0_MSC2 (1 << 12) +#define CPM_CLKGR0_MSC1 (1 << 11) +#define CPM_CLKGR0_OWI (1 << 10) +#define CPM_CLKGR0_TSSI (1 << 9) +#define CPM_CLKGR0_AIC (1 << 8) +#define CPM_CLKGR0_SCC (1 << 7) +#define CPM_CLKGR0_I2C1 (1 << 6) +#define CPM_CLKGR0_I2C0 (1 << 5) +#define CPM_CLKGR0_SSI0 (1 << 4) +#define CPM_CLKGR0_MSC0 (1 << 3) +#define CPM_CLKGR0_OTG (1 << 2) +#define CPM_CLKGR0_BCH (1 << 1) +#define CPM_CLKGR0_NEMC (1 << 0) + +/* Clock Gate Register1 */ +#define CPM_CLKGR1_GPU (1 << 9) +#define CPM_CLKGR1_PCM (1 << 8) +#define CPM_CLKGR1_AHB1 (1 << 7) +#define CPM_CLKGR1_CABAC (1 << 6) +#define CPM_CLKGR1_SRAM (1 << 5) +#define CPM_CLKGR1_DCT (1 << 4) +#define CPM_CLKGR1_ME (1 << 3) +#define CPM_CLKGR1_DBLK (1 << 2) +#define CPM_CLKGR1_MC (1 << 1) +#define CPM_CLKGR1_BDMA (1 << 0) /* Oscillator and Power Control Register */ #define CPM_OPCR_O1ST_BIT 8 -#define CPM_OPCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) -#define CPM_OPCR_UHCPHY_DISABLE (1 << 7) -#define CPM_OPCR_UDCPHY_ENABLE (1 << 6) -#define CPM_OPCR_OSC_ENABLE (1 << 4) -#define CPM_OPCR_ERCS (1 << 2) /* EXCLK/512 clock and RTCLK clock selection */ -#define CPM_OPCR_MOSE (1 << 1) /* Main Oscillator Enable */ -#define CPM_OPCR_MCS (1 << 0) /* Main clock source select register */ +#define CPM_OPCR_O1ST_MASK (0xff << CPM_OPCR_O1ST_BIT) +#define CPM_OPCR_SPENDN (1 << 7) +#define CPM_OPCR_GPSEN (1 << 6) +#define CPM_OPCR_SPENDH (1 << 5) +#define CPM_OPCR_O1SE (1 << 4) /* */ +#define CPM_OPCR_ERCS (1 << 2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */ +#define CPM_OPCR_USBM (1 << 0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */ + /* Reset Status Register */ -#define CPM_RSR_HR (1 << 2) +#define CPM_RSR_P0R (1 << 2) #define CPM_RSR_WR (1 << 1) #define CPM_RSR_PR (1 << 0) @@ -703,6 +858,43 @@ static inline u32 jz_readl(u32 address) #define WDT_TCER_TCEN (1 << 0) +/************************************************************************* + * MDMAC (MEM Copy DMA Controller) + *************************************************************************/ + +#define MAX_MDMA_NUM 3 /* max 3 channels */ + +/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */ + +#define MDMAC_DSAR(n) (MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ +#define MDMAC_DTAR(n) (MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ +#define MDMAC_DTCR(n) (MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ +#define MDMAC_DRSR(n) (MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ +#define MDMAC_DCCSR(n) (MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ +#define MDMAC_DCMD(n) (MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ +#define MDMAC_DDA(n) (MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ +#define MDMAC_DSD(n) (MDMAC_BASE + (0xc0 + (n) * 0x04)) /* DMA Stride Address */ + +#define MDMAC_DMACR (MDMAC_BASE + 0x0300) /* DMA control register */ +#define MDMAC_DMAIPR (MDMAC_BASE + 0x0304) /* DMA interrupt pending */ +#define MDMAC_DMADBR (MDMAC_BASE + 0x0308) /* DMA doorbell */ +#define MDMAC_DMADBSR (MDMAC_BASE + 0x030C) /* DMA doorbell set */ +#define MDMAC_DMACKE (MDMAC_BASE + 0x0310) + +#define REG_MDMAC_DSAR(n) REG32(MDMAC_DSAR((n))) +#define REG_MDMAC_DTAR(n) REG32(MDMAC_DTAR((n))) +#define REG_MDMAC_DTCR(n) REG32(MDMAC_DTCR((n))) +#define REG_MDMAC_DRSR(n) REG32(MDMAC_DRSR((n))) +#define REG_MDMAC_DCCSR(n) REG32(MDMAC_DCCSR((n))) +#define REG_MDMAC_DCMD(n) REG32(MDMAC_DCMD((n))) +#define REG_MDMAC_DDA(n) REG32(MDMAC_DDA((n))) +#define REG_MDMAC_DSD(n) REG32(MDMAC_DSD(n)) +#define REG_MDMAC_DMACR REG32(MDMAC_DMACR) +#define REG_MDMAC_DMAIPR REG32(MDMAC_DMAIPR) +#define REG_MDMAC_DMADBR REG32(MDMAC_DMADBR) +#define REG_MDMAC_DMADBSR REG32(MDMAC_DMADBSR) +#define REG_MDMAC_DMACKE REG32(MDMAC_DMACKE) + /************************************************************************* * DMAC (DMA Controller) @@ -726,6 +918,7 @@ static inline u32 jz_readl(u32 address) #define DMAC_DMAIPR(m) (DMAC_BASE + 0x0304 + 0x100 * m) /* DMA interrupt pending */ #define DMAC_DMADBR(m) (DMAC_BASE + 0x0308 + 0x100 * m) /* DMA doorbell */ #define DMAC_DMADBSR(m) (DMAC_BASE + 0x030C + 0x100 * m) /* DMA doorbell set */ +#define DMAC_DMADCKE(m) (DMAC_BASE + 0x0310 + 0x100 * m) #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) @@ -739,6 +932,7 @@ static inline u32 jz_readl(u32 address) #define REG_DMAC_DMAIPR(m) REG32(DMAC_DMAIPR(m)) #define REG_DMAC_DMADBR(m) REG32(DMAC_DMADBR(m)) #define REG_DMAC_DMADBSR(m) REG32(DMAC_DMADBSR(m)) +#define REG_DMAC_DMADCKE(m) REG32(DMAC_DMADCKE(m)) // DMA request source register #define DMAC_DRSR_RS_BIT 0 @@ -835,6 +1029,7 @@ static inline u32 jz_readl(u32 address) #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) + #define DMAC_DCMD_DS_64BYTE (5 << DMAC_DCMD_DS_BIT) #define DMAC_DCMD_STDE (1 << 5) /* Stride Disable/Enable */ #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ @@ -1415,14 +1610,14 @@ static inline u32 jz_readl(u32 address) /************************************************************************* * SSI (Synchronous Serial Interface) *************************************************************************/ -/* n = 0, 1 (SSI0, SSI1) */ -#define SSI_DR(n) (SSI_BASE + 0x000 + (n)*0x2000) -#define SSI_CR0(n) (SSI_BASE + 0x004 + (n)*0x2000) -#define SSI_CR1(n) (SSI_BASE + 0x008 + (n)*0x2000) -#define SSI_SR(n) (SSI_BASE + 0x00C + (n)*0x2000) -#define SSI_ITR(n) (SSI_BASE + 0x010 + (n)*0x2000) -#define SSI_ICR(n) (SSI_BASE + 0x014 + (n)*0x2000) -#define SSI_GR(n) (SSI_BASE + 0x018 + (n)*0x2000) +/* n = 0, 1, 2 (SSI0, SSI1, SSI2) */ +#define SSI_DR(n) (SSI##n##_BASE + 0x000) +#define SSI_CR0(n) (SSI##n##_BASE + 0x004) +#define SSI_CR1(n) (SSI##n##_BASE + 0x008) +#define SSI_SR(n) (SSI##n##_BASE + 0x00C) +#define SSI_ITR(n) (SSI##n##_BASE + 0x010) +#define SSI_ICR(n) (SSI##n##_BASE + 0x014) +#define SSI_GR(n) (SSI##n##_BASE + 0x018) #define REG_SSI_DR(n) REG32(SSI_DR(n)) #define REG_SSI_CR0(n) REG16(SSI_CR0(n)) @@ -1553,22 +1748,22 @@ static inline u32 jz_readl(u32 address) /************************************************************************* * MSC *************************************************************************/ -#define MSC_STRPCL (MSC_BASE + 0x000) -#define MSC_STAT (MSC_BASE + 0x004) -#define MSC_CLKRT (MSC_BASE + 0x008) -#define MSC_CMDAT (MSC_BASE + 0x00C) -#define MSC_RESTO (MSC_BASE + 0x010) -#define MSC_RDTO (MSC_BASE + 0x014) -#define MSC_BLKLEN (MSC_BASE + 0x018) -#define MSC_NOB (MSC_BASE + 0x01C) -#define MSC_SNOB (MSC_BASE + 0x020) -#define MSC_IMASK (MSC_BASE + 0x024) -#define MSC_IREG (MSC_BASE + 0x028) -#define MSC_CMD (MSC_BASE + 0x02C) -#define MSC_ARG (MSC_BASE + 0x030) -#define MSC_RES (MSC_BASE + 0x034) -#define MSC_RXFIFO (MSC_BASE + 0x038) -#define MSC_TXFIFO (MSC_BASE + 0x03C) +#define MSC_STRPCL (MSC0_BASE + 0x000) +#define MSC_STAT (MSC0_BASE + 0x004) +#define MSC_CLKRT (MSC0_BASE + 0x008) +#define MSC_CMDAT (MSC0_BASE + 0x00C) +#define MSC_RESTO (MSC0_BASE + 0x010) +#define MSC_RDTO (MSC0_BASE + 0x014) +#define MSC_BLKLEN (MSC0_BASE + 0x018) +#define MSC_NOB (MSC0_BASE + 0x01C) +#define MSC_SNOB (MSC0_BASE + 0x020) +#define MSC_IMASK (MSC0_BASE + 0x024) +#define MSC_IREG (MSC0_BASE + 0x028) +#define MSC_CMD (MSC0_BASE + 0x02C) +#define MSC_ARG (MSC0_BASE + 0x030) +#define MSC_RES (MSC0_BASE + 0x034) +#define MSC_RXFIFO (MSC0_BASE + 0x038) +#define MSC_TXFIFO (MSC0_BASE + 0x03C) #define REG_MSC_STRPCL REG16(MSC_STRPCL) #define REG_MSC_STAT REG32(MSC_STAT) @@ -1687,48 +1882,27 @@ static inline u32 jz_readl(u32 address) #define MSC_IREG_PRG_DONE (1 << 1) #define MSC_IREG_DATA_TRAN_DONE (1 << 0) - /************************************************************************* - * EMC (External Memory Controller) + * EMC (External SDR Controller) *************************************************************************/ +#define EMC_LOW_SDRAM_SPACE_SIZE 0x10000000 /* 256M */ +#define EMC_MEM_PHY_BASE 0x20000000 +#define EMC_MEM_PHY_BASE_SHIFT 24 + + #define EMC_BCR (EMC_BASE + 0x0) /* BCR */ -#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ -#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ -#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ -#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ -#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ -#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ -#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ -#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ -#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ -#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ - -#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ - #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ + #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ #define EMC_DMAR1 (EMC_BASE + 0x94) /* SDRAM Bank 1 Addr Config Register */ #define EMC_SDMR0 (EMC_BASE + 0x8000) /* Mode Register of SDRAM bank 0 */ #define REG_EMC_BCR REG32(EMC_BCR) -#define REG_EMC_SMCR0 REG32(EMC_SMCR0) -#define REG_EMC_SMCR1 REG32(EMC_SMCR1) -#define REG_EMC_SMCR2 REG32(EMC_SMCR2) -#define REG_EMC_SMCR3 REG32(EMC_SMCR3) -#define REG_EMC_SMCR4 REG32(EMC_SMCR4) -#define REG_EMC_SACR0 REG32(EMC_SACR0) -#define REG_EMC_SACR1 REG32(EMC_SACR1) -#define REG_EMC_SACR2 REG32(EMC_SACR2) -#define REG_EMC_SACR3 REG32(EMC_SACR3) -#define REG_EMC_SACR4 REG32(EMC_SACR4) - -#define REG_EMC_NFCSR REG32(EMC_NFCSR) - #define REG_EMC_DMCR REG32(EMC_DMCR) #define REG_EMC_RTCSR REG16(EMC_RTCSR) #define REG_EMC_RTCNT REG16(EMC_RTCNT) @@ -1736,56 +1910,15 @@ static inline u32 jz_readl(u32 address) #define REG_EMC_DMAR0 REG32(EMC_DMAR0) #define REG_EMC_DMAR1 REG32(EMC_DMAR1) -/* Bus Control Register */ -#define EMC_BCR_BT_SEL_BIT 30 -#define EMC_BCR_BT_SEL_MASK (0x3 << EMC_BCR_BT_SEL_BIT) -#define EMC_BCR_PK_SEL (1 << 24) -#define EMC_BCR_BSR_MASK (1 << 2) /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */ - #define EMC_BCR_BSR_SHARE (0 << 2) - #define EMC_BCR_BSR_UNSHARE (1 << 2) -#define EMC_BCR_BRE (1 << 1) -#define EMC_BCR_ENDIAN (1 << 0) +#define EMC_PMEMPS0 (EMC_BASE + 0x6000) +#define EMC_PMEMPS1 (EMC_BASE + 0x6004) +#define EMC_PMEMPS2 (EMC_BASE + 0x6008) +#define EMC_PMEMPS3 (EMC_BASE + 0x600c) -/* Static Memory Control Register */ -#define EMC_SMCR_STRV_BIT 24 -#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) -#define EMC_SMCR_TAW_BIT 20 -#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) -#define EMC_SMCR_TBP_BIT 16 -#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) -#define EMC_SMCR_TAH_BIT 12 -#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) -#define EMC_SMCR_TAS_BIT 8 -#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) -#define EMC_SMCR_BW_BIT 6 -#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) -#define EMC_SMCR_BL_BIT 1 -#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) - -/* Static Memory Bank Addr Config Reg */ -#define EMC_SACR_BASE_BIT 8 -#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) -#define EMC_SACR_MASK_BIT 0 -#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) - -/* NAND Flash Control/Status Register */ -#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ -#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ -#define EMC_NFCSR_NFCE3 (1 << 5) -#define EMC_NFCSR_NFE3 (1 << 4) -#define EMC_NFCSR_NFCE2 (1 << 3) -#define EMC_NFCSR_NFE2 (1 << 2) -#define EMC_NFCSR_NFCE1 (1 << 1) -#define EMC_NFCSR_NFE1 (1 << 0) +#define REG_EMC_PMEMPS0 REG32(EMC_PMEMPS0) +#define REG_EMC_PMEMPS1 REG32(EMC_PMEMPS1) +#define REG_EMC_PMEMPS2 REG32(EMC_PMEMPS2) +#define REG_EMC_PMEMPS3 REG32(EMC_PMEMPS3) /* DRAM Control Register */ #define EMC_DMCR_BW_BIT 31 @@ -1845,7 +1978,7 @@ static inline u32 jz_readl(u32 address) #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) /* Mode Register of SDRAM bank 0 */ -#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ +#define EMC_SDMR_BM (1 << 9) /* Write Single Mode */ #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) @@ -1905,6 +2038,458 @@ static inline u32 jz_readl(u32 address) #define EMC_DMAR_MASK_64_64 (0xfc << EMC_DMAR_MASK_BIT) /*mask for two 64M SDRAM*/ #define EMC_DMAR_MASK_128_128 (0xf8 << EMC_DMAR_MASK_BIT) /*mask for two 128M SDRAM*/ + +/************************************************************************* + * NEMC (External Normal Memory Controller) + *************************************************************************/ +#define NEMC_BCR (NEMC_BASE + 0x0) /* BCR */ + +#define NEMC_SMCR1 (NEMC_BASE + 0x14) /* Static Memory Control Register 1 */ +#define NEMC_SMCR2 (NEMC_BASE + 0x18) /* Static Memory Control Register 2 */ +#define NEMC_SMCR3 (NEMC_BASE + 0x1c) /* Static Memory Control Register 3 */ +#define NEMC_SMCR4 (NEMC_BASE + 0x20) /* Static Memory Control Register 4 */ +#define NEMC_SMCR5 (NEMC_BASE + 0x24) /* Static Memory Control Register 5 */ +#define NEMC_SMCR6 (NEMC_BASE + 0x28) /* Static Memory Control Register 6 */ +#define NEMC_SACR1 (NEMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ +#define NEMC_SACR2 (NEMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ +#define NEMC_SACR3 (NEMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ +#define NEMC_SACR4 (NEMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ +#define NEMC_SACR5 (NEMC_BASE + 0x44) /* Static Memory Bank 5 Addr Config Reg */ +#define NEMC_SACR6 (NEMC_BASE + 0x48) /* Static Memory Bank 6 Addr Config Reg */ + +#define NEMC_NFCSR (NEMC_BASE + 0x050) /* NAND Flash Control/Status Register */ + +#define REG_NEMC_BCR REG32(NEMC_BCR) +#define REG_NEMC_SMCR1 REG32(NEMC_SMCR1) +#define REG_NEMC_SMCR2 REG32(NEMC_SMCR2) +#define REG_NEMC_SMCR3 REG32(NEMC_SMCR3) +#define REG_NEMC_SMCR4 REG32(NEMC_SMCR4) +#define REG_NEMC_SMCR5 REG32(NEMC_SMCR5) +#define REG_NEMC_SMCR6 REG32(NEMC_SMCR6) +#define REG_NEMC_SACR1 REG32(NEMC_SACR1) +#define REG_NEMC_SACR2 REG32(NEMC_SACR2) +#define REG_NEMC_SACR3 REG32(NEMC_SACR3) +#define REG_NEMC_SACR4 REG32(NEMC_SACR4) +#define REG_NEMC_SACR5 REG32(NEMC_SACR5) +#define REG_NEMC_SACR6 REG32(NEMC_SACR6) + + +#define REG_NEMC_NFCSR REG32(NEMC_NFCSR) + + +/* Bus Control Register */ +#define NEMC_BCR_BT_SEL_BIT 30 +#define NEMC_BCR_BT_SEL_MASK (0x3 << NEMC_BCR_BT_SEL_BIT) +#define NEMC_BCR_PK_SEL (1 << 24) +#define NEMC_BCR_BSR_MASK (1 << 2) /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */ + #define NEMC_BCR_BSR_SHARE (0 << 2) + #define NEMC_BCR_BSR_UNSHARE (1 << 2) +#define NEMC_BCR_BRE (1 << 1) +#define NEMC_BCR_ENDIAN (1 << 0) + +/* Static Memory Control Register */ +#define NEMC_SMCR_STRV_BIT 24 +#define NEMC_SMCR_STRV_MASK (0x0f << NEMC_SMCR_STRV_BIT) +#define NEMC_SMCR_TAW_BIT 20 +#define NEMC_SMCR_TAW_MASK (0x0f << NEMC_SMCR_TAW_BIT) +#define NEMC_SMCR_TBP_BIT 16 +#define NEMC_SMCR_TBP_MASK (0x0f << NEMC_SMCR_TBP_BIT) +#define NEMC_SMCR_TAH_BIT 12 +#define NEMC_SMCR_TAH_MASK (0x07 << NEMC_SMCR_TAH_BIT) +#define NEMC_SMCR_TAS_BIT 8 +#define NEMC_SMCR_TAS_MASK (0x07 << NEMC_SMCR_TAS_BIT) +#define NEMC_SMCR_BW_BIT 6 +#define NEMC_SMCR_BW_MASK (0x03 << NEMC_SMCR_BW_BIT) + #define NEMC_SMCR_BW_8BIT (0 << NEMC_SMCR_BW_BIT) + #define NEMC_SMCR_BW_16BIT (1 << NEMC_SMCR_BW_BIT) + #define NEMC_SMCR_BW_32BIT (2 << NEMC_SMCR_BW_BIT) +#define NEMC_SMCR_BCM (1 << 3) +#define NEMC_SMCR_BL_BIT 1 +#define NEMC_SMCR_BL_MASK (0x03 << NEMC_SMCR_BL_BIT) + #define NEMC_SMCR_BL_4 (0 << NEMC_SMCR_BL_BIT) + #define NEMC_SMCR_BL_8 (1 << NEMC_SMCR_BL_BIT) + #define NEMC_SMCR_BL_16 (2 << NEMC_SMCR_BL_BIT) + #define NEMC_SMCR_BL_32 (3 << NEMC_SMCR_BL_BIT) +#define NEMC_SMCR_SMT (1 << 0) + +/* Static Memory Bank Addr Config Reg */ +#define NEMC_SACR_BASE_BIT 8 +#define NEMC_SACR_BASE_MASK (0xff << NEMC_SACR_BASE_BIT) +#define NEMC_SACR_MASK_BIT 0 +#define NEMC_SACR_MASK_MASK (0xff << NEMC_SACR_MASK_BIT) + +/* NAND Flash Control/Status Register */ +#define NEMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ +#define NEMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ +#define NEMC_NFCSR_NFCE3 (1 << 5) +#define NEMC_NFCSR_NFE3 (1 << 4) +#define NEMC_NFCSR_NFCE2 (1 << 3) +#define NEMC_NFCSR_NFE2 (1 << 2) +#define NEMC_NFCSR_NFCE1 (1 << 1) +#define NEMC_NFCSR_NFE1 (1 << 0) + +/************************************************************************* + * DDRC (DDR Controller) + *************************************************************************/ +#define DDR_MEM_PHY_BASE 0x20000000 + +#define DDRC_ST (DDRC_BASE + 0x0) /* DDR Status Register */ +#define DDRC_CFG (DDRC_BASE + 0x4) /* DDR Configure Register */ +#define DDRC_CTRL (DDRC_BASE + 0x8) /* DDR Control Register */ +#define DDRC_LMR (DDRC_BASE + 0xc) /* DDR Load-Mode-Register */ +#define DDRC_TIMING1 (DDRC_BASE + 0x10) /* DDR Timing Config Register 1 */ +#define DDRC_TIMING2 (DDRC_BASE + 0x14) /* DDR Timing Config Register 2 */ +#define DDRC_REFCNT (DDRC_BASE + 0x18) /* DDR Auto-Refresh Counter */ +#define DDRC_DQS (DDRC_BASE + 0x1c) /* DDR DQS Delay Control Register */ +#define DDRC_DQS_ADJ (DDRC_BASE + 0x20) /* DDR DQS Delay Adjust Register */ +#define DDRC_MMAP0 (DDRC_BASE + 0x24) /* DDR Memory Map Config Register */ +#define DDRC_MMAP1 (DDRC_BASE + 0x28) /* DDR Memory Map Config Register */ +#define DDRC_MDELAY (DDRC_BASE + 0x2c) /* DDR Memory Map Config Register */ + +/* DDRC Register */ +#define REG_DDRC_ST REG32(DDRC_ST) +#define REG_DDRC_CFG REG32(DDRC_CFG) +#define REG_DDRC_CTRL REG32(DDRC_CTRL) +#define REG_DDRC_LMR REG32(DDRC_LMR) +#define REG_DDRC_TIMING1 REG32(DDRC_TIMING1) +#define REG_DDRC_TIMING2 REG32(DDRC_TIMING2) +#define REG_DDRC_REFCNT REG32(DDRC_REFCNT) +#define REG_DDRC_DQS REG32(DDRC_DQS) +#define REG_DDRC_DQS_ADJ REG32(DDRC_DQS_ADJ) +#define REG_DDRC_MMAP0 REG32(DDRC_MMAP0) +#define REG_DDRC_MMAP1 REG32(DDRC_MMAP1) +#define REG_DDRC_MDELAY REG32(DDRC_MDELAY) + +/* DDRC Status Register */ +#define DDRC_ST_ENDIAN (1 << 7) /* 0 Little data endian + 1 Big data endian */ +#define DDRC_ST_DPDN (1 << 5) /* 0 DDR memory is NOT in deep-power-down state + 1 DDR memory is in deep-power-down state */ +#define DDRC_ST_PDN (1 << 4) /* 0 DDR memory is NOT in power-down state + 1 DDR memory is in power-down state */ +#define DDRC_ST_AREF (1 << 3) /* 0 DDR memory is NOT in auto-refresh state + 1 DDR memory is in auto-refresh state */ +#define DDRC_ST_SREF (1 << 2) /* 0 DDR memory is NOT in self-refresh state + 1 DDR memory is in self-refresh state */ +#define DDRC_ST_CKE1 (1 << 1) /* 0 CKE1 Pin is low + 1 CKE1 Pin is high */ +#define DDRC_ST_CKE0 (1 << 0) /* 0 CKE0 Pin is low + 1 CKE0 Pin is high */ + +/* DDRC Configure Register */ +#define DDRC_CFG_MSEL_BIT 16 /* Mask delay select */ +#define DDRC_CFG_MSEL_MASK (0x3 << DDRC_CFG_MSEL_BIT) + #define DDRC_CFG_MSEL_0 (0 << DDRC_CFG_MSEL_BIT) /* 00 No delay */ + #define DDRC_CFG_MSEL_1 (1 << DDRC_CFG_MSEL_BIT) /* 01 delay 1 tCK */ + #define DDRC_CFG_MSEL_2 (2 << DDRC_CFG_MSEL_BIT) /* 10 delay 2 tCK */ + #define DDRC_CFG_MSEL_3 (3 << DDRC_CFG_MSEL_BIT) /* 11 delay 3 tCK */ + +#define DDRC_CFG_MPRT (1 << 15) /* mem protect */ + +#define DDRC_CFG_ROW1_BIT 27 /* Row Address width. */ +#define DDRC_CFG_COL1_BIT 25 /* Row Address width. */ +#define DDRC_CFG_BA1 (1 << 24) +#define DDRC_CFG_IMBA (1 << 23) +#define DDRC_CFG_BTRUN (1 << 21) + +#define DDRC_CFG_TYPE_BIT 12 +#define DDRC_CFG_TYPE_MASK (0x7 << DDRC_CFG_TYPE_BIT) +#define DDRC_CFG_TYPE_DDR1 (2 << DDRC_CFG_TYPE_BIT) +#define DDRC_CFG_TYPE_MDDR (3 << DDRC_CFG_TYPE_BIT) +#define DDRC_CFG_TYPE_DDR2 (4 << DDRC_CFG_TYPE_BIT) + +#define DDRC_CFG_ROW_BIT 10 /* Row Address width. */ +#define DDRC_CFG_ROW_MASK (0x3 << DDRC_CFG_ROW_BIT) + #define DDRC_CFG_ROW_13 (0 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */ + #define DDRC_CFG_ROW_14 (1 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */ + +#define DDRC_CFG_COL_BIT 8 /* Column Address width. + Specify the Column address width of external DDR. */ +#define DDRC_CFG_COL_MASK (0x3 << DDRC_CFG_COL_BIT) + #define DDRC_CFG_COL_9 (0 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */ + #define DDRC_CFG_COL_10 (1 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */ + +#define DDRC_CFG_CS1EN (1 << 7) /* 0 DDR Pin CS1 un-used + 1 There're DDR memory connected to CS1 */ +#define DDRC_CFG_CS0EN (1 << 6) /* 0 DDR Pin CS0 un-used + 1 There're DDR memory connected to CS0 */ + +#define DDRC_CFG_TSEL_BIT 18 /* Read delay select */ +#define DDRC_CFG_TSEL_MASK (0x3 << DDRC_CFG_TSEL_BIT) +#define DDRC_CFG_TSEL_0 (0 << DDRC_CFG_TSEL_BIT) /* No delay */ +#define DDRC_CFG_TSEL_1 (1 << DDRC_CFG_TSEL_BIT) /* delay 1 tCK */ +#define DDRC_CFG_TSEL_2 (2 << DDRC_CFG_TSEL_BIT) /* delay 2 tCK */ +#define DDRC_CFG_TSEL_3 (3 << DDRC_CFG_TSEL_BIT) /* delay 3 tCK */ + +#define DDRC_CFG_CL_BIT 2 /* CAS Latency */ +#define DDRC_CFG_CL_MASK (0xf << DDRC_CFG_CL_BIT) +#define DDRC_CFG_CL_3 (0 << DDRC_CFG_CL_BIT) /* CL = 3 tCK */ +#define DDRC_CFG_CL_4 (1 << DDRC_CFG_CL_BIT) /* CL = 4 tCK */ +#define DDRC_CFG_CL_5 (2 << DDRC_CFG_CL_BIT) /* CL = 5 tCK */ +#define DDRC_CFG_CL_6 (3 << DDRC_CFG_CL_BIT) /* CL = 6 tCK */ + +#define DDRC_CFG_BA (1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used + 1 8 bank device, Pin ba[2:0] valid*/ +#define DDRC_CFG_DW (1 << 0) /*0 External memory data width is 16-bit + 1 External memory data width is 32-bit */ + +/* DDRC Control Register */ +#define DDRC_CTRL_ACTPD (1 << 15) /* 0 Precharge all banks before entering power-down + 1 Do not precharge banks before entering power-down */ +#define DDRC_CTRL_PDT_BIT 12 /* Power-Down Timer */ +#define DDRC_CTRL_PDT_MASK (0x7 << DDRC_CTRL_PDT_BIT) + #define DDRC_CTRL_PDT_DIS (0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */ + #define DDRC_CTRL_PDT_8 (1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */ + #define DDRC_CTRL_PDT_16 (2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */ + #define DDRC_CTRL_PDT_32 (3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */ + #define DDRC_CTRL_PDT_64 (4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */ + #define DDRC_CTRL_PDT_128 (5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */ + +#define DDRC_CTRL_PRET_BIT 8 /* Precharge Timer */ +#define DDRC_CTRL_PRET_MASK (0x7 << DDRC_CTRL_PRET_BIT) /* */ + #define DDRC_CTRL_PRET_DIS (0 << DDRC_CTRL_PRET_BIT) /* PRET function Disabled */ + #define DDRC_CTRL_PRET_8 (1 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 8 tCK idle */ + #define DDRC_CTRL_PRET_16 (2 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 16 tCK idle */ + #define DDRC_CTRL_PRET_32 (3 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 32 tCK idle */ + #define DDRC_CTRL_PRET_64 (4 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 64 tCK idle */ + #define DDRC_CTRL_PRET_128 (5 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 128 tCK idle */ + +#define DDRC_CTRL_DPD (1 << 6) /* 1 Drive external DDR device entering self-refresh mode */ + +#define DDRC_CTRL_SR (1 << 5) /* 1 Drive external DDR device entering self-refresh mode + 0 Drive external DDR device exiting self-refresh mode */ +#define DDRC_CTRL_UNALIGN (1 << 4) /* 0 Disable unaligned transfer on AXI BUS + 1 Enable unaligned transfer on AXI BUS */ +#define DDRC_CTRL_ALH (1 << 3) /* Advanced Latency Hiding: + 0 Disable ALH + 1 Enable ALH */ +#define DDRC_CTRL_RDC (1 << 2) /* 0 dclk clock frequency is lower than 60MHz + 1 dclk clock frequency is higher than 60MHz */ +#define DDRC_CTRL_CKE (1 << 1) /* 0 Not set CKE Pin High + 1 Set CKE Pin HIGH */ +#define DDRC_CTRL_RESET (1 << 0) /* 0 End resetting ddrc_controller + 1 Resetting ddrc_controller */ + +/* DDRC Load-Mode-Register */ +#define DDRC_LMR_DDR_ADDR_BIT 16 /* When performing a DDR command, DDRC_ADDR[13:0] + corresponding to external DDR address Pin A[13:0] */ +#define DDRC_LMR_DDR_ADDR_MASK (0xff << DDRC_LMR_DDR_ADDR_BIT) + +#define DDRC_LMR_BA_BIT 8 /* When performing a DDR command, BA[2:0] + corresponding to external DDR address Pin BA[2:0]. */ +#define DDRC_LMR_BA_MASK (0x7 << DDRC_LMR_BA_BIT) + /* For DDR2 */ + #define DDRC_LMR_BA_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */ + #define DDRC_LMR_BA_EMRS1 (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register1 set */ + #define DDRC_LMR_BA_EMRS2 (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register2 set */ + #define DDRC_LMR_BA_EMRS3 (3 << DDRC_LMR_BA_BIT) /* Extended Mode Register3 set */ + /* For mobile DDR */ + #define DDRC_LMR_BA_M_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */ + #define DDRC_LMR_BA_M_EMRS (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */ + #define DDRC_LMR_BA_M_SR (1 << DDRC_LMR_BA_BIT) /* Status Register set */ + /* For Normal DDR1 */ + #define DDRC_LMR_BA_N_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */ + #define DDRC_LMR_BA_N_EMRS (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */ + +#define DDRC_LMR_CMD_BIT 4 +#define DDRC_LMR_CMD_MASK (0x3 << DDRC_LMR_CMD_BIT) + #define DDRC_LMR_CMD_PREC (0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */ + #define DDRC_LMR_CMD_AUREF (1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */ + #define DDRC_LMR_CMD_LMR (2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */ + +#define DDRC_LMR_START (1 << 0) /* 0 No command is performed + 1 On the posedge of START, perform a command + defined by CMD field */ + +/* DDRC Mode Register Set */ +#define DDR2_MRS_PD_BIT 10 /* Active power down exit time */ +#define DDR2_MRS_PD_MASK (1 << DDR_MRS_PD_BIT) + #define DDR2_MRS_PD_FAST_EXIT (0 << 10) + #define DDR2_MRS_PD_SLOW_EXIT (1 << 10) +#define DDR2_MRS_WR_BIT 9 /* Write Recovery for autoprecharge */ +#define DDR2_MRS_WR_MASK (7 << DDR_MRS_WR_BIT) +#define DDR2_MRS_DLL_RST (1 << 8) /* DLL Reset */ +#define DDR2_MRS_TM_BIT 7 /* Operating Mode */ +#define DDR2_MRS_TM_MASK (1 << DDR_MRS_TM_BIT) + #define DDR2_MRS_TM_NORMAL (0 << DDR_MRS_TM_BIT) + #define DDR2_MRS_TM_TEST (1 << DDR_MRS_TM_BIT) +#define DDR_MRS_CAS_BIT 4 /* CAS Latency */ +#define DDR_MRS_CAS_MASK (7 << DDR_MRS_CAS_BIT) +#define DDR_MRS_BT_BIT 3 /* Burst Type */ +#define DDR_MRS_BT_MASK (1 << DDR_MRS_BT_BIT) + #define DDR_MRS_BT_SEQ (0 << DDR_MRS_BT_BIT) /* Sequential */ + #define DDR_MRS_BT_INT (1 << DDR_MRS_BT_BIT) /* Interleave */ +#define DDR_MRS_BL_BIT 0 /* Burst Length */ +#define DDR_MRS_BL_MASK (7 << DDR_MRS_BL_BIT) + #define DDR_MRS_BL_4 (2 << DDR_MRS_BL_BIT) + #define DDR_MRS_BL_8 (3 << DDR_MRS_BL_BIT) + +/* DDR2 Extended Mode Register1 Set */ +#define DDR_EMRS1_QOFF (1<<12) /* 0 Output buffer enabled + 1 Output buffer disabled */ +#define DDR_EMRS1_RDQS_EN (1<<11) /* 0 Disable + 1 Enable */ +#define DDR_EMRS1_DQS_DIS (1<<10) /* 0 Enable + 1 Disable */ +#define DDR_EMRS1_OCD_BIT 7 /* Additive Latency 0 -> 6 */ +#define DDR_EMRS1_OCD_MASK (0x7 << DDR_EMRS1_OCD_BIT) + #define DDR_EMRS1_OCD_EXIT (0 << DDR_EMRS1_OCD_BIT) + #define DDR_EMRS1_OCD_D0 (1 << DDR_EMRS1_OCD_BIT) + #define DDR_EMRS1_OCD_D1 (2 << DDR_EMRS1_OCD_BIT) + #define DDR_EMRS1_OCD_ADJ (4 << DDR_EMRS1_OCD_BIT) + #define DDR_EMRS1_OCD_DFLT (7 << DDR_EMRS1_OCD_BIT) +#define DDR_EMRS1_AL_BIT 3 /* Additive Latency 0 -> 6 */ +#define DDR_EMRS1_AL_MASK (7 << DDR_EMRS1_AL_BIT) +#define DDR_EMRS1_RTT_BIT 2 /* */ +#define DDR_EMRS1_RTT_MASK (0x11 << DDR_EMRS1_DIC_BIT) /* Bit 6, Bit 2 */ +#define DDR_EMRS1_DIC_BIT 1 /* Output Driver Impedence Control */ +#define DDR_EMRS1_DIC_MASK (1 << DDR_EMRS1_DIC_BIT) /* 100% */ + #define DDR_EMRS1_DIC_NORMAL (0 << DDR_EMRS1_DIC_BIT) /* 60% */ + #define DDR_EMRS1_DIC_HALF (1 << DDR_EMRS1_DIC_BIT) +#define DDR_EMRS1_DLL_BIT 0 /* DLL Enable */ +#define DDR_EMRS1_DLL_MASK (1 << DDR_EMRS1_DLL_BIT) + #define DDR_EMRS1_DLL_EN (0 << DDR_EMRS1_DLL_BIT) + #define DDR_EMRS1_DLL_DIS (1 << DDR_EMRS1_DLL_BIT) + +/* Mobile SDRAM Extended Mode Register */ +#define DDR_EMRS_DS_BIT 5 /* Driver strength */ +#define DDR_EMRS_DS_MASK (3 << DDR_EMRS_DS_BIT) + #define DDR_EMRS_DS_FULL (0 << DDR_EMRS_DS_BIT) /*Full*/ + #define DDR_EMRS_DS_HALF (1 << DDR_EMRS_DS_BIT) /*1/2 Strength*/ + #define DDR_EMRS_DS_QUTR (2 << DDR_EMRS_DS_BIT) /*1/4 Strength*/ + +#define DDR_EMRS_PRSR_BIT 0 /* Partial Array Self Refresh */ +#define DDR_EMRS_PRSR_MASK (7 << DDR_EMRS_PRSR_BIT) + #define DDR_EMRS_PRSR_ALL (0 << DDR_EMRS_PRSR_BIT) /*All Banks*/ + #define DDR_EMRS_PRSR_HALF_TL (1 << DDR_EMRS_PRSR_BIT) /*Half of Total Bank*/ + #define DDR_EMRS_PRSR_QUTR_TL (2 << DDR_EMRS_PRSR_BIT) /*Quarter of Total Bank*/ + #define DDR_EMRS_PRSR_HALF_B0 (5 << DDR_EMRS_PRSR_BIT) /*Half of Bank0*/ + #define DDR_EMRS_PRSR_QUTR_B0 (6 << DDR_EMRS_PRSR_BIT) /*Quarter of Bank0*/ + +/* DDR1 Mode Register */ +#define DDR1_MRS_OM_BIT 7 /* Operating Mode */ +#define DDR1_MRS_OM_MASK (0x3f << DDR1_MRS_OM_BIT) + #define DDR1_MRS_OM_NORMAL (0 << DDR1_MRS_OM_BIT) + #define DDR1_MRS_OM_DLLRST (1 << DDR1_MRS_OM_BIT) + #define DDR1_MRS_OM_TEST (1 << DDR1_MRS_OM_BIT) +#if 0 +#define DDR1_MRS_CAS_BIT 4 /* CAS Latency */ +#define DDR1_MRS_CAS_MASK (7 << DDR1_MRS_CAS_BIT) +#define DDR1_MRS_BT_BIT 3 /* Burst Type */ +#define DDR1_MRS_BT_MASK (1 << DDR1_MRS_BT_BIT) + #define DDR1_MRS_BT_SEQ (0 << DDR1_MRS_BT_BIT) /* Sequential */ + #define DDR1_MRS_BT_INT (1 << DDR1_MRS_BT_BIT) /* Interleave */ +#define DDR1_MRS_BL_BIT 0 /* Burst Length */ +#define DDR1_MRS_BL_MASK (7 << DDR1_MRS_BL_BIT) + #define DDR1_MRS_BL_4 (2 << DDR1_MRS_BL_BIT) + #define DDR1_MRS_BL_8 (3 << DDR1_MRS_BL_BIT) +#endif +/* DDR1 Extended Mode Register */ +#define DDR1_EMRS_OM_BIT 2 /* Partial Array Self Refresh */ +#define DDR1_EMRS_OM_MASK (0x3ff << DDR1_EMRS_OM_BIT) + #define DDR1_EMRS_OM_NORMAL (0 << DDR1_EMRS_OM_BIT) /*All Banks*/ + +#define DDR1_EMRS_DS_BIT 1 /* Driver strength */ +#define DDR1_EMRS_DS_MASK (1 << DDR1_EMRS_DS_BIT) + #define DDR1_EMRS_DS_FULL (0 << DDR1_EMRS_DS_BIT) /*Full*/ + #define DDR1_EMRS_DS_HALF (1 << DDR1_EMRS_DS_BIT) /*1/2 Strength*/ + +#define DDR1_EMRS_DLL_BIT 0 /* Driver strength */ +#define DDR1_EMRS_DLL_MASK (1 << DDR1_EMRS_DLL_BIT) + #define DDR1_EMRS_DLL_EN (0 << DDR1_EMRS_DLL_BIT) /*Full*/ + #define DDR1_EMRS_DLL_DIS (1 << DDR1_EMRS_DLL_BIT) /*1/2 Strength*/ + +/* DDRC Timing Config Register 1 */ +#define DDRC_TIMING1_TRAS_BIT 28 /* ACTIVE to PRECHARGE command period (2 * tRAS + 1) */ +#define DDRC_TIMING1_TRAS_MASK (0xf << DDRC_TIMING1_TRAS_BIT) + +#define DDRC_TIMING1_TRTP_BIT 24 /* READ to PRECHARGE command period. */ +#define DDRC_TIMING1_TRTP_MASK (0x3 << DDRC_TIMING1_TRTP_BIT) + +#define DDRC_TIMING1_TRP_BIT 20 /* PRECHARGE command period. */ +#define DDRC_TIMING1_TRP_MASK (0x7 << DDRC_TIMING1_TRP_BIT) + +#define DDRC_TIMING1_TRCD_BIT 16 /* ACTIVE to READ or WRITE command period. */ +#define DDRC_TIMING1_TRCD_MASK (0x7 << DDRC_TIMING1_TRCD_BIT) + +#define DDRC_TIMING1_TRC_BIT 12 /* ACTIVE to ACTIVE command period. */ +#define DDRC_TIMING1_TRC_MASK (0xf << DDRC_TIMING1_TRC_BIT) + +#define DDRC_TIMING1_TRRD_BIT 8 /* ACTIVE bank A to ACTIVE bank B command period. */ +#define DDRC_TIMING1_TRRD_MASK (0x3 << DDRC_TIMING1_TRRD_BIT) +#define DDRC_TIMING1_TRRD_DISABLE (0 << DDRC_TIMING1_TRRD_BIT) +#define DDRC_TIMING1_TRRD_2 (1 << DDRC_TIMING1_TRRD_BIT) +#define DDRC_TIMING1_TRRD_3 (2 << DDRC_TIMING1_TRRD_BIT) +#define DDRC_TIMING1_TRRD_4 (3 << DDRC_TIMING1_TRRD_BIT) + +#define DDRC_TIMING1_TWR_BIT 4 /* WRITE Recovery Time defined by register MR of DDR2 memory */ +#define DDRC_TIMING1_TWR_MASK (0x7 << DDRC_TIMING1_TWR_BIT) + #define DDRC_TIMING1_TWR_1 (0 << DDRC_TIMING1_TWR_BIT) + #define DDRC_TIMING1_TWR_2 (1 << DDRC_TIMING1_TWR_BIT) + #define DDRC_TIMING1_TWR_3 (2 << DDRC_TIMING1_TWR_BIT) + #define DDRC_TIMING1_TWR_4 (3 << DDRC_TIMING1_TWR_BIT) + #define DDRC_TIMING1_TWR_5 (4 << DDRC_TIMING1_TWR_BIT) + #define DDRC_TIMING1_TWR_6 (5 << DDRC_TIMING1_TWR_BIT) + +#define DDRC_TIMING1_TWTR_BIT 0 /* WRITE to READ command delay. */ +#define DDRC_TIMING1_TWTR_MASK (0x3 << DDRC_TIMING1_TWTR_BIT) + #define DDRC_TIMING1_TWTR_1 (0 << DDRC_TIMING1_TWTR_BIT) + #define DDRC_TIMING1_TWTR_2 (1 << DDRC_TIMING1_TWTR_BIT) + #define DDRC_TIMING1_TWTR_3 (2 << DDRC_TIMING1_TWTR_BIT) + #define DDRC_TIMING1_TWTR_4 (3 << DDRC_TIMING1_TWTR_BIT) + +/* DDRC Timing Config Register 2 */ +#define DDRC_TIMING2_TRFC_BIT 12 /* AUTO-REFRESH command period. */ +#define DDRC_TIMING2_TRFC_MASK (0xf << DDRC_TIMING2_TRFC_BIT) +#define DDRC_TIMING2_TMINSR_BIT 8 /* Minimum Self-Refresh / Deep-Power-Down time */ +#define DDRC_TIMING2_TMINSR_MASK (0xf << DDRC_TIMING2_TMINSR_BIT) +#define DDRC_TIMING2_TXP_BIT 4 /* EXIT-POWER-DOWN to next valid command period. */ +#define DDRC_TIMING2_TXP_MASK (0x7 << DDRC_TIMING2_TXP_BIT) +#define DDRC_TIMING2_TMRD_BIT 0 /* Load-Mode-Register to next valid command period. */ +#define DDRC_TIMING2_TMRD_MASK (0x3 << DDRC_TIMING2_TMRD_BIT) + +/* DDRC Auto-Refresh Counter */ +#define DDRC_REFCNT_CON_BIT 16 /* Constant value used to compare with CNT value. */ +#define DDRC_REFCNT_CON_MASK (0xff << DDRC_REFCNT_CON_BIT) +#define DDRC_REFCNT_CNT_BIT 8 /* 8-bit counter */ +#define DDRC_REFCNT_CNT_MASK (0xff << DDRC_REFCNT_CNT_BIT) +#define DDRC_REFCNT_CLKDIV_BIT 1 /* Clock Divider for auto-refresh counter. */ +#define DDRC_REFCNT_CLKDIV_MASK (0x7 << DDRC_REFCNT_CLKDIV_BIT) +#define DDRC_REFCNT_REF_EN (1 << 0) /* Enable Refresh Counter */ + +/* DDRC DQS Delay Control Register */ +#define DDRC_DQS_ERROR (1 << 29) /* ahb_clk Delay Detect ERROR, read-only. */ +#define DDRC_DQS_READY (1 << 28) /* ahb_clk Delay Detect READY, read-only. */ +#define DDRC_DQS_AUTO (1 << 23) /* Hardware auto-detect & set delay line */ +#define DDRC_DQS_DET (1 << 24) /* Start delay detecting. */ +#define DDRC_DQS_CLKD_BIT 16 /* CLKD is reference value for setting WDQS and RDQS.*/ +#define DDRC_DQS_CLKD_MASK (0x7f << DDRC_DQS_CLKD_BIT) +#define DDRC_DQS_WDQS_BIT 8 /* Set delay element number to write DQS delay-line. */ +#define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT) +#define DDRC_DQS_RDQS_BIT 0 /* Set delay element number to read DQS delay-line. */ +#define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT) + +/* DDRC DQS Delay Adjust Register */ +#define DDRC_DQS_ADJWDQS_BIT 8 /* The adjust value for WRITE DQS delay */ +#define DDRC_DQS_ADJWDQS_MASK (0x1f << DDRC_DQS_ADJWDQS_BIT) +#define DDRC_DQS_ADJRDQS_BIT 0 /* The adjust value for READ DQS delay */ +#define DDRC_DQS_ADJRDQS_MASK (0x1f << DDRC_DQS_ADJRDQS_BIT) + +/* DDRC Memory Map Config Register */ +#define DDRC_MMAP_BASE_BIT 8 /* base address */ +#define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT) +#define DDRC_MMAP_MASK_BIT 0 /* address mask */ +#define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT) + +#define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT) +#define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/ +#define DDRC_MMAP1_BASE_128M (0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/ +#define DDRC_MMAP1_BASE_256M (0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/ + +#define DDRC_MMAP_MASK_64_64 (0xfc << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/ +#define DDRC_MMAP_MASK_128_128 (0xf8 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/ +#define DDRC_MMAP_MASK_256_256 (0xf0 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/ + /************************************************************************* * CIM *************************************************************************/ @@ -2260,6 +2845,7 @@ static inline u32 jz_readl(u32 address) #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) +#define LCD_CFG_TVEPEH (1 << 30) /* TVE PAL enable extra halfline signal */ #define LCD_CFG_FUHOLD (1 << 29) /* hold pixel clock when outFIFO underrun */ #define LCD_CFG_NEWDES (1 << 28) /* use new descripter. old: 4words, new:8words */ #define LCD_CFG_PALBP (1 << 27) /* bypass data format and alpha blending */ @@ -2278,11 +2864,13 @@ static inline u32 jz_readl(u32 address) #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ -#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ -#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ -#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ -#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ -#define MODE_TFT_18BIT (1 << 7) /* 18bit TFT */ +#define LCD_CFG_HSP (1 << 11) /* HSYNC polarity:0-active high,1-active low */ +#define LCD_CFG_PCP (1 << 10) /* PCLK polarity:0-rising,1-falling */ +#define LCD_CFG_DEP (1 << 9) /* DE polarity:0-active high,1-active low */ +#define LCD_CFG_VSP (1 << 8) /* VSYNC polarity:0-rising,1-falling */ +#define LCD_CFG_MODE_TFT_18BIT (1 << 7) /* 18bit TFT */ +#define LCD_CFG_MODE_TFT_16BIT (0 << 7) /* 16bit TFT */ +#define LCD_CFG_MODE_TFT_24BIT (1 << 6) /* 24bit TFT */ #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ @@ -2296,17 +2884,14 @@ static inline u32 jz_readl(u32 address) #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_INTER_CCIR656 (6 << LCD_CFG_MODE_BIT) #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) #define LCD_CFG_MODE_LCM (13 << LCD_CFG_MODE_BIT) - /* JZ47XX defines */ - #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) - #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) + #define LCD_CFG_MODE_SLCD LCD_CFG_MODE_LCM /* LCD Control Register */ #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ @@ -2325,6 +2910,8 @@ static inline u32 jz_readl(u32 address) #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) +#define LCD_CTRL_VGA (1 << 15) /* VGA interface enable */ +#define LCD_CTRL_DACTE (1 << 14) /* DAC loop back test */ #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ @@ -2344,6 +2931,7 @@ static inline u32 jz_readl(u32 address) #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ + #define LCD_CTRL_BPP_CMPS_24 (6 << LCD_CTRL_BPP_BIT) /* 24 compress bpp */ /* LCD Status Register */ #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ @@ -2357,11 +2945,8 @@ static inline u32 jz_readl(u32 address) /* OSD Configure Register */ #define LCD_OSDC_SOFM1 (1 << 15) /* Start of frame interrupt mask for foreground 1 */ #define LCD_OSDC_EOFM1 (1 << 14) /* End of frame interrupt mask for foreground 1 */ -#define LCD_OSDC_REM1 (1 << 13) /* Real end of frame mask for foreground 1 */ #define LCD_OSDC_SOFM0 (1 << 11) /* Start of frame interrupt mask for foreground 0 */ #define LCD_OSDC_EOFM0 (1 << 10) /* End of frame interrupt mask for foreground 0 */ -#define LCD_OSDC_REM0 (1 << 9) /* Real end of frame mask for foreground 0 */ -#define LCD_OSDC_REMB (1 << 7) /* Real end of frame mask for background */ #define LCD_OSDC_F1EN (1 << 4) /* enable foreground 1 */ #define LCD_OSDC_F0EN (1 << 3) /* enable foreground 0 */ #define LCD_OSDC_ALPHAEN (1 << 2) /* enable alpha blending */ @@ -2374,10 +2959,11 @@ static inline u32 jz_readl(u32 address) #define LCD_OSDCTRL_RGB555 (1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */ #define LCD_OSDCTRL_CHANGES (1 << 3) /* Change size flag */ #define LCD_OSDCTRL_OSDBPP_BIT 0 /* Bits Per Pixel of OSD Channel 1 */ -#define LCD_OSDCTRL_OSDBPP_MASK (0x3<> CPM_CPPCR_PLLOD_BIT) +#define __cpm_get_pll1m() \ + ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1M_MASK) >> CPM_CPPCR1_PLL1M_BIT) +#define __cpm_get_pll1n() \ + ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1N_MASK) >> CPM_CPPCR1_PLL1N_BIT) +#define __cpm_get_pll1od() \ + ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1OD_MASK) >> CPM_CPPCR1_PLL1OD_BIT) + #define __cpm_get_cdiv() \ ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) #define __cpm_get_hdiv() \ ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) +#define __cpm_get_h2div() \ + ((REG_CPM_CPCCR & CPM_CPCCR_H2DIV_MASK) >> CPM_CPCCR_H2DIV_BIT) #define __cpm_get_pdiv() \ ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) #define __cpm_get_mdiv() \ ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) -#define __cpm_get_ldiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) -#define __cpm_get_udiv() \ - ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) +#define __cpm_get_sdiv() \ + ((REG_CPM_CPCCR & CPM_CPCCR_SDIV_MASK) >> CPM_CPCCR_SDIV_BIT) #define __cpm_get_i2sdiv() \ ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) #define __cpm_get_pixdiv() \ ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) #define __cpm_get_mscdiv(n) \ ((REG_CPM_MSCCDR(n) & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) -#define __cpm_get_uhcdiv() \ - ((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT) #define __cpm_get_ssidiv() \ ((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT) -#define __cpm_get_pcmdiv(v) \ +#define __cpm_get_pcmdiv() \ ((REG_CPM_PCMCDR & CPM_PCMCDR_PCMCD_MASK) >> CPM_PCMCDR_PCMCD_BIT) +#define __cpm_get_pll1div() \ + ((REG_CPM_CPPCR1 & CPM_CPCCR1_P1SDIV_MASK) >> CPM_CPCCR1_P1SDIV_BIT) #define __cpm_set_cdiv(v) \ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) @@ -3561,22 +4389,40 @@ do { \ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) #define __cpm_set_mdiv(v) \ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) -#define __cpm_set_ldiv(v) \ - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) +#define __cpm_set_h1div(v) \ + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_H1DIV_MASK) | ((v) << (CPM_CPCCR_H1DIV_BIT))) #define __cpm_set_udiv(v) \ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) #define __cpm_set_i2sdiv(v) \ (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) #define __cpm_set_pixdiv(v) \ (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) -#define __cpm_set_mscdiv(n, v) \ - (REG_CPM_MSCCDR(n) = (REG_CPM_MSCCDR(n) & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) -#define __cpm_set_uhcdiv(v) \ - (REG_CPM_UHCCDR = (REG_CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | ((v) << (CPM_UHCCDR_UHCDIV_BIT))) +#define __cpm_set_mscdiv(v) \ + (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) #define __cpm_set_ssidiv(v) \ (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT))) #define __cpm_set_pcmdiv(v) \ (REG_CPM_PCMCDR = (REG_CPM_PCMCDR & ~CPM_PCMCDR_PCMCD_MASK) | ((v) << (CPM_PCMCDR_PCMCD_BIT))) +#define __cpm_set_pll1div(v) \ + (REG_CPM_CPPCR1 = (REG_CPM_CPPCR1 & ~CPM_CPCCR1_P1SDIV_MASK) | ((v) << (CPM_CPCCR1_P1SDIV_BIT))) + +#define __cpm_select_i2sclk_pll1() (REG_CPM_I2SCDR |= CPM_I2SCDR_I2PCS) +#define __cpm_select_i2sclk_pll0() (REG_CPM_I2SCDR &= ~CPM_I2SCDR_I2PCS) +#define __cpm_select_otgclk_pll1() (REG_CPM_USBCDR |= CPM_USBCDR_UPCS) +#define __cpm_select_otgclk_pll0() (REG_CPM_USBCDR &= ~CPM_USBCDR_UPCS) +#define __cpm_select_lcdpclk_pll1() (REG_CPM_LPCDR |= CPM_LPCDR_LPCS) +#define __cpm_select_lcdpclk_pll0() (REG_CPM_LPCDR &= ~CPM_LPCDR_LPCS) +#define __cpm_select_uhcclk_pll1() (REG_CPM_UHCCDR |= CPM_UHCCDR_UHPCS) +#define __cpm_select_uhcclk_pll0() (REG_CPM_UHCCDR &= ~CPM_UHCCDR_UHPCS) +#define __cpm_select_gpsclk_pll1() (REG_CPM_GPSCDR |= CPM_GPSCDR_GPCS) +#define __cpm_select_gpsclk_pll0() (REG_CPM_GPSCDR &= ~CPM_GPSCDR_GPCS) +#define __cpm_select_pcmclk_pll1() (REG_CPM_PCMCDR |= CPM_PCMCDR_PCMPCS) +#define __cpm_select_pcmclk_pll0() (REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMPCS) +#define __cpm_select_gpuclk_pll1() (REG_CPM_GPUCDR |= CPM_GPUCDR_GPCS) +#define __cpm_select_gpuclk_pll0() (REG_CPM_GPUCDR &= ~CPM_GPUCDR_GPCS) +#define __cpm_select_clk_pll1() (REG_CPM_CDR |= CPM_CDR_PCS) +#define __cpm_select_clk_pll0() (REG_CPM_CDR &= ~CPM_CDR_PCS) + #define __cpm_select_pcmclk_pll() (REG_CPM_PCMCDR |= CPM_PCMCDR_PCMS) #define __cpm_select_pcmclk_exclk() (REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMS) @@ -3586,19 +4432,21 @@ do { \ #define __cpm_select_tveclk_pll() (REG_CPM_LPCDR &= ~CPM_LPCDR_LSCS) #define __cpm_select_pixclk_lcd() (REG_CPM_LPCDR &= ~CPM_LPCDR_LTCS) #define __cpm_select_pixclk_tve() (REG_CPM_LPCDR |= CPM_LPCDR_LTCS) -#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) -#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) -#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) -#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) +#define __cpm_select_i2sclk_exclk() (REG_CPM_I2SCDR &= ~CPM_I2SCDR_I2CS) +#define __cpm_select_i2sclk_pll() (REG_CPM_I2SCDR |= CPM_I2SCDR_I2CS) +//#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) +//#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) #define __cpm_enable_cko() #define __cpm_exclk_direct() (REG_CPM_CPCCR &= ~CPM_CPCCR_ECS) #define __cpm_exclk_div2() (REG_CPM_CPCCR |= CPM_CPCCR_ECS) #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) -#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) + #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) #define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) +#define __cpm_pll1_enable() (REG_CPM_CPPCR1 |= CPM_CPPCR1_PLL1EN) + #define __cpm_pll_is_off() (REG_CPM_CPPSR & CPM_CPPSR_PLLOFF) #define __cpm_pll_is_on() (REG_CPM_CPPSR & CPM_CPPSR_PLLON) #define __cpm_pll_bypass() (REG_CPM_CPPSR |= CPM_CPPSR_PLLBP) @@ -3614,69 +4462,106 @@ do { \ #define __cpm_sleep_mode() \ (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) -#define __cpm_stop_all() (REG_CPM_CLKGR = 0x1fffffff) -#define __cpm_stop_cimram() (REG_CPM_CLKGR |= CPM_CLKGR_CIMRAM) -#define __cpm_stop_idct() (REG_CPM_CLKGR |= CPM_CLKGR_IDCT) -#define __cpm_stop_db() (REG_CPM_CLKGR |= CPM_CLKGR_DB) -#define __cpm_stop_me() (REG_CPM_CLKGR |= CPM_CLKGR_ME) -#define __cpm_stop_mc() (REG_CPM_CLKGR |= CPM_CLKGR_MC) -#define __cpm_stop_tve() (REG_CPM_CLKGR |= CPM_CLKGR_TVE) -#define __cpm_stop_tssi() (REG_CPM_CLKGR |= CPM_CLKGR_TSSI) -#define __cpm_stop_owi() (REG_CPM_CLKGR |= CPM_CLKGR_OWI) -#define __cpm_stop_pcm() (REG_CPM_CLKGR |= CPM_CLKGR_PCM) -#define __cpm_stop_uart3() (REG_CPM_CLKGR |= CPM_CLKGR_UART3) -#define __cpm_stop_uart2() (REG_CPM_CLKGR |= CPM_CLKGR_UART2) -#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) -#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) -#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) -#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) -#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) -#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) -#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) -#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) -#define __cpm_stop_msc(n) (REG_CPM_CLKGR |= CPM_CLKGR_MSC##n) -#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) -#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) -#define __cpm_stop_ssi(n) (REG_CPM_CLKGR |= CPM_CLKGR_SSI##n) -#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) -#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) -#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) -#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) +#define __cpm_stop_all() \ + do {\ + (REG_CPM_CLKGR0 = 0xffffffff);\ + (REG_CPM_CLKGR1 = 0x3ff);\ + }while(0) +#define __cpm_stop_emc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_EMC) +#define __cpm_stop_ddr() (REG_CPM_CLKGR0 |= CPM_CLKGR0_DDR) +#define __cpm_stop_ipu() (REG_CPM_CLKGR0 |= CPM_CLKGR0_IPU) +#define __cpm_stop_lcd() (REG_CPM_CLKGR0 |= CPM_CLKGR0_LCD) +#define __cpm_stop_tve() (REG_CPM_CLKGR0 |= CPM_CLKGR0_TVE) +#define __cpm_stop_Cim() (REG_CPM_CLKGR0 |= CPM_CLKGR0_CIM) +#define __cpm_stop_mdma() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MDMA) +#define __cpm_stop_uhc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UHC) +#define __cpm_stop_mac() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MAC) +#define __cpm_stop_gps() (REG_CPM_CLKGR0 |= CPM_CLKGR0_GPS) +#define __cpm_stop_dmac() (REG_CPM_CLKGR0 |= CPM_CLKGR0_DMAC) +#define __cpm_stop_ssi2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI2) +#define __cpm_stop_ssi1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI1) +#define __cpm_stop_uart3() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART3) +#define __cpm_stop_uart2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART2) +#define __cpm_stop_uart1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART1) +#define __cpm_stop_uart0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART0) +#define __cpm_stop_sadc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SADC) +#define __cpm_stop_kbc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_KBC) +#define __cpm_stop_msc2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC2) +#define __cpm_stop_msc1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC1) +#define __cpm_stop_owi() (REG_CPM_CLKGR0 |= CPM_CLKGR0_OWI) +#define __cpm_stop_tssi() (REG_CPM_CLKGR0 |= CPM_CLKGR0_TSSI) +#define __cpm_stop_aic() (REG_CPM_CLKGR0 |= CPM_CLKGR0_AIC) +#define __cpm_stop_scc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SCC) +#define __cpm_stop_i2c0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_I2C1) +#define __cpm_stop_i2c1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_I2C0) +#define __cpm_stop_ssi0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI0) +#define __cpm_stop_msc0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC0) +#define __cpm_stop_otg() (REG_CPM_CLKGR0 |= CPM_CLKGR0_OTG) +#define __cpm_stop_bch() (REG_CPM_CLKGR0 |= CPM_CLKGR0_BCH) +#define __cpm_stop_nemc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_NEMC) +#define __cpm_stop_gpu() (REG_CPM_CLKGR1 |= CPM_CLKGR0_GPU) +#define __cpm_stop_pcm() (REG_CPM_CLKGR1 |= CPM_CLKGR0_PCM) +#define __cpm_stop_ahb1() (REG_CPM_CLKGR1 |= CPM_CLKGR0_AHB1) +#define __cpm_stop_cabac() (REG_CPM_CLKGR1 |= CPM_CLKGR0_CABAC) +#define __cpm_stop_sram() (REG_CPM_CLKGR1 |= CPM_CLKGR0_SRAM) +#define __cpm_stop_dct() (REG_CPM_CLKGR1 |= CPM_CLKGR0_DCT) +#define __cpm_stop_me() (REG_CPM_CLKGR1 |= CPM_CLKGR0_ME) +#define __cpm_stop_dblk() (REG_CPM_CLKGR1 |= CPM_CLKGR0_DBLK) +#define __cpm_stop_mc() (REG_CPM_CLKGR1 |= CPM_CLKGR0_MC) +#define __cpm_stop_bdma() (REG_CPM_CLKGR1 |= CPM_CLKGR0_BDMA) -#define __cpm_start_all() (REG_CPM_CLKGR = 0x0) -#define __cpm_start_cimram() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIMRAM) -#define __cpm_start_idct() (REG_CPM_CLKGR &= ~CPM_CLKGR_IDCT) -#define __cpm_start_db() (REG_CPM_CLKGR &= ~CPM_CLKGR_DB) -#define __cpm_start_me() (REG_CPM_CLKGR &= ~CPM_CLKGR_ME) -#define __cpm_start_mc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MC) -#define __cpm_start_tve() (REG_CPM_CLKGR &= ~CPM_CLKGR_TVE) -#define __cpm_start_tssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_TSSI) -#define __cpm_start_owi() (REG_CPM_CLKGR &= ~CPM_CLKGR_OWI) -#define __cpm_start_pcm() (REG_CPM_CLKGR &= ~CPM_CLKGR_PCM) -#define __cpm_start_uart3() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART3) -#define __cpm_start_uart2() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART2) -#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) -#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) -#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) -#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) -#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) -#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) -#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) -#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) -#define __cpm_start_msc(n) (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC##n) -#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) -#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) -#define __cpm_start_ssi(n) (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI##n) -#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) -#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) -#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) -#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) +#define __cpm_start_all() \ + do {\ + REG_CPM_CLKGR0 = 0x0;\ + REG_CPM_CLKGR1 = 0x0;\ + } while(0) +#define __cpm_start_emc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_EMC) +#define __cpm_start_ddr() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_DDR) +#define __cpm_start_ipu() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_IPU) +#define __cpm_start_lcd() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_LCD) +#define __cpm_start_tve() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_TVE) +#define __cpm_start_Cim() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_CIM) +#define __cpm_start_mdma() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MDMA) +#define __cpm_start_uhc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UHC) +#define __cpm_start_mac() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MAC) +#define __cpm_start_gps() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_GPS) +#define __cpm_start_dmac() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_DMAC) +#define __cpm_start_ssi2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI2) +#define __cpm_start_ssi1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI1) +#define __cpm_start_uart3() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART3) +#define __cpm_start_uart2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART2) +#define __cpm_start_uart1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART1) +#define __cpm_start_uart0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART0) +#define __cpm_start_sadc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SADC) +#define __cpm_start_kbc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_KBC) +#define __cpm_start_msc2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC2) +#define __cpm_start_msc1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC1) +#define __cpm_start_owi() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_OWI) +#define __cpm_start_tssi() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_TSSI) +#define __cpm_start_aic() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_AIC) +#define __cpm_start_scc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SCC) +#define __cpm_start_i2c0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_I2C1) +#define __cpm_start_i2c1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_I2C0) +#define __cpm_start_ssi0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI0) +#define __cpm_start_msc0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC0) +#define __cpm_start_otg() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_OTG) +#define __cpm_start_bch() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_BCH) +#define __cpm_start_nemc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_NEMC) +#define __cpm_start_gpu() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_GPU) +#define __cpm_start_pcm() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_PCM) +#define __cpm_start_ahb1() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_AHB1) +#define __cpm_start_cabac() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_CABAC) +#define __cpm_start_sram() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_SRAM) +#define __cpm_start_dct() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_DCT) +#define __cpm_start_me() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_ME) +#define __cpm_start_dblk() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_DBLK) +#define __cpm_start_mc() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_MC) +#define __cpm_start_bdma() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_BDMA) #define __cpm_get_o1st() \ ((REG_CPM_OPCR & CPM_OPCR_O1ST_MASK) >> CPM_OPCR_O1ST_BIT) #define __cpm_set_o1st(v) \ (REG_CPM_OPCR = (REG_CPM_OPCR & ~CPM_OPCR_O1ST_MASK) | ((v) << (CPM_OPCR_O1ST_BIT))) -#define __cpm_suspend_uhcphy() (REG_CPM_OPCR |= CPM_OPCR_UHCPHY_SUSPEND) #define __cpm_suspend_udcphy() (REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE) #define __cpm_enable_osc_in_sleep() (REG_CPM_OPCR |= CPM_OPCR_OSC_ENABLE) #define __cpm_select_rtcclk_rtc() (REG_CPM_OPCR |= CPM_OPCR_ERCS) @@ -3695,12 +4580,33 @@ static __inline__ unsigned int __cpm_get_pllout(void) { unsigned long m, n, no, pllout; unsigned long cppcr = REG_CPM_CPPCR; - unsigned long od[4] = {1, 2, 2, 4}; - if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { - m = __cpm_get_pllm() + 2; - n = __cpm_get_plln() + 2; + unsigned long od[4] = {1, 2, 4, 8}; + if ((cppcr & CPM_CPPCR_PLLEN) && (!(cppcr & CPM_CPPCR_PLLBP))) { + m = __cpm_get_pllm() * 2; + n = __cpm_get_plln(); no = od[__cpm_get_pllod()]; - pllout = ((JZ_EXTAL) / (n * no)) * m; + pllout = ((JZ_EXTAL) * m / (n * no)); + } else + pllout = JZ_EXTAL; + return pllout; +} + +/* PLL output frequency */ +static __inline__ unsigned int __cpm_get_pll1out(void) +{ + unsigned long m, n, no, pllout; + unsigned long cppcr1 = REG_CPM_CPPCR1; + unsigned long od[4] = {1, 2, 4, 8}; + if (cppcr1 & CPM_CPPCR1_PLL1EN) + { + m = __cpm_get_pll1m() * 2; + n = __cpm_get_pll1n(); + no = od[__cpm_get_pll1od()]; + if (cppcr1 & CPM_CPPCR1_P1SCS) + pllout = ((__cpm_get_pllout()) * m / (n * no)); + else + pllout = ((JZ_EXTAL) * m / (n * no)); + } else pllout = JZ_EXTAL; return pllout; @@ -3718,7 +4624,7 @@ static __inline__ unsigned int __cpm_get_pllout2(void) /* CPU core clock */ static __inline__ unsigned int __cpm_get_cclk(void) { - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + int div[] = {1, 2, 3, 4, 6, 8}; return __cpm_get_pllout() / div[__cpm_get_cdiv()]; } @@ -3726,7 +4632,7 @@ static __inline__ unsigned int __cpm_get_cclk(void) /* AHB system bus clock */ static __inline__ unsigned int __cpm_get_hclk(void) { - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + int div[] = {1, 2, 3, 4, 6, 8}; return __cpm_get_pllout() / div[__cpm_get_hdiv()]; } @@ -3734,7 +4640,7 @@ static __inline__ unsigned int __cpm_get_hclk(void) /* Memory bus clock */ static __inline__ unsigned int __cpm_get_mclk(void) { - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + int div[] = {1, 2, 3, 4, 6, 8}; return __cpm_get_pllout() / div[__cpm_get_mdiv()]; } @@ -3742,15 +4648,17 @@ static __inline__ unsigned int __cpm_get_mclk(void) /* APB peripheral bus clock */ static __inline__ unsigned int __cpm_get_pclk(void) { - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + int div[] = {1, 2, 3, 4, 6, 8}; return __cpm_get_pllout() / div[__cpm_get_pdiv()]; } -/* LCDC module clock */ -static __inline__ unsigned int __cpm_get_lcdclk(void) +/* AHB1 module clock */ +static __inline__ unsigned int __cpm_get_h2clk(void) { - return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); + int div[] = {1, 2, 3, 4, 6, 8}; + + return __cpm_get_pllout() / div[__cpm_get_h2div()]; } /* LCD pixel clock */ @@ -3762,7 +4670,7 @@ static __inline__ unsigned int __cpm_get_pixclk(void) /* I2S clock */ static __inline__ unsigned int __cpm_get_i2sclk(void) { - if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { + if (REG_CPM_I2SCDR & CPM_I2SCDR_I2CS) { return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); } else { @@ -3771,6 +4679,7 @@ static __inline__ unsigned int __cpm_get_i2sclk(void) } /* USB clock */ +/* static __inline__ unsigned int __cpm_get_usbclk(void) { if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { @@ -3780,7 +4689,7 @@ static __inline__ unsigned int __cpm_get_usbclk(void) return JZ_EXTAL; } } - +*/ /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ static __inline__ unsigned int __cpm_get_extalclk(void) { @@ -3793,6 +4702,26 @@ static __inline__ unsigned int __cpm_get_rtcclk(void) return JZ_EXTAL2; } +/* + * Output 24MHz for SD and 16MHz for MMC. + */ +#if 1 +static inline void __cpm_select_msc_clk(int n, int sd) +{ + unsigned int pllout2 = __cpm_get_pllout2(); + unsigned int div = 0; + + if (sd) { + div = pllout2 / 24000000; + } + else { + div = pllout2 / 16000000; + } + + REG_CPM_MSCCDR = div - 1; + REG_CPM_CPCCR |= CPM_CPCCR_CE; +} +#endif /*************************************************************************** * TCU ***************************************************************************/ @@ -3927,6 +4856,161 @@ static __inline__ unsigned int __cpm_get_rtcclk(void) /* Tx high pulse as 0, Rx low pulse as 0 */ \ ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) +/*************************************************************************** + * Mem Copy DMAC + ***************************************************************************/ + +/* n is the DMA channel index (0 - 3) */ + +#define __mdmac_enable_module \ + ( REG_MDMAC_DMACR |= DMAC_MDMACR_DMAE | DMAC_MDMACR_PR_012345 ) +#define __mdmac_disable_module \ + ( REG_MDMAC_DMACR &= ~DMAC_MDMACR_DMAE ) + +/* p=0,1,2,3 */ +#define __mdmac_set_priority(p) \ +do { \ + REG_MDMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ + REG_MDMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ +} while (0) + +#define __mdmac_test_halt_error ( REG_MDMAC_DMACR & DMAC_MDMACR_HLT ) +#define __mdmac_test_addr_error ( REG_MDMAC_DMACR & DMAC_MDMACR_AR ) + +#define __mdmac_channel_enable_clk \ + REG_MDMAC_DMACKE |= 1 << (n); + +#define __mdmac_enable_descriptor(n) \ + ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) +#define __mdmac_disable_descriptor(n) \ + ( REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) + +#define __mdmac_enable_channel(n) \ +do { \ + REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_EN; \ +} while (0) +#define __mdmac_disable_channel(n) \ +do { \ + REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN; \ +} while (0) +#define __mdmac_channel_enabled(n) \ + ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_EN ) + +#define __mdmac_channel_enable_irq(n) \ + ( REG_MDMAC_DCMD((n)) |= DMAC_DCMD_TIE ) +#define __mdmac_channel_disable_irq(n) \ + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) + +#define __mdmac_channel_transmit_halt_detected(n) \ + ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) +#define __mdmac_channel_transmit_end_detected(n) \ + ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_TT ) +#define __mdmac_channel_address_error_detected(n) \ + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) +#define __mdmac_channel_count_terminated_detected(n) \ + ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_CT ) +#define __mdmac_channel_descriptor_invalid_detected(n) \ + ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_INV ) + +#define __mdmac_channel_clear_transmit_halt(n) \ + do { \ + /* clear both channel halt error and globle halt error */ \ + REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT; \ + REG_MDMAC_DMACR &= ~DMAC_DMACR_HLT; \ + } while (0) +#define __mdmac_channel_clear_transmit_end(n) \ + ( REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) +#define __mdmac_channel_clear_address_error(n) \ + do { \ + REG_MDMAC_DDA(n) = 0; /* clear descriptor address register */ \ + REG_MDMAC_DSAR(n) = 0; /* clear source address register */ \ + REG_MDMAC_DTAR(n) = 0; /* clear target address register */ \ + /* clear both channel addr error and globle address error */ \ + REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_AR; \ + REG_MDMAC_DMACR &= ~DMAC_DMACR_AR; \ + } while (0) +#define __mdmac_channel_clear_count_terminated(n) \ + ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) +#define __mdmac_channel_clear_descriptor_invalid(n) \ + ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) + +#define __mdmac_channel_set_transfer_unit_32bit(n) \ +do { \ + REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ +} while (0) + +#define __mdmac_channel_set_transfer_unit_16bit(n) \ +do { \ + REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ +} while (0) + +#define __mdmac_channel_set_transfer_unit_8bit(n) \ +do { \ + REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ +} while (0) + +#define __mdmac_channel_set_transfer_unit_16byte(n) \ +do { \ + REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ +} while (0) + +#define __mdmac_channel_set_transfer_unit_32byte(n) \ +do { \ + REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ + REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ +} while (0) + +/* w=8,16,32 */ +#define __mdmac_channel_set_dest_port_width(n,w) \ +do { \ + REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ + REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ +} while (0) + +/* w=8,16,32 */ +#define __mdmac_channel_set_src_port_width(n,w) \ +do { \ + REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ + REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ +} while (0) + +/* v=0-15 */ +#define __mdmac_channel_set_rdil(n,v) \ +do { \ + REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ + REG_MDMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ +} while (0) + +#define __mdmac_channel_dest_addr_fixed(n) \ + (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DAI) +#define __mdmac_channel_dest_addr_increment(n) \ + (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DAI) + +#define __mdmac_channel_src_addr_fixed(n) \ + (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SAI) +#define __mdmac_channel_src_addr_increment(n) \ + (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SAI) + +#define __mdmac_channel_set_doorbell(n) \ + (REG_MDMAC_DMADBSR = (1 << (n))) + +#define __mdmac_channel_irq_detected(n) (REG_MDMAC_DMAIPR & (1 << (n))) +#define __mdmac_channel_ack_irq(n) (REG_MDMAC_DMAIPR &= ~(1 <<(n))) + +static __inline__ int __mdmac_get_irq(void) +{ + int i; + for (i = 0; i < MAX_MDMA_NUM; i++) + if (__mdmac_channel_irq_detected(i)) + return i; + return -1; +} + + /*************************************************************************** * DMAC @@ -4363,10 +5447,9 @@ do { \ /*************************************************************************** * INTC ***************************************************************************/ -#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) -#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) -#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) - +#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32))) +#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32))) +#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */ /*************************************************************************** * I2C @@ -5073,7 +6156,11 @@ do { \ * RTC ops ***************************************************************************/ -#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) +#define __rtc_write_ready() (REG_RTC_RCR & RTC_RCR_WRDY) +#define __rtc_write_enabled() (REG_RTC_WENR & RTC_WENR_WEN) +#define __rtc_write_enable() (REG_RTC_WENR |= (0xA55A << RTC_WENR_WENPAT_BIT)) +#define __rtc_write_disable() (REG_RTC_WENR &= ~RTC_WENR_WENPAT_MASK) + #define __rtc_enabled() \ do{ \ while(!__rtc_write_ready()); \ @@ -5281,38 +6368,82 @@ do{ \ *************************************************************************/ #define __ecc_encoding_4bit() \ do { \ - REG_BCH_CRS = BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \ - REG_BCH_CRC = BCH_CR_BSEL8; \ + REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \ } while(0) #define __ecc_decoding_4bit() \ do { \ - REG_BCH_CRS = BCH_CR_BRST | BCH_CR_BCHE; \ - REG_BCH_CRC = BCH_CR_ENCE | BCH_CR_BSEL8; \ + REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \ } while(0) #define __ecc_encoding_8bit() \ do { \ - REG_BCH_CRS = BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BSEL8 | BCH_CR_BCHE; \ + REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \ } while(0) #define __ecc_decoding_8bit() \ do { \ - REG_BCH_CRS = BCH_CR_BRST | BCH_CR_BSEL8 | BCH_CR_BCHE; \ - REG_BCH_CRC = BCH_CR_ENCE; \ + REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \ } while(0) +#define __ecc_encoding_12bit() \ +do { \ + REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \ +} while(0) +#define __ecc_decoding_12bit() \ +do { \ + REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \ +} while(0) +#define __ecc_encoding_16bit() \ +do { \ + REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \ +} while(0) +#define __ecc_decoding_16bit() \ +do { \ + REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \ +} while(0) +#define __ecc_encoding_20bit() \ +do { \ + REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \ +} while(0) +#define __ecc_decoding_20bit() \ +do { \ + REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \ +} while(0) +#define __ecc_encoding_24bit() \ +do { \ + REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \ +} while(0) +#define __ecc_decoding_24bit() \ +do { \ + REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \ + REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \ +} while(0) + #define __ecc_dma_enable() ( REG_BCH_CRS = BCH_CR_DMAE ) +#define __ecc_dma_disable() ( REG_BCH_CRC = BCH_CR_DMAE ) #define __ecc_disable() ( REG_BCH_CRC = BCH_CR_BCHE ) #define __ecc_encode_sync() while (!(REG_BCH_INTS & BCH_INTS_ENCF)) #define __ecc_decode_sync() while (!(REG_BCH_INTS & BCH_INTS_DECF)) + #define __ecc_cnt_dec(n) \ -do { \ - REG_BCH_CNT &= ~(BCH_CNT_DEC_MASK << BCH_CNT_DEC_BIT); \ - REG_BCH_CNT = (n) << BCH_CNT_DEC_BIT; \ +do { \ + REG_BCH_CNT &= ~BCH_CNT_DEC_MASK; \ + REG_BCH_CNT |= (n) << BCH_CNT_DEC_BIT; \ } while(0) #define __ecc_cnt_enc(n) \ do { \ - REG_BCH_CNT &= ~(BCH_CNT_ENC_MASK << BCH_CNT_ENC_BIT); \ - REG_BCH_CNT = (n) << BCH_CNT_ENC_BIT; \ + REG_BCH_CNT &= ~BCH_CNT_ENC_MASK; \ + REG_BCH_CNT |= (n) << BCH_CNT_ENC_BIT; \ } while(0) #endif /* !__ASSEMBLY__ */ -#endif /* __JZ4750_H__ */ +#endif /* __JZ4760_H__ */ diff --git a/usbboot/xburst_stage1/Makefile b/usbboot/xburst_stage1/Makefile index 2be21e3..ea17e75 100644 --- a/usbboot/xburst_stage1/Makefile +++ b/usbboot/xburst_stage1/Makefile @@ -18,7 +18,7 @@ CFLAGS := -O2 -fno-unit-at-a-time -fno-zero-initialized-in-bss -mips32 -fno-pic -mno-abicalls -I$(INFLASH_SRC_PATH) -I$(XBURST_INCLUDE_PATH) LDFLAGS := -nostdlib -EL -T target.ld -OBJS = head.o main.o common.o board_4740.o board_4750.o debug.o +OBJS = head.o main.o common.o board_4740.o board-jz4760.o debug.o all: xburst_stage1.bin diff --git a/usbboot/xburst_stage1/board-jz4760.c b/usbboot/xburst_stage1/board-jz4760.c new file mode 100644 index 0000000..59d2ca3 --- /dev/null +++ b/usbboot/xburst_stage1/board-jz4760.c @@ -0,0 +1,1263 @@ +/* + * board.c + * + * Board init routines. + * + * Copyright (C) 2006 Ingenic Semiconductor Inc. + * + */ +#include "target/jz4760.h" +#include "target/xburst_types.h" +#include "board-jz4760.h" + +extern volatile u32 UART_BASE; + +void nand_init_4760() +{ + REG_NEMC_NFCSR |= NEMC_NFCSR_NFE1 | NEMC_NFCSR_NFCE1; +} + +void cpm_start_all_4760() +{ + __cpm_start_all(); +} + +/* + * SD0 ~ SD7, SA0 ~ SA5, CS2#, RD#, WR#, WAIT# + */ +#define __gpio_as_nor() \ +do { \ + /* SD0 ~ SD7, RD#, WR#, CS2#, WAIT# */ \ + REG_GPIO_PXFUNS(0) = 0x084300ff; \ + REG_GPIO_PXTRGC(0) = 0x084300ff; \ + REG_GPIO_PXSELC(0) = 0x084300ff; \ + REG_GPIO_PXPES(0) = 0x084300ff; \ + /* SA0 ~ SA5 */ \ + REG_GPIO_PXFUNS(1) = 0x0000003f; \ + REG_GPIO_PXTRGC(1) = 0x0000003f; \ + REG_GPIO_PXSELC(1) = 0x0000003f; \ + REG_GPIO_PXPES(1) = 0x0000003f; \ +} while (0) + +void gpio_init_4760() +{ + __gpio_as_uart0(); + __gpio_as_uart1(); + __gpio_as_uart2(); + __gpio_as_uart3(); + +#ifdef CONFIG_FPGA // if the delay isn't added on FPGA, the first line that uart to print will not be normal. + __gpio_as_nor(); + { + volatile int i=1000; + while(i--); + } +#endif + __gpio_as_nand_16bit(1); +} + +#define MHZ (1000 * 1000) +static inline unsigned int pll_calc_m_n_od(unsigned int speed, unsigned int xtal) +{ + const int pll_m_max = 0x7f, pll_m_min = 4; + const int pll_n_max = 0x0f, pll_n_min = 2; + + int od[] = {1, 2, 4, 8}; + int min_od = 0; + + unsigned int plcr_m_n_od = 0; + unsigned int distance; + unsigned int tmp, raw; + + int i, j, k; + int m, n; + + distance = 0xFFFFFFFF; + + for (i = 0; i < sizeof (od) / sizeof(int); i++) { + /* Limit: 500MHZ <= CLK_OUT * OD <= 1500MHZ */ +// if (min_od != 0) +// break; + if ((speed * od[i]) < 500 * MHZ || (speed * od[i]) > 1500 * MHZ) + continue; + for (k = pll_n_min; k <= pll_n_max; k++) { + n = k; + + /* Limit: 1MHZ <= XIN/N <= 50MHZ */ + if ((xtal / n) < (1 * MHZ)) + break; + if ((xtal / n) > (15 * MHZ)) + continue; + + for (j = pll_m_min; j <= pll_m_max; j++) { + m = j*2; + + raw = xtal * m / n; + tmp = raw / od[i]; + + tmp = (tmp > speed) ? (tmp - speed) : (speed - tmp); + + if (tmp < distance) { + distance = tmp; + + plcr_m_n_od = (j << CPM_CPPCR_PLLM_BIT) + | (k << CPM_CPPCR_PLLN_BIT) + | (i << CPM_CPPCR_PLLOD_BIT); + + if (!distance) { /* Match. */ +// serial_puts("right value"); + return plcr_m_n_od; + } + } + } + min_od = od[i]; + } + } + return plcr_m_n_od; +} + +/* TODO: pll_init() need modification. */ +void pll_init_4760() +{ + register unsigned int cfcr, plcr1; + int n2FR[9] = { + 0, 0, 1, 2, 3, 0, 4, 0, 5 + }; + + /** divisors, + * for jz4760 ,I:H:H2:P:M:S. + * DIV should be one of [1, 2, 3, 4, 6, 8] like: + * div[6] = {1, 2, 2, 2, 2, 2}; + * div[6] = {1, 3, 6, 6, 6, 6}; + */ + int div[6] = {1, 2, 4, 4, 4, 4}; + + cfcr = CPM_CPCCR_PCS | + (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | + (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | + (n2FR[div[2]] << CPM_CPCCR_H2DIV_BIT) | + (n2FR[div[3]] << CPM_CPCCR_PDIV_BIT) | + (n2FR[div[4]] << CPM_CPCCR_MDIV_BIT) | + (n2FR[div[5]] << CPM_CPCCR_SDIV_BIT); + + if (CFG_EXTAL > 16000000) + cfcr |= CPM_CPCCR_ECS; + else + cfcr &= ~CPM_CPCCR_ECS; + + /* set CPM_CPCCR_MEM only for ddr1 or ddr2 */ +#if defined(CONFIG_DDRC) && (defined(CONFIG_SDRAM_DDR1) || defined(CONFIG_SDRAM_DDR2)) + cfcr |= CPM_CPCCR_MEM; +#else + cfcr &= ~CPM_CPCCR_MEM; +#endif + cfcr |= CPM_CPCCR_CE; + + plcr1 = pll_calc_m_n_od(CFG_CPU_SPEED, CFG_EXTAL); + plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT) /* PLL stable time */ + | CPM_CPPCR_PLLEN; /* enable PLL */ + + /* init PLL */ + REG_CPM_CPCCR = cfcr; + REG_CPM_CPPCR = plcr1; + + while(!(REG_CPM_CPPSR & (1 << 29))); + +#ifdef DEBUG + serial_puts("REG_CPM_CPCCR = "); + serial_put_hex(REG_CPM_CPCCR); + serial_puts("REG_CPM_CPPCR = "); + serial_put_hex(REG_CPM_CPPCR); +#endif +} + +#if (defined(CONFIG_SDRAM_MDDR)||defined(CONFIG_SDRAM_DDR1)||defined(CONFIG_SDRAM_DDR2)) +void jzmemset(void *dest,int ch,int len) +{ + unsigned int *d = (unsigned int *)dest; + int i; + int wd; + + wd = (ch << 24) | (ch << 16) | (ch << 8) | ch; + + for(i = 0;i < len / 32;i++) + { + *d++ = wd; + *d++ = wd; + *d++ = wd; + *d++ = wd; + *d++ = wd; + *d++ = wd; + *d++ = wd; + *d++ = wd; + } +} + +unsigned int gen_verify_data(unsigned int i) +{ + i = i/4*0x11111111; + return i; + //return 0xffffffff; +} + +int initdram(int board_type) +{ + u32 ddr_cfg; + u32 rows, cols, dw, banks; + unsigned long size; + ddr_cfg = REG_DDRC_CFG; + rows = 12 + ((ddr_cfg & DDRC_CFG_ROW_MASK) >> DDRC_CFG_ROW_BIT); + cols = 8 + ((ddr_cfg & DDRC_CFG_COL_MASK) >> DDRC_CFG_COL_BIT); + + dw = (ddr_cfg & DDRC_CFG_DW) ? 4 : 2; + banks = (ddr_cfg & DDRC_CFG_BA) ? 8 : 4; + + size = (1 << (rows + cols)) * dw * banks; + size *= (DDR_CS1EN + DDR_CS0EN); + + return size; +} +static int dma_check_result(void *src, void *dst, int size,int print_flag) +{ + unsigned int addr1, addr2, i, err = 0; + unsigned int data_expect,dsrc,ddst; + + addr1 = (unsigned int)src; + addr2 = (unsigned int)dst; + + for (i = 0; i < size; i += 4) { + data_expect = gen_verify_data(i); + dsrc = REG32(addr1); + ddst = REG32(addr2); + if ((dsrc != data_expect) || (ddst != data_expect)) { +#if DEBUG + serial_put_hex(addr2); + serial_puts("data:"); + serial_put_hex(data_expect); + serial_puts("src"); + serial_put_hex(dsrc); + serial_puts("dst"); + serial_put_hex(ddst); +#endif + err = 1; + if(!print_flag) + return 1; + } + + addr1 += 4; + addr2 += 4; + } + return err; +} + +#if DEBUG +void dump_jz_dma_channel(unsigned int dmanr) +{ + + if (dmanr > MAX_DMA_NUM) + return; + serial_puts("REG_DDRC_ST \t\t="); + serial_put_hex(REG_DDRC_ST); + + serial_puts("DMA Registers, Channel "); + serial_put_hex(dmanr); + + serial_puts(" DMACR = "); + serial_put_hex(REG_DMAC_DMACR(dmanr/HALF_DMA_NUM)); + serial_puts(" DSAR = "); + serial_put_hex(REG_DMAC_DSAR(dmanr)); + serial_puts(" DTAR = "); + serial_put_hex(REG_DMAC_DTAR(dmanr)); + serial_puts(" DTCR = "); + serial_put_hex(REG_DMAC_DTCR(dmanr)); + serial_puts(" DRSR = "); + serial_put_hex(REG_DMAC_DRSR(dmanr)); + serial_puts(" DCCSR = "); + serial_put_hex(REG_DMAC_DCCSR(dmanr)); + serial_puts(" DCMD = "); + serial_put_hex(REG_DMAC_DCMD(dmanr)); + serial_puts(" DDA = "); + serial_put_hex(REG_DMAC_DDA(dmanr)); + serial_puts(" DMADBR = "); + serial_put_hex(REG_DMAC_DMADBR(dmanr/HALF_DMA_NUM)); +} + +void dma_nodesc_test_single(int dma_chan, int dma_src_addr, int dma_dst_addr, int size) +{ + int dma_src_phys_addr, dma_dst_phys_addr; + + /* Allocate DMA buffers */ + dma_src_phys_addr = dma_src_addr & (~0xa0000000); + dma_dst_phys_addr = dma_dst_addr & (~0xa0000000); + + /* Init DMA module */ + REG_DMAC_DCCSR(dma_chan) = 0; + REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO; + REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr; + REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr; + REG_DMAC_DTCR(dma_chan) = size; + REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT; + REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; +} + +static void ddrc_regs_print(void) +{ + serial_puts("\nDDRC REGS:\n"); + serial_puts("REG_DDRC_ST \t\t="); + serial_put_hex(REG_DDRC_ST); + serial_puts("REG_DDRC_CFG \t\t="); + serial_put_hex( REG_DDRC_CFG); + serial_puts("REG_DDRC_CTRL \t\t="); + serial_put_hex(REG_DDRC_CTRL); + serial_puts("REG_DDRC_LMR \t\t="); + serial_put_hex(REG_DDRC_LMR); + serial_puts("REG_DDRC_TIMING1 \t="); + serial_put_hex(REG_DDRC_TIMING1); + serial_puts("REG_DDRC_TIMING2 \t="); + serial_put_hex(REG_DDRC_TIMING2); + serial_puts("REG_DDRC_REFCNT \t\t="); + serial_put_hex(REG_DDRC_REFCNT); + serial_puts("REG_DDRC_DQS \t\t="); + serial_put_hex(REG_DDRC_DQS); + serial_puts("REG_DDRC_DQS_ADJ \t="); + serial_put_hex(REG_DDRC_DQS_ADJ); + serial_puts("REG_DDRC_MMAP0 \t\t="); + serial_put_hex(REG_DDRC_MMAP0); + serial_puts("REG_DDRC_MMAP1 \t\t="); + serial_put_hex(REG_DDRC_MMAP1); + serial_puts("REG_DDRC_MDELAY \t\t="); + serial_put_hex(REG_DDRC_MDELAY); + serial_puts("REG_EMC_PMEMPS2 \t\t="); + serial_put_hex(REG_EMC_PMEMPS2); +} + +static int dma_memcpy_test(int channle_0, int channle_1) { + int i, err = 0, banks; + unsigned int addr, DDR_DMA0_SRC, DDR_DMA0_DST, DDR_DMA1_SRC, DDR_DMA1_DST; + volatile unsigned int tmp; + register unsigned int cpu_clk; + long int memsize, banksize, testsize; + int channel; + +#ifndef CONFIG_DDRC + banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS); +#else + banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN); +#endif + memsize = initdram(0); + + banksize = memsize/banks; + testsize = 4096; + + DDR_DMA0_SRC = DDR_DMA_BASE + banksize*0; + DDR_DMA0_DST = DDR_DMA_BASE + banksize*0 + testsize; + DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2; + DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3; + + cpu_clk = CFG_CPU_SPEED; + +// for(channel = 0; channel < MAX_DMA_NUM; channel++) { + + // MDMA + REG_MDMAC_DMACR = DMAC_DMACR_DMAE; + // COMMON DMA + //REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */ + //REG_DMAC_DMACR(1) = DMAC_DMACR_DMAE; /* global DMA enable bit */ + + // Write A0 + addr = DDR_DMA0_SRC; + + for (i = 0; i < testsize; i += 4) { + *(volatile unsigned int *)addr = (i/4*0x11111111); + //*(volatile unsigned int *)addr = addr; + addr += 4; + } + + // Write A2 + addr = DDR_DMA1_SRC; + for (i = 0; i < testsize; i += 4) { + *(volatile unsigned int *)addr = (i/4*0x11111111); + //*(volatile unsigned int *)addr = addr; + addr += 4; + } + + + // MDMA + REG_MDMAC_DMACR = 0; + // COMMON DMA + //REG_DMAC_DMACR(0) = 0; + //REG_DMAC_DMACR(1) = 0; + + /* Init target buffer */ + jzmemset((void *)DDR_DMA0_DST, 0, testsize); + jzmemset((void *)DDR_DMA1_DST, 0, testsize); + + // Set DMA1 for moving data from A0 -> A1 + dma_data_move(channle_0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize, DMAC_DCMD_DS_32BYTE); + // Set DMA2 for moving data from A2 -> A3 + dma_data_move(channle_1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize, DMAC_DCMD_DS_64BYTE); + + // Start DMA0 + REG_DMAC_DCCSR(0) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; + // Wait for DMA0 finishing + while(REG_DMAC_DTCR(0)); + + // Start DMA1 + REG_DMAC_DCCSR(1) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; + + // Read from A1 & check + err = check_result((void *)DDR_DMA0_SRC, (void *)DDR_DMA0_DST, testsize); + REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */ + if (err != 0) { + serial_puts("DMA0: err!\n"); + //return err; + } + + // Wait for DMA1 finishing + while(REG_DMAC_DTCR(1)); + + // Read from A3 & check + err = check_result((void *)DDR_DMA1_SRC, (void *)DDR_DMA1_DST, testsize); + REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */ + if (err != 0) { + serial_puts("DMA1: err!\n"); + //return err; + } + + serial_puts("TEST PASSED\n\n"); + + tmp = (cpu_clk / 1000000) * 1; + while (tmp--); +// } + return err; +} + +#endif + + +void dma_nodesc_test(int dma_chan, int dma_src_addr, int dma_dst_addr, int size) +{ + int dma_src_phys_addr, dma_dst_phys_addr; + + /* Allocate DMA buffers */ + dma_src_phys_addr = dma_src_addr & (~0xa0000000); + dma_dst_phys_addr = dma_dst_addr & (~0xa0000000); + + /* Init DMA module */ + REG_DMAC_DCCSR(dma_chan) = 0; + REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO; + REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr; + REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr; + REG_DMAC_DTCR(dma_chan) = size / 32; + REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE; + REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; +} + +#define DDR_DMA_BASE (0xa0000000) /*un-cached*/ +#define DMA_CHANNEL0_EN +//#define DMA_CHANNEL1_EN +static int ddr_dma_test(int print_flag) { + int i, err = 0, banks; + int times; + unsigned int addr, DDR_DMA0_SRC, DDR_DMA0_DST, DDR_DMA1_SRC, DDR_DMA1_DST; + volatile unsigned int tmp; + register unsigned int cpu_clk; + long int memsize, banksize, testsize; + REG_DMAC_DMADCKE(0) = 0x3f; + REG_DMAC_DMADCKE(1) = 0x3f; + +#ifndef CONFIG_DDRC + banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS); +#else + banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN); +#endif + memsize = initdram(0); + + banksize = memsize/banks; + testsize = 4096; + +for(times = 0; times < banks; times++) { +#if 0 + DDR_DMA0_SRC = DDR_DMA_BASE + banksize*0; + DDR_DMA0_DST = DDR_DMA_BASE + banksize*(banks - 2) + testsize; + DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize; + DDR_DMA1_DST = DDR_DMA_BASE + banksize*1; +#else + DDR_DMA0_SRC = DDR_DMA_BASE + banksize*times; + DDR_DMA0_DST = DDR_DMA_BASE + banksize*(times+1) - testsize; + DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2; + DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3; +#endif + + cpu_clk = CFG_CPU_SPEED; + +#ifdef DMA_CHANNEL0_EN + addr = DDR_DMA0_SRC; + + for (i = 0; i < testsize; i += 4) { + *(volatile unsigned int *)(addr + i) = gen_verify_data(i); + } +#endif +#ifdef DMA_CHANNEL1_EN + addr = DDR_DMA1_SRC; + for (i = 0; i < testsize; i += 4) { + + *(volatile unsigned int *)addr = gen_verify_data(i); + + addr += 4; + } +#endif + + REG_DMAC_DMACR(0) = 0; +// REG_DMAC_DMACR(1) = 0; + /* Init target buffer */ +#ifdef DMA_CHANNEL0_EN + jzmemset((void *)DDR_DMA0_DST, 0, testsize); + dma_nodesc_test(0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize); +#endif +#ifdef DMA_CHANNEL1_EN + jzmemset((void *)DDR_DMA1_DST, 0, testsize); + dma_nodesc_test(1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize); +#endif + + REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */ +// REG_DMAC_DMACR(1) = DMAC_DMACR_DMAE; /* global DMA enable bit */ +// while(REG_DMAC_DTCR(0) || REG_DMAC_DTCR(1)); + while(REG_DMAC_DTCR(0)); + tmp = (cpu_clk / 1000000) * 1; + while (tmp--); + +#ifdef DMA_CHANNEL0_EN + err = dma_check_result((void *)DDR_DMA0_SRC, (void *)DDR_DMA0_DST, testsize,print_flag); + + REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */ + + if(err == 0) { + serial_puts("passed:"); + serial_put_hex(times); + } else { + serial_put_hex(times); + } + + if (err != 0) { +#ifdef DMA_CHANNEL1_EN + REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */ +#endif + return err; + } + +#endif + +#ifdef DMA_CHANNEL1_EN + //err += dma_check_result((void *)DDR_DMA1_SRC, (void *)DDR_DMA1_DST, testsize); + //REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */ +#endif +} + return err; +} + +void ddr_mem_init(int msel, int hl, int tsel, int arg) +{ + volatile int tmp_cnt; + register unsigned int cpu_clk, ddr_twr; + register unsigned int ddrc_cfg_reg=0, init_ddrc_mdelay=0; + + cpu_clk = CFG_CPU_SPEED; + +#if defined(CONFIG_SDRAM_DDR2) // ddr2 + ddrc_cfg_reg = DDRC_CFG_TYPE_DDR2 | (DDR_ROW-12)<<10 + | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6 + | ((DDR_CL-1) | 0x8)<<2 | DDR_BANK8<<1 | DDR_DW32; +#elif defined(CONFIG_SDRAM_DDR1) // ddr1 + ddrc_cfg_reg = DDRC_CFG_BTRUN |DDRC_CFG_TYPE_DDR1 + | (DDR_ROW-12)<<10 | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6 + | ((DDR_CL_HALF?(DDR_CL&~0x8):((DDR_CL-1)|0x8))<<2) + | DDR_BANK8<<1 | DDR_DW32; +#else // mobile ddr + ddrc_cfg_reg = DDRC_CFG_TYPE_MDDR + | (DDR_ROW-12)<<10 | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6 + | ((DDR_CL-1) | 0x8)<<2 | DDR_BANK8<<1 | DDR_DW32; +#endif + + ddrc_cfg_reg |= DDRC_CFG_MPRT; + +#if defined(CONFIG_FPGA) + init_ddrc_mdelay= tsel<<18 | msel<<16 | hl<<15; +#else + init_ddrc_mdelay= tsel<<18 | msel<<16 | hl<<15 | arg << 14; +#endif + ddr_twr = ((REG_DDRC_TIMING1 & DDRC_TIMING1_TWR_MASK) >> DDRC_TIMING1_TWR_BIT) + 1; + REG_DDRC_CFG = ddrc_cfg_reg; + + REG_DDRC_MDELAY = init_ddrc_mdelay | 1 << 6; + /***** init ddrc registers & ddr memory regs ****/ + /* AR: auto refresh */ + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + /* Wait for DDR_tRP */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* Wait for number of auto-refresh cycles */ + tmp_cnt = (cpu_clk / 1000000) * 10; + while (tmp_cnt--); + +#if defined(CONFIG_SDRAM_DDR2) // ddr1 and mddr + + /* Set CKE High */ + REG_DDRC_CTRL = DDRC_CTRL_CKE; // ? + + /* Wait for number of auto-refresh cycles */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* PREA */ + REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; + + /* Wait for DDR_tRP */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* EMR2: extend mode register2 */ + REG_DDRC_LMR = DDRC_LMR_BA_EMRS2 | DDRC_LMR_CMD_LMR | DDRC_LMR_START;//0x221; + + /* EMR3: extend mode register3 */ + REG_DDRC_LMR = DDRC_LMR_BA_EMRS3 | DDRC_LMR_CMD_LMR | DDRC_LMR_START;//0x321; + + /* EMR1: extend mode register1 */ + REG_DDRC_LMR = (DDR_EMRS1_DQS_DIS << 16) | DDRC_LMR_BA_EMRS1 | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* wait DDR_tMRD */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* MR - DLL Reset A1A0 burst 2 */ + REG_DDRC_LMR = ((ddr_twr-1)<<9 | DDR2_MRS_DLL_RST | DDR_CL<<4 | DDR_MRS_BL_4)<< 16 + | DDRC_LMR_BA_MRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* wait DDR_tMRD */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* PREA */ + REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; + + /* Wait for DDR_tRP */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* AR: auto refresh */ + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + /* Wait for DDR_tRP */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + + /* Wait for DDR_tRP */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* MR - DLL Reset End */ + REG_DDRC_LMR = ((ddr_twr-1)<<9 | DDR_CL<<4 | DDR_MRS_BL_4)<< 16 + | DDRC_LMR_BA_MRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* wait 200 tCK */ + tmp_cnt = (cpu_clk / 1000000) * 2; + while (tmp_cnt--); + + /* EMR1 - OCD Default */ + REG_DDRC_LMR = (DDR_EMRS1_DQS_DIS | DDR_EMRS1_OCD_DFLT) << 16 + | DDRC_LMR_BA_EMRS1 | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* EMR1 - OCD Exit */ + REG_DDRC_LMR = (DDR_EMRS1_DQS_DIS << 16) | DDRC_LMR_BA_EMRS1 | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* wait DDR_tMRD */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + +#elif defined(CONFIG_SDRAM_DDR1) // ddr1 and mddr + /* set cke high */ + REG_DDRC_CTRL = DDRC_CTRL_CKE; // ? + + /* Nop command */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* PREA all */ +// REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; + + /* Wait for DDR_tRP */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* EMR: extend mode register: enable DLL */ + REG_DDRC_LMR = (DDR1_EMRS_OM_NORMAL | DDR1_EMRS_DS_FULL | DDR1_EMRS_DLL_EN) << 16 + | DDRC_LMR_BA_N_EMRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* MR DLL reset */ + REG_DDRC_LMR = (DDR1_MRS_OM_DLLRST | (DDR_CL_HALF?(DDR_CL|0x4):DDR_CL)<<4 | DDR_MRS_BL_4)<< 16 + | DDRC_LMR_BA_N_MRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* wait DDR_tXSRD, 200 tCK */ + tmp_cnt = (cpu_clk / 1000000) * 2; + while (tmp_cnt--); + /* PREA all */ + REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + tmp_cnt = (cpu_clk / 1000000) * 15; + while (tmp_cnt--); + /* EMR: extend mode register, clear dll en */ + REG_DDRC_LMR = (DDR1_EMRS_OM_NORMAL | DDR1_EMRS_DS_FULL) << 16 + | DDRC_LMR_BA_N_EMRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + /* wait DDR_tMRD */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + +#elif defined(CONFIG_SDRAM_MDDR) // ddr1 and mddr + REG_DDRC_CTRL = DDRC_CTRL_CKE; // ? + + /* Wait for number of auto-refresh cycles */ + tmp_cnt = (cpu_clk / 1000000) * 20; + while (tmp_cnt--); + + /* PREA */ + REG_DDRC_LMR = DDRC_LMR_CMD_PREC | DDRC_LMR_START; //0x1; + + /* Wait for DDR_tRP */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* AR: auto refresh */ + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + + /* wait DDR_tRFC */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* AR: auto refresh */ + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + /* wait DDR_tRFC */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* MR */ + REG_DDRC_LMR = (DDR_CL<<4 | DDR_MRS_BL_4)<< 16 + | DDRC_LMR_BA_M_MRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* wait DDR_tMRD */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + + /* EMR: extend mode register */ + REG_DDRC_LMR = (DDR_EMRS_DS_HALF | DDR_EMRS_PRSR_ALL) << 16 + | DDRC_LMR_BA_M_EMRS | DDRC_LMR_CMD_LMR | DDRC_LMR_START; + + /* wait DDR_tMRD */ + tmp_cnt = (cpu_clk / 1000000) * 1; + while (tmp_cnt--); + +#endif +} +void testallmem() +{ + unsigned int i,d; + unsigned int *dat; + dat = (unsigned int *)0xa0000000; + for(i = 0; i < 64*1024*1024;i+=4) + { + *dat = i; + dat++; + } + + dat = (unsigned int *)0xa0000000; + for(i = 0; i < 64*1024*1024;i+=4) + { + d = *dat; + if(d != i) + { + serial_puts("errdata:\n"); + serial_puts("expect:\n"); + serial_put_hex(i); + serial_put_hex(d); + } + dat++; + } + +} + +#define DDR_DMA_BASE (0xa0000000) /*un-cached*/ + +void dma_data_move(int dma_chan, int dma_src_addr, int dma_dst_addr, int size, int burst) +{ + int dma_src_phys_addr, dma_dst_phys_addr; + + /* set addr to uncached */ + dma_src_phys_addr = dma_src_addr & ~0xa0000000; + dma_dst_phys_addr = dma_dst_addr & ~0xa0000000; + + /* Init DMA module */ + + REG_DMAC_DCCSR(dma_chan) = 0; + REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO; + REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr; + REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr; + REG_DMAC_DTCR(dma_chan) = size / 32; + REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | burst; +// REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN; +} + +static int check_result(void *src, void *dst, int size) +{ + unsigned int addr1, addr2, i, err = 0; + + addr1 = (unsigned int)src; + addr2 = (unsigned int)dst; + + for (i = 0; i < size; i += 4) { + if ((*(volatile unsigned int *)addr1 != *(volatile unsigned int *)addr2) + || (*(volatile unsigned int *)addr1 != (i/4*0x11111111))) { +#ifdef DEBUG + err++; + if (err < 10){ + serial_puts("wrong data at");serial_put_hex(addr2); + serial_puts("data");serial_put_hex(i/4*0x11111111); + serial_puts("src");serial_put_hex(*(volatile unsigned int *)addr1); + serial_puts("dst");serial_put_hex(*(volatile unsigned int *)addr2); + } +#else + return 1; +#endif + } + + addr1 += 4; + addr2 += 4; + } + return err; +} + +#endif + +#if (defined(CONFIG_SDRAM_MDDR) || defined(CONFIG_SDRAM_DDR1) || defined(CONFIG_SDRAM_DDR2)) +#define DEF_DDR_CVT 0 +#define DDR_USE_FIRST_ARGS 0 +unsigned int testall = 0; +/* DDR sdram init */ +void sdram_init_4760(void) +{ + //add driver power + REG_EMC_PMEMPS2 |= (3 << 18); + + REG_DMAC_DMADCKE(0) = 0x3f; + REG_DMAC_DMADCKE(1) = 0x3f; + int i, num = 0, tsel = 0, msel, hl; + volatile unsigned int tmp_cnt; + register unsigned int tmp, cpu_clk, mem_clk, ddr_twr, ns, ns_int; + register unsigned int ddrc_timing1_reg=0, ddrc_timing2_reg=0; + register unsigned int init_ddrc_refcnt=0, init_ddrc_dqs=0, init_ddrc_ctrl=0; + + register unsigned int memsize, ddrc_mmap0_reg, ddrc_mmap1_reg; + register unsigned int mem_base0, mem_base1, mem_mask0, mem_mask1; + +#if defined(CONFIG_FPGA) + int cvt = DEF_DDR_CVT, cvt_cnt0 = 0, cvt_cnt1 = 1; + int max = 0, max0 = 0, max1 = 0, min0 = 0, min1 = 0; + int tsel0 = 0, tsel1 = 0; + struct ddr_delay_sel_t ddr_delay_sel[] = { + {0, 1}, {0, 0}, {1, 1}, {1, 0}, + {2, 1}, {2, 0}, {3, 1}, {3, 0} + }; +#endif + + testall = 0; + cpu_clk = CFG_CPU_SPEED; + +#ifdef DEBUG + ddrc_regs_print(); +#endif + +#if defined(CONFIG_FPGA) + mem_clk = CFG_EXTAL / CFG_DIV; + ns = 7; +#else + mem_clk = __cpm_get_mclk(); + ns = 1000000000 / mem_clk; /* ns per tck ns <= real value */ +#endif + +#ifdef DEBUG + serial_puts("mem_clk = "); + serial_put_hex(mem_clk); +#endif + + /* ACTIVE to PRECHARGE command period */ + tmp = (DDR_tRAS%ns == 0) ? (DDR_tRAS/ns) : (DDR_tRAS/ns+1); + if (tmp < 1) tmp = 1; + if (tmp > 31) tmp = 31; + ddrc_timing1_reg = ((tmp/2) << DDRC_TIMING1_TRAS_BIT); + + /* READ to PRECHARGE command period. */ + tmp = (DDR_tRTP%ns == 0) ? (DDR_tRTP/ns) : (DDR_tRTP/ns+1); + if (tmp < 1) tmp = 1; + if (tmp > 4) tmp = 4; + ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TRTP_BIT); + + /* PRECHARGE command period. */ + tmp = (DDR_tRP%ns == 0) ? DDR_tRP/ns : (DDR_tRP/ns+1); + if (tmp < 1) tmp = 1; + if (tmp > 8) tmp = 8; + ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TRP_BIT); + + /* ACTIVE to READ or WRITE command period. */ + tmp = (DDR_tRCD%ns == 0) ? DDR_tRCD/ns : (DDR_tRCD/ns+1); + if (tmp < 1) tmp = 1; + if (tmp > 8) tmp = 8; + ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TRCD_BIT); + + /* ACTIVE to ACTIVE command period. */ + tmp = (DDR_tRC%ns == 0) ? DDR_tRC/ns : (DDR_tRC/ns+1); + if (tmp < 3) tmp = 3; + if (tmp > 31) tmp = 31; + ddrc_timing1_reg |= ((tmp/2) << DDRC_TIMING1_TRC_BIT); + + /* ACTIVE bank A to ACTIVE bank B command period. */ + tmp = (DDR_tRRD%ns == 0) ? DDR_tRRD/ns : (DDR_tRRD/ns+1); + if (tmp < 2) tmp = 2; + if (tmp > 4) tmp = 4; + ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TRRD_BIT); + + + /* WRITE Recovery Time defined by register MR of DDR2 memory */ + tmp = (DDR_tWR%ns == 0) ? DDR_tWR/ns : (DDR_tWR/ns+1); + tmp = (tmp < 1) ? 1 : tmp; + tmp = (tmp < 2) ? 2 : tmp; + tmp = (tmp > 6) ? 6 : tmp; + ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TWR_BIT); + ddr_twr = tmp; + + /* WRITE to READ command delay. */ + tmp = (DDR_tWTR%ns == 0) ? DDR_tWTR/ns : (DDR_tWTR/ns+1); + if (tmp > 4) tmp = 4; + ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TWTR_BIT); + + + /* WRITE to READ command delay. */ + tmp = DDR_tWTR/ns; + if (tmp < 1) tmp = 1; + if (tmp > 4) tmp = 4; + ddrc_timing1_reg |= ((tmp-1) << DDRC_TIMING1_TWTR_BIT); + + /* AUTO-REFRESH command period. */ + tmp = (DDR_tRFC%ns == 0) ? DDR_tRFC/ns : (DDR_tRFC/ns+1); + if (tmp > 31) tmp = 31; + ddrc_timing2_reg = ((tmp/2) << DDRC_TIMING2_TRFC_BIT); + + /* Minimum Self-Refresh / Deep-Power-Down time */ + tmp = DDR_tMINSR/ns; + if (tmp < 9) tmp = 9; + if (tmp > 129) tmp = 129; + ddrc_timing2_reg |= (((tmp-1)/8-1) << DDRC_TIMING2_TMINSR_BIT); + ddrc_timing2_reg |= (DDR_tXP-1)<<4 | (DDR_tMRD-1); + + init_ddrc_refcnt = DDR_CLK_DIV << 1 | DDRC_REFCNT_REF_EN; + + ns_int = (1000000000%mem_clk == 0) ? + (1000000000/mem_clk) : (1000000000/mem_clk+1); + tmp = DDR_tREFI/ns_int; + tmp = tmp / (16 * (1 << DDR_CLK_DIV)) - 1; + if (tmp > 0xfff) + tmp = 0xfff; + if (tmp < 1) + tmp = 1; + + init_ddrc_refcnt |= tmp << DDRC_REFCNT_CON_BIT; + init_ddrc_dqs = DDRC_DQS_AUTO | DDRC_DQS_DET; + + /* precharge power down, disable power down */ + /* precharge power down, if set active power down, |= DDRC_CTRL_ACTPD */ + init_ddrc_ctrl = DDRC_CTRL_PDT_DIS | DDRC_CTRL_PRET_8 | DDRC_CTRL_UNALIGN | DDRC_CTRL_CKE; + /* Add Jz4760 chip here. Jz4760 chip have no cvt */ +#define MAX_TSEL_VALUE 4 +#define MAX_DELAY_VALUES 16 /* quars (2) * hls (2) * msels (4) */ + int j, index, quar; + int mem_index[MAX_DELAY_VALUES]; +#if 0 // probe + jzmemset(mem_index, 0, MAX_DELAY_VALUES); + for (i = 1; i < MAX_TSEL_VALUE; i ++) { + tsel = i; + for (j = 0; j < MAX_DELAY_VALUES; j++) { + msel = j/4; + hl = ((j/2)&1)^1; + quar = j&1; + + /* reset ddrc_controller */ + REG_DDRC_CTRL = DDRC_CTRL_RESET; + + /* Wait for precharge, > 200us */ + tmp_cnt = (cpu_clk / 1000000) * 200; + while (tmp_cnt--); + + REG_DDRC_CTRL = 0x0; + REG_DDRC_TIMING1 = ddrc_timing1_reg; + REG_DDRC_TIMING2 = ddrc_timing2_reg; + + ddr_mem_init(msel, hl, tsel, quar); + + memsize = initdram(0); + mem_base0 = DDR_MEM_PHY_BASE >> 24; + mem_base1 = (DDR_MEM_PHY_BASE + memsize / (DDR_CS1EN + DDR_CS0EN)) >> 24; + mem_mask1 = mem_mask0 = 0xff & + ~(((memsize/(DDR_CS1EN+DDR_CS0EN) >> 24) + - 1) & DDRC_MMAP_MASK_MASK); + + ddrc_mmap0_reg = mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0; + ddrc_mmap1_reg = mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1; + + REG_DDRC_MMAP0 = ddrc_mmap0_reg; + REG_DDRC_MMAP1 = ddrc_mmap1_reg; + + REG_DDRC_REFCNT = init_ddrc_refcnt; + + /* Enable DLL Detect */ + REG_DDRC_DQS = init_ddrc_dqs; + + while(!(REG_DDRC_DQS &( DDRC_DQS_ERROR | DDRC_DQS_READY))); + /* Set CKE High */ + REG_DDRC_CTRL = init_ddrc_ctrl; + + /* Wait for number of auto-refresh cycles */ + tmp_cnt = (cpu_clk / 1000000) * 10; + while (tmp_cnt--); + + /* Auto Refresh */ + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + + /* Wait for number of auto-refresh cycles */ + tmp_cnt = (cpu_clk / 1000000) * 10; + while (tmp_cnt--); + + tmp_cnt = (cpu_clk / 1000000) * 10; + while (tmp_cnt--); + + { + int result = 0; + result = ddr_dma_test(0); + if(result != 0) + serial_puts("FAIL!\n"); +#if DEBUG + serial_puts("result:"); + serial_put_hex(result); + serial_put_hex(num); +#endif + + if(result != 0) { + if (num > 0) + break; + else + continue; + } else { /* test pass */ + + mem_index[num] = j; + num++; + } + } + } + + if (num > 0) + break; + } + if (tsel == 3 && num == 0) + serial_puts("DDR INIT ERROR\n"); /* can't find a suitable mask delay. */ + index = 0; + for (i = 0; i < num; i++) { + index += mem_index[i]; + serial_put_hex(mem_index[i]); + } + +#ifdef DEBUG + serial_puts("index-1:"); + serial_put_hex(index); +#endif + + if (num) + index /= num; +#endif + + msel = index/4; + hl = ((index/2)&1)^1; + quar = index&1; + +#ifdef DEBUG + serial_puts("tsel"); + serial_put_hex(tsel); + serial_puts("num"); + serial_put_hex(num); + serial_puts("index-2:"); + serial_put_hex(index); +#endif + + /* reset ddrc_controller */ + REG_DDRC_CTRL = DDRC_CTRL_RESET; + + /* Wait for precharge, > 200us */ + tmp_cnt = (cpu_clk / 1000000) * 200; + while (tmp_cnt--); + + REG_DDRC_CTRL = 0x0; + REG_DDRC_TIMING1 = ddrc_timing1_reg; + REG_DDRC_TIMING2 = ddrc_timing2_reg; + + ddr_mem_init(msel, hl, tsel, quar); + + memsize = initdram(0); + mem_base0 = DDR_MEM_PHY_BASE >> 24; + mem_base1 = (DDR_MEM_PHY_BASE + memsize / (DDR_CS1EN + DDR_CS0EN)) >> 24; + mem_mask1 = mem_mask0 = 0xff & + ~(((memsize/(DDR_CS1EN+DDR_CS0EN) >> 24) + - 1) & DDRC_MMAP_MASK_MASK); + + ddrc_mmap0_reg = mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0; + ddrc_mmap1_reg = mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1; + + REG_DDRC_MMAP0 = ddrc_mmap0_reg; + REG_DDRC_MMAP1 = ddrc_mmap1_reg; + REG_DDRC_REFCNT = init_ddrc_refcnt; + + /* Enable DLL Detect */ + REG_DDRC_DQS = init_ddrc_dqs; + + /* Set CKE High */ + REG_DDRC_CTRL = init_ddrc_ctrl; + + /* Wait for number of auto-refresh cycles */ + tmp_cnt = (cpu_clk / 1000000) * 10; + while (tmp_cnt--); + + /* Auto Refresh */ + REG_DDRC_LMR = DDRC_LMR_CMD_AUREF | DDRC_LMR_START; //0x11; + + /* Wait for number of auto-refresh cycles */ + tmp_cnt = (cpu_clk / 1000000) * 10; + while (tmp_cnt--); + if(testall) + testallmem(); +} +#else +void sdram_init_4760(void) +{ + register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; + + unsigned int cas_latency_sdmr[2] = { + EMC_SDMR_CAS_2, + EMC_SDMR_CAS_3, + }; + + unsigned int cas_latency_dmcr[2] = { + 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ + 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ + }; + + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + + cpu_clk = CFG_CPU_SPEED; + mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; + + REG_EMC_BCR = 0; /* Disable bus release */ + REG_EMC_RTCSR = 0; /* Disable clock for counting */ + + /* Fault DMCR value for mode register setting*/ +#define SDRAM_ROW0 11 +#define SDRAM_COL0 8 +#define SDRAM_BANK40 0 + + dmcr0 = ((SDRAM_ROW0-11)< 11) tmp = 11; + dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); + tmp = SDRAM_RCD/ns; + if (tmp > 3) tmp = 3; + dmcr |= (tmp << EMC_DMCR_RCD_BIT); + tmp = SDRAM_TPC/ns; + if (tmp > 7) tmp = 7; + dmcr |= (tmp << EMC_DMCR_TPC_BIT); + tmp = SDRAM_TRWL/ns; + if (tmp > 3) tmp = 3; + dmcr |= (tmp << EMC_DMCR_TRWL_BIT); + tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; + if (tmp > 14) tmp = 14; + dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); + + /* SDRAM mode value */ + sdmode = EMC_SDMR_BT_SEQ | + EMC_SDMR_OM_NORMAL | + EMC_SDMR_BL_4 | + cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; + + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ + REG_EMC_DMCR = dmcr; + REG8(EMC_SDMR0|sdmode) = 0; + + /* Wait for precharge, > 200us */ + tmp = (cpu_clk / 1000000) * 1000; + while (tmp--); + + /* Stage 2. Enable auto-refresh */ + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; + + tmp = SDRAM_TREF/ns; + tmp = tmp/64 + 1; + if (tmp > 0xff) tmp = 0xff; + REG_EMC_RTCOR = tmp; + REG_EMC_RTCNT = 0; + REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ + + /* Wait for number of auto-refresh cycles */ + tmp = (cpu_clk / 1000000) * 1000; + while (tmp--); + + /* Stage 3. Mode Register Set */ + REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; + REG8(EMC_SDMR0|sdmode) = 0; + + /* Set back to basic DMCR value */ + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; + + /* everything is ok now */ +} +#endif + +void serial_setbrg_4760(void) +{ + volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR); + volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR); + volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR); + u32 baud_div, tmp; + + baud_div = (CFG_EXTAL / 16 / 57600); + tmp = *uart_lcr; + tmp |= UART_LCR_DLAB; + *uart_lcr = tmp; + + *uart_dlhr = (baud_div >> 8) & 0xff; + *uart_dllr = baud_div & 0xff; + + tmp &= ~UART_LCR_DLAB; + *uart_lcr = tmp; +} diff --git a/usbboot/xburst_stage1/board-jz4760.h b/usbboot/xburst_stage1/board-jz4760.h new file mode 100644 index 0000000..4058244 --- /dev/null +++ b/usbboot/xburst_stage1/board-jz4760.h @@ -0,0 +1,165 @@ +/* + * JZ4760 board definitions. + * + * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. + */ +#ifndef __BOARD_JZ4760_H__ +#define __BOARD_JZ4760_H__ + +//#define DEBUG +//#define CONFIG_FPGA +//#define CFG_DIV 2 /* for FPGA */ + +#define CFG_EXTAL 12000000 +#define CFG_CPU_SPEED 144000000 /* CPU clock */ + +#define CONFIG_DDRC +#define CONFIG_SDRAM_DDR2 +//#define CONFIG_SDRAM_MDDR +//#define CONFIG_SDRAM_DDR1 +//#define CONFIG_MOBILE_SDRAM + +#if (!defined(CONFIG_SDRAM_MDDR) && !defined(CONFIG_SDRAM_DDR1) && !defined(CONFIG_SDRAM_DDR2)) +/*----------------------------------------------------------------------- + * SDRAM Info. + */ +#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/ + +#ifndef CONFIG_MOBILE_SDRAM +// SDRAM paramters +#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ +#define SDRAM_ROW 13 /* Row address: 11 to 13 */ +#define SDRAM_COL 9 /* Column address: 8 to 12 */ +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ + +// SDRAM Timings, unit: ns +#define SDRAM_TRAS 45 /* RAS# Active Time */ +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ +#define SDRAM_TPC 20 /* RAS# Precharge Time */ +#define SDRAM_TRWL 7 /* Write Latency Time */ +#define SDRAM_TREF 7812 /* Refresh period: 4096 refresh cycles/64ms */ + +#else /* Mobile SDRAM */ +// SDRAM paramters +#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ +#define SDRAM_ROW 13 /* Row address: 11 to 13 */ +#define SDRAM_COL 9 /* Column address: 8 to 12 */ +#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */ + +// SDRAM Timings, unit: ns +#define SDRAM_TRAS 50 /* RAS# Active Time */ +#define SDRAM_RCD 18 /* RAS# to CAS# Delay */ +#define SDRAM_TPC 20 /* RAS# Precharge Time */ +#define SDRAM_TRWL 7 /* Write Latency Time */ +#define SDRAM_TREF 7812 /* Refresh period: 4096 refresh cycles/64ms */ +#endif /* CONFIG_MOBILE_SDRAM */ + +#else /* CONFIG_DDRC */ + +/*-------------------------------------------------------------------------------- + * DDR2 info + */ +/* Chip Select */ +#define DDR_CS1EN 0 // CSEN : whether a ddr chip exists 0 - un-used, 1 - used +#define DDR_CS0EN 1 +#define DDR_DW32 1 /* 0 - 16-bit data width, 1 - 32-bit data width */ + +/* SDRAM paramters */ +#if defined(CONFIG_SDRAM_DDR2) // ddr2 +#define DDR_ROW 13 /* ROW : 12 to 14 row address */ +#define DDR_COL 10 /* COL : 8 to 10 column address */ +#define DDR_BANK8 1 /* Banks each chip: 0-4bank, 1-8bank */ +#define DDR_CL 3 /* CAS latency: 1 to 7 */ + +/* + * ddr2 controller timing1 register + */ +#define DDR_tRAS 45 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */ +#define DDR_tRTP 8 /* 7.5ns READ to PRECHARGE command period. */ +#define DDR_tRP 42 /* tRP: PRECHARGE command period to the same bank */ +#define DDR_tRCD 42 /* ACTIVE to READ or WRITE command period to the same bank. */ +#define DDR_tRC 60 /* ACTIVE to ACTIVE command period to the same bank.*/ +#define DDR_tRRD 8 /* ACTIVE bank A to ACTIVE bank B command period. */ +#define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */ +#define DDR_tWTR 2 /* unit: tCK. WRITE to READ command delay. */ + +/* + * ddr2 controller timing2 register + */ +#define DDR_tRFC 128 /* ns, AUTO-REFRESH command period. */ +#define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */ +#define DDR_tXP 2 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */ +#define DDR_tMRD 2 /* unit: tCK. Load-Mode-Register to next valid command period: 1 to 4 tCK */ + +/* + * ddr2 controller refcnt register + */ +#define DDR_tREFI 7800 /* Refresh period: ns */ + +#elif defined(CONFIG_SDRAM_MDDR) // ddr1 and mddr +#define DDR_ROW 14 /* ROW : 12 to 14 row address */ +#define DDR_COL 10 /* COL : 8 to 10 column address */ +#define DDR_BANK8 0 /* Banks each chip: 0-4bank, 1-8bank */ +#define DDR_CL 3 /* CAS latency: 1 to 7 */ +/* + * ddr2 controller timing1 register + */ +#define DDR_tRAS 40 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */ +#define DDR_tRTP 12 /* 7.5ns READ to PRECHARGE command period. */ +#define DDR_tRP 15 /* tRP: PRECHARGE command period to the same bank */ +#define DDR_tRCD 20 /* ACTIVE to READ or WRITE command period to the same bank. */ +#define DDR_tRC 55 /* ACTIVE to ACTIVE command period to the same bank.*/ +#define DDR_tRRD 10 /* ACTIVE bank A to ACTIVE bank B command period. */ +#define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */ +#define DDR_tWTR 2 /* WRITE to READ command delay. */ +/* + * ddr2 controller timing2 register + */ +#define DDR_tRFC 90 /* ns, AUTO-REFRESH command period. */ +#define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */ +#define DDR_tXP 1 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */ +#define DDR_tMRD 2 /* unit: tCK Load-Mode-Register to next valid command period: 1 to 4 tCK */ +/* + * ddr2 controller refcnt register + */ +#define DDR_tREFI 7800 /* Refresh period: 4096 refresh cycles/64ms */ + +#elif defined(CONFIG_SDRAM_DDR1) // ddr1 and mddr +#define DDR_ROW 13 /* ROW : 12 to 14 row address */ +#define DDR_COL 10 /* COL : 8 to 10 column address */ +#define DDR_BANK8 0 /* Banks each chip: 0-4bank, 1-8bank */ +#define DDR_CL 3 /* CAS latency: 1 to 7 */ +#define DDR_CL_HALF 0 /*Only for DDR1, Half CAS latency: 0 or 1 */ +/* + * ddr2 controller timing1 register + */ +#define DDR_tRAS 40 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */ +#define DDR_tRTP 12 /* 7.5ns READ to PRECHARGE command period. */ +#define DDR_tRP 15 /* tRP: PRECHARGE command period to the same bank */ +#define DDR_tRCD 15 /* ACTIVE to READ or WRITE command period to the same bank. */ +#define DDR_tRC 55 /* ACTIVE to ACTIVE command period to the same bank.*/ +#define DDR_tRRD 10 /* ACTIVE bank A to ACTIVE bank B command period. */ +#define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */ +#define DDR_tWTR 2 /* WRITE to READ command delay 2*tCK */ +/* + * ddr2 controller timing2 register + */ +#define DDR_tRFC 70 /* ns, AUTO-REFRESH command period. */ +#define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */ +#define DDR_tXP 2 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */ +#define DDR_tMRD 2 /* unit: tCK. Load-Mode-Register to next valid command period: 1 to 4 tCK */ +/* + * ddr2 controller refcnt register + */ +#define DDR_tREFI 7800 /* Refresh period: 4096 refresh cycles/64ms */ + +#endif + +#define DDR_CLK_DIV 1 /* Clock Divider. auto refresh + * cnt_clk = memclk/(16*(2^DDR_CLK_DIV)) + */ +#endif /* CONFIG_DDRC */ + +#endif /* __BOARD_JZ4760_H__ */ diff --git a/usbboot/xburst_stage1/board_4750.c b/usbboot/xburst_stage1/board_4750.c deleted file mode 100755 index e4a75f8..0000000 --- a/usbboot/xburst_stage1/board_4750.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Board init routines. - * - * Copyright 2009 (C) Qi Hardware Inc., - * Author: Xiangfu Liu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 3 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA - */ - -#include -#include "target/jz4750.h" -#include "target/configs.h" - -void gpio_init_4750(void) -{ - __gpio_as_sdram_32bit(); - __gpio_as_uart1(); - __gpio_as_uart0(); - __gpio_as_uart2(); - __gpio_as_uart3(); - __gpio_as_nand_8bit(); -} - -void ccpll_init_4750(void) -{ - register unsigned int cfcr, plcr1; - int n2FR[33] = { - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, - 9 - }; -// int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */ - int nf, pllout2; - - cfcr = ~CPM_CPCCR_ECS & - (n2FR[1] << CPM_CPCCR_CDIV_BIT) | - (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | - (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | - (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | - (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); - - nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - /* init PLL */ - REG_CPM_CPCCR = cfcr; - REG_CPM_CPPCR = plcr1; -} - -int nf, pllout2; - -void pll_init_4750(void) -{ - register unsigned int cfcr, plcr1,tmp; - int n2FR[33] = { - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, - 9 - }; - int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */ - - cfcr = CPM_CPCCR_PCS | - (n2FR[1] << CPM_CPCCR_CDIV_BIT) | - (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | - (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | - (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | - (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); - - if (CFG_EXTAL > 16000000) - cfcr |= CPM_CPCCR_ECS; - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); - - /* Init USB Host clock, pllout2 must be n*48MHz */ -// REG_CPM_UHCCDR = pllout2 / 48000000 - 1; - - nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - cfcr |= CPM_CPCCR_UCS; /* set PLL as UDC PHY*/ - tmp = pllout2 / 1000000 / 12 - 1; - cfcr |= (tmp << CPM_CPCCR_UDIV_BIT); /* set UDC DIV*/ - - /* init PLL */ - REG_CPM_CPCCR = cfcr; - REG_CPM_CPPCR = plcr1; -} - -void sdram_init_4750(void) -{ - register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; - register unsigned int sdemode; /*SDRAM Extended Mode*/ - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - cpu_clk = CFG_CPU_SPEED; - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; - - /* set REG_EMC_DMAR0 for supporting 128MB sdram on DCS0 */ - REG_EMC_DMAR0 = EMC_DMAR0_BASE | EMC_DMAR_MASK_128_128; - - REG_EMC_BCR = 0; /* Disable bus release */ - REG_EMC_RTCSR = 0; /* Disable clock for counting */ - - /* Basic DMCR value */ - dmcr = ((SDRAM_ROW-11)< 11) tmp = 11; - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); - tmp = SDRAM_RCD/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_RCD_BIT); - tmp = SDRAM_TPC/ns; - if (tmp > 7) tmp = 7; - dmcr |= (tmp << EMC_DMCR_TPC_BIT); - tmp = SDRAM_TRWL/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_TRWL_BIT); - tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; - if (tmp > 14) tmp = 14; - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); - - /* SDRAM mode value */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ - REG_EMC_DMCR = dmcr; - REG8(EMC_SDMR0|sdmode) = 0; - - if (CONFIG_MOBILE_SDRAM == 1) - /* Mobile SDRAM Extended Mode Register */ - sdemode = EMC_SDMR_SET_BA1 | EMC_SDMR_DS_FULL | EMC_SDMR_PRSR_ALL; - - /* Wait for precharge, > 200us */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 2. Enable auto-refresh */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; - - tmp = SDRAM_TREF/ns; - tmp = tmp/64 + 1; - if (tmp > 0xff) tmp = 0xff; - REG_EMC_RTCOR = tmp; - REG_EMC_RTCNT = 0; - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ - - /* Wait for number of auto-refresh cycles */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 3. Mode Register Set */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET | EMC_DMCR_MBSEL_B0; - REG8(EMC_SDMR0|sdmode) = 0; - - if (CONFIG_MOBILE_SDRAM == 1) - REG8(EMC_SDMR0|sdemode) = 0; /* Set Mobile SDRAM Extended Mode Register */ - - /* Set back to basic DMCR value */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - - /* everything is ok now */ -} - -void serial_setbrg_4750(void) -{ - volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR); - volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR); - volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR); - u32 baud_div, tmp; - - baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ? - (CFG_EXTAL / 32 / CONFIG_BAUDRATE) : (CFG_EXTAL / 16 / CONFIG_BAUDRATE); - tmp = *uart_lcr; - tmp |= UART_LCR_DLAB; - *uart_lcr = tmp; - - *uart_dlhr = (baud_div >> 8) & 0xff; - *uart_dllr = baud_div & 0xff; - - tmp &= ~UART_LCR_DLAB; - *uart_lcr = tmp; -} - diff --git a/usbboot/xburst_stage1/common.c b/usbboot/xburst_stage1/common.c index 7d34956..3a95122 100644 --- a/usbboot/xburst_stage1/common.c +++ b/usbboot/xburst_stage1/common.c @@ -85,7 +85,7 @@ void serial_init(void) if ( CPU_ID == 0x4740 ) serial_setbrg_4740(); else - serial_setbrg_4750(); + serial_setbrg_4760(); /* Enable UART unit, enable and clear FIFO */ *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS; diff --git a/usbboot/xburst_stage1/debug.c b/usbboot/xburst_stage1/debug.c index a16f610..ff8355d 100644 --- a/usbboot/xburst_stage1/debug.c +++ b/usbboot/xburst_stage1/debug.c @@ -19,7 +19,7 @@ * Boston, MA 02110-1301, USA */ -#include "target/jz4750.h" +#include "target/jz4760.h" #include "target/configs.h" #include "usb_boot_defines.h" @@ -79,10 +79,10 @@ void do_debug() serial_init(); sdram_init_4740(); break; - case 0x4750: - gpio_init_4750(); + case 0x4760: + gpio_init_4760(); serial_init(); - sdram_init_4750(); + sdram_init_4760(); break; default: ; diff --git a/usbboot/xburst_stage1/main.c b/usbboot/xburst_stage1/main.c index 4c82f8b..89e6683 100644 --- a/usbboot/xburst_stage1/main.c +++ b/usbboot/xburst_stage1/main.c @@ -35,13 +35,13 @@ volatile u32 CFG_CPU_SPEED; volatile u32 CFG_EXTAL; volatile u8 PHM_DIV; volatile u8 IS_SHARE; -extern int pllout2; + #if 0 void test_load_args(void) { - CPU_ID = 0x4740 ; - CFG_EXTAL = 12000000 ; - CFG_CPU_SPEED = 252000000 ; + CPU_ID = 0x4760; + CFG_EXTAL = 12000000; + CFG_CPU_SPEED = 252000000; PHM_DIV = 3; fw_args->use_uart = 0; UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000; @@ -68,8 +68,6 @@ void load_args(void) CFG_CPU_SPEED = 192000000; } PHM_DIV = fw_args->phm_div; - if (fw_args->use_uart > 3) - fw_args->use_uart = 0; UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000; CONFIG_BAUDRATE = fw_args->boudrate; SDRAM_BW16 = fw_args->bus_width; @@ -96,11 +94,12 @@ void c_main(void) serial_init(); sdram_init_4740(); break; - case 0x4750: - gpio_init_4750(); - pll_init_4750(); + case 0x4760: + gpio_init_4760(); + cpm_start_all_4760(); serial_init(); - sdram_init_4750(); + pll_init_4760(); + sdram_init_4760(); break; default: return; @@ -117,8 +116,13 @@ void c_main(void) serial_put_hex(SDRAM_BANK4); serial_put_hex(SDRAM_ROW); serial_put_hex(SDRAM_COL); - serial_put_hex(pllout2); serial_put_hex(REG_CPM_CPCCR); #endif serial_puts("xburst stage1 run finish !\n"); + if (CPU_ID == 0x4760) { + __asm__ ( + "li $31, 0xbfc012e0 \n\t" + "jr $31 \n\t " + ); + } }