diff --git a/qiboot/src/cpu/s3c6410/om_3d7k.c b/qiboot/src/cpu/s3c6410/om_3d7k.c index 814d4d8..fc97705 100644 --- a/qiboot/src/cpu/s3c6410/om_3d7k.c +++ b/qiboot/src/cpu/s3c6410/om_3d7k.c @@ -96,6 +96,107 @@ void port_init_om_3d7k(void) { int n; + __REG(HCLK_GATE) = + (0 << 31) | /* 3D unit */ + (1 << 30) | /* reserved */ + (0 << 29) | /* USB host */ + (0 << 28) | /* "security subsystem" */ + (1 << 27) | /* SDMA1 */ + (1 << 26) | /* SDMA0 */ + (0 << 25) | /* iROM */ + (1 << 24) | /* DDR 1 */ + (1 << 23) | /* reserved */ + (1 << 22) | /* DMC1 */ + (1 << 21) | /* SROM / NAND controller / NAND */ + (0 << 20) | /* USB OTG */ + (0 << 19) | /* HSMMC 2 */ + (0 << 18) | /* HSMMC 1 */ + (1 << 17) | /* HSMMC 0 */ + (0 << 16) | /* MDP */ + (0 << 15) | /* direct host */ + (0 << 14) | /* indirect host */ + (1 << 13) | /* DMA1 */ + (1 << 12) | /* DMA0 */ + (0 << 11) | /* JPEG */ + (0 << 10) | /* camera */ + (0 << 9) | /* scaler */ + (0 << 8) | /* 2D */ + (0 << 7) | /* TV */ + (1 << 6) | /* reserved */ + (0 << 5) | /* POST0 */ + (0 << 4) | /* rotator */ + (1 << 3) | /* LCD controller */ + (1 << 2) | /* TZICs */ + (1 << 1) | /* VICs */ + (0 << 0) /* MFC */ + ; + __REG(PCLK_GATE) = + (0x1f << 28) | /* reserved */ + (0 << 27) | /* I2C1 */ + (0 << 26) | /* IIS2 */ + (1 << 25) | /* reserved */ + (0 << 24) | /* security key */ + (1 << 23) | /* chip ID */ + (0 << 22) | /* SPI1 */ + (0 << 21) | /* SPI0 */ + (0 << 20) | /* HSI RX */ + (0 << 19) | /* HSI TX */ + (1 << 18) | /* GPIO */ + (1 << 17) | /* I2C 0 */ + (1 << 16) | /* IIS1 */ + (1 << 15) | /* IIS0 */ + (0 << 14) | /* AC97 */ + (0 << 13) | /* TZPC */ + (0 << 12) | /* TS ADC */ + (0 << 11) | /* keypad */ + (0 << 10) | /* IRDA */ + (0 << 9) | /* PCM1 */ + (0 << 8) | /* PCM0 */ + (1 << 7) | /* PWM */ + (0 << 6) | /* RTC */ + (1 << 5) | /* WDC */ + (1 << 4) | /* UART3 */ + (1 << 3) | /* UART2 */ + (1 << 2) | /* UART1 */ + (1 << 1) | /* UART0 */ + (0 << 0) /* MFC */ + ; + + __REG(SCLK_GATE) = + (1 << 31) | + (0 << 30) | /* USB Host */ + (0 << 29) | /* HSMMC2 48MHz */ + (0 << 28) | /* HSMMC1 48MHz */ + (0 << 27) | /* HSMMC0 48MHz */ + (0 << 26) | /* HSMMC2 */ + (0 << 25) | /* HSMMC1 */ + (1 << 24) | /* HSMMC0 */ + (0 << 23) | /* SPI1 - 48MHz */ + (0 << 22) | /* SPI0 - 48MHz */ + (0 << 21) | /* SPI1 */ + (0 << 20) | /* SPI0 */ + (0 << 19) | /* TV DAC */ + (0 << 18) | /* TV encoder */ + (0 << 17) | /* scaler 27 */ + (0 << 16) | /* scaler */ + (0 << 15) | /* LCD 27MHz */ + (1 << 14) | /* LCD */ + (1 << 13) | /* camera and LCD */ + (0 << 12) | /* POST0 */ + (0 << 11) | /* AUDIO2 */ + (0 << 10) | /* POST0 again */ + (1 << 9) | /* IIS1 */ + (1 << 8) | /* IIS0 */ + (0 << 7) | /* security */ + (0 << 6) | /* IRDA */ + (1 << 5) | /* UART */ + (1 << 4) | /* reserved */ + (0 << 3) | /* MFC */ + (0 << 2) | /* Cam */ + (0 << 1) | /* JPEG */ + (1 << 0) /* reserved */ + ; + /* ---------------------------- Port A ---------------------------- */ __REG(GPACON) =