# Configuration variables:
# STAGE1_FILE, STAGE2_FILE

set STAGE1_FILE fw.bin
set STAGE2_FILE usb_boot.bin

set EXTCLK            12     # Define the external crystal in MHz
set CPUSPEED          252    # Define the PLL output frequency
set PHMDIV            3      # Define the frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK
set BAUDRATE          57600  # Define the uart baudrate
set USEUART           0      # UART number

set SDRAM_BUSWIDTH    16     # The bus width of the SDRAM in bits (16|32)
set SDRAM_BANKS       4      # The bank number (2|4)
set SDRAM_ROWADDR     13     # Row address width in bits (11-13)
set SDRAM_COLADDR     9      # Column address width in bits (8-12)
set SDRAM_ISMOBILE    0      # Define whether SDRAM is mobile SDRAM (only or Jz4750), 1: yes 0: no
set SDRAM_ISBUSSHARE  1      # Define whether SDRAM bus share with NAND 1:shared 0:unshared

set NAND_BUSWIDTH     8      # The width of the NAND flash chip in bits (8|16|32)
set NAND_ROWCYCLES    3      # The row address cycles (2|3)
set NAND_PAGESIZE     2048   # The page size of the NAND chip in bytes(512|2048|4096)
set NAND_PAGEPERBLOCK 128    # The page number per block
set NAND_FORCEERASE   1      # The force to erase flag (0|1)
set NAND_OOBSIZE      64     # OOB size in byte
set NAND_ECCPOS       8      # Specify the ECC offset inside the oob data (0-[oobsize-1])
set NAND_BADBLOCKPOS  0      # Specify the badblock flag offset inside the oob (0-[oobsize-1])
set NAND_BADBLOCKPAGE 0      # Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
set NAND_PLANENUM     1      # The planes number of target nand flash
set NAND_BCHBIT       8      # Specify the hardware BCH algorithm for 4750 (4|8)
set NAND_WPPIN        0      # Specify the write protect pin number
set NAND_BLOCKPERCHIP 4096   # Specify the block number per chip,0 means ignore

rebuildcfg