#
# usbboot configuration file
#
# Utility to respond to the Ingenic XBurst USB boot protocol, provide
# initial boot stages and ability to access NAND on device.
#
# Authors: Ingenic Semiconductor, Inc.
#          Xiangfu Liu <xiangfu@qi-hardware.com>
#          Marek Lindner <lindner_marek@yahoo.de>
#          Wolfgang Spraul <wolfgang@qi-hardware.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# as published by the Free Software Foundation; either version
# 3 of the License, or (at your option) any later version.
#

# [PLL]
EXTCLK = 12	#Define the external crystal in MHz
CPUSPEED = 252	#Define the PLL output frequency
PHMDIV = 3	#Define the frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK
BOUDRATE = 57600	#Define the uart boudrate
USEUART = 0	#Use which uart, 0/1 for jz4740,0/1/2/3 for jz4750

# [SDRAM]
BUSWIDTH = 16	#The bus width of the SDRAM in bits (16|32)
BANKS = 4	#The bank number (2|4)
ROWADDR = 13	#Row address width in bits (11-13)
COLADDR = 9	#Column address width in bits (8-12)
ISMOBILE = 0	#Define whether SDRAM is mobile SDRAM, this only valid for Jz4750 ,1:yes 0:no
ISBUSSHARE = 1	#Define whether SDRAM bus share with NAND 1:shared 0:unshared
DEBUGOPS = 0

# [NAND]
NAND_BUSWIDTH = 8	#The width of the NAND flash chip in bits (8|16|32)
NAND_ROWCYCLES = 3	#The row address cycles (2|3)
NAND_PAGESIZE = 2048	#The page size of the NAND chip in bytes(512|2048|4096)
NAND_PAGEPERBLOCK = 128	#The page number per block
NAND_FORCEERASE = 1	#The force to erase flag (0|1)
NAND_OOBSIZE = 64	#oob size in byte
NAND_ECCPOS = 6		#Specify the ECC offset inside the oob data (0-[oobsize-1])
NAND_BADBLOCKPOS = 0	#Specify the badblock flag offset inside the oob (0-[oobsize-1])
NAND_BADBLOCKPAGE = 127	#Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
NAND_PLANENUM = 1	#The planes number of target nand flash
NAND_BCHBIT = 4		#Specify the hardware BCH algorithm for 4750 (4|8)
NAND_WPPIN = 0		#Specify the write protect pin number
NAND_BLOCKPERCHIP = 0	#Specify the block number per chip,0 means ignore

#The program will calculate the total SDRAM size by : size = 2^(ROWADDR + COLADDR) * BANKNUM * (SDRAMWIDTH / 4)
#The CPUSPEED has restriction as: ( CPUSPEED % EXTCLK == 0 ) && ( CPUSPEED % 12 == 0 )
#For jz4750, the program just init BANK0(DSC0).
#Beware all variables must be set correct!