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107 lines
2.4 KiB
C
107 lines
2.4 KiB
C
/*
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* cpu.c
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*
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* CPU common routines
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*
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* Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
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* Author: Peter Wei <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <types.h>
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/*
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* Cache Operations
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*/
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#define Index_Invalidate_I 0x00
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#define Index_Writeback_Inv_D 0x01
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#define Index_Invalidate_SI 0x02
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#define Index_Writeback_Inv_SD 0x03
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#define Index_Load_Tag_I 0x04
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#define Index_Load_Tag_D 0x05
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#define Index_Load_Tag_SI 0x06
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#define Index_Load_Tag_SD 0x07
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#define Index_Store_Tag_I 0x08
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#define Index_Store_Tag_D 0x09
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#define Index_Store_Tag_SI 0x0A
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#define Index_Store_Tag_SD 0x0B
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#define Create_Dirty_Excl_D 0x0d
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#define Create_Dirty_Excl_SD 0x0f
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#define Hit_Invalidate_I 0x10
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#define Hit_Invalidate_D 0x11
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#define Hit_Invalidate_SI 0x12
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#define Hit_Invalidate_SD 0x13
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#define Fill 0x14
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#define Hit_Writeback_Inv_D 0x15
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/* 0x16 is unused */
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#define Hit_Writeback_Inv_SD 0x17
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#define Hit_Writeback_I 0x18
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#define Hit_Writeback_D 0x19
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/* 0x1a is unused */
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#define Hit_Writeback_SD 0x1b
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/* 0x1c is unused */
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/* 0x1e is unused */
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#define Hit_Set_Virtual_SI 0x1e
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#define Hit_Set_Virtual_SD 0x1f
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#define CFG_DCACHE_SIZE 16384
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#define CFG_ICACHE_SIZE 16384
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#define CFG_CACHELINE_SIZE 32
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#define K0BASE 0x80000000
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void flush_icache_all(void)
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{
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unsigned int addr, t = 0;
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asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
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asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
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for (addr = K0BASE; addr < K0BASE + CFG_ICACHE_SIZE;
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addr += CFG_CACHELINE_SIZE) {
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asm volatile (
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".set mips3\n\t"
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" cache %0, 0(%1)\n\t"
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".set mips2\n\t"
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:
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: "I" (Index_Store_Tag_I), "r"(addr));
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}
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/* invalicate btb */
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asm volatile (
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".set mips32\n\t"
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"mfc0 %0, $16, 7\n\t"
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"nop\n\t"
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"ori %0,2\n\t"
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"mtc0 %0, $16, 7\n\t"
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".set mips2\n\t"
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:
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: "r" (t));
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}
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void flush_dcache_all(void)
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{
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unsigned int addr;
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for (addr = K0BASE; addr < K0BASE + CFG_DCACHE_SIZE;
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addr += CFG_CACHELINE_SIZE) {
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asm volatile (
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".set mips3\n\t"
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" cache %0, 0(%1)\n\t"
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".set mips2\n\t"
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:
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: "I" (Index_Writeback_Inv_D), "r"(addr));
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}
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asm volatile ("sync");
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}
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void flush_cache_all(void)
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{
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flush_dcache_all();
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flush_icache_all();
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}
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