mirror of
git://projects.qi-hardware.com/xburst-tools.git
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d06a3c2c3a
This is the script for gta03 load by openocd. We use the single qi image for all purposes now so U-Boot lowlevel_foo style crap is dead. We have to run the first part of init before copying qi image to TEXT_BASE (0x33000000) because DRAM is not functional until then. Fixed branchthrough at 0x8 is used as a place to hang the breakpoint. Signed-off-by: Andy Green <andy@openmoko.com>
250 lines
5.5 KiB
ArmAsm
250 lines
5.5 KiB
ArmAsm
/*
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* (C) Copyright 2007 OpenMoko, Inc.
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*
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* Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define __ASM_MODE__
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#include <neo_gta02.h>
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.globl _start
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_start: b start_code
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/* if we are injected by JTAG, the script sets _istag content to nonzero */
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_is_jtag:
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.word 0
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/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script
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* we need to go through this hassle because before this moment, SDRAM is not
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* working so we can't prep it from JTAG
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*/
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_steppingstone_done:
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ldr pc, _start_armboot
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_start_armboot:
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.word start_qi
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_TEXT_BASE:
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.word TEXT_BASE
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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start_code:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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# define pWTCON 0x53000000
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ldr r0, =pWTCON
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mov r1, #0x0
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str r1, [r0]
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/*
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* mask all IRQs by setting all bits in the INTMR - default
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*/
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# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
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# define INTSUBMSK 0x4A00001C
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# define INTSUBMSK_val 0x0000ffff
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mov r1, #0xffffffff
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ldr r0, =INTMSK
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str r1, [r0]
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ldr r1, =INTSUBMSK_val
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ldr r0, =INTSUBMSK
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str r1, [r0]
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/* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
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# define CAMDIVN 0x4C000018
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ldr r0, =CAMDIVN
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mov r1, #0
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str r1, [r0]
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/* Clock asynchronous mode */
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mrc p15, 0, r1, c1, c0, 0
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orr r1, r1, #0xc0000000
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mcr p15, 0, r1, c1, c0, 0
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#define LOCKTIME 0x4c000000
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ldr r0, =LOCKTIME
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mov r1, #0xffffff
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str r1, [r0]
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# define UPLLCON 0x4c000008
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# define MPLLCON_val ((142 << 12) + (7 << 4) + 1)
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# define UPLLCON_val (( 88 << 12) + (8 << 4) + 2)
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ldr r0, =UPLLCON
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ldr r1, =UPLLCON_val
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str r1, [r0]
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/* Page 7-19, seven nops between UPLL and MPLL */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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ldr r1, =MPLLCON_val
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str r1, [r0, #-4] /* MPLLCON */
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# define CLKDIVN 0x4C000014 /* clock divisor register */
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# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
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/* FCLK:HCLK:PCLK = 1:3:6 */
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ldr r0, =CLKDIVN
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mov r1, #CLKDIVN_val
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str r1, [r0]
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/* enable only CPU peripheral block clocks we actually use */
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ldr r0, =0x4c00000c /* clkcon */
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ldr r1, =0x3d10 /* uart, pwm, gpio, nand clocks on */
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str r1, [r0]
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/* gpio UART2 init, H port */
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ldr r0, =0x56000070
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ldr r1, =0x001AAAAA
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str r1, [r0]
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/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
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ldr r0, =0x56000000 /* GPJ base */
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ldr r1, [r0, #0xd0] /* GPJCON */
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orr r1, r1, #(1 << 16)
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str r1, [r0, #0xd0]
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ldr r1, [r0, #0xd4] /* GPJDAT */
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orr r1, r1, #(1 << 8)
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str r1, [r0, #0xd4]
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/* init uart2 */
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ldr r0, =0x50008000
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mov r1, #0x03
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str r1, [r0]
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ldr r1, =0x245
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str r1, [r0, #0x04]
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mov r1, #0x00
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str r1, [r0, #0x08]
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mov r1, #0x00
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str r1, [r0, #0x0c]
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mov r1, #0x11
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str r1, [r0, #0x28]
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ldr r0, =0x50008000
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ldr r1, =0x54
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str r1, [r0, #0x20]
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bl cpu_init_crit
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/* reset nand controller, or it is dead to us */
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mov r1, #0x4E000000
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ldr r2, =0xfff0 @ initial value tacls=3,rph0=7,rph1=7
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ldr r3, [r1, #0]
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orr r3, r3, r2
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str r3, [r1, #0]
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ldr r3, [r1, #4]
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orr r3, r3, #1 @ enable nand controller
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str r3, [r1, #4]
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/* >> CFG_VIDEO_LOGO_MAX_SIZE */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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stack_setup:
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ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
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sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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mov r2, #0x00000000 /* clear */
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clbss_l:
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str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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ble clbss_l
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/* we are going to jump into the C part of the init now */
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spin:
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b _steppingstone_done
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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mov ip, lr
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bl lowlevel_init
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mov lr, ip
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mov pc, lr
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