2010-08-09 23:37:18 +03:00
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# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 03:31:28 PM COT
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2010-07-24 14:58:53 +03:00
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2010-08-09 23:37:18 +03:00
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( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
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( H9 N-000119 )
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( U11 N-000119 )
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( F11 N-000119 )
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( R6 N-000119 )
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( M15 N-000119 )
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( V6 N-000119 )
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( G12 N-000119 )
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( H15 N-000119 )
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( D16 N-000119 )
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( K15 N-000119 )
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( R12 N-000119 )
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( N8 N-000119 )
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( R14 N-000118 )
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( N12 N-000118 )
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( J10 N-000118 )
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( J12 N-000118 )
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( J14 N-000118 )
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( J8 N-000118 )
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( K11 N-000118 )
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( K13 N-000118 )
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( K9 N-000118 )
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( L10 N-000118 )
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( L12 N-000118 )
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( L14 N-000118 )
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( M11 N-000118 )
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( M13 N-000118 )
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( M9 N-000118 )
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( N14 N-000118 )
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( G13 ? )
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( G8 ? )
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( G9 ? )
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( H10 ? )
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( H11 ? )
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( H12 ? )
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( H13 ? )
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( H14 ? )
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( P16 ? )
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( D13 ? )
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( AA1 ? )
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( N15 ? )
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( E18 ? )
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( C18 ? )
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( G11 ? )
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( F9 ? )
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( F8 ? )
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( E8 ? )
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( R17 ? )
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( Y22 ? )
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( P10 GND )
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( V10 GND )
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( M10 GND )
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( K10 GND )
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( L13 GND )
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( A1 GND )
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( N13 GND )
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( A22 GND )
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( R5 GND )
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2010-08-08 20:15:44 +03:00
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( AA13 GND )
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2010-08-09 23:37:18 +03:00
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( W19 GND )
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2010-08-08 20:15:44 +03:00
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( AA17 GND )
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2010-08-09 23:37:18 +03:00
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( K14 GND )
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( AA5 GND )
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( L5 GND )
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( AA9 GND )
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( M14 GND )
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( AB1 GND )
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( N2 GND )
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( AB22 GND )
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( P14 GND )
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( B13 GND )
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( U21 GND )
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( B17 GND )
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( V4 GND )
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( B5 GND )
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( J9 GND )
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( B9 GND )
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( K12 GND )
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( D18 GND )
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( L11 GND )
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( D4 GND )
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( L18 GND )
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( E11 GND )
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( L9 GND )
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( E15 GND )
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( M12 GND )
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( E2 GND )
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( N11 GND )
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( E21 GND )
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( N17 GND )
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( E7 GND )
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( N21 GND )
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( G18 GND )
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( P12 GND )
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( G5 GND )
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( R18 GND )
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( H7 GND )
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( U2 GND )
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( J11 GND )
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( U7 GND )
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( J13 GND )
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( V14 GND )
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( J15 GND )
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( W16 GND )
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( J2 GND )
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( W7 GND )
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( J21 GND )
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( N9 GND )
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( AA15 N-000123 )
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( V16 N-000123 )
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( T13 N-000123 )
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( V8 N-000123 )
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( V12 N-000123 )
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( AA3 N-000123 )
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( T9 N-000123 )
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( AA19 N-000123 )
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( AA11 N-000123 )
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( W5 N-000123 )
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( AA7 N-000123 )
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( AA12 ? )
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2010-08-08 20:15:44 +03:00
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( AB12 ? )
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2010-08-09 23:37:18 +03:00
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( Y11 ? )
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( AB11 ? )
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( R11 ? )
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( T11 ? )
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( AA10 ? )
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( AB10 ? )
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( V11 ? )
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( W11 ? )
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( Y9 ? )
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( AB9 ? )
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( W10 ? )
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( Y7 ? )
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( AB7 ? )
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( T8 ? )
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( Y5 ? )
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( T5 ? )
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2010-08-08 20:15:44 +03:00
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( AB13 ? )
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2010-08-09 23:37:18 +03:00
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( Y13 ? )
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( Y12 ? )
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( W12 ? )
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( R13 ? )
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( T14 ? )
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( U12 ? )
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( T12 ? )
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2010-08-08 20:15:44 +03:00
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( AB15 ? )
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2010-08-09 23:37:18 +03:00
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( Y15 ? )
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( Y14 ? )
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( W14 ? )
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2010-08-08 20:15:44 +03:00
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( AB16 ? )
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2010-08-09 23:37:18 +03:00
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( AA16 ? )
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( W13 ? )
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( V13 ? )
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( W15 ? )
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( Y16 ? )
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( AB14 ? )
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( AA14 ? )
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2010-08-08 20:15:44 +03:00
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( AB17 ? )
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2010-08-09 23:37:18 +03:00
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( Y17 ? )
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2010-08-08 20:15:44 +03:00
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( AB18 ? )
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2010-08-09 23:37:18 +03:00
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( AA18 ? )
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( V15 ? )
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( U15 ? )
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( U13 ? )
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( U14 ? )
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( W17 ? )
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( R15 ? )
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( R16 ? )
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( V18 ? )
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( V19 ? )
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( U16 ? )
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( T15 ? )
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( T16 ? )
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( Y18 ? )
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( W18 ? )
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2010-08-08 20:15:44 +03:00
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( AB19 ? )
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2010-08-09 23:37:18 +03:00
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( Y19 ? )
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( T17 ? )
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( T18 ? )
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2010-07-24 14:58:53 +03:00
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( AB20 ? )
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2010-08-09 23:37:18 +03:00
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( AA20 ? )
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2010-08-08 20:15:44 +03:00
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( AB21 ? )
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2010-08-09 23:37:18 +03:00
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( AA21 ? )
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( AA22 ? )
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( W2 N-000120 )
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( L2 N-000120 )
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( L7 N-000120 )
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( C2 N-000120 )
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( N5 N-000120 )
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( R2 N-000120 )
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( U5 N-000120 )
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( G2 N-000120 )
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( F4 N-000120 )
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( F6 N-000120 )
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( J5 N-000120 )
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( M3 /DDR_Banks/M0_UDM )
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( L4 /DDR_Banks/M0_LDM )
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( K5 /DDR_Banks/M0_RAS# )
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( K4 /DDR_Banks/M0_CAS# )
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( K3 /DDR_Banks/M0_A5 )
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( J4 /DDR_Banks/M0_A6 )
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( K6 /DDR_Banks/M0_A3 )
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( J6 ? )
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( H4 /DDR_Banks/M0_CLK )
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( H3 /DDR_Banks/M0_CLK# )
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( H2 /DDR_Banks/M0_A0 )
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( H1 /DDR_Banks/M0_A1 )
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( G3 ? )
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( G1 ? )
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( H6 /DDR_Banks/M0_A7 )
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( H5 /DDR_Banks/M0_A2 )
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( F2 /DDR_Banks/M0_WE# )
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( F1 ? )
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( G4 /DDR_Banks/M0_A10 )
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( F3 /DDR_Banks/M0_A4 )
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( E3 /DDR_Banks/M0_A8 )
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( E1 /DDR_Banks/M0_A9 )
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( D2 /DDR_Banks/M0_CKE )
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( D1 /DDR_Banks/M0_A12 )
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( C3 ? )
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( C1 /DDR_Banks/M0_A11 )
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( G6 ? )
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( F5 ? )
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( K7 ? )
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( K8 ? )
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( D5 ? )
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( E4 ? )
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( J7 ? )
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( H8 ? )
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( B2 ? )
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( B1 ? )
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( G7 ? )
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( F7 ? )
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( D3 ? )
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( C4 ? )
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( E5 ? )
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( E6 ? )
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( A2 ? )
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( B3 ? )
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( J1 /DDR_Banks/M0_DQ5 )
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( J3 /DDR_Banks/M0_DQ4 )
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( K1 /DDR_Banks/M0_DQ7 )
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( K2 /DDR_Banks/M0_DQ6 )
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( L1 ? )
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( L3 /DDR_Banks/M0_LDQS )
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( M1 /DDR_Banks/M0_DQ3 )
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( M2 /DDR_Banks/M0_DQ2 )
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( N1 /DDR_Banks/M0_DQ1 )
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( N3 /DDR_Banks/M0_DQ0 )
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( P1 /DDR_Banks/M0_DQ9 )
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( P2 /DDR_Banks/M0_DQ8 )
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( R1 /DDR_Banks/M0_DQ11 )
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( R3 /DDR_Banks/M0_DQ10 )
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( T1 ? )
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( T2 /DDR_Banks/M0_UDQS )
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( U1 /DDR_Banks/M0_DQ13 )
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( U3 /DDR_Banks/M0_DQ12 )
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( V1 /DDR_Banks/M0_DQ15 )
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( V2 /DDR_Banks/M0_DQ14 )
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( M4 ? )
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( M5 ? )
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( N4 ? )
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( P3 ? )
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( L6 ? )
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( M6 ? )
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( P4 ? )
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( R4 ? )
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( M8 ? )
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( M7 ? )
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( N7 ? )
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( N6 ? )
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|
( V3 ? )
|
|
|
|
|
( U4 ? )
|
|
|
|
|
( T3 ? )
|
|
|
|
|
( T4 ? )
|
|
|
|
|
( P5 ? )
|
|
|
|
|
( P6 ? )
|
|
|
|
|
( P7 ? )
|
|
|
|
|
( P8 ? )
|
|
|
|
|
( W1 ? )
|
|
|
|
|
( W3 ? )
|
|
|
|
|
( Y1 ? )
|
|
|
|
|
( W21 N-000121 )
|
|
|
|
|
( C21 N-000121 )
|
|
|
|
|
( G21 N-000121 )
|
|
|
|
|
( J18 N-000121 )
|
|
|
|
|
( L16 N-000121 )
|
|
|
|
|
( L21 N-000121 )
|
|
|
|
|
( N18 N-000121 )
|
|
|
|
|
( R21 N-000121 )
|
|
|
|
|
( U18 N-000121 )
|
|
|
|
|
( E19 N-000121 )
|
|
|
|
|
( L19 /DDR_Banks/M1_LDM )
|
|
|
|
|
( J20 /DDR_Banks/M1_DQ4 )
|
|
|
|
|
( J22 /DDR_Banks/M1_DQ5 )
|
|
|
|
|
( K21 /DDR_Banks/M1_DQ6 )
|
|
|
|
|
( K22 /DDR_Banks/M1_DQ7 )
|
|
|
|
|
( L20 /DDR_Banks/M1_LDQS )
|
|
|
|
|
( L22 ? )
|
|
|
|
|
( M21 /DDR_Banks/M1_DQ2 )
|
|
|
|
|
( M22 /DDR_Banks/M1_DQ3 )
|
|
|
|
|
( N20 /DDR_Banks/M1_DQ0 )
|
|
|
|
|
( N22 /DDR_Banks/M1_DQ1 )
|
|
|
|
|
( P21 /DDR_Banks/M1_DQ8 )
|
|
|
|
|
( P22 /DDR_Banks/M1_DQ9 )
|
|
|
|
|
( R20 /DDR_Banks/M1_DQ10 )
|
|
|
|
|
( R22 /DDR_Banks/M1_DQ11 )
|
|
|
|
|
( T21 /DDR_Banks/M1_UDQS )
|
|
|
|
|
( T22 ? )
|
|
|
|
|
( U20 /DDR_Banks/M1_DQ12 )
|
|
|
|
|
( U22 /DDR_Banks/M1_DQ13 )
|
|
|
|
|
( V21 /DDR_Banks/M1_DQ14 )
|
|
|
|
|
( V22 /DDR_Banks/M1_DQ15 )
|
|
|
|
|
( M19 ? )
|
|
|
|
|
( N19 ? )
|
|
|
|
|
( M16 ? )
|
|
|
|
|
( L15 ? )
|
|
|
|
|
( P19 ? )
|
|
|
|
|
( P20 ? )
|
|
|
|
|
( W20 ? )
|
|
|
|
|
( W22 ? )
|
|
|
|
|
( L17 ? )
|
|
|
|
|
( K18 ? )
|
|
|
|
|
( U19 ? )
|
|
|
|
|
( V20 ? )
|
|
|
|
|
( M17 ? )
|
|
|
|
|
( M18 ? )
|
|
|
|
|
( P17 ? )
|
|
|
|
|
( N16 ? )
|
|
|
|
|
( P18 ? )
|
|
|
|
|
( R19 ? )
|
|
|
|
|
( T19 ? )
|
|
|
|
|
( T20 ? )
|
|
|
|
|
( M20 /DDR_Banks/M1_UDM )
|
|
|
|
|
( H22 /DDR_Banks/M1_CAS# )
|
|
|
|
|
( H21 /DDR_Banks/M1_RAS# )
|
|
|
|
|
( K19 /DDR_Banks/M1_A6 )
|
|
|
|
|
( K20 /DDR_Banks/M1_A5 )
|
|
|
|
|
( G22 ? )
|
|
|
|
|
( G20 /DDR_Banks/M1_A3 )
|
|
|
|
|
( J19 /DDR_Banks/M1_CLK# )
|
|
|
|
|
( H20 /DDR_Banks/M1_CLK )
|
|
|
|
|
( F22 /DDR_Banks/M1_A1 )
|
|
|
|
|
( F21 /DDR_Banks/M1_A0 )
|
|
|
|
|
( K17 ? )
|
|
|
|
|
( J17 ? )
|
|
|
|
|
( E22 /DDR_Banks/M1_A2 )
|
|
|
|
|
( E20 /DDR_Banks/M1_A7 )
|
|
|
|
|
( H18 ? )
|
|
|
|
|
( H19 /DDR_Banks/M1_WE# )
|
|
|
|
|
( F20 /DDR_Banks/M1_A4 )
|
|
|
|
|
( G19 /DDR_Banks/M1_A10 )
|
|
|
|
|
( C22 /DDR_Banks/M1_A9 )
|
|
|
|
|
( C20 /DDR_Banks/M1_A8 )
|
|
|
|
|
( D22 /DDR_Banks/M1_A12 )
|
|
|
|
|
( D21 /DDR_Banks/M1_CKE )
|
|
|
|
|
( F19 /DDR_Banks/M1_A11 )
|
|
|
|
|
( F18 ? )
|
|
|
|
|
( D20 ? )
|
|
|
|
|
( D19 ? )
|
|
|
|
|
( H17 ? )
|
|
|
|
|
( H16 ? )
|
|
|
|
|
( J16 ? )
|
|
|
|
|
( K16 ? )
|
|
|
|
|
( A21 ? )
|
|
|
|
|
( A20 ? )
|
|
|
|
|
( B22 ? )
|
|
|
|
|
( B21 ? )
|
|
|
|
|
( F17 ? )
|
|
|
|
|
( F16 ? )
|
|
|
|
|
( G17 ? )
|
|
|
|
|
( G16 ? )
|
|
|
|
|
( B20 ? )
|
|
|
|
|
( B4 N-000122 )
|
|
|
|
|
( B7 N-000122 )
|
|
|
|
|
( E13 N-000122 )
|
|
|
|
|
( E17 N-000122 )
|
|
|
|
|
( G10 N-000122 )
|
|
|
|
|
( G14 N-000122 )
|
|
|
|
|
( B11 N-000122 )
|
|
|
|
|
( B15 N-000122 )
|
|
|
|
|
( B19 N-000122 )
|
|
|
|
|
( E9 N-000122 )
|
|
|
|
|
( A11 ? )
|
|
|
|
|
( D11 ? )
|
|
|
|
|
( C12 ? )
|
|
|
|
|
( B12 ? )
|
|
|
|
|
( A12 ? )
|
|
|
|
|
( C13 ? )
|
|
|
|
|
( A13 ? )
|
|
|
|
|
( D14 ? )
|
|
|
|
|
( C14 ? )
|
|
|
|
|
( B14 ? )
|
|
|
|
|
( A14 ? )
|
|
|
|
|
( C15 ? )
|
|
|
|
|
( A15 ? )
|
|
|
|
|
( D15 ? )
|
|
|
|
|
( C16 ? )
|
|
|
|
|
( B16 ? )
|
|
|
|
|
( A16 ? )
|
|
|
|
|
( C17 ? )
|
|
|
|
|
( A17 ? )
|
|
|
|
|
( B18 ? )
|
|
|
|
|
( A18 ? )
|
|
|
|
|
( E16 ? )
|
|
|
|
|
( D17 ? )
|
|
|
|
|
( C11 ? )
|
|
|
|
|
( A10 ? )
|
|
|
|
|
( B10 ? )
|
|
|
|
|
( C10 ? )
|
|
|
|
|
( D10 ? )
|
|
|
|
|
( D8 ? )
|
|
|
|
|
( D7 ? )
|
|
|
|
|
( A9 ? )
|
|
|
|
|
( C9 ? )
|
|
|
|
|
( C8 ? )
|
|
|
|
|
( D9 ? )
|
|
|
|
|
( A8 ? )
|
|
|
|
|
( B8 ? )
|
|
|
|
|
( A7 ? )
|
|
|
|
|
( C7 ? )
|
|
|
|
|
( A6 ? )
|
|
|
|
|
( B6 ? )
|
|
|
|
|
( C6 ? )
|
|
|
|
|
( D6 ? )
|
|
|
|
|
( A5 /FPGA_Spartan6/ETH_INT )
|
|
|
|
|
( C5 ? )
|
|
|
|
|
( A4 ? )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2D27 $noname R? 1M {Lib=R}
|
|
|
|
|
( 1 N-000412 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2D1E $noname C? 4.7nF {Lib=C}
|
|
|
|
|
( 1 N-000412 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2CA7 $noname V? V0402MHS03 {Lib=V0402MHS03}
|
|
|
|
|
( 1 N-000410 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2CA3 $noname V? V0402MHS03 {Lib=V0402MHS03}
|
|
|
|
|
( 1 N-000409 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2B55 $noname F? MICROSMD075F {Lib=MICROSMD075F}
|
|
|
|
|
( 1 N-000411 )
|
|
|
|
|
( 2 ? )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F23DD $noname J? USB-48204-0001 {Lib=USB-48204-0001}
|
|
|
|
|
( S1 N-000412 )
|
|
|
|
|
( S2 N-000412 )
|
|
|
|
|
( S3 N-000412 )
|
|
|
|
|
( S4 N-000412 )
|
|
|
|
|
( 1 N-000411 )
|
|
|
|
|
( 2 N-000409 )
|
|
|
|
|
( 3 N-000410 )
|
|
|
|
|
( 4 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2039 $noname C? 470nF {Lib=C}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2037 $noname C? 1uF {Lib=C}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2033 $noname C? 1uF {Lib=C}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 ? )
|
|
|
|
|
( 3 ? )
|
|
|
|
|
( 4 ? )
|
|
|
|
|
( 5 ? )
|
|
|
|
|
( 7 GND )
|
|
|
|
|
( 8 GND )
|
|
|
|
|
( 9 ? )
|
|
|
|
|
( 10 N-000409 )
|
|
|
|
|
( 11 N-000410 )
|
|
|
|
|
( 12 N-000068 )
|
|
|
|
|
( 14 N-000068 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D8114 $noname C? C {Lib=C}
|
|
|
|
|
( 1 /Ethernet_Phy/ETH_PLL1.8V )
|
|
|
|
|
( 2 N-000395 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D810A $noname L? INDUCTOR {Lib=INDUCTOR}
|
|
|
|
|
( 1 /Ethernet_Phy/ETH_A1.8V )
|
|
|
|
|
( 2 /Ethernet_Phy/ETH_PLL1.8V )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D8104 $noname C? C {Lib=C}
|
|
|
|
|
( 1 /Ethernet_Phy/ETH_A1.8V )
|
|
|
|
|
( 2 N-000395 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D80F3 $noname L? INDUCTOR {Lib=INDUCTOR}
|
|
|
|
|
( 1 N-000394 )
|
|
|
|
|
( 2 /Ethernet_Phy/ETH_A1.8V )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D80F0 $noname C? C {Lib=C}
|
|
|
|
|
( 1 N-000394 )
|
|
|
|
|
( 2 N-000395 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D80ED $noname C? C {Lib=C}
|
|
|
|
|
( 1 /Ethernet_Phy/ETH_1.8V )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7FB7 $noname L? FB {Lib=INDUCTOR}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 /Ethernet_Phy/ETH_A3.3V )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7FA7 $noname C? 100nF {Lib=C}
|
|
|
|
|
( 1 /Ethernet_Phy/ETH_A3.3V )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7FA5 $noname C? 1uF {Lib=C}
|
|
|
|
|
( 1 /Ethernet_Phy/ETH_A3.3V )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7FA3 $noname C? 100nF {Lib=C}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7FA1 $noname C? 100nF {Lib=C}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7F9F $noname C? 1uF {Lib=C}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7F39 $noname R? 4.7K {Lib=R}
|
|
|
|
|
( 1 /ETH_MDIO )
|
|
|
|
|
( 2 N-000068 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7ECF $noname R? 6.65K {Lib=R}
|
|
|
|
|
( 1 N-000384 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7E43 $noname C? 100nF {Lib=C}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7E41 $noname C? 100nF {Lib=C}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7DCB $noname C? 47nF {Lib=C}
|
|
|
|
|
( 1 N-000393 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7DC4 $noname R? 1M {Lib=R}
|
|
|
|
|
( 1 N-000393 )
|
|
|
|
|
( 2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001}
|
|
|
|
|
( 1 /ETH_MDIO )
|
|
|
|
|
( 2 ? )
|
|
|
|
|
( 3 ? )
|
|
|
|
|
( 4 ? )
|
|
|
|
|
( 5 ? )
|
|
|
|
|
( 6 ? )
|
|
|
|
|
( 7 N-000068 )
|
|
|
|
|
( 8 GND )
|
|
|
|
|
( 9 ? )
|
|
|
|
|
( 10 ? )
|
|
|
|
|
( 11 ? )
|
|
|
|
|
( 12 GND )
|
|
|
|
|
( 13 /Ethernet_Phy/ETH_1.8V )
|
|
|
|
|
( 14 ? )
|
|
|
|
|
( 15 ? )
|
|
|
|
|
( 16 ? )
|
|
|
|
|
( 17 ? )
|
|
|
|
|
( 18 ? )
|
|
|
|
|
( 19 ? )
|
|
|
|
|
( 20 ? )
|
|
|
|
|
( 21 ? )
|
|
|
|
|
( 22 ? )
|
|
|
|
|
( 23 GND )
|
|
|
|
|
( 24 N-000068 )
|
|
|
|
|
( 25 /FPGA_Spartan6/ETH_INT )
|
|
|
|
|
( 26 /Ethernet_Phy/ETH_LED0 )
|
|
|
|
|
( 27 /Ethernet_Phy/ETH_LED1 )
|
|
|
|
|
( 28 ? )
|
|
|
|
|
( 29 ? )
|
|
|
|
|
( 30 ? )
|
|
|
|
|
( 31 /Ethernet_Phy/ETH_A1.8V )
|
|
|
|
|
( 32 N-000385 )
|
|
|
|
|
( 33 N-000392 )
|
|
|
|
|
( 34 ? )
|
|
|
|
|
( 35 GND )
|
|
|
|
|
( 36 GND )
|
|
|
|
|
( 37 N-000384 )
|
|
|
|
|
( 38 /Ethernet_Phy/ETH_A3.3V )
|
|
|
|
|
( 39 GND )
|
|
|
|
|
( 40 N-000386 )
|
|
|
|
|
( 41 N-000391 )
|
|
|
|
|
( 42 ? )
|
|
|
|
|
( 43 ? )
|
|
|
|
|
( 44 GND )
|
|
|
|
|
( 45 ? )
|
|
|
|
|
( 46 ? )
|
|
|
|
|
( 47 /Ethernet_Phy/ETH_PLL1.8V )
|
|
|
|
|
( 48 ? )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7AFE $noname R? 49.9 {Lib=R}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 N-000391 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7AFC $noname R? 49.9 {Lib=R}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 N-000386 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7AF9 $noname R? 49.9 {Lib=R}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 N-000385 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D7AF7 $noname R? 49.9 {Lib=R}
|
|
|
|
|
( 1 N-000068 )
|
|
|
|
|
( 2 N-000392 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D71DB $noname R? 220 {Lib=R}
|
|
|
|
|
( 1 N-000388 )
|
|
|
|
|
( 2 /Ethernet_Phy/ETH_LED1 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D719D $noname R? 220 {Lib=R}
|
|
|
|
|
( 1 N-000389 )
|
|
|
|
|
( 2 /Ethernet_Phy/ETH_LED0 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025}
|
|
|
|
|
( 1 N-000391 )
|
|
|
|
|
( 2 N-000386 )
|
|
|
|
|
( 3 N-000068 )
|
|
|
|
|
( 4 GND )
|
|
|
|
|
( 5 GND )
|
|
|
|
|
( 6 N-000068 )
|
|
|
|
|
( 7 N-000392 )
|
|
|
|
|
( 8 N-000385 )
|
|
|
|
|
( 9 N-000068 )
|
|
|
|
|
( 10 N-000389 )
|
|
|
|
|
( 11 N-000068 )
|
|
|
|
|
( 12 N-000388 )
|
|
|
|
|
( 13 N-000393 )
|
|
|
|
|
( 14 N-000393 )
|
|
|
|
|
)
|
|
|
|
|
( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD}
|
|
|
|
|
( CASE GND )
|
|
|
|
|
( CD ? )
|
|
|
|
|
( COM GND )
|
|
|
|
|
( 1 ? )
|
|
|
|
|
( 2 ? )
|
|
|
|
|
( 3 ? )
|
|
|
|
|
( 4 ? )
|
|
|
|
|
( 5 ? )
|
|
|
|
|
( 6 ? )
|
|
|
|
|
( 7 ? )
|
|
|
|
|
( 8 ? )
|
|
|
|
|
)
|
|
|
|
|
( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M}
|
|
|
|
|
( 1 ? )
|
|
|
|
|
( 2 ? )
|
|
|
|
|
( 3 ? )
|
|
|
|
|
( 4 ? )
|
|
|
|
|
( 5 ? )
|
|
|
|
|
( 6 /Non_volatile_memories/FRB_N )
|
|
|
|
|
( 7 /Non_volatile_memories/FRB_N )
|
|
|
|
|
( 8 ? )
|
|
|
|
|
( 9 ? )
|
|
|
|
|
( 10 ? )
|
|
|
|
|
( 11 ? )
|
|
|
|
|
( 12 N-000068 )
|
|
|
|
|
( 13 GND )
|
|
|
|
|
( 14 ? )
|
|
|
|
|
( 15 ? )
|
|
|
|
|
( 16 ? )
|
|
|
|
|
( 17 ? )
|
|
|
|
|
( 18 ? )
|
|
|
|
|
( 19 N-000068 )
|
|
|
|
|
( 20 ? )
|
|
|
|
|
( 21 ? )
|
|
|
|
|
( 22 ? )
|
|
|
|
|
( 23 ? )
|
|
|
|
|
( 24 ? )
|
|
|
|
|
( 25 ? )
|
|
|
|
|
( 26 ? )
|
|
|
|
|
( 27 ? )
|
|
|
|
|
( 28 ? )
|
|
|
|
|
( 29 ? )
|
|
|
|
|
( 30 ? )
|
|
|
|
|
( 31 ? )
|
|
|
|
|
( 32 ? )
|
|
|
|
|
( 33 ? )
|
|
|
|
|
( 34 ? )
|
|
|
|
|
( 35 ? )
|
|
|
|
|
( 36 GND )
|
|
|
|
|
( 37 N-000068 )
|
|
|
|
|
( 38 ? )
|
|
|
|
|
( 39 ? )
|
|
|
|
|
( 40 ? )
|
|
|
|
|
( 41 ? )
|
|
|
|
|
( 42 ? )
|
|
|
|
|
( 43 ? )
|
|
|
|
|
( 44 ? )
|
|
|
|
|
( 45 ? )
|
|
|
|
|
( 46 ? )
|
|
|
|
|
( 47 ? )
|
|
|
|
|
( 48 ? )
|
|
|
|
|
)
|
|
|
|
|
( /4C421DD3/4C58CA3A 60fbga_ddr U3 MT46V32M16FN {Lib=MT46V32M16FN}
|
|
|
|
|
( A7 N-000048 )
|
|
|
|
|
( F8 N-000048 )
|
|
|
|
|
( M7 N-000048 )
|
|
|
|
|
( A9 N-000048 )
|
|
|
|
|
( B2 N-000048 )
|
|
|
|
|
( C8 N-000048 )
|
|
|
|
|
( D2 N-000048 )
|
|
|
|
|
( E8 N-000048 )
|
|
|
|
|
( B7 /DDR_Banks/M1_DQ2 )
|
|
|
|
|
( C9 /DDR_Banks/M1_DQ3 )
|
|
|
|
|
( C7 /DDR_Banks/M1_DQ4 )
|
|
|
|
|
( D9 /DDR_Banks/M1_DQ5 )
|
|
|
|
|
( D7 /DDR_Banks/M1_DQ6 )
|
|
|
|
|
( E9 /DDR_Banks/M1_DQ7 )
|
|
|
|
|
( E1 /DDR_Banks/M1_DQ8 )
|
|
|
|
|
( D3 /DDR_Banks/M1_DQ9 )
|
|
|
|
|
( D1 /DDR_Banks/M1_DQ10 )
|
|
|
|
|
( C3 /DDR_Banks/M1_DQ11 )
|
|
|
|
|
( C1 /DDR_Banks/M1_DQ12 )
|
|
|
|
|
( B3 /DDR_Banks/M1_DQ13 )
|
|
|
|
|
( B1 /DDR_Banks/M1_DQ14 )
|
|
|
|
|
( A2 /DDR_Banks/M1_DQ15 )
|
|
|
|
|
( F7 /DDR_Banks/M1_LDM )
|
|
|
|
|
( E7 /DDR_Banks/M1_LDQS )
|
|
|
|
|
( F9 ? )
|
|
|
|
|
( H7 /DDR_Banks/M1_RAS# )
|
|
|
|
|
( F3 /DDR_Banks/M1_UDM )
|
|
|
|
|
( E3 /DDR_Banks/M1_UDQS )
|
|
|
|
|
( F1 ? )
|
|
|
|
|
( G7 /DDR_Banks/M1_WE# )
|
|
|
|
|
( B9 /DDR_Banks/M1_DQ1 )
|
|
|
|
|
( A8 /DDR_Banks/M1_DQ0 )
|
|
|
|
|
( H8 ? )
|
|
|
|
|
( G3 /DDR_Banks/M1_CLK# )
|
|
|
|
|
( G2 /DDR_Banks/M1_CLK )
|
|
|
|
|
( H3 /DDR_Banks/M1_CKE )
|
|
|
|
|
( G8 /DDR_Banks/M1_CAS# )
|
|
|
|
|
( J7 ? )
|
|
|
|
|
( J8 ? )
|
|
|
|
|
( H2 /DDR_Banks/M1_A12 )
|
|
|
|
|
( J2 /DDR_Banks/M1_A11 )
|
|
|
|
|
( K8 /DDR_Banks/M1_A10 )
|
|
|
|
|
( J3 /DDR_Banks/M1_A9 )
|
|
|
|
|
( K2 /DDR_Banks/M1_A8 )
|
|
|
|
|
( K3 /DDR_Banks/M1_A7 )
|
|
|
|
|
( L2 /DDR_Banks/M1_A6 )
|
|
|
|
|
( L3 /DDR_Banks/M1_A5 )
|
|
|
|
|
( M2 /DDR_Banks/M1_A4 )
|
|
|
|
|
( M8 /DDR_Banks/M1_A3 )
|
|
|
|
|
( L7 /DDR_Banks/M1_A2 )
|
|
|
|
|
( L8 /DDR_Banks/M1_A1 )
|
|
|
|
|
( K7 /DDR_Banks/M1_A0 )
|
|
|
|
|
( A3 GND )
|
|
|
|
|
( F2 GND )
|
|
|
|
|
( M3 GND )
|
|
|
|
|
( A1 GND )
|
|
|
|
|
( B8 GND )
|
|
|
|
|
( C2 GND )
|
|
|
|
|
( D8 GND )
|
|
|
|
|
( E2 GND )
|
|
|
|
|
)
|
|
|
|
|
( /4C421DD3/4C58C847 60fbga_ddr U2 MT46V32M16FN {Lib=MT46V32M16FN}
|
|
|
|
|
( A7 N-000046 )
|
|
|
|
|
( F8 N-000046 )
|
|
|
|
|
( M7 N-000046 )
|
|
|
|
|
( A9 N-000046 )
|
|
|
|
|
( B2 N-000046 )
|
|
|
|
|
( C8 N-000046 )
|
|
|
|
|
( D2 N-000046 )
|
|
|
|
|
( E8 N-000046 )
|
|
|
|
|
( B7 /DDR_Banks/M0_DQ2 )
|
|
|
|
|
( C9 /DDR_Banks/M0_DQ3 )
|
|
|
|
|
( C7 /DDR_Banks/M0_DQ4 )
|
|
|
|
|
( D9 /DDR_Banks/M0_DQ5 )
|
|
|
|
|
( D7 /DDR_Banks/M0_DQ6 )
|
|
|
|
|
( E9 /DDR_Banks/M0_DQ7 )
|
|
|
|
|
( E1 /DDR_Banks/M0_DQ8 )
|
|
|
|
|
( D3 /DDR_Banks/M0_DQ9 )
|
|
|
|
|
( D1 /DDR_Banks/M0_DQ10 )
|
|
|
|
|
( C3 /DDR_Banks/M0_DQ11 )
|
|
|
|
|
( C1 /DDR_Banks/M0_DQ12 )
|
|
|
|
|
( B3 /DDR_Banks/M0_DQ13 )
|
|
|
|
|
( B1 /DDR_Banks/M0_DQ14 )
|
|
|
|
|
( A2 /DDR_Banks/M0_DQ15 )
|
|
|
|
|
( F7 /DDR_Banks/M0_LDM )
|
|
|
|
|
( E7 /DDR_Banks/M0_LDQS )
|
|
|
|
|
( F9 ? )
|
|
|
|
|
( H7 /DDR_Banks/M0_RAS# )
|
|
|
|
|
( F3 /DDR_Banks/M0_UDM )
|
|
|
|
|
( E3 /DDR_Banks/M0_UDQS )
|
|
|
|
|
( F1 ? )
|
|
|
|
|
( G7 /DDR_Banks/M0_WE# )
|
|
|
|
|
( B9 /DDR_Banks/M0_DQ1 )
|
|
|
|
|
( A8 /DDR_Banks/M0_DQ0 )
|
|
|
|
|
( H8 ? )
|
|
|
|
|
( G3 /DDR_Banks/M0_CLK# )
|
|
|
|
|
( G2 /DDR_Banks/M0_CLK )
|
|
|
|
|
( H3 /DDR_Banks/M0_CKE )
|
|
|
|
|
( G8 /DDR_Banks/M0_CAS# )
|
|
|
|
|
( J7 ? )
|
|
|
|
|
( J8 ? )
|
|
|
|
|
( H2 /DDR_Banks/M0_A12 )
|
|
|
|
|
( J2 /DDR_Banks/M0_A11 )
|
|
|
|
|
( K8 /DDR_Banks/M0_A10 )
|
|
|
|
|
( J3 /DDR_Banks/M0_A9 )
|
|
|
|
|
( K2 /DDR_Banks/M0_A8 )
|
|
|
|
|
( K3 /DDR_Banks/M0_A7 )
|
|
|
|
|
( L2 /DDR_Banks/M0_A6 )
|
|
|
|
|
( L3 /DDR_Banks/M0_A5 )
|
|
|
|
|
( M2 /DDR_Banks/M0_A4 )
|
|
|
|
|
( M8 /DDR_Banks/M0_A3 )
|
|
|
|
|
( L7 /DDR_Banks/M0_A2 )
|
|
|
|
|
( L8 /DDR_Banks/M0_A1 )
|
|
|
|
|
( K7 /DDR_Banks/M0_A0 )
|
|
|
|
|
( A3 GND )
|
|
|
|
|
( F2 GND )
|
|
|
|
|
( M3 GND )
|
|
|
|
|
( A1 GND )
|
|
|
|
|
( B8 GND )
|
|
|
|
|
( C2 GND )
|
|
|
|
|
( D8 GND )
|
|
|
|
|
( E2 GND )
|
2010-07-24 14:58:53 +03:00
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
*
|
2010-08-08 20:15:44 +03:00
|
|
|
{ Allowed footprints by component:
|
2010-08-09 23:37:18 +03:00
|
|
|
$component R?
|
|
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
|
|
|
|
$endlist
|
2010-08-08 20:15:44 +03:00
|
|
|
$component C?
|
|
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
|
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
|
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
2010-08-08 20:15:44 +03:00
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
|
|
|
|
$endlist
|
|
|
|
|
$component R?
|
|
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component R?
|
2010-08-08 20:15:44 +03:00
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component C?
|
|
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
|
|
|
|
$endlist
|
|
|
|
|
$component C?
|
|
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
|
|
|
|
$endlist
|
|
|
|
|
$component C?
|
|
|
|
|
SM*
|
|
|
|
|
C?
|
|
|
|
|
C1-1
|
|
|
|
|
$endlist
|
|
|
|
|
$component R?
|
2010-08-08 20:15:44 +03:00
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component R?
|
2010-08-08 20:15:44 +03:00
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component R?
|
2010-08-08 20:15:44 +03:00
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component R?
|
2010-08-08 20:15:44 +03:00
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component R?
|
2010-08-08 20:15:44 +03:00
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component R?
|
2010-08-08 20:15:44 +03:00
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
2010-08-09 23:37:18 +03:00
|
|
|
$endlist
|
|
|
|
|
$component R?
|
2010-08-08 20:15:44 +03:00
|
|
|
R?
|
|
|
|
|
SM0603
|
|
|
|
|
SM0805
|
|
|
|
|
$endlist
|
|
|
|
|
$endfootprintlist
|
2010-07-24 14:58:53 +03:00
|
|
|
}
|
2010-08-09 23:37:18 +03:00
|
|
|
{ Pin List by Nets
|
|
|
|
|
Net 9 "/ETH_MDIO" "ETH_MDIO"
|
|
|
|
|
R? 1
|
|
|
|
|
U4 1
|
|
|
|
|
Net 13 "/DDR Banks/M1_LDM" "M1_LDM"
|
|
|
|
|
U3 F7
|
|
|
|
|
U1 L19
|
|
|
|
|
Net 14 "/DDR Banks/M1_CKE" "M1_CKE"
|
|
|
|
|
U3 H3
|
|
|
|
|
U1 D21
|
|
|
|
|
Net 15 "/DDR Banks/M1_CAS#" "M1_CAS#"
|
|
|
|
|
U3 G8
|
|
|
|
|
U1 H22
|
|
|
|
|
Net 16 "/DDR Banks/M0_CKE" "M0_CKE"
|
|
|
|
|
U2 H3
|
|
|
|
|
U1 D2
|
|
|
|
|
Net 17 "/DDR Banks/M0_WE#" "M0_WE#"
|
|
|
|
|
U2 G7
|
|
|
|
|
U1 F2
|
|
|
|
|
Net 18 "/DDR Banks/M0_CAS#" "M0_CAS#"
|
|
|
|
|
U2 G8
|
|
|
|
|
U1 K4
|
|
|
|
|
Net 19 "/DDR Banks/M0_UDM" "M0_UDM"
|
|
|
|
|
U2 F3
|
|
|
|
|
U1 M3
|
|
|
|
|
Net 20 "/DDR Banks/M0_UDQS" "M0_UDQS"
|
|
|
|
|
U2 E3
|
|
|
|
|
U1 T2
|
|
|
|
|
Net 21 "/DDR Banks/M1_CLK#" "M1_CLK#"
|
|
|
|
|
U3 G3
|
|
|
|
|
U1 J19
|
|
|
|
|
Net 22 "/DDR Banks/M0_CLK#" "M0_CLK#"
|
|
|
|
|
U2 G3
|
|
|
|
|
U1 H3
|
|
|
|
|
Net 23 "/DDR Banks/M0_CLK" "M0_CLK"
|
|
|
|
|
U2 G2
|
|
|
|
|
U1 H4
|
|
|
|
|
Net 24 "/DDR Banks/M1_CLK" "M1_CLK"
|
|
|
|
|
U3 G2
|
|
|
|
|
U1 H20
|
|
|
|
|
Net 25 "/DDR Banks/M0_LDM" "M0_LDM"
|
|
|
|
|
U2 F7
|
|
|
|
|
U1 L4
|
|
|
|
|
Net 26 "/DDR Banks/M0_LDQS" "M0_LDQS"
|
|
|
|
|
U2 E7
|
|
|
|
|
U1 L3
|
|
|
|
|
Net 27 "/DDR Banks/M0_RAS#" "M0_RAS#"
|
|
|
|
|
U2 H7
|
|
|
|
|
U1 K5
|
|
|
|
|
Net 29 "/DDR Banks/M1_RAS#" "M1_RAS#"
|
|
|
|
|
U3 H7
|
|
|
|
|
U1 H21
|
|
|
|
|
Net 30 "/DDR Banks/M1_WE#" "M1_WE#"
|
|
|
|
|
U3 G7
|
|
|
|
|
U1 H19
|
|
|
|
|
Net 31 "/DDR Banks/M1_UDM" "M1_UDM"
|
|
|
|
|
U3 F3
|
|
|
|
|
U1 M20
|
|
|
|
|
Net 32 "/DDR Banks/M1_LDQS" "M1_LDQS"
|
|
|
|
|
U3 E7
|
|
|
|
|
U1 L20
|
|
|
|
|
Net 33 "/DDR Banks/M1_UDQS" "M1_UDQS"
|
|
|
|
|
U3 E3
|
|
|
|
|
U1 T21
|
|
|
|
|
Net 34 "/FPGA Spartan6/ETH_INT" "ETH_INT"
|
|
|
|
|
U1 A5
|
|
|
|
|
U4 25
|
|
|
|
|
Net 45 "GND" "GND"
|
|
|
|
|
U3 A3
|
|
|
|
|
U3 F2
|
|
|
|
|
U3 M3
|
|
|
|
|
U3 A1
|
|
|
|
|
U3 B8
|
|
|
|
|
U3 C2
|
|
|
|
|
U3 D8
|
|
|
|
|
U3 E2
|
|
|
|
|
U2 A3
|
|
|
|
|
U2 F2
|
|
|
|
|
U2 M3
|
|
|
|
|
U2 A1
|
|
|
|
|
U2 B8
|
|
|
|
|
U2 C2
|
|
|
|
|
U2 D8
|
|
|
|
|
U2 E2
|
|
|
|
|
J1 CASE
|
|
|
|
|
J1 CASE
|
|
|
|
|
J1 CASE
|
|
|
|
|
J1 COM
|
|
|
|
|
U5 36
|
|
|
|
|
U5 13
|
|
|
|
|
U1 P10
|
|
|
|
|
U1 V10
|
|
|
|
|
U1 M10
|
|
|
|
|
U1 K10
|
|
|
|
|
U1 L13
|
|
|
|
|
U1 A1
|
|
|
|
|
U1 N13
|
|
|
|
|
U1 A22
|
|
|
|
|
U1 R5
|
|
|
|
|
U1 AA13
|
|
|
|
|
U1 W19
|
|
|
|
|
U1 AA17
|
|
|
|
|
U1 K14
|
|
|
|
|
U1 AA5
|
|
|
|
|
U1 L5
|
|
|
|
|
U1 AA9
|
|
|
|
|
U1 M14
|
|
|
|
|
U1 AB1
|
|
|
|
|
U1 N2
|
|
|
|
|
U1 AB22
|
|
|
|
|
U1 P14
|
|
|
|
|
U1 B13
|
|
|
|
|
U1 U21
|
|
|
|
|
U1 B17
|
|
|
|
|
U1 V4
|
|
|
|
|
U1 B5
|
|
|
|
|
U1 J9
|
|
|
|
|
U1 B9
|
|
|
|
|
U1 K12
|
|
|
|
|
U1 D18
|
|
|
|
|
U1 L11
|
|
|
|
|
U1 D4
|
|
|
|
|
U1 L18
|
|
|
|
|
U1 E11
|
|
|
|
|
U1 L9
|
|
|
|
|
U1 E15
|
|
|
|
|
U1 M12
|
|
|
|
|
U1 E2
|
|
|
|
|
U1 N11
|
|
|
|
|
U1 E21
|
|
|
|
|
U1 N17
|
|
|
|
|
U1 E7
|
|
|
|
|
U1 N21
|
|
|
|
|
U1 G18
|
|
|
|
|
U1 P12
|
|
|
|
|
U1 G5
|
|
|
|
|
U1 R18
|
|
|
|
|
U1 H7
|
|
|
|
|
U1 U2
|
|
|
|
|
U1 J11
|
|
|
|
|
U1 U7
|
|
|
|
|
U1 J13
|
|
|
|
|
U1 V14
|
|
|
|
|
U1 J15
|
|
|
|
|
U1 W16
|
|
|
|
|
U1 J2
|
|
|
|
|
U1 W7
|
|
|
|
|
U1 J21
|
|
|
|
|
U1 N9
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
R? 2
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
R? 2
|
|
|
|
|
U4 8
|
|
|
|
|
U4 12
|
|
|
|
|
U4 23
|
|
|
|
|
U4 35
|
|
|
|
|
U4 36
|
|
|
|
|
U4 39
|
|
|
|
|
U4 44
|
|
|
|
|
J4 5
|
|
|
|
|
J4 4
|
|
|
|
|
R? 2
|
|
|
|
|
C? 2
|
|
|
|
|
V? 2
|
|
|
|
|
V? 2
|
|
|
|
|
J? 4
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
C? 2
|
|
|
|
|
U6 8
|
|
|
|
|
U6 7
|
|
|
|
|
Net 46 "" ""
|
|
|
|
|
U2 A7
|
|
|
|
|
U2 F8
|
|
|
|
|
U2 M7
|
|
|
|
|
U2 A9
|
|
|
|
|
U2 B2
|
|
|
|
|
U2 C8
|
|
|
|
|
U2 D2
|
|
|
|
|
U2 E8
|
|
|
|
|
Net 48 "" ""
|
|
|
|
|
U3 A7
|
|
|
|
|
U3 F8
|
|
|
|
|
U3 M7
|
|
|
|
|
U3 A9
|
|
|
|
|
U3 B2
|
|
|
|
|
U3 C8
|
|
|
|
|
U3 D2
|
|
|
|
|
U3 E8
|
|
|
|
|
Net 68 "" ""
|
|
|
|
|
U5 37
|
|
|
|
|
U5 19
|
|
|
|
|
U5 12
|
|
|
|
|
L? 1
|
|
|
|
|
C? 1
|
|
|
|
|
C? 1
|
|
|
|
|
C? 1
|
|
|
|
|
R? 2
|
|
|
|
|
C? 1
|
|
|
|
|
C? 1
|
|
|
|
|
U4 7
|
|
|
|
|
U4 24
|
|
|
|
|
R? 1
|
|
|
|
|
R? 1
|
|
|
|
|
R? 1
|
|
|
|
|
R? 1
|
|
|
|
|
J4 11
|
|
|
|
|
J4 9
|
|
|
|
|
J4 6
|
|
|
|
|
J4 3
|
|
|
|
|
C? 1
|
|
|
|
|
C? 1
|
|
|
|
|
C? 1
|
|
|
|
|
U6 14
|
|
|
|
|
U6 12
|
|
|
|
|
U6 1
|
|
|
|
|
Net 71 "/Non volatile memories/FRB_N" "FRB_N"
|
|
|
|
|
U5 7
|
|
|
|
|
U5 6
|
|
|
|
|
Net 118 "" ""
|
|
|
|
|
U1 N10
|
|
|
|
|
U1 P11
|
|
|
|
|
U1 P13
|
|
|
|
|
U1 P9
|
|
|
|
|
U1 R14
|
|
|
|
|
U1 N12
|
|
|
|
|
U1 J10
|
|
|
|
|
U1 J12
|
|
|
|
|
U1 J14
|
|
|
|
|
U1 J8
|
|
|
|
|
U1 K11
|
|
|
|
|
U1 K13
|
|
|
|
|
U1 K9
|
|
|
|
|
U1 L10
|
|
|
|
|
U1 L12
|
|
|
|
|
U1 L14
|
|
|
|
|
U1 M11
|
|
|
|
|
U1 M13
|
|
|
|
|
U1 M9
|
|
|
|
|
U1 N14
|
|
|
|
|
Net 119 "" ""
|
|
|
|
|
U1 H9
|
|
|
|
|
U1 U11
|
|
|
|
|
U1 F11
|
|
|
|
|
U1 R6
|
|
|
|
|
U1 M15
|
|
|
|
|
U1 V6
|
|
|
|
|
U1 G12
|
|
|
|
|
U1 H15
|
|
|
|
|
U1 D16
|
|
|
|
|
U1 K15
|
|
|
|
|
U1 R12
|
|
|
|
|
U1 N8
|
|
|
|
|
U1 R10
|
|
|
|
|
U1 L8
|
|
|
|
|
Net 120 "" ""
|
|
|
|
|
U1 W2
|
|
|
|
|
U1 L2
|
|
|
|
|
U1 L7
|
|
|
|
|
U1 C2
|
|
|
|
|
U1 N5
|
|
|
|
|
U1 R2
|
|
|
|
|
U1 U5
|
|
|
|
|
U1 G2
|
|
|
|
|
U1 F4
|
|
|
|
|
U1 F6
|
|
|
|
|
U1 J5
|
|
|
|
|
Net 121 "" ""
|
|
|
|
|
U1 W21
|
|
|
|
|
U1 C21
|
|
|
|
|
U1 G21
|
|
|
|
|
U1 J18
|
|
|
|
|
U1 L16
|
|
|
|
|
U1 L21
|
|
|
|
|
U1 N18
|
|
|
|
|
U1 R21
|
|
|
|
|
U1 U18
|
|
|
|
|
U1 E19
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Net 122 "" ""
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U1 B4
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U1 B7
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U1 E13
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U1 E17
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U1 G10
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U1 G14
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U1 B11
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U1 B15
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U1 B19
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U1 E9
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Net 123 "" ""
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U1 AA15
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U1 V16
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U1 T13
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U1 V8
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U1 V12
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U1 AA3
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U1 T9
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U1 AA19
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U1 AA11
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U1 W5
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U1 AA7
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Net 382 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
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L? 1
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C? 1
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L? 2
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U4 31
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Net 383 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
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L? 2
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C? 1
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C? 1
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U4 38
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Net 384 "" ""
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R? 1
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U4 37
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Net 385 "" ""
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U4 32
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R? 2
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J4 8
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Net 386 "" ""
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U4 40
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R? 2
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J4 2
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Net 387 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
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U4 27
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R? 2
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Net 388 "" ""
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R? 1
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J4 12
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Net 389 "" ""
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R? 1
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J4 10
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Net 390 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
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U4 26
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R? 2
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Net 391 "" ""
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U4 41
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R? 2
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J4 1
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Net 392 "" ""
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U4 33
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R? 2
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J4 7
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Net 393 "" ""
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C? 1
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R? 1
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J4 13
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J4 14
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Net 394 "" ""
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L? 1
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C? 1
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Net 395 "" ""
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C? 2
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C? 2
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C? 2
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Net 396 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V"
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C? 1
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U4 13
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Net 397 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
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C? 1
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L? 2
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U4 47
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Net 409 "" ""
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V? 1
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V? 1
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J? 2
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U6 10
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Net 410 "" ""
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V? 1
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V? 1
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J? 3
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U6 11
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Net 411 "" ""
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F? 1
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J? 1
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Net 412 "" ""
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R? 1
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C? 1
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J? S1
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J? S2
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J? S3
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J? S4
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Net 423 "/DDR Banks/M0_A0" "M0_A0"
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U2 K7
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U1 H2
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Net 424 "/DDR Banks/M0_A1" "M0_A1"
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U2 L8
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U1 H1
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Net 425 "/DDR Banks/M0_A2" "M0_A2"
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U2 L7
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U1 H5
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Net 426 "/DDR Banks/M0_A3" "M0_A3"
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U2 M8
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U1 K6
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Net 427 "/DDR Banks/M0_A4" "M0_A4"
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U2 M2
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U1 F3
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Net 428 "/DDR Banks/M0_A5" "M0_A5"
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U2 L3
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U1 K3
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Net 429 "/DDR Banks/M0_A6" "M0_A6"
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U2 L2
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U1 J4
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Net 430 "/DDR Banks/M0_A7" "M0_A7"
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U2 K3
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U1 H6
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Net 431 "/DDR Banks/M0_A8" "M0_A8"
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U2 K2
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U1 E3
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Net 432 "/DDR Banks/M0_A9" "M0_A9"
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U2 J3
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U1 E1
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Net 433 "/DDR Banks/M0_A10" "M0_A10"
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U2 K8
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U1 G4
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Net 434 "/DDR Banks/M0_A11" "M0_A11"
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U2 J2
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U1 C1
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Net 435 "/DDR Banks/M0_A12" "M0_A12"
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U2 H2
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U1 D1
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Net 436 "/DDR Banks/M1_A0" "M1_A0"
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U3 K7
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U1 F21
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Net 437 "/DDR Banks/M1_A1" "M1_A1"
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U3 L8
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U1 F22
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Net 438 "/DDR Banks/M1_A2" "M1_A2"
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U3 L7
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U1 E22
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Net 439 "/DDR Banks/M1_A3" "M1_A3"
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U3 M8
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U1 G20
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Net 440 "/DDR Banks/M1_A4" "M1_A4"
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U3 M2
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U1 F20
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Net 441 "/DDR Banks/M1_A5" "M1_A5"
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U3 L3
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U1 K20
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Net 442 "/DDR Banks/M1_A6" "M1_A6"
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U3 L2
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U1 K19
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Net 443 "/DDR Banks/M1_A7" "M1_A7"
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U3 K3
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U1 E20
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Net 444 "/DDR Banks/M1_A8" "M1_A8"
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U3 K2
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U1 C20
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Net 445 "/DDR Banks/M1_A9" "M1_A9"
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U3 J3
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U1 C22
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Net 446 "/DDR Banks/M1_A10" "M1_A10"
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U3 K8
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U1 G19
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Net 447 "/DDR Banks/M1_A11" "M1_A11"
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U3 J2
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U1 F19
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Net 448 "/DDR Banks/M1_A12" "M1_A12"
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U3 H2
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U1 D22
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Net 449 "/DDR Banks/M0_DQ0" "M0_DQ0"
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U2 A8
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U1 N3
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Net 450 "/DDR Banks/M0_DQ1" "M0_DQ1"
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U2 B9
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U1 N1
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Net 451 "/DDR Banks/M0_DQ2" "M0_DQ2"
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U2 B7
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U1 M2
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Net 452 "/DDR Banks/M0_DQ3" "M0_DQ3"
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U2 C9
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U1 M1
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Net 453 "/DDR Banks/M0_DQ4" "M0_DQ4"
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U2 C7
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U1 J3
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Net 454 "/DDR Banks/M0_DQ5" "M0_DQ5"
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U2 D9
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U1 J1
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Net 455 "/DDR Banks/M0_DQ6" "M0_DQ6"
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U2 D7
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U1 K2
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Net 456 "/DDR Banks/M0_DQ7" "M0_DQ7"
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U2 E9
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U1 K1
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Net 457 "/DDR Banks/M0_DQ8" "M0_DQ8"
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U2 E1
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U1 P2
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Net 458 "/DDR Banks/M0_DQ9" "M0_DQ9"
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U2 D3
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U1 P1
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Net 459 "/DDR Banks/M0_DQ10" "M0_DQ10"
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U2 D1
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U1 R3
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Net 460 "/DDR Banks/M0_DQ11" "M0_DQ11"
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U2 C3
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U1 R1
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Net 461 "/DDR Banks/M0_DQ12" "M0_DQ12"
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U2 C1
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U1 U3
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Net 462 "/DDR Banks/M0_DQ13" "M0_DQ13"
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U2 B3
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U1 U1
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Net 463 "/DDR Banks/M0_DQ14" "M0_DQ14"
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U2 B1
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U1 V2
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Net 464 "/DDR Banks/M0_DQ15" "M0_DQ15"
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U2 A2
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U1 V1
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Net 465 "/DDR Banks/M1_DQ0" "M1_DQ0"
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U3 A8
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U1 N20
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Net 466 "/DDR Banks/M1_DQ1" "M1_DQ1"
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U3 B9
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U1 N22
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Net 467 "/DDR Banks/M1_DQ2" "M1_DQ2"
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U3 B7
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U1 M21
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Net 468 "/DDR Banks/M1_DQ3" "M1_DQ3"
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U3 C9
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U1 M22
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Net 469 "/DDR Banks/M1_DQ4" "M1_DQ4"
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U3 C7
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U1 J20
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Net 470 "/DDR Banks/M1_DQ5" "M1_DQ5"
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U3 D9
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U1 J22
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Net 471 "/DDR Banks/M1_DQ6" "M1_DQ6"
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U3 D7
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U1 K21
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Net 472 "/DDR Banks/M1_DQ7" "M1_DQ7"
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U3 E9
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U1 K22
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Net 473 "/DDR Banks/M1_DQ8" "M1_DQ8"
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U3 E1
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U1 P21
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Net 474 "/DDR Banks/M1_DQ9" "M1_DQ9"
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U3 D3
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U1 P22
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Net 475 "/DDR Banks/M1_DQ10" "M1_DQ10"
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U3 D1
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U1 R20
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Net 476 "/DDR Banks/M1_DQ11" "M1_DQ11"
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U3 C3
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U1 R22
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Net 477 "/DDR Banks/M1_DQ12" "M1_DQ12"
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U3 C1
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U1 U20
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Net 478 "/DDR Banks/M1_DQ13" "M1_DQ13"
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U3 B3
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U1 U22
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Net 479 "/DDR Banks/M1_DQ14" "M1_DQ14"
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U3 B1
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U1 V21
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Net 480 "/DDR Banks/M1_DQ15" "M1_DQ15"
|
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U3 A2
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U1 V22
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|
}
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#End
|
