2010-08-04 05:23:17 +03:00
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EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
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2010-07-24 14:58:53 +03:00
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:special
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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2010-08-04 05:23:17 +03:00
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LIBS:micron_ddr_512Mb
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2010-07-24 22:02:57 +03:00
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LIBS:xue-rnc-cache
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2010-07-24 14:58:53 +03:00
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EELAYER 24 0
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EELAYER END
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$Descr A4 11700 8267
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Sheet 1 5
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Title ""
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2010-08-04 05:23:17 +03:00
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Date "4 aug 2010"
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2010-07-24 14:58:53 +03:00
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2010-08-04 05:23:17 +03:00
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4000 2300 2750 2300
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2010-08-04 05:23:17 +03:00
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2750 4350 4000 4350
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2010-07-28 14:48:02 +03:00
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Wire Wire Line
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2010-08-04 05:23:17 +03:00
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7800 4550 7350 4550
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2010-07-24 14:58:53 +03:00
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Wire Bus Line
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2010-07-28 14:48:02 +03:00
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4000 3300 4000 3250
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2010-07-24 14:58:53 +03:00
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Wire Bus Line
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2010-07-28 14:48:02 +03:00
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4000 3250 2750 3250
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2010-07-24 14:58:53 +03:00
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Wire Bus Line
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2010-08-04 05:23:17 +03:00
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4000 1200 4000 1150
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2010-08-04 05:23:17 +03:00
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2750 4250 4000 4250
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2010-08-04 05:23:17 +03:00
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2750 2200 4000 2200
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Wire Bus Line
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4000 1150 2750 1150
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2010-07-24 14:58:53 +03:00
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$Sheet
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2010-07-28 14:48:02 +03:00
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S 7800 4450 1450 2200
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2010-07-24 14:58:53 +03:00
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U 4C4320F3
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F0 "Ethernet Phy" 60
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F1 "eth_phy.sch" 60
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2010-07-28 14:48:02 +03:00
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F2 "ETH_RXC" O L 7800 4700 60
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F3 "ETH_RST_N" I L 7800 4800 60
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F4 "ETH_CRS" O L 7800 4900 60
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F5 "ETH_COL" O L 7800 5000 60
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F6 "ETH_INT" O L 7800 4550 60
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F7 "ETH_MDIO" B L 7800 5100 60
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F8 "ETH_MDC" I L 7800 5200 60
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F9 "ETH_RXD[0..3]" O L 7800 5400 60
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F10 "ETH_RXDV" O L 7800 5500 60
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F11 "ETH_RXER" O L 7800 5600 60
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F12 "ETH_TXC" B L 7800 5700 60
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F13 "ETH_TXD[0..3]" I L 7800 5800 60
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F14 "ETH_TXEN" I L 7800 5900 60
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F15 "ETH_TXER" I L 7800 6000 60
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F16 "ETH_CLK" I L 7800 6100 60
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2010-07-24 14:58:53 +03:00
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$EndSheet
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$Sheet
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2010-07-28 14:48:02 +03:00
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S 4000 900 3350 5800
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2010-07-24 14:58:53 +03:00
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U 4C431A63
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F0 "FPGA Spartan6" 60
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F1 "FPGA.sch" 60
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2010-08-04 05:23:17 +03:00
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F2 "M1_CLK" O L 4000 2200 60
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F3 "M1_CLK#" O L 4000 2300 60
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F4 "M0_CLK" O L 4000 4250 60
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F5 "M0_CLK#" O L 4000 4350 60
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2010-07-28 14:48:02 +03:00
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F6 "ETH_INT" I R 7350 4550 60
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2010-07-24 14:58:53 +03:00
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$EndSheet
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$Sheet
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S 8700 900 1150 1850
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U 4C4227FE
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F0 "Non volatile memories" 60
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F1 "NV_MEMORIES.sch" 60
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$EndSheet
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$Sheet
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S 1650 900 1100 4000
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U 4C421DD3
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F0 "DDR Banks" 60
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F1 "DRAM.sch" 60
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2010-08-04 05:23:17 +03:00
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F2 "M0_BA[0..1]" I R 2750 3450 60
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F3 "M1_BA[0..1]" I R 2750 1350 60
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F4 "M0_WE#" I R 2750 4750 60
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F5 "M0_RAS#" I R 2750 4600 60
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F6 "M1_RAS#" I R 2750 2550 60
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F7 "M1_WE#" I R 2750 2700 60
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F8 "M0_CAS#" I R 2750 4500 60
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F9 "M0_CKE" I R 2750 4150 60
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F10 "M0_CLK" I R 2750 4250 60
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F11 "M0_CLK#" I R 2750 4350 60
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F12 "M0_CS#" I R 2750 3100 60
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F13 "M1_CLK#" I R 2750 2300 60
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F14 "M1_CLK" I R 2750 2200 60
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F15 "M1_CKE" I R 2750 2100 60
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F16 "M1_CAS#" I R 2750 2450 60
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F17 "M0_DQ[0..15]" B R 2750 3250 60
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F18 "M0_UDM" I R 2750 3900 60
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F19 "M0_LDQS" I R 2750 3700 60
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F20 "M0_A[0..12]" I R 2750 3350 60
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F21 "M0_LDM" I R 2750 4000 60
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F22 "M0_UDQS" I R 2750 3600 60
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F23 "M1_UDQS" I R 2750 1550 60
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F24 "M1_LDM" I R 2750 1950 60
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F25 "M1_LDQS" I R 2750 1650 60
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F26 "M1_UDM" I R 2750 1850 60
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F27 "M1_CS#" I R 2750 1000 60
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F28 "M1_A[0..12]" I R 2750 1250 60
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F29 "M1_DQ[0..15]" B R 2750 1150 60
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2010-07-24 14:58:53 +03:00
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$EndSheet
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$EndSCHEMATC
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